diff --git a/4G/tools/Luatools_v3.exe b/4G/tools/Luatools_v3.exe deleted file mode 100644 index 3518beb..0000000 Binary files a/4G/tools/Luatools_v3.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/FotaToolkit.exe b/4G/tools/_temp/dtools/ec618/FotaToolkit.exe deleted file mode 100644 index 8c8292e..0000000 Binary files a/4G/tools/_temp/dtools/ec618/FotaToolkit.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/VCRUNTIME140D.dll b/4G/tools/_temp/dtools/ec618/VCRUNTIME140D.dll deleted file mode 100644 index a384756..0000000 Binary files a/4G/tools/_temp/dtools/ec618/VCRUNTIME140D.dll and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/config/ec616(s).json b/4G/tools/_temp/dtools/ec618/config/ec616(s).json deleted file mode 100644 index 4063c34..0000000 --- a/4G/tools/_temp/dtools/ec618/config/ec616(s).json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'PatchBlockSize' must be set 32K, other block size has not been supported yet!"}, - {"Comment": "'FotaMemSize' is not the entire customized FOTA zone in flash but the one only for delta downloading!"}, - {"Comment": "'attr' in 'ImageMem' must be set with one of these choices('BINPKG/BL/AP/CP/APP/APP2'), which is forbidden to be redefined!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC616(S)", - "PatchBlockSize": 32768, - "FotaMemSize": 491520, - "ImageMem": [ - { - "attr": "APP", - "addr": 8519680, - "size": 2621440 - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec618/config/ec618.json b/4G/tools/_temp/dtools/ec618/config/ec618.json deleted file mode 100644 index cfc5008..0000000 --- a/4G/tools/_temp/dtools/ec618/config/ec618.json +++ /dev/null @@ -1,34 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'PatchBlockSize' must be set 32K, other block size has not been supported yet!"}, - {"Comment": "'FotaMemSize' is not the entire customized FOTA zone in flash but the one only for delta downloading!"}, - {"Comment": "'attr' in 'ImageMem' must be set with one of these choices('BINPKG/BL/AP/CP/APP/APP2'), which is forbidden to be redefined!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC618", - "PatchBlockSize": 32768, - "FotaMemSize": 491520, - "ImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8536064, - "size": 3014656 - }, - { - "attr": "CP", - "addr": 8388608, - "size": 524288 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec618/dep/deltagen.exe b/4G/tools/_temp/dtools/ec618/dep/deltagen.exe deleted file mode 100644 index 627f163..0000000 Binary files a/4G/tools/_temp/dtools/ec618/dep/deltagen.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/dep/fcelf.exe b/4G/tools/_temp/dtools/ec618/dep/fcelf.exe deleted file mode 100644 index cfdf29b..0000000 Binary files a/4G/tools/_temp/dtools/ec618/dep/fcelf.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/dep/sha256sum.exe b/4G/tools/_temp/dtools/ec618/dep/sha256sum.exe deleted file mode 100644 index b61a774..0000000 Binary files a/4G/tools/_temp/dtools/ec618/dep/sha256sum.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec618/run.bat b/4G/tools/_temp/dtools/ec618/run.bat deleted file mode 100644 index aac0e8b..0000000 --- a/4G/tools/_temp/dtools/ec618/run.bat +++ /dev/null @@ -1 +0,0 @@ -FotaToolkit.exe -d config\ec618.json %1 %2 old.binpkg new.binpkg \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec618/settings.json b/4G/tools/_temp/dtools/ec618/settings.json deleted file mode 100644 index 646a9f0..0000000 --- a/4G/tools/_temp/dtools/ec618/settings.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "generatorconfig": "E:/file/LTE/ec618/tools/FotaToolkit/config/ec618.json" -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec618/ucrtbased.dll b/4G/tools/_temp/dtools/ec618/ucrtbased.dll deleted file mode 100644 index 0a84948..0000000 Binary files a/4G/tools/_temp/dtools/ec618/ucrtbased.dll and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/FotaToolkit.exe b/4G/tools/_temp/dtools/ec7xx/FotaToolkit.exe deleted file mode 100644 index dd7defb..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/FotaToolkit.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/VCRUNTIME140D.dll b/4G/tools/_temp/dtools/ec7xx/VCRUNTIME140D.dll deleted file mode 100644 index a384756..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/VCRUNTIME140D.dll and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec716e.json b/4G/tools/_temp/dtools/ec7xx/config/ec716e.json deleted file mode 100644 index 18d7bfa..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec716e.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC716E", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec716s.json b/4G/tools/_temp/dtools/ec7xx/config/ec716s.json deleted file mode 100644 index aea8883..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec716s.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC716S", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 217088, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8855552, - "size": 1261568 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 360448 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "CP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 1261568 - }, - { - "enable": 0, - "attr": "CP", - "size": 360448 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718hm.json b/4G/tools/_temp/dtools/ec7xx/config/ec718hm.json deleted file mode 100644 index ae826c9..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718hm.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718HM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718p.json b/4G/tools/_temp/dtools/ec7xx/config/ec718p.json deleted file mode 100644 index 80e969f..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718p.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718P", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718pm.json b/4G/tools/_temp/dtools/ec7xx/config/ec718pm.json deleted file mode 100644 index e2d1603..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718pm.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718PM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 360448, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8921088, - "size": 3174400 - }, - { - "attr": "CP", - "addr": 8511488, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718pv.json b/4G/tools/_temp/dtools/ec7xx/config/ec718pv.json deleted file mode 100644 index 80e969f..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718pv.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718P", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718s.json b/4G/tools/_temp/dtools/ec7xx/config/ec718s.json deleted file mode 100644 index cf4691f..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718s.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718S", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 217088, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8855552, - "size": 1261568 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 360448 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "CP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 1261568 - }, - { - "enable": 0, - "attr": "CP", - "size": 360448 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718u.json b/4G/tools/_temp/dtools/ec7xx/config/ec718u.json deleted file mode 100644 index cc8d29f..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718u.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718U", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/config/ec718um.json b/4G/tools/_temp/dtools/ec7xx/config/ec718um.json deleted file mode 100644 index b229385..0000000 --- a/4G/tools/_temp/dtools/ec7xx/config/ec718um.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718UM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 1, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx/dep/posix/ecsecure b/4G/tools/_temp/dtools/ec7xx/dep/posix/ecsecure deleted file mode 100644 index e8326a3..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/dep/posix/ecsecure and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/dep/posix/fcelf b/4G/tools/_temp/dtools/ec7xx/dep/posix/fcelf deleted file mode 100644 index ca95fd8..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/dep/posix/fcelf and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/dep/windows/Release_Note_Deltagen.txt b/4G/tools/_temp/dtools/ec7xx/dep/windows/Release_Note_Deltagen.txt deleted file mode 100644 index 67acd6b..0000000 --- a/4G/tools/_temp/dtools/ec7xx/dep/windows/Release_Note_Deltagen.txt +++ /dev/null @@ -1,7 +0,0 @@ -程序名称：Deltagen -程序版本：deltagen20221121 -deltagen20221121 -1.优化了相同块的差分包生成方式，兼容新旧bootloader 差分库。 - - - diff --git a/4G/tools/_temp/dtools/ec7xx/dep/windows/deltagen.exe b/4G/tools/_temp/dtools/ec7xx/dep/windows/deltagen.exe deleted file mode 100644 index 423b99c..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/dep/windows/deltagen.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/dep/windows/ecsecure.exe b/4G/tools/_temp/dtools/ec7xx/dep/windows/ecsecure.exe deleted file mode 100644 index 8b960a2..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/dep/windows/ecsecure.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/dep/windows/fcelf.exe b/4G/tools/_temp/dtools/ec7xx/dep/windows/fcelf.exe deleted file mode 100644 index 0cb219a..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/dep/windows/fcelf.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx/ucrtbased.dll b/4G/tools/_temp/dtools/ec7xx/ucrtbased.dll deleted file mode 100644 index 0a84948..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx/ucrtbased.dll and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/FotaToolkit.exe b/4G/tools/_temp/dtools/ec7xx_no_hls/FotaToolkit.exe deleted file mode 100644 index dd7defb..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/FotaToolkit.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/VCRUNTIME140D.dll b/4G/tools/_temp/dtools/ec7xx_no_hls/VCRUNTIME140D.dll deleted file mode 100644 index a384756..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/VCRUNTIME140D.dll and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716e.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716e.json deleted file mode 100644 index 6c7e837..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716e.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC716E", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716s.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716s.json deleted file mode 100644 index 13434dd..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec716s.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC716S", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 217088, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8855552, - "size": 1261568 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 360448 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "CP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 1261568 - }, - { - "enable": 0, - "attr": "CP", - "size": 360448 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718hm.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718hm.json deleted file mode 100644 index e743ff7..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718hm.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718HM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718p.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718p.json deleted file mode 100644 index 8b5a11b..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718p.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718P", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pm.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pm.json deleted file mode 100644 index 96a08fe..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pm.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718PM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 360448, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8921088, - "size": 3174400 - }, - { - "attr": "CP", - "addr": 8511488, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pv.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pv.json deleted file mode 100644 index 8b5a11b..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718pv.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718P", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 331776, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8904704, - "size": 3190784 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 409600 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "CP", - "base": 8388608, - "size": 4194304 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 3190784 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718s.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718s.json deleted file mode 100644 index db94f8d..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718s.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718S", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 0, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 217088, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8855552, - "size": 1261568 - }, - { - "attr": "CP", - "addr": 8495104, - "size": 360448 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "CP", - "base": 8388608, - "size": 2097152 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 1261568 - }, - { - "enable": 0, - "attr": "CP", - "size": 360448 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718u.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718u.json deleted file mode 100644 index 834c495..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718u.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718U", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718um.json b/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718um.json deleted file mode 100644 index af4d798..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/config/ec718um.json +++ /dev/null @@ -1,146 +0,0 @@ -{ - "TheseAreComments!":[ - {"Comment": "'capacity' in 'FotaCapability' is the largest size of all images in one fota processing (0-4MB;1-16MB)!"}, - {"Comment": "'diffMode' in 'FotaCapability' is the flag for handling compressed section(s) in binary file (0-no zip;1-has zip)!"}, - {"Comment": "'attr' in 'SysImageMem' must be set with one of these choices('BINPKG/AP/CP/APP/APP2/SYSH'), which are forbidden to be redefined!"}, - {"Comment": "'attr' in 'ExtenOtaMem' must be set with one of these choices('EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'name' in 'StorageDevice' must be set with one of these choices('AP/CP/EF/SD'), which are forbidden to be redefined!"}, - {"Comment": "'base' in 'StorageDevice' is the global unique starting address, and it can not be modified!"}, - {"Comment": "However, other fields can be redefined to whatever you want, including the name of this config file!"} - ], - "CompanyName": "EiGENCOMM", - "ProductName": "EC718UM", - "FotaCoreVer": "2.5", - "FotaCapability": { - "capacity": 0, - "diffMode": 1, - "hasPkgHlc": 1, - "metaPseg": 32, - "bkupMemSize": 98304, - "deltaMemSize": 950272, - "avlbRamSize": 196608, - "zipAlgorithm": { - "zipMeth": 0, - "bzipMode": 0 - } - }, - "HuluSuite": { - "ver": 1, - "enable": 0, - "adjust": 1, - "wkspSize": 450560 - }, - "FotaAtCmd": { - "mode": 0, - "ate": 0, - "ver": 1, - "name": "", - "pmss": 1024, - "dmwt": 300 - }, - "SysImageMem": [ - { - "attr": "BINPKG", - "addr": 0, - "size": 0 - }, - { - "attr": "AP", - "addr": 8982528, - "size": 6795264 - }, - { - "attr": "CP", - "addr": 8572928, - "size": 655360 - }, - { - "attr": "APP", - "addr": 0, - "size": 0 - }, - { - "attr": "APP2", - "addr": 0, - "size": 0 - }, - { - "attr": "SYSH", - "addr": 8392704, - "size": 4096 - } - ], - "ExtenOtaMem": [ - { - "attr": "EF", - "addr": 2147483648, - "size": 10240 - } - ], - "StorageDevice": [ - { - "name": "AP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "CP", - "base": 8388608, - "size": 8388608 - }, - { - "name": "EF", - "base": 2147483648, - "size": 8388608 - } - ], - "CustFeature": { - "BootSecurity":{ - "enable": 1, - "shaMode": 224, - "bootCombo": [ - { - "enable": 1, - "imgs": "AP,CP", - "imgh": "SYSH", - "pemUri":"" - }, - { - "enable": 0, - "imgs": "APP", - "imgh": "APP2", - "pemUri":"" - } - ] - }, - "ResizeMem": [ - { - "enable": 0, - "attr": "AP", - "size": 6868992 - }, - { - "enable": 0, - "attr": "CP", - "size": 409600 - }, - { - "enable": 0, - "attr": "APP", - "size": 0 - } - ] - }, - "MiscSetting": { - "pollRx": 30, - "filter": { - "prefix": "XPKGD,PKGFLX,EF" - }, - "debug": { - "delta": { - "patMem": 0, - "patVeri": 7 - } - } - } -} \ No newline at end of file diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/ecsecure b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/ecsecure deleted file mode 100644 index e8326a3..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/ecsecure and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/fcelf b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/fcelf deleted file mode 100644 index ca95fd8..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/posix/fcelf and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/Release_Note_Deltagen.txt b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/Release_Note_Deltagen.txt deleted file mode 100644 index 67acd6b..0000000 --- a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/Release_Note_Deltagen.txt +++ /dev/null @@ -1,7 +0,0 @@ -程序名称：Deltagen -程序版本：deltagen20221121 -deltagen20221121 -1.优化了相同块的差分包生成方式，兼容新旧bootloader 差分库。 - - - diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/deltagen.exe b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/deltagen.exe deleted file mode 100644 index 423b99c..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/deltagen.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/ecsecure.exe b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/ecsecure.exe deleted file mode 100644 index 8b960a2..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/ecsecure.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/fcelf.exe b/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/fcelf.exe deleted file mode 100644 index 0cb219a..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/dep/windows/fcelf.exe and /dev/null differ diff --git a/4G/tools/_temp/dtools/ec7xx_no_hls/ucrtbased.dll b/4G/tools/_temp/dtools/ec7xx_no_hls/ucrtbased.dll deleted file mode 100644 index 0a84948..0000000 Binary files a/4G/tools/_temp/dtools/ec7xx_no_hls/ucrtbased.dll and /dev/null differ diff --git a/4G/tools/_temp/dummy.bin b/4G/tools/_temp/dummy.bin deleted file mode 100644 index e69de29..0000000 diff --git a/4G/tools/_temp/ec_download/FlashToolCLI.exe b/4G/tools/_temp/ec_download/FlashToolCLI.exe deleted file mode 100644 index 94fab6d..0000000 Binary files a/4G/tools/_temp/ec_download/FlashToolCLI.exe and /dev/null differ diff --git a/4G/tools/_temp/ec_download/PrMgrCfg.json b/4G/tools/_temp/ec_download/PrMgrCfg.json deleted file mode 100644 index 4322ead..0000000 --- a/4G/tools/_temp/ec_download/PrMgrCfg.json +++ /dev/null @@ -1,320 +0,0 @@ -{ - "product_sets": - [ - { - "prod_name":"EC618_OLDPKG_DEFAULT", - "file_basedir_keys_back":"base_uart_config_file;base_usb_config_file;format_path", - "base_uart_config_file":"./product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_uart.baseini", - "base_usb_config_file":"./product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec618_products/618_legacy/format/format_ec618_legacy.json" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"CP", - "BASE_LNA":"0x8800000", - "BASE_SIZE":"0x100000" - } - ] - }, - { - "prod_name":"EC618_CUSTOM_TEST", - "base_uart_config_file":"./product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_uart.baseini", - "base_usb_config_file":"./product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_all.json" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"CP", - "BASE_LNA":"0x8800000", - "BASE_SIZE":"0x100000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"EC718U_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718u/format/format_ec718u.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x800000" - } - ] - }, - { - "prod_name":"EC718H_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718h/format/format_ec718h.json", - "cp_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"CP", - "BASE_LNA":"0x8000000", - "BASE_SIZE":"0x100000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - - ] - }, - { - "prod_name":"EC718P_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718p/format/format_ec718p.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"EC718S_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718s/format/format_ec718s.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x200000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - - }, - { - "prod_name":"EC718HM_PRD", - "base_uart_config_file":"./product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718m_products/ec718hm/format/format_ec718hm.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x800000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"EC718UM_PRD", - "base_uart_config_file":"./product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718m_products/ec718um/format/format_ec718um.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x800000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"EC718PM_PRD", - "base_uart_config_file":"./product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718m_products/ec718pm/format/format_ec718pm.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"EC718SM_PRD", - "base_uart_config_file":"./product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718m_products/ec718sm/format/format_ec718sm.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x200000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - - }, - { - "prod_name":"EC718SEF_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718s/format/format_ec718s.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x200000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - - }, - { - "prod_name":"EC718PEF_PRD", - "base_uart_config_file":"./product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec718_products/ec718p/format/format_ec718p.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x200000" - } - ] - }, - { - "prod_name":"EC716S_PRD", - "base_uart_config_file":"./product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec716_products/ec716s/format/format_ec716s.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x200000" - } - ] - - }, - { - "prod_name":"EC716E_PRD", - "base_uart_config_file":"./product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec716_products/ec716e/format/format_ec716e.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x400000" - }, - { - "NAME":"EF", - "BASE_LNA":"0x80000000", - "BASE_SIZE":"0x400000" - } - ] - }, - { - "prod_name":"QCX217_PRD", - "base_uart_config_file":"./product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_uart.baseini", - "base_usb_config_file":"./product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_usb.baseini", - "specific_info":{ - "format_path":"./product_sets/ec217_products/ec217/format/format_ec217.json", - "ap_flash_spec_images":"cp_system" - }, - "storage_info":[ - { - "NAME":"AP", - "BASE_LNA":"0x800000", - "BASE_SIZE":"0x800000" - } - ] - - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/agentboot_usb.bin b/4G/tools/_temp/ec_download/agentboot_usb.bin deleted file mode 100644 index cae5e0f..0000000 Binary files a/4G/tools/_temp/ec_download/agentboot_usb.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/cfg.digest b/4G/tools/_temp/ec_download/cfg.digest deleted file mode 100644 index c990a7e..0000000 --- a/4G/tools/_temp/ec_download/cfg.digest +++ /dev/null @@ -1 +0,0 @@ -丐3T鉵陔p?/2囤└蕋牳:[b} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/config_ec616.ini b/4G/tools/_temp/ec_download/config_ec616.ini deleted file mode 100644 index 6f89758..0000000 --- a/4G/tools/_temp/ec_download/config_ec616.ini +++ /dev/null @@ -1,37 +0,0 @@ -[config] -line_0_com = COM59 -agbaud = 921600 - -[agentboot] -tool_basedir = 1 -agpath =.\agentboot_ec616(s).bin - -[storage_cfg] -opt_storage_list="" -format_path=format_ec616(s).json - -;bootloader.bin file infomation -[bootloader] -blpath = .\image_ec616\bootloader.bin -blloadskip = 0 - -;system.bin file infomation -[system] -syspath = .\image_ec616\app-demo-flash.bin -sysloadskip = 0 - -;control such as reset before download -[control] -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 - -rom_version=0000000101000001 - -[flexfile0] -filepath = .\rfCaliTb_ec616\MergeRfTable.bin -burnaddr = 0x3A4000 - -[flexfile1] -filepath = .\rfCaliTb_ec616\MergeRfTable.bin -burnaddr = 0x16000 \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/config_ec616s.ini b/4G/tools/_temp/ec_download/config_ec616s.ini deleted file mode 100644 index 6a95b7b..0000000 --- a/4G/tools/_temp/ec_download/config_ec616s.ini +++ /dev/null @@ -1,42 +0,0 @@ -[config] -line_0_com = COM29 -agbaud=921600 - -;agentboot.bin file infomation -[agentboot] -tool_basedir = 1 -agpath =.\agentboot_ec616(s).bin - -;agloadskip = 0 -[storage_cfg] -opt_storage_list="" -format_path=format_ec616(s).json - -;bootloader.bin file infomation -[bootloader] -blpath = .\image_ec616s\bootloader.bin -blloadskip = 0 - -;system.bin file infomation -[system] -syspath =.\image_ec616s\app-demo-flash.bin -sysloadskip = 0 - -;control such as reset before download -[control] -detect = 2 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -rom_version= 0000000101020000 - -[flexfile0] -filepath = .\rfCaliTb_ec616s\MergeRfTable.bin -burnaddr = 0x3A4000 - -[flexfile1] -filepath = .\rfCaliTb_ec616s\MergeRfTable.bin -burnaddr = 0x16000 \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/config_ec618.ini b/4G/tools/_temp/ec_download/config_ec618.ini deleted file mode 100644 index 34897d0..0000000 --- a/4G/tools/_temp/ec_download/config_ec618.ini +++ /dev/null @@ -1,66 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 0 -filter_externcom = 1 -comment_filter = "filter for com config" - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\t1.binpkg -arg_pkg_path_val = .\t2.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -select_product_support = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = usb -selected_base_inicfg_rec = .\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_usb.baseini@hash:1ef001a607ecbba39c5f03f6c736c942e10863fb167409c2d8b606726a01bafb -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = .\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000102000000 -comment_default = "control such as reset before download" - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/config_ec618_usb.ini b/4G/tools/_temp/ec_download/config_ec618_usb.ini deleted file mode 100644 index 43c367c..0000000 --- a/4G/tools/_temp/ec_download/config_ec618_usb.ini +++ /dev/null @@ -1,63 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -;filter com config -filter_embedusb=0 -filter_externcom=1 - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -arg_pkg_path_val =.\image_ec618\pkgdir\merge.binpkg - - -;agentboot.bin file infomation -[agentboot] -tool_basedir = 1 -agpath =.\image_ec618\agentboot_usb\agentboot.bin - -[storage_cfg] -opt_storage_list="cp_flash" -format_path=format_ec618.json - -;bootloader.bin file infomation -[bootloader] -blpath = .\image_ec618\ap_bootloader.bin -blloadskip = 0 - -;system.bin file infomation -[system] -syspath =.\image_ec618\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 - -[cp_system] -cp_syspath = .\image_ec618\cp-demo-flash.bin -cp_sysloadskip = 0 - -;control such as reset before download -[control] -;detect = 1 -;reset = 2 -;atreset=at+ecrst=delay,500 -;atbaud=115200 - -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -rom_version= 0000000102000000 - -[flexfile0] -filepath = .\rfCaliTb_ec618\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - - -[flexfile1] -filepath = .\rfCaliTb_ec618\MergeRfTable.bin -burnaddr = 0xce000 -storage_type=cp_flash diff --git a/4G/tools/_temp/ec_download/config_ec626.ini b/4G/tools/_temp/ec_download/config_ec626.ini deleted file mode 100644 index 246a05f..0000000 --- a/4G/tools/_temp/ec_download/config_ec626.ini +++ /dev/null @@ -1,63 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -;filter com config -filter_embedusb=1 -filter_externcom=0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[package_info] -pkgflag = 0 -pkg_extract_exe = .\fcelf.exe -arg_pkg_path_val =.\image_ec626_fpga\pkgdir\merge.binpkg - - -;agentboot.bin file infomation -[agentboot] -tool_basedir = 1 -agpath =.\image_ec626\agentboot.bin - -[storage_cfg] -opt_storage_list="" -format_path=format_ec626.json - -;bootloader.bin file infomation -[bootloader] -blpath = .\image_ec626\bootloader.bin - -blloadskip = 0 - -;system.bin file infomation -[system] -syspath =.\image_ec626\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x1f000 - -;control such as reset before download -[control] -detect = 2 -atbaud=115200 - -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -;remap_dld_addr = 32768 -rom_version=0000000104000000 -;send and receive - - -[flexfile0] -filepath = .\rfCaliTb_ec626\MergeRfTable.bin -burnaddr = 0x1ec000 -storage_type=ap_flash - - -[flexfile1] -filepath = .\rfCaliTb_ec626\MergeRfTable.bin -burnaddr = 0x15000 -storage_type=ap_flash \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/config_pkg_product_uart.ini b/4G/tools/_temp/ec_download/config_pkg_product_uart.ini deleted file mode 100644 index 9ce936c..0000000 --- a/4G/tools/_temp/ec_download/config_pkg_product_uart.ini +++ /dev/null @@ -1,71 +0,0 @@ -[config] -line_0_com = COM14 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\temp.binpkg -arg_pkg_path_val = .\temp.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -select_product_support = 1 -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = uart -selected_base_inicfg_rec = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_uart.baseini@hash:7750549aeaff4f8dab1799ca4312cee47ae197b45cd44182a0dbc0d29443521d -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_uart\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 30 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000103010000 -trc_ser = 1 - - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/config_pkg_product_uart_org.ini b/4G/tools/_temp/ec_download/config_pkg_product_uart_org.ini deleted file mode 100644 index 9ce936c..0000000 --- a/4G/tools/_temp/ec_download/config_pkg_product_uart_org.ini +++ /dev/null @@ -1,71 +0,0 @@ -[config] -line_0_com = COM14 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\temp.binpkg -arg_pkg_path_val = .\temp.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -select_product_support = 1 -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = uart -selected_base_inicfg_rec = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_uart.baseini@hash:7750549aeaff4f8dab1799ca4312cee47ae197b45cd44182a0dbc0d29443521d -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_uart\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 30 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000103010000 -trc_ser = 1 - - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/config_pkg_product_usb.ini b/4G/tools/_temp/ec_download/config_pkg_product_usb.ini deleted file mode 100644 index 116a6f1..0000000 --- a/4G/tools/_temp/ec_download/config_pkg_product_usb.ini +++ /dev/null @@ -1,66 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 0 -filter_externcom = 1 -comment_filter = "filter for com config" - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\temp.binpkg -arg_pkg_path_val = .\temp.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -select_product_support = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = usb -selected_base_inicfg_rec = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_usb.baseini@hash:1ef001a607ecbba39c5f03f6c736c942e10863fb167409c2d8b606726a01bafb -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000103010000 -trc_ser = 1 - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/config_pkg_product_usb_org.ini b/4G/tools/_temp/ec_download/config_pkg_product_usb_org.ini deleted file mode 100644 index 116a6f1..0000000 --- a/4G/tools/_temp/ec_download/config_pkg_product_usb_org.ini +++ /dev/null @@ -1,66 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 0 -filter_externcom = 1 -comment_filter = "filter for com config" - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\temp.binpkg -arg_pkg_path_val = .\temp.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -select_product_support = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = usb -selected_base_inicfg_rec = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_usb.baseini@hash:1ef001a607ecbba39c5f03f6c736c942e10863fb167409c2d8b606726a01bafb -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = C:\Users\ivan\Documents\projects\ec616_00\release_ec616_01\jwzhuang20191121_20191031_flashtoolcli\FlashToolsEC618\FlashToolCLI_V4.1.4p01_20230825\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000103010000 -trc_ser = 1 - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/config_test.ini b/4G/tools/_temp/ec_download/config_test.ini deleted file mode 100644 index 8fc295d..0000000 --- a/4G/tools/_temp/ec_download/config_test.ini +++ /dev/null @@ -1,66 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 0 -filter_externcom = 1 -comment_filter = "filter for com config" - -[package_info] -pkgflag = 1 -pkg_extract_exe = .\fcelf.exe -pkg_bins_regen_targetdir = .\pkgimg_gen -arg_pkg_path_val_comment1 = .\t1.binpkg -arg_pkg_path_val = .\t2.binpkg -comment_inicfg_regened_state = "initial_no_change,backward_restored,forward_regened" -pkg_inicfg_regened_state = backward_restored -backward_cfg_restore_en = 1 -select_product_support = 1 -old_package_defined_product = EC618_OLDPKG_DEFAULT -selected_product = EC618_OLDPKG_DEFAULT -selected_base_inicfg_type = usb -selected_base_inicfg_rec = .\product_sets\ec618_products\618_legacy\base_config_files\config_ec618_legacy_pkg_usb.baseini@hash:1ef001a607ecbba39c5f03f6c736c942e10863fb167409c2d8b606726a01bafb -selected_xpk_prmgrcfg_rec = @hash:@SelPrd: - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin -comment_agentboot = "agentboot.bin file infomation" - -[storage_cfg] -format_path = .\product_sets\ec618_products\618_legacy\format\format_ec618_legacy.json - -[bootloader] -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr = 0x4000 -comment_default = "bootloader.bin file infomation" - -[system] -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 -comment_default = "system.bin file infomation" - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -rom_version = 0000000102000000 -comment_default = "control such as reset before download" - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type = cp_flash - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type = cp_flash - diff --git a/4G/tools/_temp/ec_download/fcelf.exe b/4G/tools/_temp/ec_download/fcelf.exe deleted file mode 100644 index cfdf29b..0000000 Binary files a/4G/tools/_temp/ec_download/fcelf.exe and /dev/null differ diff --git a/4G/tools/_temp/ec_download/fcelf_c.exe b/4G/tools/_temp/ec_download/fcelf_c.exe deleted file mode 100644 index 4a85857..0000000 Binary files a/4G/tools/_temp/ec_download/fcelf_c.exe and /dev/null differ diff --git a/4G/tools/_temp/ec_download/fcelf_ec618.exe b/4G/tools/_temp/ec_download/fcelf_ec618.exe deleted file mode 100644 index 27dab3c..0000000 Binary files a/4G/tools/_temp/ec_download/fcelf_ec618.exe and /dev/null differ diff --git a/4G/tools/_temp/ec_download/flashrbf b/4G/tools/_temp/ec_download/flashrbf deleted file mode 100644 index 18c5ecb..0000000 Binary files a/4G/tools/_temp/ec_download/flashrbf and /dev/null differ diff --git a/4G/tools/_temp/ec_download/flhtool_chinese_test.cfg b/4G/tools/_temp/ec_download/flhtool_chinese_test.cfg deleted file mode 100644 index e69de29..0000000 diff --git a/4G/tools/_temp/ec_download/image_ec618/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/image_ec618/agentboot_uart/agentboot.bin deleted file mode 100644 index 29b713e..0000000 Binary files a/4G/tools/_temp/ec_download/image_ec618/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/image_ec618/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/image_ec618/agentboot_usb/agentboot.bin deleted file mode 100644 index cae5e0f..0000000 Binary files a/4G/tools/_temp/ec_download/image_ec618/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/image_ec618/pkgdir/imagedata.json b/4G/tools/_temp/ec_download/image_ec618/pkgdir/imagedata.json deleted file mode 100644 index 2ac6be8..0000000 --- a/4G/tools/_temp/ec_download/image_ec618/pkgdir/imagedata.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "HashAlgorithm": "SHA256", - "imageinfo": [ - { - "addr": 16384, - "file": "ap_bootloader.bin", - "flashsize": 32768, - "hash": "1CC29C411DFAE044FBB68BB7E6783E9FB84F4523E589299CEE4F7ED72D8C406B", - "type": "BL" - }, - { - "addr": 147456, - "file": "ap_at_command.bin", - "flashsize": 2998272, - "hash": "EC5204C878A7315FF5B7C6847C34F508B14C9CFDB4871BD13205E8C7626ECC62", - "type": "AP" - }, - { - "addr": 0, - "file": "cp-demo-flash.bin", - "flashsize": 524288, - "hash": "2EE71BFA864F128A8264997D01B67738BE07D0ECCF6DD727A596E240B1C52C3F", - "type": "CP" - } - ], - "imagepath": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\jwzhuang20191121_20191031_flashtoolcli\\FlashToolsEC618\\FlashToolCLI_V4.1.4p01_20230825\\image_ec618\\pkgdir\\pkg_extract_tmp/", - "version": "106", - "ExtractSyncRec": { - "LastSyncTime": 1694153660, - "LastSyncStat": 1, - "PackagePath": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\jwzhuang20191121_20191031_flashtoolcli\\FlashToolsEC618\\FlashToolCLI_V4.1.4p01_20230825\\image_ec618\\pkgdir\\at_command.binpkg", - "PackageExtDir": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\jwzhuang20191121_20191031_flashtoolcli\\FlashToolsEC618\\FlashToolCLI_V4.1.4p01_20230825\\image_ec618\\pkgdir\\pkg_extract_tmp", - "PackageModTime": 1638429667, - "PackageSize": 2405258, - "PackageHash": "6cb10dbcb7333163503b9c0ef4558bbb7882851fa2df0527ff932ace6323082a" - } -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/image_ec618/pkgsingle_dir/imagedata.json b/4G/tools/_temp/ec_download/image_ec618/pkgsingle_dir/imagedata.json deleted file mode 100644 index a1c96b7..0000000 --- a/4G/tools/_temp/ec_download/image_ec618/pkgsingle_dir/imagedata.json +++ /dev/null @@ -1,69 +0,0 @@ -{ - "HashAlgorithm": "SHA256", - "imageinfo": [ - { - "addr": 0, - "file": "ban_old_tool_poison.bin", - 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-} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/image_ec718/named_product/ec718s/pkgdir/imagedata.json b/4G/tools/_temp/ec_download/image_ec718/named_product/ec718s/pkgdir/imagedata.json deleted file mode 100644 index 05fd247..0000000 --- a/4G/tools/_temp/ec_download/image_ec718/named_product/ec718s/pkgdir/imagedata.json +++ /dev/null @@ -1,48 +0,0 @@ -{ - "HashAlgorithm": "SHA256", - "imageinfo": [ - { - "addr": 0, - "file": "ban_old_tool_poison.bin", - "flashsize": 0, - "hash": "0", - "type": "VIRTUALIMG" - }, - { - "addr": 8400896, - "file": "ap_bootloader.bin", - "flashsize": 73728, - "hash": "E8B1A8A586F105818AA29E8A3CB2B4003E1658E469909A4EC431E974AFD57590", - "type": "BL" - }, - { - "addr": 8855552, - "file": "ap_at_command.bin", - "flashsize": 1261568, - "hash": "60CEEEBD6FD52FAF626315FCD6A035B9A1C2EABCBEFF420F252F4704AD510E92", - "type": "AP" - }, - { - "addr": 8495104, - "file": "cp-demo-flash.bin", - "flashsize": 360448, - "hash": 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1697308, - "PackageHash": "75d3ca8b432a035a4126f09221951d46af631a97077fb05c6962d368b95b893a" - } -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/image_ec718/named_product/ec718u/pkgdir/imagedata.json b/4G/tools/_temp/ec_download/image_ec718/named_product/ec718u/pkgdir/imagedata.json deleted file mode 100644 index 97fa0a2..0000000 --- a/4G/tools/_temp/ec_download/image_ec718/named_product/ec718u/pkgdir/imagedata.json +++ /dev/null @@ -1,48 +0,0 @@ -{ - "HashAlgorithm": "SHA256", - "imageinfo": [ - { - "addr": 0, - "file": "ban_old_tool_poison.bin", - "flashsize": 0, - "hash": "0", - "type": "VIRTUALIMG" - }, - { - "addr": 8400896, - "file": "ap_bootloader.bin", - "flashsize": 131072, - "hash": "908EB83D963318A49DF537DDAE2D18A955C25ABDB2FB6CE29CD7BD31457A74E7", - "type": "BL" - }, - { - "addr": 9494528, - "file": "ap_at_command.bin", - "flashsize": 4268032, - "hash": "6CA153E74B7B4A3A41198D9D946B7CCC312BA03A9A6C76E8C5F0D43BAFBAA422", - "type": "AP" - }, - { - "addr": 8650752, - "file": "cp-demo-flash.bin", - "flashsize": 843776, - "hash": "DC1CCB5772E0604E6B085291D8DB00CAA034E8CD15F85AD065A8863BFED0E348", - "type": "CP" - } - ], - "imagepath": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\FlashToolsRelease\\FlashTools_V4.0.10\\FlashTools_V4.1.3_20230606_p01\\image_ec718\\named_product\\ec718u\\pkgdir\\pkg_extract_tmp/", - "pkgarg": { - "pkgmode": 1, - "productname": "EC718U_PRD" - }, - "version": "111", - "ExtractSyncRec": { - "LastSyncTime": 1689229670, - "LastSyncStat": 1, - "PackagePath": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\FlashToolsRelease\\FlashTools_V4.0.10\\FlashTools_V4.1.3_20230606_p01\\image_ec718\\named_product\\ec718u\\pkgdir\\at_command.binpkg", - "PackageExtDir": "C:\\Users\\ivan\\Documents\\projects\\ec616_00\\release_ec616_01\\FlashToolsRelease\\FlashTools_V4.0.10\\FlashTools_V4.1.3_20230606_p01\\image_ec718\\named_product\\ec718u\\pkgdir\\pkg_extract_tmp", - "PackageModTime": 1686017103, - "PackageSize": 2288132, - "PackageHash": "5c872484dd5c2410f20e85fb35517b6d900b1cd566db93407f9107fe60917c7a" - } -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/logging.conf b/4G/tools/_temp/ec_download/logging.conf deleted file mode 100644 index 437f33d..0000000 --- a/4G/tools/_temp/ec_download/logging.conf +++ /dev/null @@ -1,30 +0,0 @@ -[loggers] -keys=root - -[handlers] -keys=stream_handler,file_handler - -[formatters] -keys=formatter - -[logger_root] -level=DEBUG -handlers=stream_handler,file_handler -;handlers=file_handler - -[handler_stream_handler] -class=StreamHandler -level=DEBUG -formatter=formatter -args=(sys.stderr,) - -[handler_file_handler] -class=FileHandler -level=DEBUG -formatter=formatter -args=('logging_output.log', 'a', None, True) - -[formatter_formatter] -format=%(asctime)s %(levelname)-8s %(message)s -;format=%(asctime)s %(levelname)-8s %(funcName)s %(lineno)s %(message)s - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index 0e1dd1d..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_usb/agentboot.bin deleted file mode 100644 index 39dc9de..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/common_data/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini deleted file mode 100644 index 35c997d..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini +++ /dev/null @@ -1,51 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718h\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini deleted file mode 100644 index 89bc561..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini +++ /dev/null @@ -1,47 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 - -dribble_dld_en=0 -[flexfile0] -filepath = .\product_sets\ec718_products\ec718h\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/format/format_ec718h.json b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/format/format_ec718h.json deleted file mode 100644 index f79e6f3..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/format/format_ec718h.json +++ /dev/null @@ -1,60 +0,0 @@ -{ - "fs": { - "begin":"0xb88000", - "length":"294912" - }, - "fraw": { - "begin":"0xbfc000", - "length":"16384" - }, - "rr": { - "begin":"0x88e7000", - "length":"102400" - }, - "drr": { - "begin":"0x8900000", - "length":"102400" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0xe7000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x27000", - "length":"0x3b9000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3e4000", - "length":"0x1c000" - }, - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0xcd000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/layout_718h_rev1601_2023-04-21_102933.png b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/layout_718h_rev1601_2023-04-21_102933.png deleted file mode 100644 index 7663814..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/layout_718h_rev1601_2023-04-21_102933.png and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index 7cf53e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/718p_rev1601_2023-04-21_110456.png b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/718p_rev1601_2023-04-21_110456.png deleted file mode 100644 index 44dc3e2..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/718p_rev1601_2023-04-21_110456.png and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini deleted file mode 100644 index 16c7c10..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718p\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini deleted file mode 100644 index 1838d67..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini +++ /dev/null @@ -1,46 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x3000 -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x7c000 - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x18000 - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 - -dribble_dld_en=0 -[flexfile0] -filepath = .\product_sets\ec718_products\ec718p\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/format/format_ec718p.json b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/format/format_ec718p.json deleted file mode 100644 index f6fc67e..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718p/format/format_ec718p.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xbc9000", - "length":"65536" - }, - "fraw": { - "begin":"0xbfe000", - "length":"8192" - }, - "rr": { - "begin":"0xbf2000", - "length":"49152" - }, - "drr": { - "begin":"0x813000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3f2000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x13000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x18000", - "length":"0x3d9000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/718s_rev1601_2023-04-21_111045.png b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/718s_rev1601_2023-04-21_111045.png deleted file mode 100644 index 2925644..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/718s_rev1601_2023-04-21_111045.png and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini deleted file mode 100644 index b68ced3..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x3000 -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x86000 - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x20000 - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\rfCaliTb_ec619\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini deleted file mode 100644 index fe618bb..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini +++ /dev/null @@ -1,46 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x3000 -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x86000 - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x20000 - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 - -dribble_dld_en=0 -[flexfile0] -filepath = .\rfCaliTb_ec619\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/format/format_ec718s.json b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/format/format_ec718s.json deleted file mode 100644 index 4eeee8c..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/format/format_ec718s.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0x9e2000", - "length":"65536" - }, - "fraw": { - "begin":"0x9ff000", - "length":"4096" - }, - "rr": { - "begin":"0x9f2000", - "length":"53248" - }, - "drr": { - "begin":"0x813000", - "length":"53248" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"2097152" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1f3000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x13000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x20000", - "length":"0x1d2000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1ff000", - "length":"0x1000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index a0754e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/718s_trunk_rev13980鈥斺2023-04-24_173313.png b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/718s_trunk_rev13980鈥斺2023-04-24_173313.png deleted file mode 100644 index e354305..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/718s_trunk_rev13980鈥斺2023-04-24_173313.png and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_uart.baseini deleted file mode 100644 index a257b64..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_uart.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_usb.baseini deleted file mode 100644 index 67f02a5..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/base_config_files/config_ec718s_prd_usb.baseini +++ /dev/null @@ -1,46 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 - -dribble_dld_en=0 -[flexfile0] -filepath = .\product_sets\ec718_products\ec718s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/format/format_ec718s.json b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/format/format_ec718s.json deleted file mode 100644 index 13a84fa..0000000 --- a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/format/format_ec718s.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0x9e2000", - "length":"65536" - }, - "fraw": { - "begin":"0x9ff000", - "length":"4096" - }, - "rr": { - "begin":"0x9f3000", - "length":"49152" - }, - "drr": { - "begin":"0x813000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"2097152" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1f3000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x13000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x18000", - "length":"0x1da000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1ff000", - "length":"0x1000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index a0754e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/20230420_rev1601_update/ec718_products/ec718s_trunk/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index c3c453f..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin_pubkey64 b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin_pubkey64 deleted file mode 100644 index 50f26bc..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot.bin_pubkey64 and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_fusemirror/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_fusemirror/agentboot.bin deleted file mode 100644 index 8be52ee..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_fusemirror/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_small_case_1_3.bin b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_small_case_1_3.bin deleted file mode 100644 index b1ea779..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_small_case_1_3.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_update20221202/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_update20221202/agentboot.bin deleted file mode 100644 index aff439b..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_update20221202/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_uart/agentboot_update20221202/agentboot_update_record.txt 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b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_usb/agentboot_large.bin deleted file mode 100644 index 268b9bc..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_usb/agentboot_large.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_usb/agentboot_rev135.bin b/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_usb/agentboot_rev135.bin deleted file mode 100644 index ab0eb89..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec217_products/common_data/agentboot_usb/agentboot_rev135.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_uart.baseini deleted file mode 100644 index f233934..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_uart.baseini +++ /dev/null @@ -1,52 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 -filter_explicitcom2 =17D1 -embedusb_hwid_list=05C6:9330 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec217_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\empty.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\empty.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\empty.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103020000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec217_products\ec217\rfCaliTb\MergeRfTable.bin -burnaddr = 0x74b000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_usb.baseini deleted file mode 100644 index db17738..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/base_config_files/config_ec217_prd_usb.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -;baud=130000 -filter_embedusb=0 -filter_externcom=1 -embedusb_hwid_list=05C6:9330 - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec217_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\empty.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\empty.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\empty.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103020000 - -;dld_upg_ctrl_valid=1 -;dld_upg_connwait_100ms_cnt=50 -;dld_upg_ctrlwait_100ms_cnt=100 - -[flexfile0] -filepath = .\product_sets\ec217_products\ec217\rfCaliTb\MergeRfTable.bin -burnaddr = 0x74b000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/format/format_ec217.json b/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/format/format_ec217.json deleted file mode 100644 index 0103813..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec217_products/ec217/format/format_ec217.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xe20000", - "length":"1142784" - }, - "fraw": { - "begin":"0xf7c000", - "length":"16384" - }, - "rr": { - "begin":"0xf4b000", - "length":"102400" - }, - "drr": { - "begin":"0x827000", - "length":"102400" - }, - "hfd": { - "begin":"0xf80000", - "length":"524288" - }, - "opt": { - "begin":"0x0800000", - "length":"8388608" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x74b000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x40000", - "length":"0x6f7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x764000", - "length":"0x9c000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_uart.baseini deleted file mode 100644 index 87daf8e..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_uart.baseini +++ /dev/null @@ -1,61 +0,0 @@ -[config] -line_0_com = COM14 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 - - - -[agentboot] -comment_agentboot = "agentboot.bin file infomation" -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -format_path = format_ec618_none.json - -[bootloader] -comment_default="bootloader.bin file infomation" -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x4000 - -;system.bin file infomation -[system] -comment_default="system.bin file infomation" -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -;control such as reset before download -[control] -comment_default="control such as reset before download" -detect = 2 -reset = 2 -atreset=at+ecrst=delay,600 -atbaud=115200 - -prempt_detect_time = 30 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -;remap_dld_addr = 32768 -rom_version= 0000000102000000 - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type=cp_flash \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_usb.baseini deleted file mode 100644 index 7f65a06..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/base_config_files/config_ec618_legacy_pkg_usb.baseini +++ /dev/null @@ -1,59 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -;filter com config -comment_filter= "filter for com config" -filter_embedusb=0 -filter_externcom=1 - - -;agentboot.bin file infomation -[agentboot] -comment_agentboot="agentboot.bin file infomation" -tool_basedir = 1 -agpath =.\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -format_path = format_ec618_none.json - -[bootloader] -comment_default="bootloader.bin file infomation" -blpath = .\image_ec618\legacy_product\618_legacy\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x4000 - -;system.bin file infomation -[system] -comment_default="system.bin file infomation" -syspath = .\image_ec618\legacy_product\618_legacy\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 - -[cp_system] -cp_syspath = .\image_ec618\legacy_product\618_legacy\cp-demo-flash.bin -cp_sysloadskip = 0 - -;control such as reset before download -[control] -comment_default="control such as reset before download" - -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -;remap_dld_addr = 32768 -rom_version= 0000000102000000 - -[flexfile0] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - - -[flexfile1] -filepath = .\product_sets\ec618_products\618_legacy\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type=cp_flash \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/format/format_ec618_legacy.json b/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/format/format_ec618_legacy.json deleted file mode 100644 index 14ca1b8..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/format/format_ec618_legacy.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xb84000", - "length":"294912" - }, - "fraw": { - "begin":"0xbfc000", - "length":"4096" - }, - "rr": { - "begin":"0x88e7000", - "length":"102400" - }, - "drr": { - "begin":"0x88ce000", - "length":"102400" - }, - "hfd": { - "begin":"0x8880000", - "length":"315392" - }, - "opt": { - "begin":"0x00824000", - "length":"2048000" - }, - "cal":[ - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0xe7000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x3cc000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3e4000", - "length":"0x1c000" - }, - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0xcd000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index b83a329..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin deleted file mode 100644 index b83a329..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/618_legacy/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index 29b713e..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_usb/agentboot.bin deleted file mode 100644 index cae5e0f..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/common_data/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_uart.baseini deleted file mode 100644 index a1c385b..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_uart.baseini +++ /dev/null @@ -1,64 +0,0 @@ -[config] -line_0_com = COM14 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 - - - -[agentboot] -comment_agentboot = "agentboot.bin file infomation" -tool_basedir = 1 -agpath = .\product_sets\ec618_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -format_path = format_ec618_none.json - -[bootloader] -comment_default="bootloader.bin file infomation" -blpath = .\image_ec618\named_product\ec618_custom_test\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x4000 - -;system.bin file infomation -[system] -comment_default="system.bin file infomation" -syspath = .\image_ec618\named_product\ec618_custom_test\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 - -[cp_system] -cp_syspath = .\image_ec618\named_product\ec618_custom_test\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x0 - -;control such as reset before download -[control] -comment_default="control such as reset before download" -detect = 1 -reset = 2 -atreset=at+ecrst=delay,600 -atbaud=115200 - -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -;remap_dld_addr = 32768 -rom_version= 0000000102000000 -auto_disconnect = reset,poweroff -automode_not_support = 1 - -[flexfile0] -filepath = .\product_sets\ec618_products\ec618_custom_test\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - - -[flexfile1] -filepath = .\product_sets\ec618_products\ec618_custom_test\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type=cp_flash \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_usb.baseini deleted file mode 100644 index 740bd2f..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/base_config_files/config_ec618_custom_test_pkg_usb.baseini +++ /dev/null @@ -1,62 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -;filter com config -comment_filter= "filter for com config" -filter_embedusb=0 -filter_externcom=1 - - -;agentboot.bin file infomation -[agentboot] -comment_agentboot="agentboot.bin file infomation" -tool_basedir = 1 -agpath =.\product_sets\ec618_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -format_path = format_ec618_none.json - -[bootloader] -comment_default="bootloader.bin file infomation" -blpath = .\image_ec618\named_product\ec618_custom_test\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x4000 - -;system.bin file infomation -[system] -comment_default="system.bin file infomation" -syspath = .\image_ec618\named_product\ec618_custom_test\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x24000 - -[cp_system] -cp_syspath = .\image_ec618\named_product\ec618_custom_test\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x0 - -;control such as reset before download -[control] -comment_default="control such as reset before download" - -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -;remap_dld_addr = 32768 -rom_version= 0000000102000000 -;auto_disconnect = reset,poweroff -auto_disconnect =none,poweroff - -[flexfile0] -filepath = .\product_sets\ec618_products\ec618_custom_test\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - - -[flexfile1] -filepath = .\product_sets\ec618_products\ec618_custom_test\rfCaliTb\MergeRfTable.bin -burnaddr = 0xce000 -storage_type=cp_flash \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_all.json b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_all.json deleted file mode 100644 index 049c559..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_all.json +++ /dev/null @@ -1,48 +0,0 @@ -{ - "fs": { - "begin":"0xb84000", - "length":"294912" - }, - "fraw": { - "begin":"0xbfc000", - "length":"4096" - }, - "rr": { - "begin":"0x88e7000", - "length":"102400" - }, - "drr": { - "begin":"0x88ce000", - "length":"102400" - }, - "hfd": { - "begin":"0x8880000", - "length":"315392" - }, - "opt": { - "begin":"0x00824000", - "length":"2048000" - }, - "cal":[ - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0xe7000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x400000" - }, - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x100000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_upgrade.json b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_upgrade.json deleted file mode 100644 index 14ca1b8..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/format/format_ec618_custom_test_upgrade.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xb84000", - "length":"294912" - }, - "fraw": { - "begin":"0xbfc000", - "length":"4096" - }, - "rr": { - "begin":"0x88e7000", - "length":"102400" - }, - "drr": { - "begin":"0x88ce000", - "length":"102400" - }, - "hfd": { - "begin":"0x8880000", - "length":"315392" - }, - "opt": { - "begin":"0x00824000", - "length":"2048000" - }, - "cal":[ - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0xe7000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x3cc000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3e4000", - "length":"0x1c000" - }, - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0xcd000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index b83a329..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin b/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin deleted file mode 100644 index b83a329..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec618_products/ec618_custom_test/rfCaliTb/SYS_EVB_NZ5627E_NZ5708SQ_v22a - 鍓湰.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index 8504810..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot_26M.bin b/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot_26M.bin deleted file mode 100644 index 41c0386..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_uart/agentboot_26M.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_usb/agentboot.bin deleted file mode 100644 index 79360f7..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec716_products/common_data/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_uart.baseini deleted file mode 100644 index 28bcded..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_uart.baseini +++ /dev/null @@ -1,52 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec716_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec716_none.json - - -[bootloader] -blpath = .\image_ec716\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec716\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec716\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 30 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103010000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec716_products\ec716e\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_usb.baseini deleted file mode 100644 index 8f88ab7..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/base_config_files/config_ec716e_prd_usb.baseini +++ /dev/null @@ -1,58 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec716_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec716_none.json - -[bootloader] -blpath = .\image_ec716\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec716\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec716\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103010000 -;assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 -;io_vol_18_or_33 = 1 -;ext_flash_pwrctl_need = 1 -;ext_flash_pwrctl_gpio = 35 -;ext_flash_pwrctl_dly = 2 - -[flexfile0] -filepath = .\product_sets\ec716_products\ec716e\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/format/format_ec716e.json b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/format/format_ec716e.json deleted file mode 100644 index 135a026..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716e/format/format_ec716e.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xba1000", - "length":"49152" - }, - "fraw": { - "begin":"0xbfe000", - "length":"8192" - }, - "rr": { - "begin":"0xbf2000", - "length":"49152" - }, - "drr": { - "begin":"0x815000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3f2000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x15000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1a000", - "length":"0x3d7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_uart.baseini deleted file mode 100644 index 9d76ed6..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_uart.baseini +++ /dev/null @@ -1,55 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec716_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec716_none.json - - -[bootloader] -blpath = .\image_ec716\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec716\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec716\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103010000 -dribble_dld_en = 1 - -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - - -[flexfile0] -filepath = .\product_sets\ec716_products\ec716s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_usb.baseini deleted file mode 100644 index fd2af42..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/base_config_files/config_ec716s_prd_usb.baseini +++ /dev/null @@ -1,55 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -;baud=130000 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec716_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec716_none.json - -[bootloader] -blpath = .\image_ec716\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec716\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec716\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103010000 - -;dld_upg_ctrl_valid=1 -;dld_upg_connwait_100ms_cnt=50 -;dld_upg_ctrlwait_100ms_cnt=100 - -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - - -[flexfile0] -filepath = .\product_sets\ec716_products\ec716s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/format/format_ec716s.json b/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/format/format_ec716s.json deleted file mode 100644 index eff7308..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec716_products/ec716s/format/format_ec716s.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0x9a6000", - "length":"49152" - }, - "fraw": { - "begin":"0x9ff000", - "length":"4096" - }, - "rr": { - "begin":"0x9f3000", - "length":"49152" - }, - "drr": { - "begin":"0x815000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"2097152" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1f3000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x15000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1a000", - "length":"0x1d8000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1ff000", - "length":"0x1000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index 9523deb..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_26M b/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_26M deleted file mode 100644 index d779b13..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_26M and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_XINKAI_TIMING_READ_DATAERR b/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_XINKAI_TIMING_READ_DATAERR deleted file mode 100644 index dd36b3f..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_uart/agentboot.bin_XINKAI_TIMING_READ_DATAERR and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_usb/agentboot.bin deleted file mode 100644 index 767569f..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/common_data/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini deleted file mode 100644 index 5555be9..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_uart.baseini +++ /dev/null @@ -1,51 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718h\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini deleted file mode 100644 index 396ffa0..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/base_config_files/config_ec718h_prd_usb.baseini +++ /dev/null @@ -1,49 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 -assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -[flexfile0] -filepath = .\product_sets\ec718_products\ec718h\rfCaliTb\MergeRfTable.bin -burnaddr = 0xe7000 -storage_type=cp_flash - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/format/format_ec718h.json b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/format/format_ec718h.json deleted file mode 100644 index 8236dc3..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/format/format_ec718h.json +++ /dev/null @@ -1,60 +0,0 @@ -{ - "fs": { - "begin":"0xb88000", - "length":"294912" - }, - "fraw": { - "begin":"0xbfc000", - "length":"16384" - }, - "rr": { - "begin":"0x80e7000", - "length":"102400" - }, - "drr": { - "begin":"0x80ce000", - "length":"102400" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0xe7000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x27000", - "length":"0x3b9000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3e4000", - "length":"0x1c000" - }, - { - "stor_type": "cp_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0xcd000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index 7cf53e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718h/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini deleted file mode 100644 index 0bf4050..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_uart.baseini +++ /dev/null @@ -1,53 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718p\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini deleted file mode 100644 index bdc905c..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/base_config_files/config_ec718p_prd_usb.baseini +++ /dev/null @@ -1,53 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0x3000 -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0x7c000 - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0x18000 - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 -assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718p\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/format/format_ec718p.json b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/format/format_ec718p.json deleted file mode 100644 index 135a026..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718p/format/format_ec718p.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xba1000", - "length":"49152" - }, - "fraw": { - "begin":"0xbfe000", - "length":"8192" - }, - "rr": { - "begin":"0xbf2000", - "length":"49152" - }, - "drr": { - "begin":"0x815000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3f2000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x15000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1a000", - "length":"0x3d7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini deleted file mode 100644 index 45b4ee4..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_uart.baseini +++ /dev/null @@ -1,54 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini deleted file mode 100644 index c501ae3..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/base_config_files/config_ec718s_prd_usb.baseini +++ /dev/null @@ -1,55 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 -assist_second_port_cmd=at+ecrst=delay,599 -;dld_upg_ctrl_valid=1 -;dld_upg_connwait_100ms_cnt=50 -;dld_upg_ctrlwait_100ms_cnt=100 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718s\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/format/format_ec718s.json b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/format/format_ec718s.json deleted file mode 100644 index eff7308..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/format/format_ec718s.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0x9a6000", - "length":"49152" - }, - "fraw": { - "begin":"0x9ff000", - "length":"4096" - }, - "rr": { - "begin":"0x9f3000", - "length":"49152" - }, - "drr": { - "begin":"0x815000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"2097152" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1f3000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x15000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1a000", - "length":"0x1d8000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1ff000", - "length":"0x1000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index a0754e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718s/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_uart.baseini deleted file mode 100644 index 4984463..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_uart.baseini +++ /dev/null @@ -1,54 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 2000000 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,600 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000203000000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718u\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_usb.baseini deleted file mode 100644 index ac7390e..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/base_config_files/config_ec718u_prd_usb.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000203000000 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718u\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/format/format_ec718u.json b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/format/format_ec718u.json deleted file mode 100644 index b9b8315..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/format/format_ec718u.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xf24000", - "length":"262144" - }, - "fraw": { - "begin":"0xffe000", - "length":"8192" - }, - "rr": { - "begin":"0xfe5000", - "length":"102400" - }, - "drr": { - "begin":"0x823000", - "length":"40960" - }, - "hfd": { - "begin":"0x0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"8388608" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7E5000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x2D000", - "length":"0x7B7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/rfCaliTb/MergeRfTable.bin b/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/rfCaliTb/MergeRfTable.bin deleted file mode 100644 index 7cf53e8..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718_products/ec718u/rfCaliTb/MergeRfTable.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_uart/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_uart/agentboot.bin deleted file mode 100644 index 69af286..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_uart/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_usb/agentboot.bin b/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_usb/agentboot.bin deleted file mode 100644 index 48067fc..0000000 Binary files a/4G/tools/_temp/ec_download/product_sets/ec718m_products/common_data/agentboot_usb/agentboot.bin and /dev/null differ diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_uart.baseini deleted file mode 100644 index ca4ca65..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_uart.baseini +++ /dev/null @@ -1,53 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,650 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103030000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718um\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_usb.baseini deleted file mode 100644 index 2bd5a84..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/base_config_files/config_ec718hm_prd_usb.baseini +++ /dev/null @@ -1,57 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103030000 -assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 -;io_vol_18_or_33 = 1 -;ext_flash_pwrctl_need = 1 -;ext_flash_pwrctl_gpio = 35 -;ext_flash_pwrctl_dly = 2 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718um\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/format/format_ec718hm.json b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/format/format_ec718hm.json deleted file mode 100644 index b9b8315..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718hm/format/format_ec718hm.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xf24000", - "length":"262144" - }, - "fraw": { - "begin":"0xffe000", - "length":"8192" - }, - "rr": { - "begin":"0xfe5000", - "length":"102400" - }, - "drr": { - "begin":"0x823000", - "length":"40960" - }, - "hfd": { - "begin":"0x0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"8388608" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7E5000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x2D000", - "length":"0x7B7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_uart.baseini deleted file mode 100644 index 1925c67..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_uart.baseini +++ /dev/null @@ -1,53 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,650 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103030000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718m_products\ec718pm\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_usb.baseini deleted file mode 100644 index ee75918..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/base_config_files/config_ec718pm_prd_usb.baseini +++ /dev/null @@ -1,58 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 - -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103030000 -assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 -;io_vol_18_or_33 = 1 -;ext_flash_pwrctl_need = 1 -;ext_flash_pwrctl_gpio = 35 -;ext_flash_pwrctl_dly = 2 - -[flexfile0] -filepath = .\product_sets\ec718m_products\ec718pm\rfCaliTb\MergeRfTable.bin -burnaddr = 0x3f2000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/format/format_ec718pm.json b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/format/format_ec718pm.json deleted file mode 100644 index b3fa7ea..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718pm/format/format_ec718pm.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xba1000", - "length":"49152" - }, - "fraw": { - "begin":"0xbfe000", - "length":"8192" - }, - "rr": { - "begin":"0xbf2000", - "length":"49152" - }, - "drr": { - "begin":"0x819000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"4194304" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3f2000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x19000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1e000", - "length":"0x3d3000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x3fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_uart.baseini deleted file mode 100644 index 7d78712..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_uart.baseini +++ /dev/null @@ -1,50 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 1 -reset = 2 -atreset = at+ecrst=delay,650 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103030000 -dribble_dld_en = 1 - -[flexfile0] -filepath = .\product_sets\ec718m_products\ec718sm\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_usb.baseini deleted file mode 100644 index 6225744..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/base_config_files/config_ec718sm_prd_usb.baseini +++ /dev/null @@ -1,61 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103030000 -assist_second_port_cmd=at+ecrst=delay,599 -;dld_upg_ctrl_valid=1 -;dld_upg_connwait_100ms_cnt=5 -;dld_upg_ctrlwait_100ms_cnt=10 - -;pr_runtime_ctrl_en = 1 -;chip_ctl_para_en = 0 -;board_ctl_para_en = 1 -;verify_flash_size_need = 1 -;io_vol_18_or_33 = 1 -;ext_flash_pwrctl_need = 1 -;ext_flash_pwrctl_gpio = 35 -;ext_flash_pwrctl_dly = 2 - -[flexfile0] -filepath = .\product_sets\ec718m_products\ec718sm\rfCaliTb\MergeRfTable.bin -burnaddr = 0x1f3000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/format/format_ec718sm.json b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/format/format_ec718sm.json deleted file mode 100644 index eff7308..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718sm/format/format_ec718sm.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0x9a6000", - "length":"49152" - }, - "fraw": { - "begin":"0x9ff000", - "length":"4096" - }, - "rr": { - "begin":"0x9f3000", - "length":"49152" - }, - "drr": { - "begin":"0x815000", - "length":"20480" - }, - "hfd": { - "begin":"0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"2097152" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1f3000", - "length":"0xc000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x15000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1a000", - "length":"0x1d8000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x1ff000", - "length":"0x1000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_uart.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_uart.baseini deleted file mode 100644 index ca4ca65..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_uart.baseini +++ /dev/null @@ -1,53 +0,0 @@ -[config] -line_0_com = COM9 -agbaud = 921600 -filter_embedusb = 1 -filter_externcom = 0 -filter_explicitcom0 = 19D1 -filter_explicitcom1 = 1366 - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_uart\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -detect = 2 -reset = 2 -atreset = at+ecrst=delay,650 -atbaud = 115200 -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -pullup_qspi = 1 -trc_ser = 1 -rom_version= 0000000103030000 -dribble_dld_en = 1 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -verify_flash_size_need = 1 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718um\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_usb.baseini b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_usb.baseini deleted file mode 100644 index 2bd5a84..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/base_config_files/config_ec718um_prd_usb.baseini +++ /dev/null @@ -1,57 +0,0 @@ -[config] -line_0_com = COM9 -agbaud=921600 -filter_embedusb=0 -filter_externcom=1 -line_0_snd_ass_com=COM65535 -baud=130000 - - - -[agentboot] -tool_basedir = 1 -agpath = .\product_sets\ec718m_products\common_data\agentboot_usb\agentboot.bin - -[storage_cfg] -#will be update when load -format_path = format_ec718m_none.json - -[bootloader] -blpath = .\image_ec619\ap_bootloader.bin -blloadskip = 0 -burnaddr=0xf -;system.bin file infomation -[system] -syspath =.\image_ec619\ap_demo-flash.bin -sysloadskip = 0 -burnaddr = 0xf - -[cp_system] -cp_syspath = .\image_ec619\cp-demo-flash.bin -cp_sysloadskip = 0 -burnaddr = 0xf - -[control] -prempt_detect_time = 6 -msg_waittime = 2 -max_preamble_cnt = 8 -lpc_recover_en = 0 -;cfg reset to 2, skip reset pin -pullup_qspi =1 -trc_ser= 1 -rom_version= 0000000103030000 -assist_second_port_cmd=at+ecrst=delay,599 -dribble_dld_en=0 -pr_runtime_ctrl_en = 1 -chip_ctl_para_en = 1 -;board_ctl_para_en = 1 -verify_flash_size_need = 1 -;io_vol_18_or_33 = 1 -;ext_flash_pwrctl_need = 1 -;ext_flash_pwrctl_gpio = 35 -;ext_flash_pwrctl_dly = 2 - -[flexfile0] -filepath = .\product_sets\ec718_products\ec718um\rfCaliTb\MergeRfTable.bin -burnaddr = 0x7E5000 - diff --git a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/format/format_ec718um.json b/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/format/format_ec718um.json deleted file mode 100644 index b9b8315..0000000 --- a/4G/tools/_temp/ec_download/product_sets/ec718m_products/ec718um/format/format_ec718um.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "fs": { - "begin":"0xf24000", - "length":"262144" - }, - "fraw": { - "begin":"0xffe000", - "length":"8192" - }, - "rr": { - "begin":"0xfe5000", - "length":"102400" - }, - "drr": { - "begin":"0x823000", - "length":"40960" - }, - "hfd": { - "begin":"0x0", - "length":"0" - }, - "opt": { - "begin":"0x0800000", - "length":"8388608" - }, - "cal":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7E5000", - "length":"0x19000" - } - ], - "erallum":[ - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x0", - "length":"0x23000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x2D000", - "length":"0x7B7000" - }, - { - "stor_type": "ap_flash", - "offst_flag": "1", - "begin":"0x7fe000", - "length":"0x2000" - } - ] -} \ No newline at end of file diff --git a/4G/tools/_temp/tools/Qt5Core.dll b/4G/tools/_temp/tools/Qt5Core.dll deleted file mode 100644 index 652e18c..0000000 Binary files a/4G/tools/_temp/tools/Qt5Core.dll and /dev/null differ diff --git a/4G/tools/_temp/tools/Qt5Network.dll b/4G/tools/_temp/tools/Qt5Network.dll deleted file mode 100644 index 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a/4G/tools/_temp/uis_download/BMAConfig.xml b/4G/tools/_temp/uis_download/BMAConfig.xml deleted file mode 100644 index af3bde7..0000000 --- a/4G/tools/_temp/uis_download/BMAConfig.xml +++ /dev/null @@ -1,421 +0,0 @@ - - - - - - - - - - - - - - - - SC8800G - 1 - 0 - 0 - 1 - 1 - 1 - 1 - - - 0xFFFFFFFF - - - - - - - 0xFFFFFFFF - - - - - - 0xFFFFFFFF - - - - - - - 0x191 - - - - - - 0x199 - - - - - - 0xD - - - - - - 0x19A - - - - - - - - - NOR_FLASH_6600L - 0 - 0 - - - 0xFFFFFFFF - - - - - - - 0xFFFFFFFF - - - - - - 0x191 - - - - - - 0xD - - - - - - 0x19A - - - - - - 0x199 - - - - - - - - - - - - - - - - FDL - NOR_FDL - FDL - - 0x34000000 - 0x0 - - 1 - 1 - Nor flash download image file - - - NV - NV - NV - - 0x90000001 - 0x0 - - 1 - 0 - Download-NV image file - - - PS - PS - CODE - - 0x80000003 - 0x0 - - 1 - 0 - Protocol station image file - - - MMIRes - MMIRES - CODE - - 0x90000004 - 0x0 - - 1 - 2 - MMI resource image file - - - EraseUdisk - ERASE_UDISK - EraseFlash - - 0x90000005 - - 0x0 - - 0 - 2 - Erase NOR-UDisk section, depended on costomer's need - - - UDISK - UDISK_IMG - CODE - - 0x90000006 - 0x0 - - 1 - 2 - UDisk image file, depended on costomer's need - - - FLASH - FLASH - EraseFlash - - 0x90000003 - 0xC0000 - - 0 - 0 - Erase running-NV section operation - - - PhaseCheck - PHASE_CHECK - CODE - - 0x90000002 - 0x0 - - 0 - 0 - Producing phases information section - - - - - FDL - FDL1 - FDL - - 0x40000000 - 0x0 - - 1 - 1 - First nand flash download image file - - - FDL2 - FDL2 - NAND_FDL - - 0x30000000 - 0x0 - - 1 - 1 - Second nand flash download image file - - - NV - NV - NV_NAND - - 0x90000001 - 0x0 - - - 0x9000000C - 0x0 - - 1 - 0 - Download-NV image file - - - BootLoader - BOOT_LOADER - BOOT_LOADER - - 0x80000000 - 0x0 - - 1 - 0 - Bootloader image file - - - KernelImg2 - KERNEL_IMG2 - CODE - - 0x9000000D - 0x0 - - 1 - 2 - Second Kernel image file - - - UserImg - USER_IMG - CODE - - 0x80000004 - 0x0 - - 1 - 0 - User image file - - - MMIRes - MMIRES - CODE - - 0x90000004 - 0x0 - - 1 - 0 - MMI resource image file - - - SPLOAD - SPLOAD_IMG - CODE - - 0x90000010 - 0x0 - - 1 - 2 - LCD and Sensor image file, depended on customer's need - - - DSPCode - DSP_CODE - CODE - - 0x90000005 - 0x0 - - 1 - 0 - DSP code image file - - - OmadmFota - OMADM_FOTA - CODE - - 0x90000008 - 0x0 - - 1 - 2 - Device management upgrade imgage file, depended on FDL2 - - - Preload - PRELOAD - CODE - - 0x90000007 - 0x0 - - 1 - 2 - Hiden image file, depended on FDL2 - - - RomDisk - ROM_DISK - CODE - - 0x9000000E - 0x0 - - 1 - 2 - Be used to drivers auto run, depended on FDL2 - - - FLASH - FLASH - EraseFlash - - 0x90000003 - 0x4000 - - 0 - 0 - Erase running-NV section operation - - - EraseDU - ERASE_DU - EraseFlash - - 0x9000000A - 0x140000 - - 0 - 2 - Erase delta-package section operation, depended on FDL2 - - - PhaseCheck - PHASE_CHECK - CODE - - 0x90000002 - 0x0 - - 0 - 0 - Producing phases information section - - - KernelImg - KERNEL_IMG - MasterImage - - 0x80000003 - 0x0 - - 1 - 0 - Kernel image file - - - - diff --git a/4G/tools/_temp/uis_download/BMAFrame9.dll b/4G/tools/_temp/uis_download/BMAFrame9.dll deleted file mode 100644 index f464733..0000000 Binary files a/4G/tools/_temp/uis_download/BMAFrame9.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/BMError.ini b/4G/tools/_temp/uis_download/BMError.ini deleted file mode 100644 index ef3c021..0000000 --- a/4G/tools/_temp/uis_download/BMError.ini +++ /dev/null @@ -1,71 +0,0 @@ -[ErrorDescription] -130=[DL1130]Invalid command -131=[DL1131]Unknown command -132=[UB1132]Operation failed -133=[DL1133]Not support this baudrate -134=[DL1134]Download not started -135=[DL1135]Download multi-started -136=[DL1136]Download early end -137=[DL1137]Download destination error -138=[DL1138]Image size is over its partition -139=[DL1139]Verify error -140=[UB1140]Not verify -141=[UB1141]Not enough memory -142=[UB1142]Wait input time out -145=[UB1145]Repeat continue -146=[UB1146]Repeat break -150=[DL1150]Incompatible partition -151=[UB1151]Unknow device -152=[UB1152]Invalid device size -153=[UB1153]Illegal SDRAM -160=[SW1160]Fixed NV checksum error,cannot be equal with zero -161=[UB1161]Flash checksum failed -162=[UB1162]Write flash failed -163=[UB1163]Chip ID not match -164=[UB1164]Flash configure error -165=[UB1165]STL size error -166=[UB1166]Security verification fail -167=[UB1167]Phone has been rooted -168=[UB1168]Don't support to lock sim -169=[UB1169]Don't support to unlock sim -170=[UB1170]Security data verify error -172=[UB1172]Not enabled write flash -173=[UB1173]Failure to enable secure boot -179=[UB1179]Flash written protection -180=[UB1180]Flash initializing failed -182=[UB1182]DDR check failed -183=[UB1183]Self refresh failed -185=[DL1185]Download Failed -208=[DL1208]Magic Check Failed -209=[DL1209]Repartition Failed -210=[DL1210]Read Flash Failed -211=[DL1211]Malloc Failed -254=[UB1254]Software has not supported this feature -257=[PS2257]Uart send error -258=[UB2258]Decode or verify received buffer error -259=[UB2259]Received buffer is not in the format we want -260=[UB2260]Read error -261=[PS2261]Too much data -262=[PS2262]User cancel -263=[PS2263]Startdata size is zero -264=[PS2264]Open port fail -265=Second Hand Memory : [SW2265]Register modified. Please stop using this memory! -266=Second Hand Memory : [SW2266]EMMC Partition done. Please stop using this memory! -267=Second Hand Memory : [SW2267]RPMB written. Please stop using this memory! -268=Second Hand Memory : [SW2268]Register modified & EMMC Partition done. Please stop using this memory! -269=Second Hand Memory : [SW2269]Register modified & RPMB written. Please stop using this memory! -270=Second Hand Memory : [SW2270]EMMC Partition done & RPMB written. Please stop using this memory! -271=Second Hand Memory : [SW2271]Register modified & EMMC Partition done & RPMB written. Please stop using this memory! -272=Second Hand Memory : [SW2272]Software has not supported this feature -273=[SW2273]CRC Check Error -274=[SW2274]Create readback file failed -275=[SW2275]The data packet with type(0x96) returned was misformatted -276=[SW2276]Check baud time out -277=[SW2277]Compare Software: The amount to be compared from DUT more than Pac -278=[SW2278]Compare Software: CompareID in Pac not equal to that from DUT -279=[SW2279]Compare Software: Pac has no CompareID from DUT - -;APP_AUTH_ERROR_CODE -513=[SW2513][Authentic]M1 data from DUT is wrong -514=[SW2514][Authentic]M2 data from Server is wrong -515=[SW2515][Authentic]M2 size from Server is zero diff --git a/4G/tools/_temp/uis_download/BMFileType.ini b/4G/tools/_temp/uis_download/BMFileType.ini deleted file mode 100644 index db53d94..0000000 --- a/4G/tools/_temp/uis_download/BMFileType.ini +++ /dev/null @@ -1,513 +0,0 @@ -锘縖CheckBaud] -1=CheckBaudRom -2=GetCheckBaudCrcType - -[FDL1] -1=Connect2 -2=Download -3=Excute - -[FDL2] -1=Connect2 -2=ChangeBaud -3=Download -4=ExecNandInit - -[HOST_FDL] -1=HostConnect -2=HostDownload -3=HostExcute -4=ResetCRC -5=Connect -6=ChangeBaud - -[FDL] -1=SetCRC -2=ConnectRom -3=Download -4=Excute -5=ResetCRC -6=Connect -7=ChangeBaud - -[Init] -1=ResetCRC -2=Connect - -[NAND_FDL] -1=Download -2=ExecNandInit - -[NV] -1=ReadFlash -2=Download - -[NV_NAND] -1=ReadFlash -2=Download - -[NV_COMM] -1=ReadFlashByID -2=DownloadByID - -[ReadFlash] -1=ReadFlash - -[ReadFlash2] -1=ReadFlashByID - -[EraseFlash] -1=EraseFlash2 - -[EraseFlash2] -1=EraseFlashByID - -[CheckDUT] -1=CheckDUT - -[CODE] -1=Download - -[CODE2] -1=DownloadByID - -[MiscDataCode2] -1=DownloadByID -2=SetTimeStamp - -[MiscDataCode] -1=Download -2=SetTimeStamp - -[Reset] -1=Reset - -[SetFirstMode] -1=SetFirstMode - -[DumpUbootLog] -1=DumpUbootLog - -[PowerOff] -1=PowerOff - -[BOOT_LOADER] -1=Download - -[BOOT_LOADER2] -1=DownloadByID - -[READFLASHTYPE] -1=ReadFlashType - -[CHECK_MCPTYPE] -1=ReadFlashType - -[ReadSN] -1=ReadFlash - -[ReadSN2] -1=ReadFlashByID - -[UDISK_IMG] -1=ReadSectorSize -2=Download - -[UDISK_IMG2] -1=ReadSectorSize -2=DownloadByID - -[ReadFlashAndSave] -1=ReadFlashAndSave - -[ReadFlashAndSave2] -1=ReadFlashAndSaveByID - -[ReadFlashAndDirectSave] -1=ReadFlashAndDirectSave - -[ReadFlashAndDirectSave2] -1=ReadFlashAndDirectSaveByID - -[ReadFlashAndDirectSave2_64] -1=ReadFlashAndDirectSaveByIDEx - -[CHIP_DSP] -1=ReadChipType -2=Download - -[CHIP_DSP2] -1=ReadChipType -2=DownloadByID - -[READ_CHIPID] -1=ReadChipType - -[UBOOT_LOADER] -1=Download - -[UBOOT_LOADER2] -1=DownloadByID - -[YAFFS_IMG] -1=Download - -[YAFFS_IMG2] -1=DownloadByID - -[CHECK_NV] -1=ReadFlash -2=Download - -[CHECK_NV2] -1=ReadFlashByID -2=DownloadByID - -[REPARTITION] -1=Repartition - -[REPARTITION2] -1=RepartitionByID - -[FORCE_REPARTITION] -1=ForceRepartition - -[FORCE_REPARTITION2] -1=ForceRepartitionByID - -[DONOTHING] -1=DoNothing - -[KeepCharge] -1=KeepCharge - -[READ_FLASHINFO] -1=ReadFlashInfo - -[EXTTABLE] -1=SendExtTable - -[Soft_SIM] -1=ReadFlashUID -2=Download -3=ReadSoftSimEID - -[READ_CHIPUID] -1=ReadChipUID - -[Enable_Flash] -1=EnableFlash - -[EnableSecureBoot] -1=EnableSecureBoot - -[FDL2_64] -1=Connect2 -2=ChangeBaud -3=DownloadEx -4=ExecNandInit - -[NAND_FDL_64] -1=DownloadEx -2=ExecNandInit - -[CODE2_64] -1=DownloadByIDEx - -[YAFFS_IMG2_64] -1=DownloadByIDEx - -[ReadFlashAndSave2_64] -1=ReadFlashAndSaveByIDEx - -[REF_INFO] -1=ReadRefInfo - -[APR] -1=WriteAPRInfo - -[READ_RF_CHIP_TYPE] -1=ReadTransceiverType - -[DEBUG_MODE] -1=EnableDebugMode - -[ReadNandBlockInfo] -1=ReadNandBlockInfo - -[DDRCheck] -1=DDRCheck - -[SelfRefresh] -1=SelfRefresh - -[EndProcess] -1=EndProcess - -[ReadPartitionInfo] -1=ReadPartitionInfo - -[CHANGE_SELINUX] -1=ChangeSelinux - -[ReadVpac] -1=ReadVpac - -[WriteVpac] -1=WriteVpac - -[WritePartitionValue] -1=WritePartitionValue - -[EndWatchdog] -1=EndWatchdog - -[WriteEfuse] -1=WriteEfuse - -[SendFlag] -1=SendFlag - -[WriteTimestamp] -1=WriteTimestamp - -[Max Length] -HOST_FDL=0x800 -FDL1=0x210 -FDL=0x210 -CODE=0x800 -CODE2=0x5000 -MiscDataCode=0x800 -MiscDataCode2=0x5000 -NV=0x800 -NAND_FDL=0x210 -FDL2=0x210 -;if change max length of boot_loader -;the size must be 2112 times, eg. 4224, 6336... -BOOT_LOADER=2112 -BOOT_LOADER2=2112 -ReadFlash=0x3000 -ReadFlash2=0x3000 -ReadFlashAndSave=0x3000 -ReadFlashAndSave2=0x3000 -NV_NAND=0x800 -NAND_FDL_OPT=0x840 -ReadSN=0x1000 -UDISK_IMG=0x800 -CHIP_DSP=0x800 -UBOOT_LOADER=0x800 -UBOOT_LOADER2=0x800 -YAFFS_IMG=0x3180 -YAFFS_IMG2=0xA000 -ReadPartitionInfo=0x3000 -FDL2_64=0x840 -NAND_FDL_64=0x840 -CODE2_64=0xE000 -YAFFS_IMG2_64=0xE000 -ReadFlashAndSave2_64=0xE000 -Download=0xFC00 - -[SC8810] -CODE=0x3000 -CODE2=0x3000 - -[SC8810e] -CODE=0x3000 -CODE2=0x3000 - -[UMS9117] -CODE=0xb000 -NAND_FDL=0x2200 - -[UIS8310] -CODE=0xb000 -NAND_FDL=0x2200 - -[Repartition] -; -;strategy of repartition actions -; -;0 means do repartition action anyway -;1 means stop all action and report error when imcompatible partition error occured -;2 means ignore imcompatible partition error -;3 means do repartition action when imcompatible partition error occured -;Default value is 1 -strategy = 1 - -[ReadFlashBeforeRepartition] -;0 means not to read flash before repartiton -;1 means to read flash before retpartition -strategy = 0 - -[ReadDUTInfo] -PartitionName = uboot -MaxReadLength = 0x100000 -;CheckMatchPolicy -; -;if 0, PACKey exist,but DUTKey don't exist,Not allow to downloaded -;if 1, PACKey exist,but DUTKey don't exist,Allow to downloaded -CheckMatchPolicy = 0 -EnableWriteFlash = 0 - -[DownloadNV] -CheckNVTimes = 3 -MaxReadLength = 0x100000 -;GSMCaliVaPolicy -; -;if 0, not backup following data for GSM calibration Ver FF0A/FF0B -; -; RF_ramp_delta_timing -; -;if 1, not backup following data for GSM calibration Ver FF0A/FF0B -; -; temperature_and_voltage_composate_structure (reserved) -; RF_ramp_table -; RF_ramp_PA_power_on_duration -; RF_ramp_delta_timing -; -;if 2, backup following data for GSM calibration Ver FF0A/FF0B -; -; rf_common_param_dsp_use -; -; rf_gsm_param_dsp_use->agc_ctrl_word -; rf_gsm_param_dsp_use->rx_compensate_value -; rf_gsm_param_dsp_use-rssi_campensate_div -; rf_gsm_param_dsp_use->max_rf_gain_index -; rf_gsm_param_dsp_use->agc_ctrl_word_div -; rf_gsm_param_dsp_use->max_rf_gain_index_div -; -; rf_gsm_param_dsp_use->rf_ramppwr_step_factor -; rf_gsm_param_dsp_use->rf_edge_tx_gain_table -; rf_gsm_param_dsp_use->rf_8psk_tx_compensation -; rf_gsm_param_dsp_use->rf_ramp_param_constant_value -; -; adc -; -;if 3, backup all data for GSM calibration Ver FF0A/FF0B -; -; -GSMCaliVaPolicy = 2 - -[ChipDSPMap] -0x8850A002=8800S2A_3200B0_DM_DSP.bin -0x8850A007=8800S3B_3200B0_DM_DSP.bin - -[IMEI_ID] -IMEI2=0x179 -IMEI3=0x186 -IMEI4=0x1E4 - - -[MultiLangs] -1=English -2=SimpleChinese -3=TraditionalChinese -4=Arabic -5=french -6=Hindi -7=Hungarian -8=Indonesian -9=Malay -10=Portuguese -11=Russian -12=Spanish -13=Tagalog -14=Thai -15=Vietnamese -16=Urdu -17=Italian -18=Persian -19=Turkish -20=German -21=Greek -22=Hebrew -23=Bengali -24=Czech -25=Slovenian -26=Romanian -27=Telugu -28=Marathi -29=Tamil -30=Gujarati -31=Kannada -32=Malayalam -33=Oriya -34=Punjabi -35=Afrikanns -36=Albanian -37=Armenian -38=Azerbaijani -39=Basque -40=Bulgarian -41=Catalan -42=Croatian -43=Danish -44=Dutch -45=Estonian -46=Filipino -47=Finnish -48=Galician -49=Georgian -50=Hausa -51=Icelandic -52=Igbo -53=Irish -54=Kazakh -55=Latvian -56=Lithuanian -57=Macedonian -58=Moldovan -59=Norwegian -60=Polish -61=Serbian -62=Sesotho -63=Slovak -64=Swedish -65=Ukrainian -66=Yoruba - -[AT_REBOOT_SETTING] -ATPort = Spreadtrum Control Port,SPRD AT,SPRD LTE AT,UNISOC AT PORT -DLPort = SPRD U2S Diag,SCI USB2Serial,SCI Anroid USB2Serial,SCI Android USB2Serial,USB Serial Port,Prolific USB-to-Serial Comm Port,UNISOC DIAG PORT -AT_BaudRate = 115200 - -[Misc] -;DoCheckSum: if 1, Support to check image's integrity. -DoCheckSum = 0 -;SupportZroPkg: if 1, Support to segment USB packet to avoid USB's Zero-Length-Packet problem. -SupportZroPkg = 1 -;SupportUnTransCode: if 1,Enable UnTransCode; 0,disable UnTransCode -SupportUnTransCode = 1 -;NeedCheckOldMemory: if 1, Support to check the memory's used -NeedCheckOldMemory =0 -;Check Register modified -CheckRegModify=1 -;Check EMMC Partition done -CheckEmmcPartition=1 -;Check RPMB written -CheckRpmbWritten=1 -;StopDownloadIfOldMemory: if 1, Stop download when check the memory's used -StopDownloadIfOldMemory =0 -GenCrcCfgFile=0 -EnableCrcCfgCheck=0 -CrcFile= - -[CheckSecondHandMemory] -;unit:hour -Time=24 - -[DownloadBySparse2Raw] -;CheckSparse2Raw 0锛歯ot use Sparse2Raw -;CheckSparse2Raw 1锛歶se Sparse2Raw in all partition -;CheckSparse2Raw 2锛歶se Sparse2Raw only in super -;CheckSparse2Raw 3锛歶se Sparse2Raw not in userdata -;CheckSparse2Raw 4锛歶se Sparse2Raw only in system -CheckSparse2Raw = 2 - -[DownloadByPoweroff] -DownloadByPoweroff = 0 - -[WatchDog] -WatchDog = 0 -;Watchdog_Time : ;Unit is milesecond -WatchDogTime = 150000 diff --git a/4G/tools/_temp/uis_download/BMPlatform9.dll b/4G/tools/_temp/uis_download/BMPlatform9.dll deleted file mode 100644 index a640c1a..0000000 Binary files a/4G/tools/_temp/uis_download/BMPlatform9.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/BMTimeout.ini b/4G/tools/_temp/uis_download/BMTimeout.ini deleted file mode 100644 index 5fa81c9..0000000 --- a/4G/tools/_temp/uis_download/BMTimeout.ini +++ /dev/null @@ -1,108 +0,0 @@ -[Timeout] -CheckBaudRom=20 -Check Baud=1000 -HostConnect=1000 -HostDownload=10000 -HostExcute=2000 -Connect=3000 -Erase Flash=3600000 -Read Flash=10000 -StartData=30000 -Download=120000 -Excute=1000 -ExecNandInit=60000 -Repartition=60000 -EndData=60000 -ReadFlashType=1000 -ReadSectorSize=1000 -KeepCharge=3000 -SendExtTable=1000 -ReadFlashUID=1000 -ReadSoftSimEID=2000 -ChangeBaud=2000 -StartRead=20000 -MidstRead=20000 -EndRead=20000 -DDRCheck=30000 -;SelfRefresh > 20000 -SelfRefresh=40000 -ReadNandBlockInfo=3000 -SetFirstMode=1000 -CheckDUT=500 -EnableRawData=20000 -FlushData=20000 -MidstRawStart=20000 -SetRandomData=20000 -ReadPartitionInfo=1000 -DumpUbootLog=5000 -ReadVpac=1000 -Watchdog=1000 - -[OperationInterval] -Connect=0 - -[Check Baud Times] -CheckBaud = 100 -FDL=50 -ReadSN=10 -HostConnect = 2000 - -[CheckDUT] -CheckTimes = 0 -WaitTimeForNextChip= 2000 - -[CheckBaudSetting] -;only 1 to 4 -7ENumPerTime = 1 - -[NVItem] -ItemID=0x8 - -[Log] -SerialDDRLogEnable = 0 -PassRemoveLog = 0 - - -[SC7701] -Download=80000 -EndData=50000 - -[SC7702] -Download=80000 -EndData=50000 - - -[SC8501C] -Check Baud=1000 - -[SC8501C_SAMSUNG] -Check Baud=1000 - -[SharkL3Mode] -Check Baud=2000 - -[SharkL4Mode] -Check Baud=2000 - -[SharkL5Mode] -Check Baud=2000 - -[SharkL3ModeMarlin] -Check Baud=2000 - -[SharkL4ModeMarlin] -Check Baud=2000 - -[SharkL5ModeMarlin] -Check Baud=2000 - -[SharkLSGLobalMarlinAndroid5.1] -Check Baud=10000 - -[sp9853i] -Check Baud=10000 - -[SecondEnumPort] -;Unit is millisecond -EnumPortTimeOut=60000 -EnumPortErrorMsg=The second enumemration port timeout diff --git a/4G/tools/_temp/uis_download/BinPack.ini b/4G/tools/_temp/uis_download/BinPack.ini deleted file mode 100644 index 6386bf0..0000000 --- a/4G/tools/_temp/uis_download/BinPack.ini +++ /dev/null @@ -1,11 +0,0 @@ -[Setting] - -;MaxDataLength,unit is M,when MaxDataLength is zero,the loadpolicy is invalid. -MaxDataLength = 50 - -;LoadPolicy -;if 0, CRC check and generate the temporary download image -;if 1, CRC check and don't generate the temporary download image ( Recommended ) -;if 2, don't check crc and don't generate the temporary download image -LoadPolicy = 2 - diff --git a/4G/tools/_temp/uis_download/Channel.ini b/4G/tools/_temp/uis_download/Channel.ini deleted file mode 100644 index 94e6047..0000000 --- a/4G/tools/_temp/uis_download/Channel.ini +++ /dev/null @@ -1,55 +0,0 @@ -[Log] -; Text log level -; 0, No text log -; 1, Log errors,default value -; 2, Log warnings -; 3, Log runtime information -; 4, Log data only -; 5, Log everything -Level = 0 - -; 0x4000, Text log,default value -; 0x8100, Binary log,log received data -; 0x8200, Binary log,log sent data -; 0x8300, Binary log,log received data and sent data -; you can conbine these flags -Type = 0x4000 - -[Settings] -;use memory pool flag, default value is 1 -UseMempool =1 -;above is common for SOCKET and UART - -;COM input/output queue size, default value is 4096 (4K) -CommQueueSize = 4096 - -;SOCKET receive buffer size, default value is 2048 (2K) -MaxRcvSize = 2048 - -;SOCKET client connect timeout,, default value is 500ms -ConnectTimeout = 1000 - -[CommTimeouts] -;this configure is for COM(UART) -;Default values as below if you don't set these values -ReadIntervalTimeout = 0xFFFFFFFF -ReadTotalTimeoutMultiplier = 0 -ReadTotalTimeoutConstant = 0 -WriteTotalTimeoutMultiplier = 1 -WriteTotalTimeoutConstant = 2000 - -;ReadIntervalTimeout = 5 -;ReadTotalTimeoutMultiplier = 1 -;ReadTotalTimeoutConstant = 80 -;WriteTotalTimeoutMultiplier = 1 -;WriteTotalTimeoutConstant = 0 - -;[CommState] -;-1, keep original value -;fDtrControl=0 -;fRtsControl=-1 -;fOutX=0 -;fInX=0 -;fOutxCtsFlow=0 -;fOutxDsrFlow=0 -;fTXContinueOnXoff=0 diff --git a/4G/tools/_temp/uis_download/Channel9.dll b/4G/tools/_temp/uis_download/Channel9.dll deleted file mode 100644 index 563fb86..0000000 Binary files a/4G/tools/_temp/uis_download/Channel9.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Channel9D.dll b/4G/tools/_temp/uis_download/Channel9D.dll deleted file mode 100644 index af433a0..0000000 Binary files a/4G/tools/_temp/uis_download/Channel9D.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/ChannelD.dll b/4G/tools/_temp/uis_download/ChannelD.dll deleted file mode 100644 index 52b232d..0000000 Binary files a/4G/tools/_temp/uis_download/ChannelD.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/CmdDloader.exe b/4G/tools/_temp/uis_download/CmdDloader.exe deleted file mode 100644 index 15d2498..0000000 Binary files a/4G/tools/_temp/uis_download/CmdDloader.exe and /dev/null differ diff --git a/4G/tools/_temp/uis_download/CmdDloader.ini b/4G/tools/_temp/uis_download/CmdDloader.ini deleted file mode 100644 index 02927a8..0000000 --- a/4G/tools/_temp/uis_download/CmdDloader.ini +++ /dev/null @@ -1,9 +0,0 @@ -[Setting] -FlashApp=ResearchDownload.exe -PipeName = ResearchDownload -ShowProcess = 1 -EZMode = 0 -;WaitDUTTimeout unit is milliscond -WaitDUTTimeout =120000 - -PartialFlash = 0 \ No newline at end of file diff --git a/4G/tools/_temp/uis_download/Codec.dll b/4G/tools/_temp/uis_download/Codec.dll deleted file mode 100644 index c3ccbce..0000000 Binary files a/4G/tools/_temp/uis_download/Codec.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Config.dll b/4G/tools/_temp/uis_download/Config.dll deleted file mode 100644 index b2d10c7..0000000 Binary files a/4G/tools/_temp/uis_download/Config.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/CrashDump.dll b/4G/tools/_temp/uis_download/CrashDump.dll deleted file mode 100644 index a6fbd24..0000000 Binary files a/4G/tools/_temp/uis_download/CrashDump.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/Auth/Auth.dll b/4G/tools/_temp/uis_download/Customized/Auth/Auth.dll deleted file mode 100644 index 7bb0c46..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/Auth/Auth.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/Auth/Auth.lib b/4G/tools/_temp/uis_download/Customized/Auth/Auth.lib deleted file mode 100644 index ba593a3..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/Auth/Auth.lib and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/Auth/Security_Encryption.dll b/4G/tools/_temp/uis_download/Customized/Auth/Security_Encryption.dll deleted file mode 100644 index 8109c46..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/Auth/Security_Encryption.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/Auth/libeay32.dll b/4G/tools/_temp/uis_download/Customized/Auth/libeay32.dll deleted file mode 100644 index 5952ae9..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/Auth/libeay32.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/Auth/rsa2048.pem b/4G/tools/_temp/uis_download/Customized/Auth/rsa2048.pem deleted file mode 100644 index 7ea21b3..0000000 --- a/4G/tools/_temp/uis_download/Customized/Auth/rsa2048.pem +++ /dev/null @@ -1,27 +0,0 @@ ------BEGIN RSA PRIVATE KEY----- -MIIEpAIBAAKCAQEAurQJ+5JmL8x8Xa1QZ/C7wpKQ9YCLuSOgDyYYZuAs0caFXKdd -L9amElW6/pryRv7hQfiWHAjr9Vg1BZepgQVhTw9uUgeOMID0gF7Dy9j7Z4kzCrZr -KbDavG7w4jOYgXq8ihW3MCZg1pM869I/mxRsY/YTx4BGW8EUMYLfdtOObbJiRLzA -wDvG1lFUbQwaylszCKjdcF2jfiFvgHhQIekWy9JhLGuBtZZLTS5QClI09j+y3wMn -hcCsgYRpRAvOGYoI0GFu3fhDiEyN7cdHLEpk5arQPrreJuR2t1b6VDXBlFnlEOwg -Csj6025J+rsBtfWFWR4ALxPyio0uAn1ECSwfSQIDAQABAoIBAF4bpfSCpLNvNTja -xW6+70VyL1MwCj218VXxc9dXJABROqOrUNNuNKOFRw5S99BFZTGlpbRX4uf2IDPD -cJMyLQx20LrUSB22wod6POMhageUJoA91uJa3MaifRTnwPVy8ln//ChvD9zYtpp/ -jcQTlVcFkI6837ocJpuWRiFVHbO4mzpfbUCuSBtS8aL0F2Lj/QKhExcSiCMqMJpI -Mqnrs+BcYhbfL4kfLWzJgOeen5L3yQTYigQVt0XllBDqzJ7y7AABLDpltLwn4hf8 -zn1Fc3rNtkrAYAAPS5G8NrvPcKgI6MRvLJl0HBOV1HMVP3tTB1MOcdAuzxfnkuIL -jFUXCckCgYEA8gL2jKHMAknsqbhg2ncYrTV2rwGFEBQdIQDmhUkBzLz2F9gQTYM/ -V7kj5TnaYTruNKKzkxNv7lr9ujbtS1Kc0Cs7Oqk1chSNk9/3fPg7KstNixs5OwQ9 -A2+8PSZRqWVsayNcjbdUn8Mt5XDkxjP5wsmPy/6TXkkHEguKLsxx13cCgYEAxX6u -Un8X1bWFGWLdyp3opM2VrD0cr3RaLIU8amEjcXTbzW9QoVrhRwaySpE8LU3999ZY -XHlilloB/t5CKZy51YlB0lj7rQe2P7FaIcH0eDTL9O1FA51KAjSG0aNTs1GWUXL+ -ZfJslCoyqQG5sa9AqhJHAma2rUgXIQU0mFcA7z8CgYAur/mmSbRUoLRCTaqJmr4s -9ApwWoe0AV1ZN5ZBEkOBntaO5QTIH1DB+Jp/JzkE1tyLVPP1pKNMRUt7eAsxI7/S -vPRRLcF8v5BMfcF931lyuQO9mUPiKcAngI+88D6Cwmk3Bfxd7ocpxvp8r9nCjtZZ -CI9wGC2P2+C8T3OZ8aDoowKBgQCu6jACqMW3ZXloroO5PHob3Gk/jzCkxOxImgiU -P0xg5Br4rCpBfngfq/Kk0FT32yegJZtE681BVJ6H2NnIeSKt2U8OufjNmxLy/mTR -mTKodDpfxvVk6h3uLg9qBLnRC+WSZcKjED7SSz1rKjgJAyrGdkGmAsqwVjUF7dJT -SlttiQKBgQCJ8FUeLMhIsCW5ha0qIQaVyGxGmpCAN2jL31cbryA5j5jvw1ce9qGE -SdhO1gg+WsFwTQNhnYvr4U0TA03HRxhp1GdhqOQ6v/LHBKN3xP7oC+L5c4TqXF1f -hH/cjg9M0I6EEJwqsly4/WOTvRKmJhgUZFnMXnp5LKerUEZKn+9Y7Q== ------END RSA PRIVATE KEY----- diff --git a/4G/tools/_temp/uis_download/Customized/Auth/ssleay32.dll b/4G/tools/_temp/uis_download/Customized/Auth/ssleay32.dll deleted file mode 100644 index b058a14..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/Auth/ssleay32.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.dll b/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.dll deleted file mode 100644 index 5763061..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.lib b/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.lib deleted file mode 100644 index 7ecae1a..0000000 Binary files a/4G/tools/_temp/uis_download/Customized/ReadFlash/ReadFlash.lib and /dev/null differ diff --git a/4G/tools/_temp/uis_download/DLFrame.dll b/4G/tools/_temp/uis_download/DLFrame.dll deleted file mode 100644 index 8368881..0000000 Binary files a/4G/tools/_temp/uis_download/DLFrame.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/LiveUpdatesDLL.dll b/4G/tools/_temp/uis_download/LiveUpdatesDLL.dll deleted file mode 100644 index a5911fc..0000000 Binary files a/4G/tools/_temp/uis_download/LiveUpdatesDLL.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/LiveUpdatesDLL.ini b/4G/tools/_temp/uis_download/LiveUpdatesDLL.ini deleted file mode 100644 index cc63a30..0000000 --- a/4G/tools/_temp/uis_download/LiveUpdatesDLL.ini +++ /dev/null @@ -1,29 +0,0 @@ - -[Settings] -LiveUpdatesON = 1 -Domain=sprd.com - -[FileList] -File0=LiveUpdatesApp.exe -File1=unrar.dll - -[ftp] -Address=ftp.unisoc.com -Username=bsptool -;Password : passsword - -[SharePath] -ExternalIsFtp = 0 -Ftp_Path=/ -External_Path=\\shnas01\PublicShared\ShareData\Debug_Tools\LatestVersion\ -Internal_Path=\\filer2\Public_Folder\ShareData\Debug_Tools\LatestVersion\ - -FolderName=Download - -[LiveUpdatesApp] -;LiveUpdatesApp/LiveUpdatesApp.exe -PackageName=LiveUpdatesApp -AppName=LiveUpdatesApp.exe -AppCfg=LiveUpdatesApp.ini - - diff --git a/4G/tools/_temp/uis_download/MCPType.ini b/4G/tools/_temp/uis_download/MCPType.ini deleted file mode 100644 index 5313228..0000000 --- a/4G/tools/_temp/uis_download/MCPType.ini +++ /dev/null @@ -1,78 +0,0 @@ -[MCPSetting] -CheckMCPType =0 -MCPTypeRange =2CB39066-64000000 - -[MCPTypeList] -;ID = Description -;NOR flash ID format is "MID-DID-EID", %X-%X-%X -;NAND flash ID format is "MID-DID", %X-%X - -2CB39066-64000000 = -4kpage-224oob - - -;1-7E1001-0 = S71GL064NB0 -;1-7E2000-1 = S71PL127N -;1-7E2101-0 = SVSE28xxUXA -;1-7E4400-0 = s71ws128pc0hf3sr -;1-7E6101-0 = S71VS064RB0ZHKZ00 -;1-7E6301-0 = S71VS128RC0ZHK4L0 - -;20-880D-0 = M36L0T80x0T3 -;20-880E-0 = M36L0T80x0B3 -;20-8810-0 = M36W0T6050T3 -;20-8810-1 = m36w0r6050t4zaq -;20-8811-0 = M36W0T6050B3 -;20-8811-1 = m36w0r6050b4zaq -;20-881C-0 = m36l0r8060u0zamf -;20-882E-0 = m36l0r7050u3 -;20-882F-0 = m36l0r7050l3 -;20-8832-0 = M36P0R8060N0ZS -;20-883C-0 = m36l0r8060u0 -;20-8848-0 = M36C0W6050T0/Memcom_Ksp6432_Top -;20-8849-0 = M36C0W6050B0/Memcom_Ksp6432_Bottom -;20-88C0-0 = m36w0r6050u4 -;20-88C1-0 = m36w0r6050l4 -;20-88C4-0 = M36L0T70x0T4ZSP/m36l0r7050t4zaq -;20-88C4-1 = M36L0T70x0T3/m36l0r7050t4zaq_1 -;20-88C5-0 = M36L0T70x0B4ZSP/m36l0r7050b4zaq -;20-88C5-1 = M36L0T70x0B3/m36l0r7050b4zaq_1 - -;7F-7E1000-0 = CFEON_EN71GL064_Bottom -;7F-7E1001-0 = CFEON_EN71GL064_Top -;7F-7E2101-0 = CFEON_EN71GL128B0 - -;89-8809-0 = PF38F3040L0YUQ3 -;89-880A-0 = PF38F4050L0YUQ3 -;89-8835-0 = PF38F3040L0YUQ3_B -;89-8836-0 = PF38F4050L0YUQ3_B -;89-8900-0 = PF38F3050M0Y0YE -;89-8901-0 = PF38F4050M0Y0YE -;89-8903-0 = PF38F3050M0Y3Q - -;98-3-0 = TSB_TV00570002 -;98-49-0 = TSB_TV00570002ADGB -;98-96-0 = TSB_TV00560002 -;98-97-0 = TSB_TV00560003 -;98-9E-0 = TY5701111183KC04_Top -;98-9F-0 = TY5701111183KC04_Bottom - -;C2-227E-0 = SILICON7_SVME2832UTA -;C2-22C9-0 = W64F32S_Top/SILICON7_SVME6432UTA_Top -;C2-22CB-0 = W64F32S_Bottom/SILICON7_SVME6432UTA_Bottom -;C2-7E0C01-0 = SILICON7_SVME6432UTB - -;EC-2402-0 = k5l2833ata_af66 -;EC-2403-0 = k5l2833aba_af66 -;EC-2404-0 = k5n2833atm_aq11 -;EC-2405-0 = k5n2833abm_aq11 - -;EC-2254-0 = k5n6433atm -;EC-2255-0 = k5n6433abm -;EC-2256-0 = k5l6433atm -;EC-2257-0 = k5l6433abm -;EC-227A-0 = k5n6433atb -;EC-227B-0 = k5n6433abb -;EC-257E-0 = K5L2731CAM -;EC-257E-1 = K5L6331CAA - - diff --git a/4G/tools/_temp/uis_download/PhaseCheck.ini b/4G/tools/_temp/uis_download/PhaseCheck.ini deleted file mode 100644 index 464ff70..0000000 --- a/4G/tools/_temp/uis_download/PhaseCheck.ini +++ /dev/null @@ -1,27 +0,0 @@ -[VERSION] -# Old Version: SP05 -# New Version: SP09 -# SP15: Support 64-bits SN -MAGIC NUMBER = SP09 - -[STATE FLAG] -# Value indicate PASS (Only available for SP09) -PASS VALUE = 0 - - -[STATION] -# Max. station number is 20 for SP15. -# Max. station number is 15 for SP09. -# Max. station number is 12 for SP05. -STATION NUMBER = 7 - -# Len of station name must be less than: -# SP09: 10 bytes -# SP15: 15 bytes -STATION 1 =DOWNLOAD -STATION 2 =WRITESN -STATION 3 =CFT -STATION 4 =BBAT -STATION 5 =WCN -STATION 6 =ANTENNA -STATION 7 =IMEI diff --git a/4G/tools/_temp/uis_download/PortHound.dll b/4G/tools/_temp/uis_download/PortHound.dll deleted file mode 100644 index f845754..0000000 Binary files a/4G/tools/_temp/uis_download/PortHound.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/PortHound9.dll b/4G/tools/_temp/uis_download/PortHound9.dll deleted file mode 100644 index 1a425a8..0000000 Binary files a/4G/tools/_temp/uis_download/PortHound9.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/ProcessFlow.dll b/4G/tools/_temp/uis_download/ProcessFlow.dll deleted file mode 100644 index 67a3eaa..0000000 Binary files a/4G/tools/_temp/uis_download/ProcessFlow.dll and /dev/null differ diff --git a/4G/tools/_temp/uis_download/ProcessFlowSetting.ini b/4G/tools/_temp/uis_download/ProcessFlowSetting.ini deleted file mode 100644 index c4dcb37..0000000 --- a/4G/tools/_temp/uis_download/ProcessFlowSetting.ini +++ /dev/null @@ -1,19 +0,0 @@ -[Setting] -Enable =0 -SnLength =17 -ProjectMode =0 -OrderNumber = -SaveMode =2 -CkLastStase =0 -StationMode =0 -PreStationMode =0 - -ProjectList = 5735C,6531,6815A,7703,7715A,7730A,7730G,7731G,8730S,8830A,8830G,9620M,9830A,9836A,9820A,7720A,8820A -StationList = FactoryDownLoad,ResearchDownload,WRITESN,CFT,WCFT,TDCFT,LTECFT,G+WCFT,G+TDCFT,ANTENNA,MMI,WriteIMEI,UpgradeDownload - - -[SERVER] -//Internal IP: 10.0.11.87, Internet IP: 210.13.81.28 -SqlServer =10.0.11.87 - - diff --git a/4G/tools/_temp/uis_download/RSAKeyGen.exe b/4G/tools/_temp/uis_download/RSAKeyGen.exe deleted file mode 100644 index f5c175e..0000000 Binary files a/4G/tools/_temp/uis_download/RSAKeyGen.exe and /dev/null differ diff --git a/4G/tools/_temp/uis_download/ResearchDownload.exe b/4G/tools/_temp/uis_download/ResearchDownload.exe deleted file mode 100644 index 7d21dfe..0000000 Binary files a/4G/tools/_temp/uis_download/ResearchDownload.exe and /dev/null differ diff --git a/4G/tools/_temp/uis_download/ResearchDownload.ini b/4G/tools/_temp/uis_download/ResearchDownload.ini deleted file mode 100644 index cb5b117..0000000 --- a/4G/tools/_temp/uis_download/ResearchDownload.ini +++ /dev/null @@ -1,174 +0,0 @@ -[ChipDspMap] -enable=0 -[Comparison] -Enable=0 -Parameter=""%s" "%s"" -Policy=1 -Program=C:\Program Files (x86)\Beyond Compare 3\BCompare.exe -[Debug] -Data=enable:level=- -[DownloadByPoweroff] -DownloadByPoweroff=0 -[Download_Packet] -Floader= -ShowConfirmDialog=1 -UnpacketDir=.\ -packet=E:\code\UIS8850\hex\8850DG_LuatOS_debug\core.pac -[EraseFlash] -[FirstMode] -Enable=0 -FirstMode=0x0 -SupportFeaturePhone=0 -[GUI] -BaudRates=57600,115200,230400,460800,921600,1000000,2000000,3250000,4000000 -CanEdit=1 -CanSelect=1 -ClosePortFlag=0 -CmdPackage=0 -FileFilter=All file(*.*)|*.*|Image file (*.bin;*.img)|*.bin;*.img|| -FileMode=0 -InDLProcess=1 -MarkLastState=0 -PacketMode=1 -PowerManageFlag=0 -PowerManageInterval=10 -SafetyTipsMsg=1 -ScriptControl=0 -ScriptControlStop=1 -ShowFailedMsgBox=0 -ShowPacPath=0 -ShowRate=1 -ShowSecurityTips=0 -SkipBackupNV=0 -[Mes] -Enable=0 -[NV] -FileNameWithSN=1 -SaveToLocalFlag=0 -[Options] -CheckMatch=0 -DDRCheck=0 -EraseAll=0 -FlashPageType=0 -KeepCharge=0 -PowerOff=0 -ReadChipUID=0 -Repartition=1 -Reset=1 -SelfRefresh=0 -UartDownload=0 -WriteEfuse=0 -ReadPartition=0 -DumpUbootLog=0 -VpacCheck=0 -ReadMCPType=0 -CheckNvItemReadCrc=0 -[PAC_ums312_1h10] -BOOT=1@E:\08.Tools\trunk\NPI\2022\Download\tag_0607_1\Win\ResearchDownload\Bin\ImageFiles\PAC_ums312_1h10_DownloadFiles_MocorDroidR_23E8_2CD943_0\boot.img.flag -CACHE=1@E:\08.Tools\trunk\NPI\2022\Download\tag_0607_1\Win\ResearchDownload\Bin\ImageFiles\PAC_ums312_1h10_DownloadFiles_MocorDroidR_23E8_2CD943_0\cache.img -CONFILE=0@ -DFS=1@E:\08.Tools\trunk\NPI\2022\Download\tag_0607_1\Win\ResearchDownload\Bin\ImageFiles\PAC_ums312_1h10_DownloadFiles_MocorDroidR_23E8_2CD943_0\sharkl5_cm4.bin -DSP_LTE_AG=1@E:\08.Tools\trunk\NPI\2022\Download\tag_0607_1\Win\ResearchDownload\Bin\ImageFiles\PAC_ums312_1h10_DownloadFiles_MocorDroidR_23E8_2CD943_0\sharkl5_pubcp_6m_evdo_AGCP_DSP.bin -DSP_LTE_CDMA=1@E:\08.Tools\trunk\NPI\2022\Download\tag_0607_1\Win\ResearchDownload\Bin\ImageFiles\PAC_ums312_1h10_DownloadFiles_MocorDroidR_23E8_2CD943_0\sharkl5_pubcp_6m_evdo_CDMA_DSP.bin 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/8850_bsdump.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/8850_bsdump.xml deleted file mode 100644 index a01a9e0..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/8850_bsdump.xml +++ /dev/null @@ -1,207 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/8850_hard.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/8850_hard.xml deleted file mode 100644 index ba3adb4..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/8850_hard.xml +++ /dev/null @@ -1,89916 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AON_SOFT_RST_CTRL0 - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - - CLKEN_LTE - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - LTE module function clock software register control bit -0:off -1:on - - - - CLKEN_LTE_INTF - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - LTE module interface clock software register control bit -0:off -1:on - - - - RSTCTRL_LTE - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - LTE module reset software register control bit -0:no reset -1:reset - - - - LTE_AUTOGATE_MODE - - 0: LTE module clock auto gating individual -1: LTE modules invide into two parties : "uplink" and "downlink", and auto gating individual - - - - LTE_AUTOGATE_EN - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - LTE_AUTOGATE_DELAY_NUM - - When LTE autogating function enable, After module "running" signal was pull down, a counter begin to count from zero.LTE modules clock will be gated when the counter counts to this number value. - - - - AON_LPC_CTRL - - waiting time of bus entered low power mode,calculated by bus clock - - - waiting time of bus entered normal power mode,calculated by bus clock - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - AON_CLOCK_EN0 - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - AON_CLOCK_EN1 - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - AON_CLOCK_AUTO_SEL0 - - - AON_CLOCK_AUTO_SEL1 - - - AON_CLOCK_AUTO_SEL2 - - - AON_CLOCK_AUTO_SEL3 - - - AON_CLOCK_FORCE_EN0 - - - AON_CLOCK_FORCE_EN1 - - - AON_CLOCK_FORCE_EN2 - - - AON_CLOCK_FORCE_EN3 - - - AON_SOFT_RST_CTRL1 - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - 1:reset -0:reset release - - - - MIPI_CSI_CFG_REG - - - - - CFG_CLK_UART2 - - - - - - CFG_CLK_UART3 - - - - - - CFG_CLK_DEBUG_HOST - - - - - - - RC_CALIB_CTRL - - write 1 to clear interrupt. Read data always be "0". - - - 0:disable interrupt -1:enable interrupt - - - 0:disable -1:enable -write 1 to enable RC caliberation, clear to 0 automatically when caliberation done. - - - - RC_CALIB_TH_VAL - - - RC_CALIB_OUT_VAL - - - EMMC_SLICE_PHY_CTRL - - 1:enable -0:disable - - - 1:sel lte dbgio -0:sel emmc - - - - DMA_REQ_CTRL - - 1:sel cp axidma -0:sel ap axidma - - - 1:sel cp axidma -0:sel ap axidma - - - - APT_TRIGGER_SEL - - 1:sel lte_up_rfctrl[3] -0:sel rf_gpio[9] - - - - AHB2AHB_AB_FUNCDMA_CTRL - - - - - - - - - - - - - - - AHB2AHB_AB_FUNCDMA_STS - - - - - - - - - - - - - - - - AHB2AHB_AB_DAP_CTRL - - - - - - - - - - - - - - - AHB2AHB_AB_DAP_STS - - - - - - - - - - - - - - - - AHB2AXI_PUB_CTRL - - - - - - - - - AHB2AXI_PUB_STS - - - - - - - AXI2AXI_PUB_STS_0 - - - - - - AXI2AXI_PUB_STS_1 - - - AHB2AHB_AB_AON2LPS_CTRL - - - - - - - - - - AHB2AHB_AB_AON2LPS_STS - - - - - - - - - AHB2AHB_AB_LPS2AON_CTRL - - - - - - - - - - AHB2AHB_AB_LPS2AON_STS - - - - - - - - - SYSCTRL_REG0 - - 1: enable rf_dig clock -0: disable rf_dig clock - - - 1: output to PMIC 26M clock enable -0: output to PMIC 26M clock disable - - - 1: IIS_PLL reference clock enable -0: IIS_PLL reference clock disable - - - 1: MPLL reference clock enable -0: MPLL reference clock disable - - - 1: APLL reference clock enable -0: APLL reference clock disable - - - 1: aud_sclk clock output invert(source from clk_audio) -0: aud_sclk clock output do not invert(source from clk_audio) - - - usb20 utmi_width_sel value - - - usb20 con testmode value - - - usb20 iddig value - - - 1: sel usbphy signal to controller; -0: sel sysctrl register signal(usb20_vbus_valid_sw) to controller. - - - 1:valid -0:not valid - - - 1: USB exit suspend mode after xtal 26m stable -0: USB exit suspend mode not rely on the status of xtal 26m - - - 0: sel ptest_func_clk to instead pll output clock in ptest mode -1: use pll output clock in ptest mode - - - 1:nandflash -0:norflash - - - - PLLS_STS - - - - - - CFG_AON_ANTI_HANG - - 1: sel software force register bit -0: sel hardware signal - - - 1: disable downstream path of aon to rf -0: no disable downstream path of aon to rf - - - 1: sel software force register bit -0: sel hardware signal - - - 1: disable downstream path of aon to cp -0: no disable downstream path of aon to cp - - - 1: sel software force register bit -0: sel hardware signal - - - 1: disable downstream path of aon to ap -0: no disable downstream path of aon to ap - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: sel software force register bit -0: sel hardware signal - - - 1: disable downstream path of aon to psram -0: no disable downstream path of aon to psram - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - - CFG_AON_QOS - - R-channel QOS value of AON - - - W-channel QOS value of AON - - - - AON_AHB_MTX_SLICE_AUTOGATE_EN - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - 鈥1鈥: clock auto gating enable. -鈥0鈥: clock auto gating disable. - - - - DAP_DJTAG_EN_CFG - - 鈥1鈥: enable dap djtag. -鈥0鈥: dap djtag enable by dap jtag chain. - - - - LTE_AHB2AHB_SYNC_CFG - - 鈥1鈥: enable cpu2phy閫氳矾ahb2ahb_sync auto clock gating. -鈥0鈥: disable cpu2phy閫氳矾ahb2ahb_sync auto clock gating. - - - 鈥1鈥: enable cpu2phy閫氳矾ahb2ahb_sync write early_resp_en. -鈥0鈥: disable cpu2phy閫氳矾ahb2ahb_sync write early_resp_en.. - - - 鈥1鈥: enable dma2phy閫氳矾ahb2ahb_sync auto clock gating. -鈥0鈥: disable dma2phy閫氳矾ahb2ahb_sync auto clock gating. - - - 鈥1鈥: enable dma2phy閫氳矾ahb2ahb_sync write early_resp_en. -鈥0鈥: disable dma2phy閫氳矾ahb2ahb_sync write early_resp_en.. - - - - CFG_AON_IO_CORE_IE_0 - - - CFG_AON_IO_CORE_IE_1 - - - CFG_AON_IO_CORE_IE_2 - - - CFG_AON_IO_CORE_IE_3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCC_TUNE_LMT_CFG - - VOLT_TUNE_VAL_MAX[7:5]: -3'b000 : DCDC 0.6V -3'b001 : DCDC 0.7V -3'b010 : DCDC 0.8V -3'b011 : DCDC 0.9V -3'b100 : DCDC 1.0V -3'b101 : DCDC 1.1V -3'b110 : DCDC 1.2V -3'b111 : DCDC 1.3V -VOLT_TUNE_VAL_MAX[4:0] represent 0.1V/32. -The result voltage = VOLT_TUNE_VAL_MAX[7:5] + VOLT_TUNE_VAL_MAX[4:0]*3mV - - - Same to VOLT_TUNE_VAL_MAX - - - - SCC_TUNE_STATUS - - the voltage give to A_DIE for voltage setting: -VOLT_TUNE_VAL[7:5]:change the voltage 100mv for each step; -VOLT_TUNE_VAL[4:0]:change the voltage about 3mv each step - - - the current voltage of A_DIE,observed through ADI bus: -3'b000 : DCDC 0.6V -3'b001 : DCDC 0.7V -3'b010 : DCDC 0.8V -3'b011 : DCDC 0.9V -3'b100 : DCDC 1.0V -3'b101 : DCDC 1.1V -3'b110 : DCDC 1.2V -3'b111 : DCDC 1.3V - - - - SCC_CFG - - Voltage Tune/Obs 0 Interface Select - - - Voltage Tune/Obs 1 Interface Select - - - not used in Whale - - - stop tuning the voltage - - - stop observating of voltage - - - - SCC_TUNE_STEP_CFG - - voltage set down step,fine tuning - - - voltage set up step,fine tuning - - - - SCC_WAIT_CFG - - the time that SCC state_machine remain RND_INTVAL_WAIT - - - the time that SCC state_machine remain VOLT_STB_WAIT - - - - SCC_INT_CFG - - mask status of interrupt caused by tune over - - - mask status of interrupt caused by tune voltage over flow or under flow - - - raw status of interrupt caused by tune over - - - raw status of interrupt caused by tune voltage over flow or under flow - - - clear the interrupt caused by SCC done interrupt - - - clear the interrupt caused by SCC tune error interrupt - - - software configuration to enable the interrupt of SCC - - - software configuration to enable the error interrupt - - - - SCC_TUNE_MARK - - the boundary that need to tune down voltage - - - the boundary that need to tune up voltage - - - - SCC_FSM_STS - - SCC Finite State Machine current state - - - - SCC_ROSC_MODE - - SCC IDEL CTRL - - - SCC Voltage Tuning Bypass - - - SCC Initialization Pattern Fail Halt Bypass - - - SCC ROSC Report Read Control - - - OSC through all the chain in preselected sequence - - - OSC through a sequence in preselected chain - - - REPEAT The RUN Operation - - - - SCC_ROSC_CFG - - SCC ROSC Oscillation duration - - - SCC ROSC Ring Select - - - SCC ROSC Sequence Select - - - SCC ROSC Chain Select - - - - SCC_ROSC_CTRL - - SCC ROSC Report To Read - - - ROSC Gross Ring Enable - - - ROSC RUN - - - - SCC_ROSC_RPT - - Initialization Pattern Fail - - - SCC ROSC REPORT VALID - - - Selected ROSC Setting: GRE + RING number - - - rosc - - - - SCC_ROSC_SW_RST - - SCC ROSC Chain Reset, Active Low - - - - - - - - - DJTAG_IR_LEN - - the instruction register length - - - - DJTAG_DR_LEN - - the data register length - - - - DJTAG_IR - - - DJTAG_DR - - - DR_PAUSE_RECOV - - the signal to recover from PAUSE state - - - - DJTAG_RND_EN - - the signal to start DJTAG scan - - - - DJTAG_UPD_DR - - - DJTAG_DAP_MUX_CTRL_SOFT_RST - - reset of dap mux control chain - - - - - - - - - - soft_cnt_done0_cfg - - apll_1000m_soft_cnt_done counter wait for source stable - - - mempll_1000m_soft_cnt_done counter wait for source stable - - - audio_pll_122m_soft_cnt_done counter wait for source stable - - - xtal_26m_soft_cnt_done counter wait for source stable - - - xtal_lp_26m_soft_cnt_done counter wait for source stable - - - rc26m_78m_soft_cnt_done counter wait for source stable - - - - pll_wait_sel0_cfg - - apll_1000m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - mempll_1000m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - audio_pll_122m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - xtal_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - xtal_lp_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - rc26m_78m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - - pll_wait_sw_ctl0_cfg - - apll_1000m_wait_force_en pll wait's enable sw control - - - mempll_1000m_wait_force_en pll wait's enable sw control - - - audio_pll_122m_wait_force_en pll wait's enable sw control - - - xtal_26m_wait_force_en pll wait's enable sw control - - - xtal_lp_26m_wait_force_en pll wait's enable sw control - - - rc26m_78m_wait_force_en pll wait's enable sw control - - - - div_en_sel0_cfg - - apll_div_1000m_90m9_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_500m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_250m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_125m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_62m5_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_31m2_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_333m3_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_166m7_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_200m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - apll_div_1000m_100m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - audio_div_pll_122m_30m7_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - mempll_div_1000m_500m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control - - - - div_en_sw_ctl0_cfg - - apll_div_1000m_90m9_force_en pre div clock's enable sw control - - - apll_div_1000m_500m_force_en pre div clock's enable sw control - - - apll_div_1000m_250m_force_en pre div clock's enable sw control - - - apll_div_1000m_125m_force_en pre div clock's enable sw control - - - apll_div_1000m_62m5_force_en pre div clock's enable sw control - - - apll_div_1000m_31m2_force_en pre div clock's enable sw control - - - apll_div_1000m_333m3_force_en pre div clock's enable sw control - - - apll_div_1000m_166m7_force_en pre div clock's enable sw control - - - apll_div_1000m_200m_force_en pre div clock's enable sw control - - - apll_div_1000m_100m_force_en pre div clock's enable sw control - - - audio_div_pll_122m_30m7_force_en pre div clock's enable sw control - - - mempll_div_1000m_500m_force_en pre div clock's enable sw control - - - - gate_en_sel0_cfg - - cgm_rtc_32k_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_500m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_400m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_250m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_167m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_125m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_100m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_62_5m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_31_25m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rtc_32k_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_400m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_200m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_lp_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_400m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_333m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_250m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_200m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_167m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_125m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_100m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_62_5m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_31_25m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_audiopll_122_88m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_audiopll_30_72m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_mempll_500m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - - gate_en_sel1_cfg - - cgm_apll_500m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_400m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_250m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_167m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_125m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_apll_62_5m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_xtal_26m_rf_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - - gate_en_sw_ctl0_cfg - - cgm_rtc_32k_ap_force_en clock gating enable sw control - - - cgm_rc_26m_ap_force_en clock gating enable sw control - - - cgm_xtal_26m_ap_force_en clock gating enable sw control - - - cgm_apll_500m_ap_force_en clock gating enable sw control - - - cgm_apll_400m_ap_force_en clock gating enable sw control - - - cgm_apll_250m_ap_force_en clock gating enable sw control - - - cgm_apll_167m_ap_force_en clock gating enable sw control - - - cgm_apll_125m_ap_force_en clock gating enable sw control - - - cgm_apll_100m_ap_force_en clock gating enable sw control - - - cgm_apll_62_5m_ap_force_en clock gating enable sw control - - - cgm_apll_31_25m_ap_force_en clock gating enable sw control - - - cgm_rtc_32k_cp_force_en clock gating enable sw control - - - cgm_xtal_26m_cp_force_en clock gating enable sw control - - - cgm_apll_400m_cp_force_en clock gating enable sw control - - - cgm_apll_200m_cp_force_en clock gating enable sw control - - - cgm_rc_26m_aon_force_en clock gating enable sw control - - - cgm_xtal_26m_aon_force_en clock gating enable sw control - - - cgm_xtal_lp_26m_aon_force_en clock gating enable sw control - - - cgm_apll_400m_aon_force_en clock gating enable sw control - - - cgm_apll_333m_aon_force_en clock gating enable sw control - - - cgm_apll_250m_aon_force_en clock gating enable sw control - - - cgm_apll_200m_aon_force_en clock gating enable sw control - - - cgm_apll_167m_aon_force_en clock gating enable sw control - - - cgm_apll_125m_aon_force_en clock gating enable sw control - - - cgm_apll_100m_aon_force_en clock gating enable sw control - - - cgm_apll_62_5m_aon_force_en clock gating enable sw control - - - cgm_apll_31_25m_aon_force_en clock gating enable sw control - - - cgm_audiopll_122_88m_aon_force_en clock gating enable sw control - - - cgm_audiopll_30_72m_aon_force_en clock gating enable sw control - - - cgm_rc_26m_pub_force_en clock gating enable sw control - - - cgm_xtal_26m_pub_force_en clock gating enable sw control - - - cgm_mempll_500m_pub_force_en clock gating enable sw control - - - - gate_en_sw_ctl1_cfg - - cgm_apll_500m_pub_force_en clock gating enable sw control - - - cgm_apll_400m_pub_force_en clock gating enable sw control - - - cgm_apll_250m_pub_force_en clock gating enable sw control - - - cgm_xtal_26m_gnss_force_en clock gating enable sw control - - - cgm_apll_167m_gnss_force_en clock gating enable sw control - - - cgm_apll_125m_gnss_force_en clock gating enable sw control - - - cgm_apll_62_5m_gnss_force_en clock gating enable sw control - - - cgm_xtal_26m_rf_force_en clock gating enable sw control - - - - monitor_wait_en_status0_cfg - - monitor_wait_en_status , 0:apll_1000m, 1:mempll_1000m, 2:audio_pll_122m, 3:xtal_26m, 4:xtal_lp_26m, 5:rc26m_78m - - - - monitor_div_auto_en_status0_cfg - - monitor_div_auto_en_status , 0:apll_div_1000m_90m9, 1:apll_div_1000m_500m, 2:apll_div_1000m_250m, 3:apll_div_1000m_125m, 4:apll_div_1000m_62m5, 5:apll_div_1000m_31m2, 6:apll_div_1000m_333m3, 7:apll_div_1000m_166m7, 8:apll_div_1000m_200m, 9:apll_div_1000m_100m, 10:audio_div_pll_122m_30m7, 11:mempll_div_1000m_500m - - - - monitor_gate_auto_en_status00_cfg - - - monitor_gate_auto_en_status10_cfg - - monitor_gate_auto_en_status1 , 32:cgm_apll_500m_pub, 33:cgm_apll_400m_pub, 34:cgm_apll_250m_pub, 35:cgm_xtal_26m_gnss, 36:cgm_apll_167m_gnss, 37:cgm_apll_125m_gnss, 38:cgm_apll_62_5m_gnss, 39:cgm_xtal_26m_rf - - - - - - - - - analog_apll_APLL_CTRL1 - - - - - - - - - analog_apll_APLL_CTRL2 - - - - - - - - - - - - - analog_apll_APLL_INT_Value - - - - - analog_apll_APLL_CCS_CTRL - - - - analog_apll_APLL_KSTEP - - - - analog_apll_ANA_BIAS - - - - - - - analog_apll_ANA_BIAS1 - - - - - - - analog_apll_REG_SEL_CFG_0 - - - - - - - - analog_mpll_APLL_CTRL1 - - - - - - - - - analog_mpll_APLL_CTRL2 - - - - - - - - - - - - - analog_mpll_APLL_INT_Value - - - - - analog_mpll_APLL_CCS_CTRL - - - - analog_mpll_APLL_KSTEP - - - - analog_mpll_ANA_BIAS - - - - - - - analog_mpll_ANA_BIAS1 - - - - - - - analog_mpll_REG_SEL_CFG_0 - - - - - - - - analog_iis_pll_APLL_CTRL1 - - - - - - - - - analog_iis_pll_APLL_CTRL2 - - - - - - - - - - - - - analog_iis_pll_APLL_INT_Value - - - - - analog_iis_pll_APLL_CCS_CTRL - - - - analog_iis_pll_APLL_KSTEP - - - - analog_iis_pll_ANA_BIAS - - - - - - - analog_iis_pll_ANA_BIAS1 - - - - - - - analog_iis_pll_REG_SEL_CFG_0 - - - - - - - - analog_efuse4k_EFUSE_PIN_PW_CTL - - - - - analog_efuse4k_REG_SEL_CFG_0 - - - - - analog_efuse2k_EFUSE_PIN_PW_CTL - - - - - analog_efuse2k_REG_SEL_CFG_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - analog_usb20_USB20_TEST_PIN - - - - - - - - - - - analog_usb20_USB20_UTMI_CTL1 - - - - - - - - - - - - - - - - analog_usb20_USB20_BATTER_PLL - - - - - - analog_usb20_USB20_UTMI_CTL2 - - - - - - - - analog_usb20_USB20_TRIMMING - - - - - - - - - - - - analog_usb20_REG_SEL_CFG_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - analog_osc_26m_APLL_CTRL - - - - - - - analog_osc_26m_REG_SEL_CFG_0 - - - - - - - - - - - - - - - - - - cgm_aon_ahb_div_cfg - - cgm_aon_ahb_div: clk_aon_ahb = clk_src/(div +1), default value = 2'h0 - - - - cgm_aon_ahb_sel_cfg - - cgm_aon_ahb_sel: clk_aon_ahb source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: apll_100m, 4: gnss_pll_133m, 5: apll_167m, 6: gnss_pll_198m, 7: apll_200m, default: 3'h1 - - - - - cgm_uart2_bf_div_sel_cfg - - cgm_uart2_bf_div_sel: clk_uart2_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, 4: apll_31_25m, 5: apll_125m, 6: gnss_pll_133m, 7: apll_167m, default: 3'h1 - - - - - cgm_uart3_bf_div_sel_cfg - - cgm_uart3_bf_div_sel: clk_uart3_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, 4: apll_31_25m, 5: apll_125m, 6: gnss_pll_133m, 7: apll_167m, default: 3'h1 - - - - - cgm_debug_host_bf_div_sel_cfg - - cgm_debug_host_bf_div_sel: clk_debug_host_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, default: 2'h1 - - - - - cgm_audio_div_cfg - - cgm_audio_div: clk_audio = clk_src/(div +1), default value = 4'h0 - - - - cgm_audio_sel_cfg - - cgm_audio_sel: clk_audio source , 0: xtal_26m, 1: rc26m_78m, 2: audio_pll_30_72m, 3: apll_31_25m, 4: gnss_pll_33_25m, 5: apll_62_5m, default: 3'h0 - - - - - cgm_codec_mclock_div_cfg - - cgm_codec_mclock_div: clk_codec_mclock = clk_src/(div +1), default value = 4'h0 - - - - cgm_codec_mclock_sel_cfg - - cgm_codec_mclock_sel: clk_codec_mclock source , 0: xtal_26m, 1: rc26m_78m, 2: audio_pll_30_72m, 3: apll_31_25m, 4: gnss_pll_33_25m, 5: apll_62_5m, default: 3'h0 - - - - - cgm_i2s_bck_bf_div_div_cfg - - cgm_i2s_bck_bf_div_div: clk_i2s_bck_bf_div = clk_src/(div +1), default value = 12'hf - - - - cgm_i2s_bck_bf_div_sel_cfg - - cgm_i2s_bck_bf_div_pad_sel: reserved, no use. - - - cgm_i2s_bck_bf_div_sel: clk_i2s_bck_bf_div source , 0: xtal_26m, 1: rc26m_78m, 2: gnss_pll_133m, 3: audio_pll_122_88m, 4: apll_167m, default: 3'h0 - - - - - cgm_out_div_cfg - - cgm_out_div: clk_out = clk_src/(div +1), default value = 8'h0 - - - - cgm_out_sel_cfg - - cgm_out_sel: clk_out source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: audio_pll_122_88m, 4: gnss_pll_133m, 5: apll_167m, default: 3'h1 - - - - - cgm_efuse_sel_cfg - - cgm_efuse_sel: clk_efuse source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, default: 2'h1 - - - - - cgm_adi_sel_cfg - - cgm_adi_sel: clk_adi source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, default: 2'h1 - - - - - cgm_dap_sel_cfg - - cgm_dap_sel: clk_dap source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 - - - - - cgm_djtag_tck_sel_cfg - - cgm_djtag_tck_pad_sel: clock source from pad, high active, default: 1'h0 - - - cgm_djtag_tck_sel: clk_djtag_tck source , 0: rtc_32k, 1: xtal_26m, default: 1'h0 - - - - - cgm_swcgm_hw_sel_cfg - - cgm_swcgm_hw_pad_sel: clock source from pad, high active, default: 1'h0 - - - - - cgm_gpt2_sel_cfg - - cgm_gpt2_sel: clk_gpt2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 - - - - - cgm_i2c3_sel_cfg - - cgm_i2c3_sel: clk_i2c3 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 - - - - - cgm_usb_ref_sel_cfg - - cgm_usb_ref_sel: clk_usb_ref source , 0: rtc_32k, 1: xtal_26m, default: 1'h1 - - - - - cgm_usb_ahb_div_cfg - - cgm_usb_ahb_div: clk_usb_ahb = clk_src/(div +1), default value = 2'h0 - - - - cgm_usb_ahb_sel_cfg - - cgm_usb_ahb_sel: clk_usb_ahb source , 0: rtc_32k, 1: xtal_26m, 2: apll_125m, 3: gnss_pll_133m, 4: apll_167m, 5: apll_200m, default: 3'h1 - - - - - cgm_spi2_div_cfg - - cgm_spi2_div: clk_spi2 = clk_src/(div +1), default value = 3'h0 - - - - cgm_spi2_sel_cfg - - cgm_spi2_pad_sel: clock source from pad, high active, default: 1'h0 - - - cgm_spi2_sel: clk_spi2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_167m, default: 3'h1 - - - - - cgm_scc_sel_cfg - - cgm_scc_pad_sel: clock source from pad, high active, default: 1'h0 - - - - - cgm_sdio_2x_div_cfg - - cgm_sdio_2x_div: reserved, no use. - - - - cgm_sdio_2x_sel_cfg - - cgm_sdio_2x_sel: clk_sdio_2x source , 0: xtal_26m, 1: rc26m_78m, 2: apll_333m, 3: gnss_pll_397m, 4: apll_400m, default: 3'h0 - - - - - cgm_sdio_1x_div_cfg - - cgm_sdio_1x_div: clk_sdio_1x = clk_src/(div +1), default value = 1'h1 - - - - - cgm_busy_src_monitor_cfg0 - - - cgm_busy_src_monitor_cfg1 - - - cgm_busy_src_monitor_cfg2 - - - cgm_busy_src_monitor_cfg3 - - - - - - - - Transmit word or Receive word Write data to this address initiates a character transmission through TX FIFO -Read this address retrieve data from RX fifo - - - Clock divisor Clock divisor bit 0 to 15 - - Specify the clock ratio between spi_sck and clk_spi. -If clk_spi runs at 48 MHz, and spi_sck runs at 12MHz, SPI_CLKD should be 1, -spi_sck = clk_spi/2(n+1). -If IS_FST bit is assert, the valid SPI_CLKD is 0, 1, 2 and 3. - - - - Configure register This register is used to configuration of the SPI interface - - Sync_polarity, positive or negative pulse for SPI or 3-wire mode ,read command polarity - - - 鈥1鈥 : sync mode - - - 鈥1鈥 : spi_sck reverse - - - 1 bit chip select. -鈥0鈥: cs0 is valid -鈥1鈥: cs0 is invalid - - - In default, The input data is shifted high order first into the chip; the output data is shifted out high order first from the Most Significant Bit (MSB) on SO. When this bit is set, the data will be shift out or in from the LSB - - - Transmit data bit number. -鈥0鈥 : 32 bits per word -鈥1鈥 : 1 bits per word -鈥 -鈥31鈥: 31 bits per word - - - 鈥1鈥 enable TX data shift out at clock neg-edge - - - 鈥1鈥 enable RX data shift in at clock neg-edge - - - - Configure register This register is used to configuration of the SPI interface - - 鈥00鈥 : default(follow before version) -鈥01鈥 : spi do stay 0 value when in idle -鈥10鈥 : spi do stay 1 value when in idle -鈥11鈥 : spi do stay last-bit value when in idle - - - 1:is tx mode 0:not tx mode - - - 1:is rx mode 0:not rx mode - - - S8 CD or SYNC signal maps to csn number -鈥0x0001鈥 selects csn0 as cd signal -鈥0x0010鈥 selects csn1 as cd signal -In SPI_HS it must be 0x0000 and disable sync and s8 mode - - - 鈥1鈥 : enable S8 mode - - - 3-wire Melody timing 1, csn high mode enable - - - 鈥1鈥 : enable 3-wire mode - - - 3-wire mode, w/r control position -or the sync pulse position(the pulse will -locates on top of bit N) - - - - Configure register This register is used to configuration of the SPI interface - - 0:DMA TX and RX REQ independent -1:DMA TX REQ are depended on RX REQ status - - - 0: tx_dma_req keep 1 until receiving the tx_dma_ack -1: tx_dma_req is 鈥1鈥 when tx_empty is 鈥1鈥,else 鈥0鈥 - - - 0: rx_dma_req keep 1 until receiving the rx_dma_ack -1: rx_dma_req is 鈥1鈥 when rx_full is 鈥1鈥,else 鈥0鈥 - - - 鈥0鈥 : working on only receive -mode, when rxf_realfull is high, SPI will be held until rxf_realfull is low -鈥1鈥 : no holding - - - 鈥1鈥 enable DMA mode - - - 鈥0鈥 : master -鈥1鈥 : slave, only support microplus mode - - - Read data start bit, used for 3 wire mode and 3 wire 9bit RW mode. -The 3 wire 9bit RW mode reuse this config registers, it indicated read data start position. - - - - RXF watermark SPI RX FIFO FULL/EMPTY watermark - - Receive FIFO data empty threshold. Relative with rx_fifo_empty interrupt - - - Receive FIFO data full threshold. Relative with rx_fifo_full interrupt - - - - Configure register This register is used to configuration of the SPI interface - - working in only receive mode, -鈥0鈥 : SPI send all 0 to slave -鈥1鈥 : SPI send all 1 to slave - - - working in only receive mode, -鈥0鈥 : SPI send all 0 to slave -鈥1鈥 : SPI send all 1 to slave - - - 鈥0鈥 : normal mode -鈥1鈥 : fast mode -Both for matser mode and slave mode,and in master mode SPI_SCK must be quicker than 1/8 spi_clk - - - Phase delay. Relate to fast mode. -When in normal mode, this bit is not used . Only used for slave mode - - - 鈥1鈥 Mask out the first clock pulse in SPI mode - - - Sync_half, sync width is half spi_sck cycle - - - Number of data words ready to receive in 鈥渞eceive only鈥 mode. Only used for master mode. - - - - Configure register This register is used to configuration of the SPI interface - - For master, transmit data interval, programmable n from 0 to 65535, delay is (n*4+3) clock cycle. -For slave, max receive data interval. If the slave has not sampled the edge of spi_clk in the interval(n*4+3), slave will stop the receive process and send timout interrupt - - - - Interrupt enable SPI interrupt enable register - - Rx end interrupt enable - - - Tx end interrupt enable - - - txf_empty interrupt enable - - - Rxf_full interrupt enable - - - Slave mode timeout interrupt enable - - - Rx_overrun_reg interrupt enable - - - - Tx_fifo_full interrupt enable - - - Rx_fifo_empty interrupt enable - - - Rx_fifo_full interrupt enable - - - - Interrupt clear SPI interrupt clear register - - Rx data end interrupt clear - - - Tx data end interrupt clear - - - Write 鈥1鈥 clear slave mode timeout interrupt - - - Write 鈥1鈥 clear Rx_overrun_reg interrupt - - - Write 鈥1鈥 clear Tx_fifo_empty interrupt - - - Write 鈥1鈥 clear Tx_fifo_full interrupt - - - Write 鈥1鈥 clear Rx_fifo_empty interrupt - - - Write 鈥1鈥 clear Rx_fifo_full interrupt - - - - Raw status SPI interrupt raw status - - Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. - - - Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. - - - Raw txf_empty interrupt, This bit is set when the number of tx fifo data byte is less than the tx empty watermark value. Auto cleared when the condition disappears. - - - Raw rxf_full interrupt.This bit is set when the number of rx fifo data byte is larger than the rx full watermark value. Auto cleared when the condition disappears. - - - Raw slave mode time out interrupt - - - Raw Rx_overrun_reg interrupt - - - Txf_empty_w(for debug) - - - Raw Tx_fifo_full interrupt - - - Raw rx_fifo_empty interrupt - - - Rxf_full_r(for debug) - - - - Mask status SPI interrupt mask status - - Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. - - - Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. - - - Txf_empty interrupt mask status. - - - Rxf_full interrupt mask status. - - - Slave mode time out interrupt mask status - - - Rx_overrun_reg interrupt mask status - - - Tx_fifo_full interrupt mask status - - - Rx_fifo_empty interrupt mask status - - - - RXF address SPI RX FIFO write address and read address - - RX FIFO write address - - - RX FIFO read address - - - - latch SPI status SPI status register - - Spi_cs(for debug) - - - Spi_sck(for debug) - - - Spi_txd(for debug) - - - Spi_rxd(for debug) - - - 鈥1鈥 transmit process -鈥0鈥 idle state - - - TX FIFO has no data - - - TX FIFO is real full. (not relates to TX full threshold) - - - RX FIFO has no data - - - RX FIFO is real full. (not relates to TX full threshold) - - - This bit is set when the number of TX FIFO data byte is less than the TX empty interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of TX FIFO data byte is larger than the TX full interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of RX FIFO data byte is less than the RX empty interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of RX FIFO data byte is larger than the RX full interrupt watermark value. Auto cleared when the condition disappears. - - - - DSP Register This register is used for DSP control - - Write data switch. -2鈥檅0: WDATA=PDATA; -2鈥檅1: WDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; -2鈥檅2: WDATA={PDATA[15:0],PDATA[31:16]}; -2鈥檅3: WDATA={PDATA[23:16], PDATA[31:24], PDATA[7:0], PDATA[15:8]}; - - - Read data switch. -2鈥檅0: RDATA=PDATA; -2鈥檅1: RDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; -2鈥檅2: RDATA={PDATA[15:0],PDATA[31:16]}; - - - This register is used for DSP control - - - - RX conunter monitor This register is used to observe the status - - working in only receive mode -as master - - - - TXF configuration This register is used to configuration of the SPI interface - - TX FIFO data empty threshold. Relative with rx_fifo_empty interrupt - - - TX FIFO data full threshold. Relative with rx_fifo_full interrupt - - - - TXF address This register is used to configuration of the SPI interface - - TX FIFO write address - - - TX FIFO read address - - - - FIFO reset configuration Used to reset TX/RX FIFO - - 鈥1鈥 : reset all FIFOs. FIFO address will changed to 0 - - - - Configure register This register is used to configuration of the SPI interface - - 1: two data line function enable -0: two data line function disable - - - 1: enable RGB565 data format -0: disable RGB565 data format - - - 1: enable RGB666 data format -0: disable RGB666 data format - - - 1: enable RGB888 data format -0: disable RGB888 data format - - - 1: SPI slave in Low speed mode -0: SPI slave in High speed mode - - - Used when SPI slave in High speed mode. -1: enable spi slave rtx -0: disable spi slave rtx - - - Use for 3 wire 9bit RW mode and 4 wire 8bit RW mode (SPI_MODE=5 or SPI_MODE=6). -0: Data in and data out of SPI share one IO (SDA). -1: Data in and data out of SPI use separated IO (SDI, SDO). - - - 1: enable ahb2apb bridge read hold when rx fifo empty -0: disable ahb2apb bridge read hold - - - 1: enable ahb2apb bridge write hold when tx fifo full -0: disable ahb2apb bridge write hold - - - 1: select fmark as the dma request -0: select software dma request - - - Used for master only -0: SPI_MODE disable -1: 3 wire 9 bit, cd bit, SDI/SDO share one IO -2: 3 wire 9 bit, cd bit, SDI, SDO -3: 4 wire 8 bit, cd pin, SDI/SDO share one IO -4: 4 wire 8 bit, cd pin, SDI, SDO -5: 3 wire 9bit RW mode, 9 bit command and 8 bit read data, cd bit is enable. Design for LCD driver. -6: 4 wire 8bit RW mode, 8bit command and 8 bit read data. Use CD PAD indicates command or data. Design for LCD driver. - - - CSN select control: -0: CSN 0 -1: CSN 1 -2: CSN 2 -3: CSN 3 - - - CSN IE output set(only slave) -0: not support csn input -1: support csn intput - - - - Statue Register Used to observe csn error - - 1: indicates csn occurring a exception - - - csn for slave - - - - Configure Register Used for configure SPI interface - - Spi tx cd bit: -0: indicates command -1: indicates data - - - Use for 4 wire 8bit RW mode. Determine CD PAD high or low in read data phase. - - - Second data line of two data line function select bit: -0: CD PAD as second data line -1: DI PAD as second data line - - - Two data line RGB data format mode: -0: 1pixel mode -1: 2/3 pixel mode - - - 2-data-line switch. Only valid in 2-data-line mode(DATA_LINE2_EN set to 1): -0: use spi_do as first data line,spi_di as second data line. -1: use spi_di as first data line, spi_do as second data line. - - - Spi tx dummy clock length - - - Indicates tx data length from tx fifo, High 4 bits of spi tx data length - - - - Configure register This register is used to configuration of the SPI interface - - Indicates: spi tx data length from tx fifo, Low 16bit of tx data length - - - - Configure register SPI status register - - Spi rx dummy clock length - - - Indicates receives data length from slave, high 4 bits of spi rx data length - - - - Configure register This register is used to configuration of the SPI interface - - Indicates: spi receives data length from slave, Low 16bit of rx data length - - - - Configure register This register is used to configuration of the SPI interface - - Software TX data request, for write LCD - - - Software RX data request, for read LCD - - - - Statue Register Used to observe TX data counter - - Tx data cnt - - - - Statue Register Used to observe TX statue - - tx dummy counter - - - tx data counter - - - - Statue Register Used to observe RX data counter - - Rx data cnt - - - - Statue Register Used to observe RX statue - - rx dummy counter - - - rx data counter - - - - Statue Register Used to observe spi version - - Spi version - - - - - - - - - - - refclk_sel - - - Input triger number count enable - - - slave_mode trigger select - - - auto preload value - - - Center-aligned mode select 00: disable , other:enable - - - counter dir , 0: cnt ++ , 1: cnt -- - - - one pulse mode, 0:disable 1:enable - - - update disable, 0:disable, 1:enable - - - clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass - - - counter enable, 0: disbale, 1:enable - - - - - - slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable - - - - - - bit type is changed from w1c to rc. user trigger gen - - - - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[24] 0: output enable, 1 output disable bit[25] 0: use ti4, 1: use ti3 - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[17] 0: output enable, 1 output disable bit[16] 0: use ti3, 1: use ti4 - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 - - - - - - ti4 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti4 prescale, 01:0 div2, 10: div4, others: bypass - - - ti3 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti3 prescale, 01:0 div2, 10: div4, others: bypass - - - ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti2 prescale, 01:0 div2, 10: div4, others: bypass - - - ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti1 prescale, 01:0 div2, 10: div4, others: bypass - - - - - - ti4 polarity - - - ti4 enable - - - ti3 polarity - - - ti3 enable - - - ti2 polarity - - - ti2 enable - - - ti1 polarity - - - ti1 enable - - - - - - cnt_value - - - - - - cnt prescale value - - - - - - cnt max value - - - - - - ic1 capture value - - - - - - ic2 capture value - - - - - - ic3 capture value - - - - - - ic4 capture value - - - - - - ic1 compare value - - - - - - ic2 compare value - - - - - - ic3 compare value - - - - - - ic4 compare value - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - bit type is changed from w1c to rc. trig gens, when counter works in slave mode - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - Spinlock Total Status Register - - - - Spinlock Master ID Registers - - - - Spinlock Individual Status Registers - - Read 0x0000_0000, Request and get the lock. -Read 0x0000_0001, Request but does not get the lock. -Write Unlock Token, Unlock the lock. -Write not Unlock Token, takes no effect. - - - - - Spinlock Version ID Register - - - - - - - - - cgm_ap_a5_div_cfg - - cgm_ap_a5_div: clk_ap_a5 = clk_src/(div +1), default value = 2'h0 - - - - cgm_ap_a5_sel_cfg - - cgm_ap_a5_sel: clk_ap_a5 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_400m, 5: apll_500m, default: 3'h1 - - - - - cgm_ap_bus_div_cfg - - cgm_ap_bus_div: clk_ap_bus = clk_src/(div +1), default value = 2'h1 - - - - - cgm_uart4_bf_div_sel_cfg - - cgm_uart4_bf_div_sel: clk_uart4_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 - - - - - cgm_uart5_bf_div_sel_cfg - - cgm_uart5_bf_div_sel: clk_uart5_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 - - - - - cgm_uart6_bf_div_sel_cfg - - cgm_uart6_bf_div_sel: clk_uart6_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 - - - - - cgm_spiflash1_sel_cfg - - cgm_spiflash1_sel: clk_spiflash1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_500m, default: 3'h1 - - - - - cgm_spiflash2_sel_cfg - - cgm_spiflash2_sel: clk_spiflash2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_500m, default: 3'h1 - - - - - cgm_camera_pix_div_cfg - - cgm_camera_pix_div: clk_camera_pix = clk_src/(div +1), default value = 11'h7 - - - - cgm_camera_pix_sel_cfg - - cgm_camera_pix_sel: clk_camera_pix source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 - - - - - cgm_camera_ref_div_cfg - - cgm_camera_ref_div: clk_camera_ref = clk_src/(div +1), default value = 11'h7 - - - - cgm_camera_ref_sel_cfg - - cgm_camera_ref_sel: clk_camera_ref source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 - - - - - cgm_camera_csi_div_cfg - - cgm_camera_csi_div: clk_camera_csi = clk_src/(div +1), default value = 11'h7 - - - - cgm_camera_csi_sel_cfg - - cgm_camera_csi_sel: clk_camera_csi source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 - - - - - cgm_camera_csi_data_hs_sel_cfg - - cgm_camera_csi_data_hs_pad_sel: clock source from pad, high active, default: 1'h0 - - - - - cgm_spi1_sel_cfg - - cgm_spi1_sel: clk_spi1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_133m, 4: apll_167m, default: 3'h1 - - - - - cgm_i2c1_sel_cfg - - cgm_i2c1_sel: clk_i2c1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 - - - - - cgm_i2c2_sel_cfg - - cgm_i2c2_sel: clk_i2c2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 - - - - - cgm_gpt3_sel_cfg - - cgm_gpt3_sel: clk_gpt3 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 - - - - - cgm_26m_sel_cfg - - cgm_26m_sel: clk_26m source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, default: 2'h1 - - - - - cgm_busy_src_monitor_cfg0 - - - cgm_busy_src_monitor_cfg1 - - - cgm_busy_src_monitor_cfg2 - - cgm_busy_src_monitor2, 64:(cgm_uart5_bf_div_sel_ac == 3) & cgm_busy_uart5_bf_div 65:(cgm_uart6_bf_div_sel_ac == 3) & cgm_busy_uart6_bf_div 66:cgm_busy_ap_a5_sel_0 & cgm_busy_ap_a5_src 67:(cgm_uart4_bf_div_sel_ac == 0) & cgm_busy_uart4_bf_div 68:(cgm_uart5_bf_div_sel_ac == 0) & cgm_busy_uart5_bf_div 69:(cgm_uart6_bf_div_sel_ac == 0) & cgm_busy_uart6_bf_div 70:cgm_busy_spiflash1_sel_0 & cgm_busy_spiflash1 71:cgm_busy_spiflash2_sel_0 & cgm_busy_spiflash2 72:(cgm_camera_pix_sel_ac == 0) & cgm_busy_camera_pix 73:(cgm_camera_ref_sel_ac == 0) & cgm_busy_camera_ref 74:(cgm_camera_csi_sel_ac == 0) & cgm_busy_camera_csi 75:(cgm_spi1_sel_ac == 0) & cgm_busy_spi1 76:(cgm_i2c1_sel_ac == 0) & cgm_busy_i2c1 77:(cgm_i2c2_sel_ac == 0) & cgm_busy_i2c2 78:(cgm_gpt3_sel_ac == 0) & cgm_busy_gpt3 79:cgm_busy_32k 80:(cgm_26m_sel_ac == 0) & cgm_busy_26m - - - - - - - - - CLK_AP_MODE0 - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - - CLK_AP_EN0 - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - - CLK_AP_MODE1 - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - - CLK_AP_EN1 - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - - CLK_AP_MODE2 - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - Clock Gating Mode. -0 : Clock Auto Gating ; -1 : Clock Manual Gating ; - - - - CLK_AP_EN2 - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - When Clock Manual Gating Mode. -0 : Manual Clock Disable Gating ; -1 : Manual Clock Enable Gating ; - - - - AP_RST0 - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - - AP_RST1 - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - - AP_RST2 - - Soft Reset. Active High; -0 : in normal mode; -1 : Reset; - - - - M0_LPC - - - - - - M1_LPC - - - - - - M2_LPC - - - - - - M3_LPC - - - - - - M4_LPC - - - - - - M5_LPC - - - - - - M6_LPC - - - - - - M7_LPC - - - - - - M8_LPC - - - - - - M9_LPC - - - - - - S0_LPC - - - - - - S1_LPC - - - - - - S2_LPC - - - - - - S3_LPC - - - - - - S4_LPC - - - - - - S5_LPC - - - - - - S6_LPC - - - - - - MAIN_LPC - - - - - - CACHE_EMMC_SDIO - - arcache of emmc - - - awcache of emmc - - - - MISC_CFG - - 1: If camera fifo is almost full, disable clk_camera_out - - - 1: clk_camera_out enable - - - 1: invert pix clk polarity. -0: keep pix clk polarity. - - - ap ifc dma not operate error response from bus - - - med read data from bus instead of flash - - - gic400 cfgsdisable - - - - CHIP_PROD_ID - - production id - - - bond id - - - metal id - - - - CFG_QOS0 - - lzma_awqos - - - lzma_arqos - - - emmc_awqos - - - emmc_arqos - - - ce_awqos - - - ce_arqos - - - ap_a5_awqos - - - ap_a5_arqos - - - - CFG_QOS1 - - aon_awqos - - - aon_arqos - - - ap_ifc_awqos - - - ap_ifc_arqos - - - usb_awqos - - - usb_arqos - - - gouda_awqos - - - gouda_arqos - - - - CFG_QOS2 - - ap_axidma_awqos - - - ap_axidma_arqos - - - med_awqos - - - med_arqos - - - - DEBUG_MONITOR - - med dbg bus select - - - - XHB_AWSPARSE - - ap2aon xhb400 awsparse - - - spiflash2 xhb400 awsparse - - - spiflash1 xhb400 awsparse - - - ap_ahb xhb400 awsparse - - - - CLK_MNT26M_TH0 - - monitor counter number of rc26m - - - - CLK_MNT26M_TH1 - - monitor interval counter number of rc26m - - - - CLK_MNT26M_TH2 - - monitor counter number of xtal26m, low limited - - - - CLK_MNT26M_TH3 - - monitor counter number of xtal26m, high limited - - - - CLK_MNT32K_TH0 - - monitor counter number of 32k clock, low limited - - - - CLK_MNT32K_TH1 - - monitor counter number of 32k clock, high limited - - - - CLK_MNT_CTRL - - - - - - - - - CFG_BRIDGE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CGM_GATE_AUTO_SEL0 - - - CGM_GATE_AUTO_SEL1 - - - CGM_GATE_AUTO_SEL2 - - - CGM_GATE_AUTO_SEL3 - - - CGM_GATE_FORCE_EN0 - - - CGM_GATE_FORCE_EN1 - - - CGM_GATE_FORCE_EN2 - - - CGM_GATE_FORCE_EN3 - - - MNT_GATE_EN_STATUS0 - - - MNT_GATE_EN_STATUS1 - - - MNT_GATE_EN_STATUS2 - - - MNT_GATE_EN_STATUS3 - - - MNT_CGM_BUSY_STATUS0 - - - MNT_CGM_BUSY_STATUS1 - - - MNT_CGM_BUSY_STATUS2 - - - MNT_CGM_BUSY_STATUS3 - - - MNT_CGM_BUSY_STATUS4 - - - - CFG_CLK_UART4 - - numerator - - - denominator - - - - CFG_CLK_UART5 - - numerator - - - denominator - - - - CFG_CLK_UART6 - - numerator - - - denominator - - - - CFG_CLK_SPIFLASH1 - - select spiflash1 controller clock frequency. default 26MHz - - - - CFG_CLK_SPIFLASH2 - - select spiflash2 controller clock frequency. default 26MHz - - - - CFG_CLK_APCPU_DBGEN - - 1: clock div disable; -0: clock div enable; - - - 0: no div; -1: 2div; -2: 3div; -3: 4div; -4: 5div; -5: 6div; -6: 7div; -7: 8div; - - - - LP_FORCE - - - - - - - - - - - - - - - - - - - - - SLEEP_CTRL - - - - - - - - - - - - - - - - - - - - 1: when ap_sys enter deepsleep, this bit can bypass ap_a5 wfi signal, only care about slp_req signal. - - - 1: when ap_a5 enter wfi, the ap_a5 clock will auto switch to rc26MHz and the bus clock will auto change along with the ap_a5 clock. - - - 1: when ap_a5 enter wfi, ap_a5 clk will be stopped. - - - 1: when ap_a5 enter wfi, the ap_a5 clock will auto switch to xtal26MHz and the bus clock will auto change along with the ap_a5 clock. - - - 1: when ap_sys enter deepsleep, this bit can prevent fiq/irq from waking up ap_a5 exit wfi. - - - - LIGHT_SLEEP_BYPASS0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LIGHT_SLEEP_BYPASS1 - - - - - - - - - - - - - - - - - - - - - - - - - - ANTI_HANG - - 1: ap a5 can receive error response from matrix; -0: error response from matrix to ap a5 will be masked; - - - lzma/ap_imem/ap_busmon/apb_reg/gouda/tiimer1/timer2/i2c1/i2c2/gpt3/ap_clk - - - uart4/uart5/uart6/sdmmc/camera/ap_ifc - - - med/ce_pub/ce_sec/emmc/spi1 - - - spiflash1/spiflash2/ap_axidma/usb - - - - - - - AP_APB_RSD0 - - - AP_APB_RSD1 - - - AP_APB_RSD2 - - - AP_APB_RSD3 - - - AP2PUB_BRIDGE_STATUS - - - - - - AP2PUB_BRIDGE_DEBUG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - axi bus status and dma work state status - - axi write data channel ready - - - axi write address channel ready - - - axi read address channel ready - - - dma is working,and CPU can't access ce registers except ce_clear register. - - - dma write port state: 4'd0: idle 4'd1: write burst calculate 4'd2: write burst calculate data number 4'd3: write burst wait enough data 4'd4: write burst start 4'd5: write burst execute 4'd6: write burst wait burst end 4'd7: write burst end - - - dma read port state: 4'd0: idle 4'd1: read burst wait enough buffer space 4'd2: read burst wait one cycle 4'd3: read burst start 4'd4: read burst execute 4'd5: read burst wait burst end 4'd6: read burst done - - - pka cmd fifo is non-empty - - - cmd fifo is non-empty - - - interrupt raw status is valid - - - ce in error status - - - dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done - - - 3'd0: idle 3'd1: pka read instruction start 3'd2: pka load start 3'd3: pka wait done 3'd4: pka send done 3'd5: pka jump judgement - - - dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done - - - - aes module state - - rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done - - - rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - sm4 state: 3'd0: idle 3'd1: generate key 3'd2: round start 3'd3: rounding 3'd4: xts generate key 3'd5: xts round start 3'd6: xts rounding 3'd7: done - - - wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait - - - - tdes module state - - tdes module status: [3:0]: des run cycle counter -[4]: des key check error - - - generate wvalid state: 4'd0: idle 4'd1: wait enough data 4'd2: generate wvalid 4'd3: wait enough data when bursting 4'd4: wait wready for next burst data - - - efuse access status: 5'd0: idle 5'd1: read selec between hmac and symmetric 5'd2: trng write start 5'd3: hmac session key read start 5'd4: trng write 5'd5: hmac read 5'd6: symmetric key1 read start 5'd7: symmetric key2 read start 5'd8: symmetric key1 read 5'd9: symmetric key2 read 5'd10: done 5'd11: hmac session key read 5'd12: read huk after write err 5'd13: trng write next 5'd15: iram key done 5'd16: pka non-symmetric key read start 5'd17: pka non-symmetric key read 5'd18: pka non-symmetric key write start 5'd19: pka non-symmetric key write 5'd20: pka non-symmetric key write next 5'd21: ce read non-symmetric key after write err - - - 3'd0: idle 3'd1: pka store start 3'd2: pka wait done 3'd3: pka send done 3'd4: pka jump judgement - - - dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 5'd20: pka store start 5'd21: pka wait done 5'd22: pka send done 5'd23: pka jump judgement - - - [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait - - - - hash module state 0 - - - hash module state 1 - - hash module status: [2:0]: hash state 3'd0: idle 3'd1: data request 3'd2: no-hmac 3'd3: hmac key 3'd4: first hmac message 3'd5: second hmac message 3'd6: digest out [8:3]: hash run cycle - - - - - ce module clock enable - - force fde aes clock enable - - - force pub rng autogate clock enable - - - pub trng clock enable - - - force chacha engine clock enable - - - force poly engine clock enable - - - force rng autogate clock enable - - - force aes key expan autogate clock enable - - - force dma axi autogate clock enable - - - force dma ctrl autogate clock enable - - - force apb regbank autogate clock enable - - - simon speck clock enable - - - pka clock enable - - - chacha poly clock enable - - - sm4 clock enable - - - trng clock enable - - - des clock enable - - - hash clock enable - - - fde aes clock enable - - - aes clock enable - - - dma_main clock enable - - - - ce interrupt enable - - enable pka load efuse addr is out of range int - - - enable pka store efuse addr is out of range int - - - enable pka load or store length is zero int - - - enable ce pka one task done flag - - - enable can't fime prime int - - - enable divisor zero int - - - enable ce use efuse error int - - - enable ce pka one cmd done int - - - enable ce pka store done int - - - enable rng/trng int - - - enable tdes key check error int - - - enable src/dst length error int - - - enable the efuse huk check zero int - - - enable the efuse huk check unstable int - - - enable one command done int - - - - ce interrupt status - - pka load efuse addr is out of range - - - pka store efuse addr is out of range,when the int is valid , ap clear it ,and then need reset the ce - - - pka load or store length is zero - - - ce pka one task done flag - - - can't fime prime flag - - - divisor zero flag - - - ce use efuse error flag - - - ce pka one cmd done flag - - - ce pka store done flag - - - ce rng/trng int status - - - ce tdes key check error int status - - - src/dst length error int status - - - when ce write the huk parameters, the efuse ctrl response the error, then ce will check the write huk parameters is 0 or not; if it is 0, then intrrupt - - - when ce write the huk parameters, the efuse ctrl response the error, then ce will check the write huk parameters is 0 or not; if it is not 0 & is unstable, then intrrupt - - - one command done int status, - - - - ce interrupt clear - - clear pka load efuse addr is out of range int - - - clear pka store efuse addr is out of range int - - - clear pka load or store length is zero int - - - clear ce pka one task done flag - - - clear can't fime prime int - - - clear divisor zero int - - - clear ce use efuse error flag - - - clear ce pka one cmd done flag - - - clear ce pka store done flag - - - clear tdes key check error int status - - - clear error int status - - - clear the huk is zero int - - - clear the huk is unstable int - - - clear one command done int status, - - - - start ce - - start ce one fo the AES/SM4/HASH cipher module - - - - clear ce - - reset ce status one fo the AES/SM4/HASH cipher module - - - - aes work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 0: rtl rotation, 1: no-rotation - - - 00: key 128bits,01:192bits,10,11:256bits - - - 0000:ECB,0001:CBC,0010:CTR,0011:XTS,0100:CMAC,0101:GCM,0110:GMAC,0111:CCM,1000:CBCMAC,1001:CFB,1010:OFB - - - aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid - - - 0:encode,1:decode - - - aes module enable - - - - tdes work mode cfg - - 0: disable, 1: enable even/odd check - - - 0:odd check,1:even check - - - 00:ECB,01:CBC - - - 0:encode,1:decode - - - tdes module enable - - - - hash work mode cfg - - sha3 shake out length - - - 00: normal hash; 01: ipad ;10: opad; 11: reserved - - - hash work module, -5鈥檇0: Doesn鈥檛 work -5鈥檇1: MD5 -5鈥檇2: SHA-1 mode -5鈥檇3: SHA-224 mode -5鈥檇4: SHA-256 mode -5鈥檇5: SHA-384 mode -5鈥檇6: SHA-512 mode -5鈥檇7: SHA-512/224 mode -5鈥檇8: SHA-512/256 mode -5鈥檇9: SM3 mode -5鈥檇10: SHA3-224 -5鈥檇11: SHA3-256 -5鈥檇12: SHA3-384 -5鈥檇13: SHA3-512 -5鈥檇14: SHA3-SHAKE128 -5鈥檇15: SHA3-SHAKE256 - - - hash module enable - - - - chacha poly work mode cfg - - 00:chacha20 ; 01:poly1305; -10:AEAD_CHACHA20_POLY1305 - - - 0:encrypt,1:decrypt - - - chacha poly module enable - - - - simon speck work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 00: key 128bits,01:192bits,10:256bits - - - 000:ECB,001:CBC,010:CTR,100:CFB,101:OFB - - - 0:speck; 1:simon - - - 0:encrypt,1:decrypt - - - chacha poly module enable - - - - ce basic configure - - switch source high 32bits and low 32bits - - - switch destination high 32bits and low 32bits - - - source data switch of one word - - - destination data switch of one word - - - 0:disable hdcp mode, 1: enable hdcp mode - - - list update iv/sec/cnt flag - - - data end in link list mode - - - list end flag - - - 0: isn't aad list 1: is aad list - - - 0: aad no-end list 1: aad end list - - - wait axi B channel bready - - - 0:normal mode, 1: iram key or secure ddr key - - - 0: normal mode, 1: aes/sm4 key from session key - - - 0: normal mode, 1: aes/sm4 key from efuse - - - 1: all crypto key in ddr/iram; 0: from registers - - - 0:normal mode, 1: bypass ce - - - 0: std flag 1: std aad flag - - - 0: std aad no-end flag 1: std aad end flag - - - std end flag - - - 0: enable cmd int output: 1: don't output int - - - 0: dump from ddr; 1: don't dump - - - 0: rcv from ddr; 1: don't rcv - - - 0:std mode, 1: link mode - - - - dma read port node data length - - source address high 4bits; or aes mac aad address high 4bits - - - source fragment length of each node; or aes mac aad length - - - - dma write port node data length - - destination address high 4bits - - - destination fragment length of each node - - - - dma source address - - - dma destination address - - - dma one length - - ce_list_ptr high 4bits - - - first list length,support max 256 nodes - - - - dma list pointer - - - aes tdes rsa key length - - aes hmac key address high 4bits - - - aes hmac key length - - - - aes tdes rsa key address - - - aes tag length - - aes tag address high 4bits - - - aes tag length - - - - aes tag address - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - sm4 work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 0: rtl rotation, 1: no-rotation - - - 000:ECB,001:CBC,010:CTR,011:XTS,100:CFB,101:OFB - - - 0:encode,1:decode - - - sm4 module enable - - - - - IP version - - r4 - - - px - - - - pka work mode cfg - - pka instruction address high 4bits - - - switch source high 32bits and low 32bits - - - switch destination high 32bits and low 32bits - - - source data switch of one word - - - destination data switch of one word - - - find prime counter threshold - - - pka register number select; 0: 32, 1:16 - - - pka module enable - - - - pka register length01 - - ce pka register length1 - - - ce pka register length0 - - - - pka register length23 - - ce pka register length3 - - - ce pka register length2 - - - - - pka instruction pointer - - divisor zero - - - ce pka infinity point - - - ce pka mod inv error - - - ce pka add/sub carry - - - can't fime prime - - - 1: pka one cmd instruction done - - - 1: pka store instruction done - - - pka instruction pointer - - - - pka debug info - - - pka debug info - - - pka debug info - - - pka debug info - - - - ce performace counter - - - ce use flag - - the signal only can be confgi in the security apb,when the ce write the huk parameter,the bit should be 1'b1; - - - when the siganl is high ,then flag the pub aes/sm4/hash is catch the cmd from the pub cmd buf or the pub is working - - - when the siganl is high ,then flag the sec aes/sm4/hash is catch the cmd from the sec cmd buf or the sec is working - - - ce sec or pub use the ce aes/sm4/hash cicpher module - - - - axi bus cache - - axi read port outstanding number - - - axi write port outstanding number - - - axi bus wcache - - - axi bus rcache - - - - cmd stop ctrl - - to restart - - - 1: stop command is valid - - - 0: to execute next cmd; 1: finish current cmd,then stop - - - to restart - - - 1: stop command is valid - - - 0: to execute next cmd; 1: finish current cmd,then stop - - - - axi prot sel - - reserved - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: disable pka side sel; 1: enable pka side axi sel - - - reserved - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: disable sec side sel; 1: enable sec side axi sel - - - - ce performace counter high 32 bit - - - - RNG module enable RNG module enable - - if the signal is high,then the rng data come from cpu. - - - if the signal is high,then the osc rings sel signal come from rf_rng_src_sel_enable. - - - if the signal is high,then the osc rings is auto choose to work - - - the signal control which osc ring is work,when the least bit is high,then the first one osc ring is choose as the entropy. - - - trng source test enable - - - the rst signal to the exotic trng module - - - the signal can change when the trng is work ,which can control the trng start or stop by cpu. - - - trng source enable - - - RNG module enable bit: -1:enbale RNG module to generate random number when auto mode is not enable - - - - RNG module config RNG module config - - Threshold bit value for random data , indicates that the cycle of the src_en is high, the max value is 12'hFFF. - - - when the data_in is 0,the test result should be 1,and the data_in is 1,the test result should be 0; - - - Threshold value for rng_data_valid, indicates that when rng_data_valid high, there area at least number of rng_data_valid_threshold words in SRAM锛宼he max value is 4'hf. - - - ce_rng_exotic_fault_rst_sel: 1'b0:the rst generated by the fault signal, 1'b1:don't generated the rst signal,the rst signal come from the cpu - - - local RNG entropty source select - - - when it's 1,the the post process module need data bitwith is 440bit,else is 256bit - - - the signal select the trng data come from exotic or local trng module 1:exotic 0:local - - - select entropy source,the range is 0x0 to 0x7 - - - - RNG data for cpu to read RNG data for cpu to read - - - time interval between two samples time interval between two samples - - enable first level sample - - - sample period between two samples, the value is from 0 to 255 - - - sample period between two samples, the value is from 0 to 255 - - - - post process functions select post process functions select - - when it's 1,the the PRNG data xor with trng data - - - when it's 1,the the final post process module is enable - - - when it's 1,the the xor process module is enable - - - when it's 1,the the cycle_code module is enable - - - when it's 1,the the lfsr module is enable - - - - post data path 1 enable - - - post data path 0 enable - - - - rng work status rng work status - - rand data number when keygen done - - - 2'b01:Instantiate ; 2'b10:Reseed ; 2'b11:Genarate. - - - when it's 1,cpu can send next 64bit pattern - - - when it's 1,the drbg KAT test fail - - - DRBG KAT test done - - - when it's 1,the start-up/on-demand test fail(1024 sample) - - - start-up/on-demand test done - - - the result of test mode - - - when it's 1,indicate that the drbg test result data in 0x260 register is valid (cpu can read to check) - - - 2'b01: C [439:0] ; 2'b10: V[439:0] ; 2'b11: reseed_counter[31:0]. Corresponds to the data of each process in [15:14] . - - - the fifo status - - - the exotic rng module status - - - - when high indicates that RNG module has generate 256 bits random data - - - when high indicates that auto mode is ongoing, CPU can't access rng_data register - - - - rng time out counter rng time out counter - - - rng interrupt enable rng interrupt enable - - enable continuous health test interrupt - - - enable sram short interrupt - - - enable timeout interrupt - - - enable process2 interrupt - - - enable process1 interrupt - - - enable process0 interrupt - - - - rng interrupt status rng interrupt status - - continuous health test interrupt status - - - sram_short_interrrupt status - - - timeout interrrupt status - - - process2 interrrupt status - - - process1 interrrupt status - - - process0 interrrupt status - - - - rng interrupt clear rng interrupt clear - - clear continuous health test interrupt - - - clear sram short interrupt - - - clear timeout interrupt - - - clear process2 interrupt - - - clear process1 interrupt - - - clear process0 interrupt - - - - RNG module work mode RNG module work mode - - PRNG work mode: -1: Auto Seed update Mode -0: Mannual seed update Mode - - - RNG module work mode: -10: PRNG mode -01: TRNG mode 00锛11: Mixed mode for TRNG - - - - PRNG mode seed update config PRNG mode seed update config - - When Write to 1, PRNG will update seed to PRNG_SEED_CONFIG register value - - - - PRNG mode seed update config PRNG mode seed update config - - - RNG Bit Rate RNG Bit Rate - - RNG Bit Counter - - - RNG Bit number each 10000 clock cycle - - - - SRAM data numuber threshold SRAM data numuber threshold - - SRAM data numuber threshold, - - - - rng_sram_data_residue_num rng_sram_data_residue_num - - rng_sram_data_residue_num - - - - exotic fault counter rng exotic fault counter config - - config the fault counter and read the counter - - - - drbg seed count drbg seed count - - config the drbg seed after certain time - - - - config ring ring number config ring ring number - - - config ring ring number config ring ring number - - - rng_health_test_config rng_health_test_config - - default:11'd607(freq 0/1 in 1024) - - - default:6'd47 (conse 48 0/1) [23] - - - open drbg test(on-demand test) - - - open es test(on-demand test) - - - - ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_l - - - ce_rng_drbg_test_pattern_h ce_rng_drbg_test_pattern_h - - - raw_random_number raw_random_number - - - ce_rng_drbg_sha256_result ce_rng_drbg_sha256_result - - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - ce secure key work mode - - trng output random data for secure key flag;when 256bits HUK output into efuse,the bit will be zero. - - - cpu access secure key flag;the falling edge is to let efuse controller sync data into efuse memory - - - secure key length configure for key in efuse feature,when read key from efuse, need know this key length - - - secure key2 start read address of efuse memory - - - secure key1 start read address of efuse memory - - - need to read secure key2 from efuse;when need two key(key1 and key2), this bit should be set. - - - - ce huk key config - - HUK key initial address - - - HUK key length - - - - ce pka key config - - PKA private key end address,default value depends on the parameter value passed by AP to CE top,this register writing funciton is standing off . - - - PKA private key start address,default value depends on the parameter value passed by AP to CE top ,this register writing funciton is standing off . - - - - - ce_cmd_fifo_entry - - - ce_cmd_fifo_status - - - ce_rcv_addr_lo - - - ce_dump_addr_lo - - - ce_dump_addr_hi - - ce dump address hi - - - ce rcv address hi - - - - ce_finish_cmd_cnt - - - - ce_pka_cmd_fifo_entry - - - ce_pka_cmd_fifo_status - - - pka cmd dma source address - - - pka store dma destination address - - pka store high 19bits addr - - - - pka load address - - pka load high 19bits addr - - - - ce_pka_finish_cmd_cnt - - - start ce pka - - start ce pka - - - - clear ce pka - - reset ce pka status - - - - - ce_pka_rng_force_ssb_bit - - force the prime ssb bit is 1 - - - - ce_pka_ctrl_operate_bit - - this bit control the store inst, -1:when the bit set 1, then the store data from pka ram to ddr don't have any limit; -when the bit set 0, then the store inst need judge the buf can store out or not, the store register index can config through the pka load_rng inst; - - - - pka write efuse and read efuse work status - - bit[23]:reserved bit[22]:pka read efuse cmd vaild; bit[21]:pka write efuse cmd vaild; bit[20]:used to control pka load FSM state jump; - - - bit[19]:indicates pka would read efuse when the huk is reading or writing efuse; bit[18]:indicates pka would write efuse when the huk is reading or writing efuse; bit[17]:indicates huk would read efuse when the pka is reading or writing efuse; bit[16]:indicates huk would write efuse when the pka is reading or writing efuse; - - - depend on read pka private key length,ce top starts to count,when this count - - - depend on write pka private key length,ce top starts to count - - - - - - - - - axi bus status and dma work state status - - axi write data channel ready - - - axi write address channel ready - - - axi read address channel ready - - - dma is working,and CPU can't access ce registers except ce_clear register. - - - dma write port state: 4'd0: idle 4'd1: write burst calculate 4'd2: write burst calculate data number 4'd3: write burst wait enough data 4'd4: write burst start 4'd5: write burst execute 4'd6: write burst wait burst end 4'd7: write burst end - - - dma read port state: 4'd0: idle 4'd1: read burst wait enough buffer space 4'd2: read burst wait one cycle 4'd3: read burst start 4'd4: read burst execute 4'd5: read burst wait burst end 4'd6: read burst done - - - fde cmd fifo is non-empty - - - cmd fifo is non-empty - - - interrupt raw status is valid - - - ce in error status - - - dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done - - - 3'd0: idle 3'd1: pka read instruction start 3'd2: pka load start 3'd3: pka wait done 3'd4: pka send done 3'd5: pka jump judgement - - - dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done - - - - aes module state - - rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done - - - rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - sm4 state: 3'd0: idle 3'd1: generate key 3'd2: round start 3'd3: rounding 3'd4: xts generate key 3'd5: xts round start 3'd6: xts rounding 3'd7: done - - - wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish - - - [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait - - - - tdes module state - - tdes module status: [3:0]: des run cycle counter -[4]: des key check error - - - generate wvalid state: 4'd0: idle 4'd1: wait enough data 4'd2: generate wvalid 4'd3: wait enough data when bursting 4'd4: wait wready for next burst data - - - efuse access status: 5'd0: idle 5'd1: read selec between hmac and symmetric 5'd2: trng write start 5'd3: hmac session key read start 5'd4: trng write 5'd5: hmac read 5'd6: symmetric key1 read start 5'd7: symmetric key2 read start 5'd8: symmetric key1 read 5'd9: symmetric key2 read 5'd10: done 5'd11: hmac session key read 5'd12: read huk after write err 5'd13: trng write next 5'd15: iram key done 5'd16: pka non-symmetric key read start 5'd17: pka non-symmetric key read 5'd18: pka non-symmetric key write start 5'd19: pka non-symmetric key write 5'd20: pka non-symmetric key write next 5'd21: ce read non-symmetric key after write err - - - 3'd0: idle 3'd1: pka store start 3'd2: pka wait done 3'd3: pka send done 3'd4: pka jump judgement - - - dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 5'd20: pka store start 5'd21: pka wait done 5'd22: pka send done 5'd23: pka jump judgement - - - [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait - - - - hash module state 0 - - - hash module state 1 - - hash module status: [2:0]: hash state 3'd0: idle 3'd1: data request 3'd2: no-hmac 3'd3: hmac key 3'd4: first hmac message 3'd5: second hmac message 3'd6: digest out [8:3]: hash run cycle - - - - - ce module clock enable - - force fde aes clock enable - - - force pub rng autogate clock enable - - - pub trng clock enable - - - force chacha engine clock enable - - - force poly engine clock enable - - - force rng autogate clock enable - - - force aes key expan autogate clock enable - - - force dma axi autogate clock enable - - - force dma ctrl autogate clock enable - - - force apb regbank autogate clock enable - - - simon speck clock enable - - - pka clock enable - - - chacha poly clock enable - - - sm4 clock enable - - - trng clock enable - - - des clock enable - - - hash clock enable - - - fde aes clock enable - - - aes clock enable - - - dma_main clock enable - - - - ce interrupt enable - - enable src/dst length error int - - - enable one command done int - - - enable src/dst length error int - - - enable one command done int - - - enable rng/trng int - - - enable tdes key check error int - - - - ce interrupt status - - src/dst length error int status - - - one command done int status, - - - src/dst length error int status - - - one command done int status, - - - ce rng/trng int status - - - ce tdes key check error int status - - - - ce interrupt clear - - src/dst length error int status - - - one command done int status, - - - clear error int status - - - clear one command done int status, - - - clear tdes key check error int status - - - - start ce - - start ce - - - - clear ce - - reset ce status - - - - aes work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 0: rtl rotation, 1: no-rotation - - - 00: key 128bits,01:192bits,10,11:256bits - - - 0000:ECB,0001:CBC,0010:CTR,0011:XTS,0100:CMAC,0101:GCM,0110:GMAC,0111:CCM,1000:CBCMAC,1001:CFB,1010:OFB - - - aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid - - - 0:encode,1:decode - - - aes module enable - - - - tdes work mode cfg - - 0: disable, 1: enable even/odd check - - - 0:odd check,1:even check - - - 00:ECB,01:CBC - - - 0:encode,1:decode - - - tdes module enable - - - - hash work mode cfg - - sha3 shake out length - - - 00: normal hash; 01: ipad ;10: opad; 11: reserved - - - hash work module, -5鈥檇0: Doesn鈥檛 work -5鈥檇1: MD5 -5鈥檇2: SHA-1 mode -5鈥檇3: SHA-224 mode -5鈥檇4: SHA-256 mode -5鈥檇5: SHA-384 mode -5鈥檇6: SHA-512 mode -5鈥檇7: SHA-512/224 mode -5鈥檇8: SHA-512/256 mode -5鈥檇9: SM3 mode -5鈥檇10: SHA3-224 -5鈥檇11: SHA3-256 -5鈥檇12: SHA3-384 -5鈥檇13: SHA3-512 -5鈥檇14: SHA3-SHAKE128 -5鈥檇15: SHA3-SHAKE256 - - - hash module enable - - - - chacha poly work mode cfg - - 00:chacha20 ; 01:poly1305; -10:AEAD_CHACHA20_POLY1305 - - - 0:encrypt,1:decrypt - - - chacha poly module enable - - - - simon speck work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 00: key 128bits,01:192bits,10:256bits - - - 000:ECB,001:CBC,010:CTR,100:CFB,101:OFB - - - 0:speck; 1:simon - - - 0:encrypt,1:decrypt - - - chacha poly module enable - - - - ce basic configure - - switch source high 32bits and low 32bits - - - switch destination high 32bits and low 32bits - - - source data switch of one word - - - destination data switch of one word - - - 0:disable hdcp mode, 1: enable hdcp mode - - - list update iv/sec/cnt flag - - - data end in link list mode - - - list end flag - - - 0: isn't aad list 1: is aad list - - - 0: aad no-end list 1: aad end list - - - wait axi B channel bready - - - 0:normal mode, 1: iram key or secure ddr key - - - 0: normal mode, 1: aes/sm4 key from session key - - - 1: all crypto key in ddr/iram; 0: from registers - - - 0:normal mode, 1: bypass ce - - - 0: std flag 1: std aad flag - - - 0: std aad no-end flag 1: std aad end flag - - - std end flag - - - 0: enable cmd int output: 1: don't output int - - - 0: dump from ddr; 1: don't dump - - - 0: rcv from ddr; 1: don't rcv - - - 0:std mode, 1: link mode - - - - dma read port node data length - - source address high 4bits; or aes mac aad address high 4bits - - - source fragment length of each node; or aes mac aad length - - - - dma write port node data length - - destination address high 4bits - - - destination fragment length of each node - - - - dma source address - - - dma destination address - - - dma one length - - ce_list_ptr high 4bits - - - first list length,support max 256 nodes - - - - dma list pointer - - - aes tdes rsa key length - - aes hmac key address high 4bits - - - aes hmac key length - - - - aes tdes rsa key address - - - aes tag length - - aes tag address high 4bits - - - aes tag length - - - - aes tag address - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key1 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - key2 - - - sm4 work mode cfg - - 1: don鈥檛 update key, 0: update key - - - 0: rtl rotation, 1: no-rotation - - - 000:ECB,001:CBC,010:CTR,011:XTS,100:CFB,101:OFB - - - 0:encode,1:decode - - - sm4 module enable - - - - - IP version - - r4 - - - px - - - - - ce performace counter - - - ce use flag - - when the siganl is high ,then flag the pub aes/sm4/hash is catch the cmd from the pub cmd buf or the pub is working - - - when the siganl is high ,then flag the sec aes/sm4/hash is catch the cmd from the sec cmd buf or the sec is working - - - ce sec or pub use the ce aes/sm4/hash cicpher module - - - - axi bus cache - - axi read port outstanding number - - - axi write port outstanding number - - - axi bus wcache - - - axi bus rcache - - - - cmd stop ctrl - - fde to restart - - - 1: fde stop command is valid - - - 0:fde to execute next cmd; 1: fde finish current cmd,then stop - - - to restart - - - 1: stop command is valid - - - 0: to execute next cmd; 1: finish current cmd,then stop - - - - axi prot sel - - reserved - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: disable fde side sel; 1: enable fde side axi sel - - - reserved - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: non_prot; 1: prot; - - - 0: disable pub side sel; 1: enable pub side axi sel - - - - ce performace counter high 32 bit - - - - RNG module enable RNG module enable - - if the signal is high,then the rng data come from cpu. - - - if the signal is high,then the osc rings sel signal come from rf_rng_src_sel_enable. - - - if the signal is high,then the osc rings is auto choose to work - - - the signal control which osc ring is work,when the least bit is high,then the first one osc ring is choose as the entropy. - - - trng source test enable - - - the rst signal to the exotic trng module - - - the signal can change when the trng is work ,which can control the trng start or stop by cpu. - - - trng source enable - - - RNG module enable bit: -1:enbale RNG module to generate random number when auto mode is not enable - - - - RNG module config RNG module config - - Threshold bit value for random data , indicates that the cycle of the src_en is high, the max value is 12'hFFF. - - - when the data_in is 0,the test result should be 1,and the data_in is 1,the test result should be 0; - - - Threshold value for rng_data_valid, indicates that when rng_data_valid high, there area at least number of rng_data_valid_threshold words in SRAM锛宼he max value is 4'hf. - - - ce_rng_exotic_fault_rst_sel: 1'b0:the rst generated by the fault signal, 1'b1:don't generated the rst signal,the rst signal come from the cpu - - - local RNG entropty source select - - - when it's 1,the the post process module need data bitwith is 440bit,else is 256bit - - - the signal select the trng data come from exotic or local trng module 1:exotic 0:local - - - select entropy source,the range is 0x0 to 0x7 - - - - RNG data for cpu to read RNG data for cpu to read - - - time interval between two samples time interval between two samples - - enable first level sample - - - sample period between two samples, the value is from 0 to 255 - - - sample period between two samples, the value is from 0 to 255 - - - - post process functions select post process functions select - - when it's 1,the the PRNG data xor with trng data - - - when it's 1,the the final post process module is enable - - - when it's 1,the the xor process module is enable - - - when it's 1,the the cycle_code module is enable - - - when it's 1,the the lfsr module is enable - - - - post data path 1 enable - - - post data path 0 enable - - - - rng work status rng work status - - rand data number when keygen done - - - 2'b01:Instantiate ; 2'b10:Reseed ; 2'b11:Genarate. - - - when it's 1,cpu can send next 64bit pattern - - - when it's 1,the drbg KAT test fail - - - DRBG KAT test done - - - when it's 1,the start-up/on-demand test fail(1024 sample) - - - start-up/on-demand test done - - - the result of test mode - - - when it's 1,indicate that the drbg test result data in 0x260 register is valid (cpu can read to check) - - - 2'b01: C [439:0] ; 2'b10: V[439:0] ; 2'b11: reseed_counter[31:0]. Corresponds to the data of each process in [15:14] . - - - the fifo status - - - the exotic rng module status - - - - when high indicates that RNG module has generate 256 bits random data - - - when high indicates that auto mode is ongoing, CPU can't access rng_data register - - - - rng time out counter rng time out counter - - - rng interrupt enable rng interrupt enable - - enable continuous health test interrupt - - - enable sram short interrupt - - - enable timeout interrupt - - - enable process2 interrupt - - - enable process1 interrupt - - - enable process0 interrupt - - - - rng interrupt status rng interrupt status - - continuous health test interrupt status - - - sram_short_interrrupt status - - - timeout interrrupt status - - - process2 interrrupt status - - - process1 interrrupt status - - - process0 interrrupt status - - - - rng interrupt clear rng interrupt clear - - clear continuous health test interrupt - - - clear sram short interrupt - - - clear timeout interrupt - - - clear process2 interrupt - - - clear process1 interrupt - - - clear process0 interrupt - - - - RNG module work mode RNG module work mode - - PRNG work mode: -1: Auto Seed update Mode -0: Mannual seed update Mode - - - RNG module work mode: -10: PRNG mode -01: TRNG mode 00锛11: Mixed mode for TRNG - - - - PRNG mode seed update config PRNG mode seed update config - - When Write to 1, PRNG will update seed to PRNG_SEED_CONFIG register value - - - - PRNG mode seed update config PRNG mode seed update config - - - RNG Bit Rate RNG Bit Rate - - RNG Bit Counter - - - RNG Bit number each 10000 clock cycle - - - - SRAM data numuber threshold SRAM data numuber threshold - - SRAM data numuber threshold, - - - - rng_sram_data_residue_num rng_sram_data_residue_num - - rng_sram_data_residue_num - - - - exotic fault counter rng exotic fault counter config - - config the fault counter and read the counter - - - - drbg seed count drbg seed count - - config the drbg seed after certain time - - - - config ring ring number config ring ring number - - - config ring ring number config ring ring number - - - rng_health_test_config rng_health_test_config - - default:11'd607(freq 0/1 in 1024) - - - default:6'd47 (conse 48 0/1) [23] - - - open drbg test(on-demand test) - - - open es test(on-demand test) - - - - ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_l - - - ce_rng_drbg_test_pattern_h ce_rng_drbg_test_pattern_h - - - raw_random_number raw_random_number - - - ce_rng_drbg_sha256_result ce_rng_drbg_sha256_result - - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - session key from secure OS - - - - ce_cmd_fifo_entry - - - ce_cmd_fifo_status - - - ce_rcv_addr_lo - - - ce_dump_addr_lo - - - ce_dump_addr_hi - - ce dump address hi - - - ce rcv address hi - - - - ce_finish_cmd_cnt - - - - ce_fde_aes_cmd_fifo_entry - - - ce_fde_aes_cmd_fifo_status - - - ce_fde_aes_rcv_addr_lo - - - ce_fde_aes_dump_addr_lo - - - ce_fde_aes_dump_addr_hi - - ce fde_aes cipher dump address hi,or aes tag address high 4bits - - - ce fde_aes cipher rcv address hi - - - - ce_fde_aes_finish_cmd_cnt - - - start fde_aes cipher ce - - start fde_aes cipher ce(TDES/AES/SM4/SM1/SM7/GHASH) - - - - clear fde_aes cipher ce - - reset ce fde_aes cipher status - - - - fde_aes cipher work mode cfg - - aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid - - - 00: key 128bits,01:192bits,10,11:256bits - - - 0: rtl rotation, 1: no-rotation(sm4/aes) - - - 0000:ECB,0001:CBC,0010:CTR,0011:XTS - - - 0:encode,1:decode - - - fde_aes cipher module enable - - - - ce fde_aes cipher basic configure - - ce fde iv auto add 1鈥榖1 each 512Byte msg - - - fde_aes switch source high 32bits and low 32bits - - - fde_aes switch destination high 32bits and low 32bits - - - fde_aes cipher source data switch of one byte - - - fde_aes cipher destination data switch of one byte - - - list update iv/sec/cnt flag - - - fde_aes cipher data end in link list mode - - - fde_aes cipher list end flag - - - 0:normal mode, 1: iram key or secure ddr key - - - 0: normal mode, 1: aes key from session key - - - 1: fde_aes cipher all crypto key in ddr/iram,and the iv also come from drr except the link list mode; 0:fde_aes cipher from registers - - - - fde_aes cipher std end flag - - - 0: fde_aes cipher enable cmd int output: 1: don't output int - - - 0:fde_aes cipher dump from ddr; 1:fde_aes cipher don't dump - - - 0:fde_aes cipher rcv from ddr; 1:fde_aes cipher don't rcv - - - 0:fde_aes cipher std mode, 1:fde_aes cipher link mode - - - - fde_aes cipher dma one length - - ce_fde_aes_list_ptr high 4bits - - - fde_aes cipher first list length,support max 40 nodes - - - - fde_aes cipher dma list pointer - - - fde_aes cipher dma read port node data length - - fde_aes cipher destination address high 4bits - - - fde_aes cipher source address high 4bits; or aes mac aad address high 4bits - - - fde_aes cipher source fragment length of each node; or aes mac aad length - - - - fde_aes cipher dma source address - - - fde_aes cipher dma destination address - - - fde aes key length - - fde aes key address high 4bits - - - fde aes key length - - - - fde aes key address - - - fde aes dst ddr select - - axi awprot under key in iram mode -0: non_sec 1: sec - - - - ce fde aes dummy register - - ce fde aes dummy register - - - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - aes tdes iv sector counter - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key1 - - - fde key2 - - - fde key2 - - - fde key2 - - - fde key2 - - - fde key2 - - - fde key2 - - - fde key2 - - - fde key2 - - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - fde session key from secure OS - - - - - - - - DMA Block Count - - - Block Size and Count - - Transfer blocks size. This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. -0x0000: no data transfer -0x0001: 1 byte - - - - Argument - - - Transfer mode and command - - Set to indicate the host whether card will send boot ack -1鈥檅1: send boot ack -1鈥檅0: not send boot ack - - - Set to begin drive low cmd line and waiting to receive boot data block -1鈥檅1: Drive cmd line low -1鈥檅0: not drive cmd line - - - Command index, set to the command number (CMD0-63, ACMD0-63) - - - Commend type. There are three types of special commands, Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. -00: Normal -01/10: Reserved -11: Abort - - - Data present select -0: no data present -1: data present -This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: -1. Commands using only CMD line (e.g., CMD52) -2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b, e.g., CMD38) -3. Resume Command - - - Command index check enable -0: disable -1: enable -If this bit is set to 1, the HC shall check the index field in the Response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked. - - - Command CRC check enable -0: disable -1: enable -If this bit is set to 1, the HC shall check the CRC field in the Response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked - - - Sub Command Flag -0: Main Command -1: Sub Command - - - Response type select -00: no response -01: response length 136 -10: response length 48 -11: response length 48, check Busy after response - - - Response Interrupt Disable -0: Response Interrupt is enabled. -1: Response Interrupt is disabled. -Support response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. -If Host Driver checks response error, sets this bit to 0 and waits Command Complete Interrupt and then checks the response register. -If Host Controller checks response error, sets this bit to 1 and sets Response Error Check Enable to 1, Command Complete Interrupt is disabled by this bit regardless of Command Complete Signal Enable - - - Response Error Check Enable -0: Response Error check is disabled -1: Response Error check is enabled. -Support response error check function to avoid overhead of response error check by Host driver. Only R1 or R5 can be checked. -If Host Driver check response error, this bit is set to 0 and Response Interrupt Disable is set to 0, -If Host Controller checks response error, sets this bit to 1 and sets Response Interrupt Disable to 1. Response Type R1/R5 selects either R1 or R5 response type. If an error is detected, Response Error Interrupt is generated in the Error Interrupt Status register. - - - Response Type R1/R5 -0: R1 (Memory) -1: R5 (SDIO) -When response error check is enabled, this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. -Error Statues checked in R1 -Bit: 19/20/21/23/25/26/29/30/31 -Response Flags Checked in R5: -Bit: 0/1/3/7 - - - Multiple/single block select -0: single block -1: multiple blocks - - - Data transfer direction select -0: write (Host to Card) -1: read (Card to Host) - - - Auto CMD enable -00: disable -01: Auto CMD12 Enable -10: Auto CMD23 Enable -11: Auto CMD auto select -1: Auto CMD12 Enable: Multiple block transfers for memory require CMD12 to stop the transaction. When this bit is set to 1, the HC shall issue CMD12 automatically when last block transfer is completed. The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer. -2: Auto CMD23 Enable: -When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register -3: Auto CMD auto select. -When this mode select, selection of auto CMD depends on setting of CMD23 Enable in the Host Ctrl 2 register which indicated whether card support CMD23. If CMD23 Enable=1, auto CMD23 is used and if CMD23 Enable=0, auto CMD12 is used. Use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. - - - Block count enable -(This design not support infinite mode, so it is always 1) - - - DMA enable -(This design not support NO-DMA mode, so it is always 1) - - - - RESP0 - - - RESP1 - - - RESP2 - - - RESP3 - - - - DMC AXI channel 0 configuration register - - Sub Command Flag -0: Main Command -1: Sub Command - - - CMD line signal level. This status is used to check CMD line level to recover from errors, and for debugging - - - DAT [3:0] line signal level. This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT [0]. -[23]: for DAT[3] -[22]: for DAT[2] -[21]: for DAT[1] -[20]: for DAT[0] - - - Read transfer active. This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: -1. After the end bit of the read command -2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer -This bit is cleared to 0 for either of the following conditions: -1. When the last data block as specified by block length is transferred to the system. -2. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop at Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. -0: no valid data -1: transferring data - - - Write transfer active. This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: -1. After the end bit of the write command -2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer -This bit is cleared in either of the following cases: -1. After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) -2. After getting a CRC status of any block where data transmission is about to be stopped by a Stop at Block Gap Request. -During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop at Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. -0: no valid data -1: transferring data - - - This bit selects 32B or 64B size when splitting AXI burst to DDR bursts. -0 : only 32byte split size -1 : dynamic split size, 32B or 64B, based on AXI transactions - - - DAT line active. This bit indicates whether one of the DAT line on SD bus is in use. -0: DAT line inactive -1: DAT line active - - - Command inhibit (DAT) -This status bit is generated if either the DAT Line Active or the Read Transfer Active is 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (e.g., R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt status register. Note: The SD Host Driver can save registers in the range of 0x0000 ~ 0x000D for a suspend transaction after this bit has changed from 1 to 0. -0: can issue command that uses the DAT line -1: cannot issue command that uses the DAT line - - - Command inhibit (CMD) -If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (0x000F) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. - - - - SD Host Control Register1 - - Interrupt at block gap. This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. - - - Read wait control. The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise, the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1 or DAT line conflict may occur. If this bit is set to 0, Suspend/Resume cannot be supported. -0: disable read wait control -1: enable read wait control - - - SD8 bit mode -Extended Data Transfer Width -This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controller by Data Transfer Width in the Host Control 1 register. -1: 8-bit Bus Width -0: Bus Width is Selected by Data Transfer Width - - - DMA Select -2鈥檅00: SDMA is select -2鈥檅01: Reserved -2鈥檅10: ADMA2 is select -2鈥檅11: ADMA2/3 is select - - - Data transfer width, SD1 or SD4. This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. -0: 1-bit mode -1: 4-bit mode - - - - SD Control Register2 - - Hardware reset for card -1: Normal work -0: card reset , should be set back to 1 manually - - - Software reset for DAT line. Only part of data circuit is reset. DMA circuit is also reset. The following registers and bits are cleared by this bit: -鈥 Buffer Data Port Register: -飩 Buffer is cleared and initialized. -鈥 Present State register: -飩 Buffer Read Enable -飩 Buffer Write Enable -飩 Read Transfer Active -飩 Write Transfer Active -飩 DAT Line Active -飩 Command Inhibit (DAT) -鈥 Block Gap Control register: -飩 Continue Request -飩 Stop At Block Gap Request -鈥 Normal Interrupt Status register -飩 Buffer Read Ready -飩 Buffer Write Ready -飩 Block Gap Event Transfer Complete -0: work -1: reset - - - Software reset for CMD line. Only part of command circuit is reset. The following registers and bits are cleared by this bit: -鈥 Present State register -飩 Command Inhibit (CMD) -鈥 Normal Interrupt Status register -飩 Command Complete -0: work -1: reset - - - Software reset for all. This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when Capabilities registers are valid and the HD can read them. Additional use of Software Reset for All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be reinitialized by the HD. -0: work -1: reset - - - Data timeout counter value. This value determines the interval by which DAT line timeouts are detected. Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate timeout generation. Timeout clock frequency will be generated by dividing the base clock TMCLK by this value. When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -0000: TMCLK * 2^(16) -0001: TMCLK * 2^(17) -鈥 -1110: TMCLK * 2^(30) -1111: TMCLK * 2^(31) - - - SDCLK/RCLK Frequency Select -If Freq_div = 0:Base clk - Freq_div = 1:Base clk/2 - Freq_div = 2:Base clk/4 - Freq_div = 3:Base clk/6 -鈥︹ - Freq_div= n:Base clk/(2*n) - - - SDCLK/RCLK Frequency Select[9:8] - - - SD clock enable. The HC shall stop SDCLK when writing this bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared. -0: disable -1: enable - - - Internal clock stable. This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is 1.Note: This is useful when using PLL for a clock oscillator that requires setup time. -0: not ready -1: ready - - - Internal clock enable. This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go to the very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection. -0: stop -1: oscillate -Note: -It is recommended to set this bit to 0 before changing the clock source, and then set it to 1 after the changing is done. -But changing the frequency divider need not to set this bit to 0. - - - - Normal and error interrupt status - - AXI Bus Error -0: no error -1: error - - - Response Error -0: no error - - - ADMA Error -0: no error -1: error - - - Auto CMD12 error. This occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error. -0: no error -1: error - - - Data end bit error. This occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. -0: no error -1: error - - - Data CRC error. This occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 鈥010鈥. -0: no error -1: error - - - Data timeout error. This occurs when detecting one of the following timeout conditions. -1. Busy Timeout for R1b, R5b type -2. Busy Timeout after Write CRC status -3. Write CRC status Timeout -4. Read Data Timeout -0: no error -1: timeout - - - Command index error. This occurs if a Command Index error occurs in the Command Response. -0: no error -1: error - - - Command end bit error. This occurs when detecting that the end bit of a command response is 0. -0: no error -1: end bit error generated - - - Command CRC error. Command CRC Error is generated in two cases. -1. If a response is returned and the Command Timeout Error is set to 0, this bit is set to 1 when detecting a CRC error in the command response -2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 levels on the CMD line at the next SDCLK edge, then the HC shall abort the command (stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict. -0: no error -1: CRC error generated - - - Command timeout error. This occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC. -0: no error -1: timeout - - - Error Interrupt -If any of the bits in the Error Interrpt Status register are set, then this bit is set. Therefore the Host Driver can efficiently test for an error by checking this bit first. This bit is read only. -0: no error -1: error - - - ADMA3 Complete - - - Card interrupts. Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. When this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again. -0: no card interrupt -1: card interrupt generated - - - DMA interrupt. This status is set if the HC detects the Host DMA Interrupt. -0: no DMA interrupt -1: DMA interrupt generated - - - Transfer complete. This bit is set when a read/write transaction is completed. -Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (after the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop at Block Gap Request in the Block Gap Control register (after valid data has been read to the Host System). -Write Transaction: This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop at Block Gap Request in the Block Gap Control register and data transfers completed (after valid data is written to the SD card and the busy signal is released). -0: no data transfer complete -1: data transfer complete - - - Command complete. This bit is set when getting the end bit of the command response (except auto CMD12 and auto CMD23). -Note: Command Timeout Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly. -0: no command complete -1: command complete - - - - Normal and error interrupt status enable - - AXI Bus Error status enable - - - Response Error status enable - - - ADMA Error status enable - - - Auto CMD12 error status enable - - - Data end bit error status enable - - - Data CRC error status enable - - - Data timeout error status enable - - - Command index error status enable - - - Command end bit error status enable - - - Command CRC error status enable - - - Command timeout error status enable - - - ADMA3 Complete status enable - - - Card interrupt status enable - - - DMA interrupt status enable - - - Transfer complete status enable - - - Command complete status enable - - - - Normal and error interrupt signal enable - - AXI Bus Error signal enable - - - Response Error signal enable - - - ADMA Error signal enable - - - Auto CMD12 error signal enable - - - Current limit error signal enable - - - Data end bit error signal enable - - - Data CRC error signal enable - - - Data timeout error signal enable - - - Command index error signal enable - - - Command end bit error signal enable - - - Command CRC error signal enable - - - Command timeout error signal enable - - - ADMA3 transfer complete signal enable - - - Card interrupt signal enable - - - DMA interrupt signal enable - - - Transfer complete signal enable - - - Command complete signal enable - - - - Host controller 2 and Auto CMD12 error status - - The system address is 32 bit or 64 bits -0: 32 bit address -1: 64 bit address - - - This design is host version 4 - - - CMD23 Enable -This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. Refer to Auto CMD Enable in the Transfer Mode Register -0: AutoCMD auto select CMD12 -1: AutoCMD auto select CMD23 - - - The ADMA2 length mode is 26 bit or 16bit -0: 16 bit data length mode -1: 26 bit data length mode - - - UHS Mode Select -This field is used to select one of UHS-I mode and effective when 1.8V Signaling Enable is set to 1. -If Preset Value Enable in the SD_CTRL3 register is set to 1, Host controller sets SDCLK Frequency Select, Clock Generator Select in the Clock Control register according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again. -4鈥檅0000: SDR12 -4鈥檅0001: SDR25 -4鈥檅0010: SDR50 -4鈥檅0011: SDR104 -4鈥檅0100: DDR50 -4鈥檅0101: HS200 -4鈥檅0110: HS400 -4鈥檅0111: HS401 (EMMC5.1) HS400 mode -4鈥檅1000: DDR200, SD6.0 - - - Command not issued error. Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error ([4:1]) in this register. -0: no error -1: not issued - - - Auto CMD index error. This occurs if the Command Index error occurs in response to a command. -0: no error -1: error - - - Auto CMD end bit error. This occurs when detecting that the end bit of command response is 0. -0: no error -1: end bit error generated - - - Auto CMD CRC error. This occurs when detecting a CRC error in the command response. -0: no error -1: CRC error generated - - - Auto CMD timeout error. This occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits ([4:2]) are meaningless. -0: no error -1: timeout - - - Auto CMD12 Not Executed -If memory multiple block data transfer is not started due to command error. This bit is not set because it is not necessary to issue auto cmd12. Setting this bit to 1 means the Host Controller cannot issue auto cmd12 to stop memory multiple block data transfer due to some error. If this bit is set to 1. Other error status bits are meaningless. - - - - Capabilities - - Slot Type -2鈥檅00: Removable Card Slot - - - Asynchronous Interrupt Support -1鈥檅0:Asynchronous Interrupt Not Supported - - - 64 bit System Bus Support -1鈥檅0 64 bit System Bus Support - - - 64 bit System Bus Support -1鈥檅0 64 bit System Bus Support - - - Voltage support 1.8 V. -0: 1.8 V not supported -1: 1.8 V supported - - - Voltage support 3.0 V. -0: 3.0 V not supported -1: 3.0 V supported - - - Voltage support 3.3 V. -0: 3.3 V not supported -1: 3.3 V supported - - - Suspend/resume support. This bit indicates whether the HC supports Suspend/Resume function. If this bit is 0, the Suspend and Resume mechanism is not supported and the HD shall not issue either Suspend/Resume command. -0: not supported -1: supported - - - DMA support. This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. -0: DMA not supported -1: DMA supported - - - High speed support. This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz -0: high speed not supported -1: high speed supported - - - ADMA2 Support -1鈥檅0: ADMA2 is not supported -1鈥檅1: ADMA2 is supported - - - 8-bit Support for Device -1鈥檅1: 8-bit Bus Width Supported - - - This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. -00: 512 bytes -01: 1024 bytes -10: 2048 bytes -11: 4096 bytes - - - This value indicates the base (maximum) clock frequency for the SD clock. The unit is MHz If the real frequency is 16.5 MHz, a larger value shall be set, i.e., 010001b (17 MHz) because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock frequency. The supported range is 10 to 63 MHz If these bits are all 0, the Host System has to get information via another method. -0: get information via another method (Registry Entry) -1: 1 MHz -2: 2 MHz -鈥 -FF: 255 MHz - - - This bit shows the unit of base clock frequency used to detect Data Timeout Error. -0: kHz -1: MHz - - - This bit shows the base clock frequency used to detect Data Timeout Error. -0: get information via another method -1: 1 MHz -2: 2 MHz -鈥 -63: 63 MHz - - - - Capabilities 2 - - ADMA3 is support - - - DDR50 Support -1鈥檅0: DDR50 is Supported - - - SDR104 Support -1鈥檅0 : SDR104 is Supported - - - SDR50 Support -1鈥檅0: SDR50 is Supported - - - - - Force event register - - Force Event for Auto CMD Error - - - Force Event for tuning Error - - - Force Event for Response Error - - - Force Event for Data End Bit Error - - - Force Event for Data CRC Error - - - Force Event for Data Timeout Error - - - Force Event for Command Index Error - - - Force Event for Command End Bit Error - - - Force Event for Command CRC Error - - - Force Event for Command Time Out Error - - - Force Event for Command Not Issued By Auto CMD12 Error - - - Force Event for Auto CMD Index Error - - - Force Event for Auto CMD End Bit Error - - - Force Event for Auto CMD Timeout Error - - - Force Event for Auto CMD Timeout Error - - - Force Event for Auto CMD 12 Not Executed -1: Interrupt is generated -0: No Interrupt - - - - ADMA Error State register - - If BRESP = SLVERR or DECERR, then BRESP_ERR is occurred, and this register will indicted the type of Error. -00: OKAY -01: EXOKAY -10: SLVERR -11: DECERR - - - If RRESP = SLVERR or DECERR, then RRESP_ERR is occurred, and this register will indicted the type of Error. -00: OKAY -01: EXOKAY -10: SLVERR -11: DECERR - - - ADMA Length Mismatch Error -1: Error -0: No Error -This error occurs in the following 2 cases: -1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -2) Total data length cannot be divided by the block length. - - - ADMA Error State -This field indicates the state of ADMA when error is occurred during ADMA data transfer. -2鈥檅00: ST_STOP (Stop DMA), Points next of the error descriptor. -2鈥檅01: ST_FDS (Fetch Descriptor), Points the error descriptor -2鈥檅10: Reserved -2鈥檅11: ST_TFR (Transfer Data), Points the next of the error descriptor - - - - ADMA2 System Address Low registers - - - ADMA2 System Address High registers - - - - ADMA3 System Address Low registers - - - ADMA3 System Address High registers - - - - Host version number - - This status indicates the Host Controller Spec Version. The upper and lower 4 bits indicate the version. -00: SD Host Specification version 1.0 -01 SD Host Specification Version 2.0 -02 SD Host Specification Version 3.0 -03 SD Host Specification Version 4.0 -04 SD Host Specification Version 4.1 -Others: reserved - - - One slot, it is equal to the int_to_arm - - - - - EMMC PHY DLL CFG registers - - Cycles to wait DLL locked signals. - - - Read negedge delay cell select -0:use user defined value from CLKNEGRD_DLY_ VAL -1:use dll generated value which referenced form CLKNEGRD_DLY_ VAL - - - Read posedge delay cell select -0:use user defined value from CLKPOSRD_DLY_VAL -1:use dll generated value which referenced form CLKPOSRD_DLY_VAL - - - Read cmd delay cell select -0:use user defined value from CLKCMDRD_DLY_VAL -1:use dll generated value which referenced form CLKCMDRD_DLY_VAL - - - write delay cell select -0:use user defined value from CLKDATWR_DLY_VAL -1:use dll generated value which referenced form CLKDATWR_DLY_VAL - - - DLL Clock source selection -0: Select 1x clock -1: Select 2x clock - - - DLL enable signal -0:DLL disable -1:DLL enable - - - DLL clear signal -1:clear DLL - - - Don鈥檛 support in this version - - - DLL output delay value enable - - - DLL start enable signal, this bit should be write to 1鈥檅0 when it is enabled to 1鈥檅1 - - - DLL lock mode: -0: full cycle lock mode -1: half cycle lock mode - - - DLL count initial value, DLL use it as the initial value to count the delay value. - - - DLL change threshold value, DLL update rd/wr/cmd delay line value if the DLL count delta bigger then DLL_CPST_THRESHOLD - - - DLL phase interval , DLL use it as the interval of phase 1 and phase2 - - - OUPUT clock phase select - - - - EMMC PHY DLL DLY registers - - Clock Read Data Negedge Delay Value -Based Phase is same as PHY Clock -Refer to description of CLKDATWR_DLY_VAL - - - Clock Read Data Posedge Delay Value -Based Phase is same as PHY Clock -Refer to description of CLKDATWR_DLY_VAL - - - Clock Read Command Line Delay Value -Based Phase is same as PHY Clock -Refer to description of CLKDATWR_DLY_VAL - - - Clock Data Write Line Delay Value -Based Phase is invert of PHY Clock -When DLL_DATWR_CPST_EN is enable, -This register is act as proportion of DLL clock cycle. -E.g.(when DLL_DATWR _CPST_EN==1) -If CLKDATWR _DLY_ VAL ==鈥檋40, it means delay 鈥榟40/鈥檋100 鈮 1/4 cycle. -If CLKDATWR_DLY_ VAL ==鈥檋80, it means delay 鈥榟80/鈥檋100F 鈮 1/2 cycle. - - - - EMMC PHY DLL Offset Read registers - - Clock Read Data Negedge Delay Invert - - - Refer to description of CLKDATWR_DLY_OFFSET - - - Clock Read Data Posedge Delay Invert - - - Refer to description of CLKDATWR_DLY_OFFSET - - - Clock Read Command Line Delay Invert - - - Refer to description of CLKDATWR_DLY_OFFSET - - - Clock Data Write Line Delay Invert - - - Data Write Delay offset. The highest bit indicates if it is add or sub. -OFFSET [4]=0: CLKDATWR_DLY_VAL + OFFSET [3:0] -OFFSET [4]=1: CLKDATWR_DLY_VAL 鈥 OFFSET [3:0]. -If DLL_DATWR _CPST_EN==1, the offset is added after the proportion. -E.g. If -Clock cycle (CYC)== 5ns -CLKDATWR _DLY_ VAL (VAL) ==鈥檋40, CLKDATWR_DLY_OFFSET (OFSET) == 鈥榟6, -DLL_CNT(CNT) == 鈥榟20 - it means delay: -(VAL/鈥檋100)*CYC + (CYC * OFSET) / CN = - (鈥榟40/鈥檋100)*5ns + (5ns * 鈥榟6) / 鈥榟20 鈮2.2ns - - - - - EMMC PHY DLL STS0 registers - - Reserved for vender asic only - - - Reserved for vender asic only - - - If use DLL, software should wait this value to 1鈥檅1 - - - If use DLL, soft ware should wait DLL_LOCKED to 1鈥檅1 and at that time ,this bit is 1鈥檅0 - - - Reserved for vender asic only - - - Reserved for vender asic only - - - DLL delay cell counts of 1 cycle - - - - EMMC PHY DLL STS1 registers - - Reserved for vender asic only - - - Reserved for vender asic only - - - Reserved for vender asic only - - - Reserved for vender asic only - - - - - EMMC Buffer Processing System Low address - - - EMMC Buffer Processing System High address - - - EMMC Buffer Processing Block Count - - - EMMC IO Processing Block Count - - - - EMMC Processing ADMA2 Low address - - - EMMC Processing ADMA2 High address - - - EMMC Processing ADMA3 Low address - - - EMMC Processing ADMA3 High address - - - EMMC Busy/CRC Status Position registers - - Control the Output clock SD_CLK auto gating -0: disable auto gating -1: enable auto gating - - - Control the internal clock auto gating -0: disable auto gating -1: enable auto gating - - - Reserved for vender asic only - - - Reserved for vender asic only - - - Reserved for vender asic only - - - Master PROT attributes. -It directly maps to the AXI master bus. AWPROT_emmc and ARPROT_emmc port. - - - Control the Output enable of clock SD_CLK -0: Clock OE is 0 -1: Clock OE is 1 - - - Control the Input enable of clock SD_CLK, -0: Clock IE is 0 -1: Clock IE is 1 - - - CRC Status Position Force Enable -0: use default value -1: use CRCSTS_POSI value -(Debug or designer set only) - - - Read Busy Position Force Enable -0: use default value -1: use READ_BUSY_POSI value -(Debug or designer set only) - - - CRC Status Position Adjustment -This register can adjust the sample position of CRC status, the need of this register is because of the HS200 or HS400 read data or CRC status may delay more cycles than legacy mode -When CRCSTS_POSI_FORCE is set 1 this register is valid, else the actual value is used internal set value. - - - Read Busy Position Adjustment -This register can adjust the sample position of read busy, the need of this register is because of the HS200 or HS400 read data or CRC status may delay more cycles than legacy mode. -When controller is read busy, the moment of stopping clock may be adjust through this register. -When READ_BUSY_POSI_FORCE is set 1 this register is valid, else the actual value is used internal set value. - - - - EMMC CRC Error Status registers - - (Debug only) -Bit[15] : Neg 7 -Bit[14] : neg 6 -Bit[13] : neg 5 -Bit[12] : neg 4 -Bit[11] : neg 3 -Bit[10] : neg 2 -Bit[9] : neg 1 -Bit[8] : neg 0 -Bit[7] : pos 7 -Bit[6] : pos 6 -Bit[5] : pos 5 -Bit[4] : pos 4 -Bit[3] : pos 3 -Bit[2] : pos 2 -Bit[1] : pos 1 -Bit[0] : pos 0 -The BIT[15:8] just used in DDR mode. - - - - - EMMC FSM Debug0 register - - This bit indicate whether the pad clock is working or stop. -0: clock is stopped. -1: clock is working - - - (Debug only) - - - (Debug only) - - - (Debug only) - - - - EMMC FSM Debug1 register - - (Debug only) - - - (Debug only) - - - (Debug only) - - - (Debug only) - - - - EMMC FSM Debug2 register - - (Debug only) - - - (Debug only) - - - - - DLL USED BACKUP SIGNAL - - Oe_ext_optional( Reserved for vender asic only) - - - Force slice en value( Reserved for vender asic only) - - - Force slice enable( Reserved for vender asic only) - - - Force dll use backup mode value( Reserved for vender asic only) - - - Force dll use backup mode( Reserved for vender asic only) - - - - - - - - - - - refclk_sel - - - Input triger number count enable - - - slave_mode trigger select - - - auto preload value - - - Center-aligned mode select 00: disable , other:enable - - - counter dir , 0: cnt ++ , 1: cnt -- - - - one pulse mode, 0:disable 1:enable - - - update disable, 0:disable, 1:enable - - - clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass - - - counter enable, 0: disbale, 1:enable - - - - - - slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable - - - - - - bit type is changed from w1c to rc. user trigger gen - - - - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 - - - no used yet - - - output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 - - - compare value preload 0: disable, 1:enable - - - no used yet - - - channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 - - - - - - ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti2 prescale, 01:0 div2, 10: div4, others: bypass - - - ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, - - - ti1 prescale, 01:0 div2, 10: div4, others: bypass - - - - - - ti2 polarity - - - ti2 enable - - - ti1 polarity - - - ti1 enable - - - - - - cnt_value - - - - - - cnt prescale value - - - - - - cnt max value - - - - - - ic1 capture value - - - - - - ic2 capture value - - - - - - ic1 compare value - - - - - - ic2 compare value - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - trig gens, when counter works in slave mode - - - - - - - - bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 - - - bit type is changed from w1c to rc. trig gens, when counter works in slave mode - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - med_ch0_work_cfg - - 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption - - - 1:enable ch0; 0:disable ch0; - - - - med_ch0_base_addr_cfg - - the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 - - - - med_ch0_addr_size_cfg - - the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF - - - - med_ch0_read_addr_remap - - the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 - - - - - med_ch1_work_cfg - - 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption - - - 1:enable ch1; 0:disable ch1; - - - - med_ch1_base_addr_cfg - - the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 - - - - med_ch1_addr_size_cfg - - the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF - - - - med_ch1_read_addr_remap - - the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 - - - - - med_ch2_work_cfg - - 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption - - - 1:enable ch2; 0:disable ch2; - - - - med_ch2_base_addr_cfg - - the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 - - - - med_ch2_addr_size_cfg - - the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF - - - - med_ch2_read_addr_remap - - the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 - - - - - med_ch3_work_cfg - - 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption - - - 1:enable ch3; 0:disable ch3; - - - - med_ch3_base_addr_cfg - - the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 - - - - med_ch3_addr_size_cfg - - the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF - - - - med_ch3_read_addr_remap - - the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 - - - - - med_write_addr_remap - - the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu write address is 0x1000_0024,then after med , then address is is 0x2000_0024 - - - - med_write_base_addr_cfg - - the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 - - - - med_write_addr_size_cfg - - the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF - - - - - med_clr - - 1:active,clear the 0x118 address bit31~bit12; - - - 1:active,clear the simon core - - - 1:active,clear the med inner write ram - - - 1:active,clear the med inner read ram - - - - med_work_mode - - can force the med clk gate always on, then the clk freerun - - - when the med send cmd to write flash data, and the slave happen bus error, then the med will back the slave bus error to master. - - - when the med send cmd to read flash data, and the slave happen bus error, then the med will back the slave bus error to master. - - - enable the med module ahb bus error,when the master access to med, and the access address is error, the med will generate the buss error to master. - - - 1:sel the key from efuse, 0: key from soft ware - - - - med_int_en - - enable med ahb addr out of range all channel - - - enable med error response int - - - enable med channel3 addr error int - - - enable med channel2 addr error int - - - enable med channel1 addr error int - - - enable med channel0 addr error int - - - enable med write done int - - - - emd_int_raw - - med ahb addr out of range all channel status - - - med error response int status - - - med channel3 addr error int status - - - med channel2 addr error int status - - - med channel1 addr error int status - - - med channel0 addr error int status - - - med write done int status - - - - med_int_clear - - clear med ahb addr out of range all channel status - - - clear med error response int - - - clear med channel3 addr error int - - - clear med channel2 addr error int - - - clear med channel1 addr error int - - - clear med channel0 addr error int - - - clear med write done int - - - - med_error_addr - - - med_status0 - - - - - - - - - - med_status1 - - - med_status2 - - - med_status3 - - - med_soft_key - - - - - - - - Transmit word or Receive word Write data to this address initiates a character transmission through TX FIFO -Read this address retrieve data from RX fifo - - - Clock divisor Clock divisor bit 0 to 15 - - Specify the clock ratio between spi_sck and clk_spi. -If clk_spi runs at 48 MHz, and spi_sck runs at 12MHz, SPI_CLKD should be 1, -spi_sck = clk_spi/2(n+1). -If IS_FST bit is assert, the valid SPI_CLKD is 0, 1, 2 and 3. - - - - Configure register This register is used to configuration of the SPI interface - - Sync_polarity, positive or negative pulse for SPI or 3-wire mode ,read command polarity - - - 鈥1鈥 : sync mode - - - 鈥1鈥 : spi_sck reverse - - - 1 bit chip select. -鈥0鈥: cs0 is valid -鈥1鈥: cs0 is invalid - - - In default, The input data is shifted high order first into the chip; the output data is shifted out high order first from the Most Significant Bit (MSB) on SO. When this bit is set, the data will be shift out or in from the LSB - - - Transmit data bit number. -鈥0鈥 : 32 bits per word -鈥1鈥 : 1 bits per word -鈥 -鈥31鈥: 31 bits per word - - - 鈥1鈥 enable TX data shift out at clock neg-edge - - - 鈥1鈥 enable RX data shift in at clock neg-edge - - - - Configure register This register is used to configuration of the SPI interface - - 鈥00鈥 : default(follow before version) -鈥01鈥 : spi do stay 0 value when in idle -鈥10鈥 : spi do stay 1 value when in idle -鈥11鈥 : spi do stay last-bit value when in idle - - - 1:is tx mode 0:not tx mode - - - 1:is rx mode 0:not rx mode - - - S8 CD or SYNC signal maps to csn number -鈥0x0001鈥 selects csn0 as cd signal -鈥0x0010鈥 selects csn1 as cd signal -In SPI_HS it must be 0x0000 and disable sync and s8 mode - - - 鈥1鈥 : enable S8 mode - - - 3-wire Melody timing 1, csn high mode enable - - - 鈥1鈥 : enable 3-wire mode - - - 3-wire mode, w/r control position -or the sync pulse position(the pulse will -locates on top of bit N) - - - - Configure register This register is used to configuration of the SPI interface - - 0:DMA TX and RX REQ independent -1:DMA TX REQ are depended on RX REQ status - - - 0: tx_dma_req keep 1 until receiving the tx_dma_ack -1: tx_dma_req is 鈥1鈥 when tx_empty is 鈥1鈥,else 鈥0鈥 - - - 0: rx_dma_req keep 1 until receiving the rx_dma_ack -1: rx_dma_req is 鈥1鈥 when rx_full is 鈥1鈥,else 鈥0鈥 - - - 鈥0鈥 : working on only receive -mode, when rxf_realfull is high, SPI will be held until rxf_realfull is low -鈥1鈥 : no holding - - - 鈥1鈥 enable DMA mode - - - 鈥0鈥 : master -鈥1鈥 : slave, only support microplus mode - - - Read data start bit, used for 3 wire mode and 3 wire 9bit RW mode. -The 3 wire 9bit RW mode reuse this config registers, it indicated read data start position. - - - - RXF watermark SPI RX FIFO FULL/EMPTY watermark - - Receive FIFO data empty threshold. Relative with rx_fifo_empty interrupt - - - Receive FIFO data full threshold. Relative with rx_fifo_full interrupt - - - - Configure register This register is used to configuration of the SPI interface - - working in only receive mode, -鈥0鈥 : SPI send all 0 to slave -鈥1鈥 : SPI send all 1 to slave - - - 鈥0鈥 : normal mode -鈥1鈥 : fast mode -Both for matser mode and slave mode,and in master mode SPI_SCK must be quicker than 1/8 spi_clk - - - Phase delay. Relate to fast mode. -When in normal mode, this bit is not used . Only used for slave mode - - - 鈥1鈥 Mask out the first clock pulse in SPI mode - - - Sync_half, sync width is half spi_sck cycle - - - 鈥1鈥:receive data only. -The bit should be written at last. -Only used for master mode - - - Number of data words ready to receive in 鈥渞eceive only鈥 mode. Only used for master mode. - - - - Configure register This register is used to configuration of the SPI interface - - For master, transmit data interval, programmable n from 0 to 65535, delay is (n*4+3) clock cycle. -For slave, max receive data interval. If the slave has not sampled the edge of spi_clk in the interval(n*4+3), slave will stop the receive process and send timout interrupt - - - - Interrupt enable SPI interrupt enable register - - Rx end interrupt enable - - - Tx end interrupt enable - - - txf_empty interrupt enable - - - Rxf_full interrupt enable - - - Slave mode timeout interrupt enable - - - Rx_overrun_reg interrupt enable - - - - Tx_fifo_full interrupt enable - - - Rx_fifo_empty interrupt enable - - - Rx_fifo_full interrupt enable - - - - Interrupt clear SPI interrupt clear register - - Rx data end interrupt clear - - - Tx data end interrupt clear - - - Write 鈥1鈥 clear slave mode timeout interrupt - - - Write 鈥1鈥 clear Rx_overrun_reg interrupt - - - Write 鈥1鈥 clear Tx_fifo_empty interrupt - - - Write 鈥1鈥 clear Tx_fifo_full interrupt - - - Write 鈥1鈥 clear Rx_fifo_empty interrupt - - - Write 鈥1鈥 clear Rx_fifo_full interrupt - - - - Raw status SPI interrupt raw status - - Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. - - - Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. - - - Raw txf_empty interrupt, This bit is set when the number of tx fifo data byte is less than the tx empty watermark value. Auto cleared when the condition disappears. - - - Raw rxf_full interrupt.This bit is set when the number of rx fifo data byte is larger than the rx full watermark value. Auto cleared when the condition disappears. - - - Raw slave mode time out interrupt - - - Raw Rx_overrun_reg interrupt - - - Txf_empty_w(for debug) - - - Raw Tx_fifo_full interrupt - - - Raw rx_fifo_empty interrupt - - - Rxf_full_r(for debug) - - - - Mask status SPI interrupt mask status - - Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. - - - Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. - - - Txf_empty interrupt mask status. - - - Rxf_full interrupt mask status. - - - Slave mode time out interrupt mask status - - - Rx_overrun_reg interrupt mask status - - - Tx_fifo_full interrupt mask status - - - Rx_fifo_empty interrupt mask status - - - - RXF address SPI RX FIFO write address and read address - - RX FIFO write address - - - RX FIFO read address - - - - latch SPI status SPI status register - - Spi_cs(for debug) - - - Spi_sck(for debug) - - - Spi_txd(for debug) - - - Spi_rxd(for debug) - - - 鈥1鈥 transmit process -鈥0鈥 idle state - - - TX FIFO has no data - - - TX FIFO is real full. (not relates to TX full threshold) - - - RX FIFO has no data - - - RX FIFO is real full. (not relates to TX full threshold) - - - This bit is set when the number of TX FIFO data byte is less than the TX empty interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of TX FIFO data byte is larger than the TX full interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of RX FIFO data byte is less than the RX empty interrupt watermark value. Auto cleared when the condition disappears. - - - This bit is set when the number of RX FIFO data byte is larger than the RX full interrupt watermark value. Auto cleared when the condition disappears. - - - - DSP Register This register is used for DSP control - - Write data switch. -2鈥檅0: WDATA=PDATA; -2鈥檅1: WDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; -2鈥檅2: WDATA={PDATA[15:0],PDATA[31:16]}; -2鈥檅3: WDATA={PDATA[23:16], PDATA[31:24], PDATA[7:0], PDATA[15:8]}; - - - Read data switch. -2鈥檅0: RDATA=PDATA; -2鈥檅1: RDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; -2鈥檅2: RDATA={PDATA[15:0],PDATA[31:16]}; - - - This register is used for DSP control - - - - RX conunter monitor This register is used to observe the status - - working in only receive mode -as master - - - - TXF configuration This register is used to configuration of the SPI interface - - TX FIFO data empty threshold. Relative with rx_fifo_empty interrupt - - - TX FIFO data full threshold. Relative with rx_fifo_full interrupt - - - - TXF address This register is used to configuration of the SPI interface - - TX FIFO write address - - - TX FIFO read address - - - - FIFO reset configuration Used to reset TX/RX FIFO - - 鈥1鈥 : reset all FIFOs. FIFO address will changed to 0 - - - - Configure register This register is used to configuration of the SPI interface - - 1: two data line function enable -0: two data line function disable - - - 1: enable RGB565 data format -0: disable RGB565 data format - - - 1: enable RGB666 data format -0: disable RGB666 data format - - - 1: enable RGB888 data format -0: disable RGB888 data format - - - 1: SPI slave in Low speed mode -0: SPI slave in High speed mode - - - Used when SPI slave in High speed mode. -1: enable spi slave rtx -0: disable spi slave rtx - - - Use for 3 wire 9bit RW mode and 4 wire 8bit RW mode (SPI_MODE=5 or SPI_MODE=6). -0: Data in and data out of SPI share one IO (SDA). -1: Data in and data out of SPI use separated IO (SDI, SDO). - - - 1: enable ahb2apb bridge read hold when rx fifo empty -0: disable ahb2apb bridge read hold - - - 1: enable ahb2apb bridge write hold when tx fifo full -0: disable ahb2apb bridge write hold - - - 1: select fmark as the dma request -0: select software dma request - - - Used for master only -0: SPI_MODE disable -1: 3 wire 9 bit, cd bit, SDI/SDO share one IO -2: 3 wire 9 bit, cd bit, SDI, SDO -3: 4 wire 8 bit, cd pin, SDI/SDO share one IO -4: 4 wire 8 bit, cd pin, SDI, SDO -5: 3 wire 9bit RW mode, 9 bit command and 8 bit read data, cd bit is enable. Design for LCD driver. -6: 4 wire 8bit RW mode, 8bit command and 8 bit read data. Use CD PAD indicates command or data. Design for LCD driver. - - - CSN select control: -0: CSN 0 -1: CSN 1 -2: CSN 2 -3: CSN 3 - - - CSN IE output set(only slave) -0: not support csn input -1: support csn intput - - - - Statue Register Used to observe csn error - - 1: indicates csn occurring a exception - - - csn for slave - - - - Configure Register Used for configure SPI interface - - Spi tx cd bit: -0: indicates command -1: indicates data - - - Use for 4 wire 8bit RW mode. Determine CD PAD high or low in read data phase. - - - Second data line of two data line function select bit: -0: CD PAD as second data line -1: DI PAD as second data line - - - Two data line RGB data format mode: -0: 1pixel mode -1: 2/3 pixel mode - - - 2-data-line switch. Only valid in 2-data-line mode(DATA_LINE2_EN set to 1): -0: use spi_do as first data line,spi_di as second data line. -1: use spi_di as first data line, spi_do as second data line. - - - Spi tx dummy clock length - - - Indicates tx data length from tx fifo, High 4 bits of spi tx data length - - - - Configure register This register is used to configuration of the SPI interface - - Indicates: spi tx data length from tx fifo, Low 16bit of tx data length - - - - Configure register SPI status register - - Spi rx dummy clock length - - - Indicates receives data length from slave, high 4 bits of spi rx data length - - - - Configure register This register is used to configuration of the SPI interface - - Indicates: spi receives data length from slave, Low 16bit of rx data length - - - - Configure register This register is used to configuration of the SPI interface - - Software TX data request, for write LCD - - - Software RX data request, for read LCD - - - - Statue Register Used to observe TX data counter - - Tx data cnt - - - - Statue Register Used to observe TX statue - - tx dummy counter - - - tx data counter - - - - Statue Register Used to observe RX data counter - - Rx data cnt - - - - Statue Register Used to observe RX statue - - rx dummy counter - - - rx data counter - - - - Statue Register Used to observe spi version - - Spi version - - - - - - - - - - - - - - - - - - - - - - - - protocol_version - - - - - - Protocol Type - - - - - - Protocol Subtype - - - - - - - - - Beacon Destination address high - - - - - - - - - Beacon Source address high - - - - - - - - - BSSID address high - - - - - - Beacon sequence control - - - - - - Wlan rssi value - - - - - - - RX mode enable signal,0:enable,1:disable - - - beacon type,should be 00 - - - beacon type,should be 1000 - - - hold enable from apb,0:disable,1:enable,wlan interrupt can only be cleared by software when this bit set 1 and the walue of registers is kept until the interrupt is cleared - - - Wlan rssi value - - - - - - data receive ready interrupt - - - - - - - Beacon frame control - - - - - - Beacon duratin - - - - - - - - - - - - - - - Beacon interval - - - - - - Beacon Capbility information - - - - - - Beacon SSID Elment ID - - - - - - Beacon SSID length - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - patch_addrs00鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs00杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100000-0x1010000f锛 - - - - - - patch_addrs01鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs01杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100010-0x1010001f锛 - - - - - - patch_addrs02鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs02杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100020-0x1010002f锛 - - - - - - patch_addrs03鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs03杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100030-0x1010003f锛 - - - - - - patch_addrs04鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs04杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100040-0x1010004f锛 - - - - - - patch_addrs05鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs05杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100050-0x1010005f锛 - - - - - - patch_addrs06鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs06杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100060-0x1010006f锛 - - - - - - patch_addrs07鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs07杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100070-0x1010007f锛 - - - - - - patch_addrs08鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs08杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100080-0x1010008f锛 - - - - - - patch_addrs09鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs09杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100090-0x1010009f锛 - - - - - - patch_addrs10鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs10杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000a0-0x101000af锛 - - - - - - patch_addrs11鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs11杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000b0-0x101000bf锛 - - - - - - patch_addrs12鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs12杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000c0-0x101000cf锛 - - - - - - patch_addrs13鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs13杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000d0-0x101000df锛 - - - - - - patch_addrs14鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs14杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000e0-0x101000ef锛 - - - - - - patch_addrs15鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs15杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101000f0-0x101000ff锛 - - - - - - patch_addrs16鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs16杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100100-0x1010010f锛 - - - - - - patch_addrs17鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs17杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100110-0x1010011f锛 - - - - - - patch_addrs18鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs18杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100120-0x1010012f锛 - - - - - - patch_addrs19鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs19杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100130-0x1010013f锛 - - - - - - patch_addrs20鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs20杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100140-0x1010014f锛 - - - - - - patch_addrs21鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs21杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100150-0x1010015f锛 - - - - - - patch_addrs22鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs22杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100160-0x1010016f锛 - - - - - - patch_addrs23鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs23杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100170-0x1010017f锛 - - - - - - patch_addrs24鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs24杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100180-0x1010018f锛 - - - - - - patch_addrs25鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs25杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x10100190-0x1010019f锛 - - - - - - patch_addrs26鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs26杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001a0-0x101001af锛 - - - - - - patch_addrs27鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs27杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001b0-0x101001bf锛 - - - - - - patch_addrs28鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs28杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001c0-0x101001cf锛 - - - - - - patch_addrs29鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs29杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001d0-0x101001df锛 - - - - - - patch_addrs30鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs30杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001e0-0x101001ef锛 - - - - - - patch_addrs31鍦板潃瀵瑰簲鐨刾atch鍔熻兘浣胯兘 - - - 瀵筊OM鍦板潃patch_addrs31杩涜璇诲啓鏃惰浆鎹㈠埌RAM鐨勫浐瀹氬湴鍧涓紙0x101001f0-0x101001ff锛 - - - - - - pagespy鍔熻兘浣胯兘 - - - 鐩戞帶璇绘搷浣滀娇鑳 - - - 鐩戞帶鍐欐搷浣滀娇鑳 - - - pagespy鐩戞帶鐨勫紑濮嬪湴鍧 - - - - - - pagespy鐩戞帶鐨勭粨鏉熷湴鍧 - - - - - - pagespy鍔熻兘浣胯兘 - - - 鐩戞帶璇绘搷浣滀娇鑳 - - - 鐩戞帶鍐欐搷浣滀娇鑳 - - - pagespy鐩戞帶鐨勫紑濮嬪湴鍧 - - - - - - pagespy鐩戞帶鐨勭粨鏉熷湴鍧 - - - - - - pagespy鍔熻兘浣胯兘 - - - 鐩戞帶璇绘搷浣滀娇鑳 - - - 鐩戞帶鍐欐搷浣滀娇鑳 - - - pagespy鐩戞帶鐨勫紑濮嬪湴鍧 - - - - - - pagespy鐩戞帶鐨勭粨鏉熷湴鍧 - - - - - - pagespy鍔熻兘浣胯兘 - - - 鐩戞帶璇绘搷浣滀娇鑳 - - - 鐩戞帶鍐欐搷浣滀娇鑳 - - - pagespy鐩戞帶鐨勫紑濮嬪湴鍧 - - - - - - pagespy鐩戞帶鐨勭粨鏉熷湴鍧 - - - - - - pagespy杩斿洖鐨勬爣蹇椾綅锛岀洃鎺у湴鍧娈靛唴浜х敓璇绘垨鍐欐搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓璇绘搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓鍐欐搷浣滄椂涓1 - - - 杩斿洖璇ヨ鎴栧啓鎿嶄綔鐨凜PU鐨処D鍙 - - - - - - - - - pagespy杩斿洖鐨勬爣蹇椾綅锛岀洃鎺у湴鍧娈靛唴浜х敓璇绘垨鍐欐搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓璇绘搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓鍐欐搷浣滄椂涓1 - - - 杩斿洖璇ヨ鎴栧啓鎿嶄綔鐨凜PU鐨処D鍙 - - - - - - - - - pagespy杩斿洖鐨勬爣蹇椾綅锛岀洃鎺у湴鍧娈靛唴浜х敓璇绘垨鍐欐搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓璇绘搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓鍐欐搷浣滄椂涓1 - - - 杩斿洖璇ヨ鎴栧啓鎿嶄綔鐨凜PU鐨処D鍙 - - - - - - - - - pagespy杩斿洖鐨勬爣蹇椾綅锛岀洃鎺у湴鍧娈靛唴浜х敓璇绘垨鍐欐搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓璇绘搷浣滄椂涓1 - - - 鐩戞帶鍦板潃娈靛唴浜х敓鍐欐搷浣滄椂涓1 - - - 杩斿洖璇ヨ鎴栧啓鎿嶄綔鐨凜PU鐨処D鍙 - - - - - - - - - - - - raw interrupt status Register raw interrupt status Register - - - interrupt enable Register interrupt enable Register - - - masked interrupt status Register masked interrupt status Register - - - interrupt clear Register interrupt clear Register - - - tempurature control register tempurature control register - - 1: frac freq div mode -0: integer freq div mode - - - 1: ext osc static mode -0: ext tsx static mode - - - 1: sw config ,ext tsx/osc static mode -0: ext tsx/osc swtich mode - - - 1: External OSC option -0: Internal OSC option - - - 0:hardware mode -1:software mode - - - osc left shift control of tempurature offset - - - left shift control of tempurature offset - - - 1:first do OSC -0:first do TSX - - - 1: switch osx tsx enable -0: switch osx tsx disable - - - 1: OSC option -0: TSX option - - - 1: External TSX option -0: Internal TSX option - - - 1: enable osc internal thermal ADS synchronous reset - - - 1: sample the osc adc data at the posedge of adc clock -0: sample the osc dac data at the negedge of adc clock - - - 1: enable internal thermal ADS synchronous reset - - - 1: sample the adc data at the posedge of adc clock -0: sample the dac data at the negedge of adc clock - - - enable the osc filter filter in the calculation(update) - - - enable the tsx filter filter in the calculation(update) - - - enable the thermal ADC data dump to Memory - - - enable the osc calcualtion of tempurature compensation - - - enable the tsx calcualtion of tempurature compensation - - - - the length of intergration the length of intergration - - the length of intergration - - - - the coef0 of frequency calculation the coef1 of frequency calculation - - c0 of frequency bias calculation - - - - the coef1 of frequency calculation the coef2 of frequency calculation - - c0 of frequency bias calculation - - - - the coef2 of frequency calculation the coef3 of frequency calculation - - c2of frequency bias calculation - - - - the coef3 of frequency calculation the coef4 of frequency calculation - - c0 of frequency bias calculation - - - - the reserved register of frequency calculation the reserved register of frequency calculation - - - the configur register of external sigma-delta ADC over resampling the configur register of external sigma-delta ADC over resampling - - external TSX over resampling output divider clk second inverse position. - - - external TSX over resampling output divider clk initial inverse position. - - - external TSX over resampling resampling ration over origin signma delta ADC working clk frequency. For example, the origin sampling clk and resmapling clk is 6.5M and 26M, and the ratio is 4 .then the value of this register should be ration-1 =3. - - - external TSX over resampling first pulse generate postion in delay chain. -Typital is 1 - - - external TSX over resampling best sampling positon . - - - external TSX over resampling output divider clk init value. - - - external TSX over resampling delay chain sync mode select. -1: high first -0: low first - - - external TSX over resampling work enable - - - - offset of osc frequency calculation offset of osc frequency calculation - - offset of osc frequency calculation - - - - the coef0 of osc frequency calculation the coef1 of osc frequency calculation - - c0 of osc frequency calculation - - - - the freq bias cal val reg in software mode the freq bias cal val reg in software mode - - software calculation frequency bias update.Write to this reg will gen an plus. - - - software calculation frequency bias - - - - the counter of frequency calculation done the counter of frequency calculation done - - - the counter of tempurature calculation done the counter of tempurature calculation done - - - the coef1 of osc frequency calculation the coef2 of osc frequency calculation - - c1 of osc frequency calculation - - - - the coef2 of osc frequency calculation the coef3 of osc frequency calculation - - c2 of osc frequency bias calculation - - - - the coef3 of osc frequency calculation the coef4 of osc frequency calculation - - c3 of osc frequency bias calculation - - - - switch ctrl switch ctrl - - osc_data_num - - - tsx_data_num - - - adc delay num - - - - the configur register of external sigma-delta ADC over resampling(frac freq div) the configur register of external sigma-delta ADC over resampling(frac freq div) - - external TSX/OSC over resampling output divider neg clk inverse position. - - - external TSX/OSC over resampling output divider pos clk inverse position. - - - external TSX/OSC over resampling first pulse generate postion in delay chain. -Typital is 1 - - - external TSX/OSC over resampling resampling ration over origin signma delta ADC working clk frequency. For example, the origin sampling clk and resmapling clk is 26/3.5M and 26M, and the ratio is 3.5 .then the value of this register should be ration*2-1 =6. - - - 1: neg clk sample -0: pos clk sample - - - external TSX/OSC over resampling delay chain sync mode select. -1: high first -0: low first - - - external TSX/OSC over resampling work enable - - - - - the status reg of frequency bias calculation the status reg of frequency bias calculation - - hardware calculation frequency bias update.Write to this reg will gen an plus - - - hardware calculation frequency bias value - - - - the status reg of tempurature calculation the status reg of tempurature calculation - - hardware calculation frequency bias update.Write to this reg will gen an plus - - - hardware integration value of calculation tempurature - - - - the status reg of frequency bias calculation the status reg of frequency bias calculation - - hardware calculation frequency bias update.Write to this reg will gen an plus - - - hardware calculation frequency bias value - - - - the status reg of tempurature calculation the status reg of tempurature calculation - - hardware calculation frequency bias update.Write to this reg will gen an plus - - - hardware integration value of calculation tempurature - - - - the status reg of tempurature calculation the status reg of tempurature calculation - - hardware calculation frequency bias update.Write to this reg will gen an plus - - - hardware integration value of calculation tempurature - - - - osc_cal_post ctrl osc_cal_post ctrl - - - - - osc_cal_post ctrl osc_cal_post ctrl - - 0 is osc_freq_bias_pre, 1 is osc_freq_bias_post - - - t2reset_cnt th - - - clear osc t2reset_cnt - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - 0 is tsx_freq_bias_pre, 1 is tsx_freq_bias_post - - - - - - clear osc t2reset_cnt - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - t2reset_cnt th - - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - t2reset_cnt th - - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - t2reset_cnt th - - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - - tsx_cal_post ctrl tsx_cal_post ctrl - - - - - freq_bias_rpt0 freq_bias_rpt0 - - - - freq_bias_rpt1 freq_bias_rpt1 - - - - freq_bias_rpt2 freq_bias_rpt2 - - - - freq_bias_rpt3 freq_bias_rpt3 - - - - freq_bias_rpt4 freq_bias_rpt4 - - - - - - - - - - - 1锛歝p cpu璁块棶lte鏃惰蒋浠舵帶鍒剁殑闃叉寕姝诲姛鑳戒娇鑳 - - - 1锛歝p cpu璁块棶lte鏃堕槻鎸傛鍔熻兘鐢辫蒋浠舵帶鍒讹紱0锛氱敱纭欢鎺у埗 - - - 1锛歝p璁块棶lte dma鏃惰蒋浠舵帶鍒剁殑闃叉寕姝诲姛鑳戒娇鑳 - - - 1锛歝p璁块棶lte dma鏃堕槻鎸傛鍔熻兘鐢辫蒋浠舵帶鍒讹紱0锛氱敱纭欢鎺у埗 - - - 1锛歝p璁块棶psram鏃惰蒋浠舵帶鍒剁殑闃叉寕姝诲姛鑳戒娇鑳 - - - 1锛歝p璁块棶psram鏃堕槻鎸傛鍔熻兘鐢辫蒋浠舵帶鍒讹紱0锛氱敱纭欢鎺у埗 - - - 1锛歝p璁块棶gnss鏃惰蒋浠舵帶鍒剁殑闃叉寕姝诲姛鑳戒娇鑳 - - - 1锛歩fc2cp鐨勫紓姝ユˉauto gate浣胯兘 - - - 1锛歩fc鍙戦佹暟鎹埌寮傛妗ュ悗锛屽氨鍙繑鍥瀝esponds,鎶婁笉鍙紦瀛樼殑鍐欐搷浣滆浣滃彲缂撳瓨鐨勫啓鎿嶄綔 - - - axi鐨剋strb锛堟寚绀哄摢8bitS鏈夋晥淇″彿锛夎浆鍒癮hb鎸囩ず淇″彿,浣滀负AHB鐨刟wsparse淇″彿 - - - 1锛歵sx_sclk鐨勫紓姝ユˉauto gate浣胯兘 - - - 1锛歵sx_mclk鐨勫紓姝ユˉauto gate浣胯兘 - - - 1锛氭荤嚎浼犳暟鎹埌buffer锛屾湭浠巄uffer杈撳嚭瀹屾垚锛屽氨鍙繑鍥瀝esponds锛屾妸涓嶅彲缂撳瓨鐨勫啓鎿嶄綔瑙嗕綔鍙紦瀛樼殑鍐欐搷浣 - - - 1锛歛on2cp_sclk鐨勫紓姝ユˉauto gate浣胯兘 - - - 1锛歛on2cp_mclk鐨勫紓姝ユˉauto gate浣胯兘 - - - 1锛歛on鍒癱p浼犺緭鏁版嵁鍒癰uffer锛屾湭浠巄uffer杈撳嚭瀹屾垚锛屽氨鍙繑鍥瀝esponds锛屾妸涓嶅彲缂撳瓨鐨勫啓鎿嶄綔瑙嗕綔鍙紦瀛樼殑鍐欐搷浣 - - - axi鐨剋strb锛堟寚绀哄摢8bitS鏈夋晥淇″彿锛夎浆鍒癮hb鎸囩ず淇″彿锛屼綔涓篈HB鐨刟wsparse淇″彿 - - - axi鐨剋strb锛堟寚绀哄摢8bitS鏈夋晥淇″彿锛夎浆鍒癮hb鎸囩ず淇″彿锛屼綔涓篈HB鐨刟wsparse淇″彿 - - - - - - ifc鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - ifc璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - axidma鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - axidma璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - f8鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - f8璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - cp a5鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - cp a5璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - - - - lte dma鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - lte dma璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - lte cpu鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - lte cpu璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - aon m鍐欐暟鎹荤嚎鐨勪紭鍏堢骇 - - - aon m璇绘暟鎹荤嚎鐨勪紭鍏堢骇 - - - - - - 1锛歭pc_main鐨剋akeup鍔熻兘浣胯兘锛屾棤闇绛夊緟澶栬鐨刢active淇″彿渚垮彲鍞ら啋鏃堕挓 - - - 1锛歴6鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴5鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴4鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴3鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴2鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴1鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歴0鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮ain鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮4鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮3鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮2鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮1鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1锛歮0鐨勫己鍒跺叧闂荤嚎浣胯兘鎵撳紑锛屼繚璇佸綋鍓嶄紶杈撳畬鎴 - - - 1:s6鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s5鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s4鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s3鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s2鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s1鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:s0鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:main鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:m4鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:m3鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:m2鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:m1鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - 1:m0鐨勬帶鍒朵綆鍔熻椾娇鑳芥墦寮 - - - - - - m0閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - m0鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - m1閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - m1鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - m2閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - m2鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - m3閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - m3鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - m4閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - m4鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - s0閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s0鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - s1閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s1鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - s2閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s2鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - s3閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s3鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - s4閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s4鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - s5閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s5鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - 路 - - s6閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - s6鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - 1锛歝lk_thm_osc鏃堕挓鍙嶅悜 - - - 1锛歝lk_thm_tsx鏃堕挓鍙嶅悜 - - - 1锛歠req_bias鐨刢h3鏃堕挓寮鍚 - - - 1锛歠req_bias鐨刢h2鏃堕挓寮鍚 - - - 1锛歠req_bias鐨刢h1鏃堕挓寮鍚 - - - 1锛歠req_bias鐨刢h0鏃堕挓寮鍚 - - - 1锛歛5鏀跺埌axi bresp鍜宺resp鏃跺拷鐣 - - - 1锛歩fc鎬荤嚎respond杩斿洖error鏃跺拷鐣 - - - 1:wlan_iq浣跨敤鍚屾鍚庣殑淇″彿锛0锛歸lan_iq浣跨敤鏈綔鍚屾鐨勪俊鍙 - - - - - - 1锛歝gm_cp_ahb鎬荤嚎浣胯兘 - - - 1锛歝gm_cp_axi鎬荤嚎浣胯兘 - - - 1锛歝gm_cp_a5鎬荤嚎浣胯兘 - - - 1锛歝gm_cp_update鐨勪娇鑳芥墦寮 - - - 1锛歝gm_cp_ahb鍒嗛鐨勪娇鑳芥墦寮 - - - 1:cgm_cp_axi鍒嗛鐨勪娇鑳芥墦寮 - - - 1锛歝gm_cp_axi閫夋嫨鍝釜鍒嗛淇″彿 - - - - - - 1锛歠req_bias_ahb鏃堕挓鎵撳紑锛0锛歠req_bias_ahb鏃堕挓鍏抽棴 - - - 1锛歛on2cp_ahb鏃堕挓鎵撳紑锛0锛歛on2cp_ahb鏃堕挓鍏抽棴 - - - 1锛歝p_ahb_ifc鏃堕挓鎵撳紑锛0锛歝p_ahb_ifc鏃堕挓鍏抽棴APB Master use, can auto gate - - - 1锛歝p_apb_ifc鏃堕挓鎵撳紑锛0锛歝p_apb_ifc鏃堕挓鍏抽棴APB DMA master use - - - 1:dap鏃堕挓鎵撳紑锛0锛歞ap鏃堕挓鍏抽棴 - - - 1锛歠req_bias_func鏃堕挓鎵撳紑锛0锛歠req_bias_func鏃堕挓鍏抽棴 - - - 1锛歸lan_11b鏃堕挓鎵撳紑锛0锛歸lan_11b鏃堕挓鍏抽棴 - - - 1锛歜usmon_func鏃堕挓鎵撳紑锛0锛歜usmon_func鏃堕挓鍏抽棴 - - - 1锛歴ci2_func鏃堕挓鎵撳紑锛0锛歜usmon鏃堕挓鍏抽棴 - - - 1锛歴ci2_conf鏃堕挓鎵撳紑锛0锛歴ci2_conf鏃堕挓鍏抽棴 - - - 1锛歴ci2_mod鏃堕挓鎵撳紑锛0锛歴ci2_mod鏃堕挓鍏抽棴 - - - 1锛歴ci1_func鏃堕挓鎵撳紑锛0锛歴ci1_func鏃堕挓鍏抽棴 - - - 1锛歴ci1_conf鏃堕挓鎵撳紑锛0锛歴ci1_conf鏃堕挓鍏抽棴 - - - 1锛歴ci1_mod鏃堕挓鎵撳紑锛0锛歴ci1_mod鏃堕挓鍏抽棴 - - - 1锛歵imer3_mod鏃堕挓鎵撳紑锛0锛歵imer3_mod鏃堕挓鍏抽棴 - - - 1锛歵imer3_conf鏃堕挓鎵撳紑锛0锛歵imer3_conf鏃堕挓鍏抽棴 - - - 1锛歵imer4_mod鏃堕挓鎵撳紑锛0锛歵imer4_mod鏃堕挓鍏抽棴 - - - 1锛歵imer4_conf鏃堕挓鎵撳紑锛0锛歵imer4_conf鏃堕挓鍏抽棴 - - - 1锛歴ysram_conf鏃堕挓鎵撳紑锛0锛歴ysram_conf鏃堕挓鍏抽棴 - - - 1锛歛xidma鏃堕挓鎵撳紑锛0锛歛xidma鏃堕挓鍏抽棴 - - - 1锛歛hb_ch3鏃堕挓鎵撳紑锛0锛歛hb_ch3鏃堕挓鍏抽棴 - - - 1锛歛hb_ch2鏃堕挓鎵撳紑锛0锛歛hb_ch2鏃堕挓鍏抽棴 - - - 1锛歛hb_ch1鏃堕挓鎵撳紑锛0锛歛hb_ch1鏃堕挓鍏抽棴 - - - 1锛歛hb_ch0鏃堕挓鎵撳紑锛0锛歛hb_ch0鏃堕挓鍏抽棴 - - - 1锛歛hb_ch_dbg鏃堕挓鎵撳紑锛0锛歛hb_ch_dbg鏃堕挓鍏抽棴 - - - 1锛歛hb_f8鏃堕挓鎵撳紑锛0锛歛hb_f8鏃堕挓鍏抽棴 - - - 1锛歛hb_irq1鏃堕挓鎵撳紑锛0锛歛hb_irq1鏃堕挓鍏抽棴 - - - 1锛歛hb_irq0鏃堕挓鎵撳紑锛0锛歛hb_irq0鏃堕挓鍏抽棴 - - - - - - 1:clk_thm_osc_gen鏃堕挓鎵撳紑锛0锛歝lk_thm_osc_gen鏃堕挓鍏抽棴 - - - 1:clk_thm_tsx_gen鏃堕挓鎵撳紑锛0锛歝lk_thm_tsx_gen鏃堕挓鍏抽棴 - - - 1:clk_gnss_tsx_gen鏃堕挓鎵撳紑锛0锛歝lk_gnss_tsx_gen鏃堕挓鍏抽棴 - - - 1:clk_gnss_tsx_mux鏃堕挓鎵撳紑锛0锛歝lk_gnss_tsx_mux鏃堕挓鍏抽棴 - - - 1:clk_wcn_11b_adc_gen鏃堕挓鎵撳紑锛0锛歝lk_wcn_11b_adc_gen鏃堕挓鍏抽棴 - - - 1:clk_wdg_32k_gen鏃堕挓鎵撳紑锛0锛歝lk_wdg_32k_gen鏃堕挓鍏抽棴 - - - 1:clk_timer_26m_gen鏃堕挓鎵撳紑锛0锛歝lk_timer_26m_gen鏃堕挓鍏抽棴 - - - 1:clk_wcn_11b_dfe_gen鏃堕挓鎵撳紑锛0锛歝lk_wcn_11b_dfe_gen鏃堕挓鍏抽棴 - - - - - - 1锛歳st_osc_26m閫氳繃杞欢澶嶄綅 - - - 1锛歳st_tsx_ab_m閫氳繃杞欢澶嶄綅 - - - 1:async_bridge_cp_soft_rst閫氳繃杞欢澶嶄綅 - - - 1:cp_ltedma_async_soft_rst_to_lte閫氳繃杞欢澶嶄綅 - - - 1:cp_ltecpu_async_soft_rst_to_lte閫氳繃杞欢澶嶄綅 - - - 1锛歳st_cp2aon_aon閫氳繃杞欢澶嶄綅 - - - 1锛歳st_cp2gnss_cp閫氳繃杞欢澶嶄綅 - - - 1锛歳st_aon2cp_aon閫氳繃杞欢澶嶄綅 - - - 1锛歳st_timer4_26m閫氳繃杞欢澶嶄綅 - - - 1锛歳st_sci1閫氳繃杞欢澶嶄綅 - - - 1锛歳st_sci2閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_apb閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_m0閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_m1閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_m2閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_m3閫氳繃杞欢澶嶄綅 - - - 1锛歳st_busmon_m4閫氳繃杞欢澶嶄綅 - - - 1锛歳st_wlan_apb閫氳繃杞欢澶嶄綅 - - - 1锛歳st_f8閫氳繃杞欢澶嶄綅 - - - 1锛歳st_axidma閫氳繃杞欢澶嶄綅 - - - 1锛歳st_imem_axi閫氳繃杞欢澶嶄綅 - - - 1锛歳st_imem_apb閫氳繃杞欢澶嶄綅 - - - 1锛歳st_timer3閫氳繃杞欢澶嶄綅 - - - 1锛歳st_irq0閫氳繃杞欢澶嶄綅 - - - 1锛歳st_irq1閫氳繃杞欢澶嶄綅 - - - 1锛歳st_a5dbg閫氳繃杞欢澶嶄綅 - - - 1锛歳st_a5cs閫氳繃杞欢澶嶄綅 - - - 1锛歳st_a5閫氳繃杞欢澶嶄綅 - - - - - - 1:cp_axi鐨刟uto_gate浣胯兘 - - - 1:cp_a5鐨刟uto_gate浣胯兘 - - - 1:cp2freq_ahb鐨刟uto_gate浣胯兘 - - - 1:ifc2cp_ahb鐨刟uto_gate浣胯兘 - - - 1:aon2cp_ahb鐨刟uto_gate浣胯兘 - - - 1:cp_sci2鐨刟uto_gate浣胯兘 - - - 1:cp_sci1鐨刟uto_gate浣胯兘 - - - 1:cp_ifc鐨刟uto_gate浣胯兘 - - - 1:cp_ifc_ch3鐨刟uto_gate浣胯兘 - - - 1:cp_ifc_ch2鐨刟uto_gate浣胯兘 - - - 1:cp_ifc_ch1鐨刟uto_gate浣胯兘 - - - 1:cp_ifc_ch0鐨刟uto_gate浣胯兘 - - - 1:cp_ifc_ch_dbg鐨刟uto_gate浣胯兘 - - - - 路 - - 1:rst_cp_apbreg閫氳繃杞欢澶嶄綅 - - - - - - - - - - - - - - - cp ltecpu鐨則rans idle淇″彿锛1锛氳〃绀烘妯″潡鐩戞帶鍦扮鍙ｅ凡缁忓畬鎴愭墍鏈変紶杈 - - - cp ltecpu鐨刾wr_handshk_clk_req淇″彿 - - - cp ltecpu鐨刟xi_detector_overflow淇″彿 - - - cp ltedma鐨則rans idle淇″彿锛1锛氳〃绀烘妯″潡鐩戞帶鍦扮鍙ｅ凡缁忓畬鎴愭墍鏈変紶杈 - - - cp ltedma鐨刾wr_handshk_clk_req淇″彿 - - - cp ltedma鐨刟xi_detector_overflow淇″彿 - - - cp psram鐨則rans idle淇″彿锛1锛氳〃绀烘妯″潡鐩戞帶鍦扮鍙ｅ凡缁忓畬鎴愭墍鏈変紶杈 - - - cp psram鐨刾wr_handshk_clk_req淇″彿 - - - cp psram鐨刟xi_detector_overflow淇″彿 - - - - - - 1:鎵鏈塻lave鐨刣eep_sleep浣胯兘鎵撳紑 - - - 1:鎵鏈塵aster鐨刣eep_sleep浣胯兘鎵撳紑 - - - 1锛歝p鐨刣eep_sleep鐨刟ck淇″彿 - - - 1锛歝p鐨刲ight sleep浣胯兘鍏抽棴 - - - 1锛歴6鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴5鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴4鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴3鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴2鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴1鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歴0鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮ain鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮4鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮3鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮2鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮1鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1锛歮0鐨刲pc澶勪簬busy鐘舵侊紝lpc鐨勮緭鍏ユ椂閽熼渶瑕侀鍑篻ated鐘舵 - - - 1:s6宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s5宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s4宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s3宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s2宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s1宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:s0宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:main宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:m4宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:m3宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:m2宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:m1宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - 1:m0宸茬粡杩涘叆浣庡姛鑰楁ā寮 - - - - - - 1锛歴6 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴5 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴4 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴3 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴2 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴1 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歴0 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮ain lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮4 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮3 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮2 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮1 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - 1锛歮0 lpc杩涘叆Low_powe鐘舵侊紝涓旀鏃惰lp_force寮哄埗缁存寔鍦↙P鐘舵侊紝鐭ラ亾lp_force=0 - - - - - - cp_dbg鐨刴onitor淇″彿 - - - master4鍗犵敤鎬荤嚎淇″彿 - - - master4鍐欏崰鐢ㄦ荤嚎淇″彿 - - - master4璇诲崰鐢ㄦ荤嚎淇″彿 - - - master3鍗犵敤鎬荤嚎淇″彿 - - - master3鍐欏崰鐢ㄦ荤嚎淇″彿 - - - master3璇诲崰鐢ㄦ荤嚎淇″彿 - - - master2鍗犵敤鎬荤嚎淇″彿 - - - master2鍐欏崰鐢ㄦ荤嚎淇″彿 - - - master2璇诲崰鐢ㄦ荤嚎淇″彿 - - - master1鍗犵敤鎬荤嚎淇″彿 - - - master1鍐欏崰鐢ㄦ荤嚎淇″彿 - - - master1璇诲崰鐢ㄦ荤嚎淇″彿 - - - master0鍗犵敤鎬荤嚎淇″彿 - - - master0鍐欏崰鐢ㄦ荤嚎淇″彿 - - - master0璇诲崰鐢ㄦ荤嚎淇″彿 - - - master4閿佹 - - - master3閿佹 - - - master2閿佹 - - - master1閿佹 - - - master0閿佹 - - - - - - - - - - - - - - - - - - - - - - - - 1:cp deep sleep璇锋眰涓嶇瓑寰匔P-A5杩涘叆WFI锛屽己鍒秄orce LPC - - - 1:杩涘叆light sleep鍚庯紝涓嶇wlan鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇timer4鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇timer3鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇sci2鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇sci1鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s6鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s5鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s4鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s3鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s2鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s1鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇s0鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m4鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m3鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m2鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m1鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m0鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇main_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m4_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m3_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m2_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m1_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1:杩涘叆light sleep鍚庯紝涓嶇m0_lpc鏄惁鏈変紶杈撻兘杩涘叆light sleep鍔熻兘 - - - 1锛歝p鐨刲ight sleep鍔熻兘鍏抽棴 - - - 1锛氳繘鍏eep sleep鍚庯紝cpu涓嶅啀鎺ユ敹涓柇 - - - - - - wlan鍐呴儴鐘舵佷俊鍙 - - - wlan鍐呴儴鐘舵佷俊鍙 - - - wlan鍐呴儴鐘舵佷俊鍙 - - - wlan鍐呴儴鐘舵佷俊鍙 - - - - - - main閫鍑轰綆鍔熻楁ā寮忓悗寤惰繜鍑犱釜cycle鍚庢墦寮clk - - - main鎬荤嚎娌℃湁浼犺緭鍚庯紝绛夊灏戠殑cycle杩涘叆浣庡姛鑰楁ā寮 - - - - - - 1:cp鍙氳繃纭欢浼犳暟鎹埌rf_bitmap妯″潡锛屼笖璇ユā鍧楃殑鏁版嵁鍙互涓嶉氳繃鎬荤嚎鐩存帴浼犲埌cp - - - - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛屼腑闂16bits銆17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛屼綆16bits銆17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - - - - Bitmap wptr鍐欐寚閽堬紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛岄珮16bits銆17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AHB_EB0 - - NEW锛宑lk_mtx_dump浣胯兘淇″彿锛孏NSS dump鏁版嵁澶勭悊妯″潡浣跨敤 - - - 鍘烲6绗4bit锛岀敤浜庢帶鍒禛NSS MTX鏃堕挓锛屼笅寮忎腑钃濊壊瀛椾綋涓鸿EB淇″彿锛宑gm_gnss_mtx_en涓篗TX鏃堕挓浣胯兘淇″彿锛 -cgm_gnss_mtx_en = ~cp2gnss_lp_stat | gnss_mtx_en -cp2gnss_lp_stat涓篊P-sys鐨凩PC鐘舵佷俊鍙 - - - NEW锛孯FAD_SPI妯″潡鍔熻兘鏃堕挓浣胯兘淇″彿 - - - NEW锛孯FAD_SPI妯″潡鎬荤嚎鏃堕挓浣胯兘淇″彿 - - - 鍘烲6绗8bit锛孭PS妯″潡鍔熻兘鏃堕挓浣胯兘淇″彿 - - - 鍘烲6绗7bit锛孭PS妯″潡鎬荤嚎鏃堕挓浣胯兘淇″彿 - - - 鍘烲6绗6bit锛孯FT妯″潡鍔熻兘鏃堕挓浣胯兘淇″彿 - - - 鍘烲6绗5bit锛孯FT妯″潡鎬荤嚎鏃堕挓浣胯兘淇″彿 - - - NEW锛孏NSS2PSRAM寮傛妗PC鏃堕挓浣胯兘淇″彿 - - - NEW锛宑lk_top鐨勬荤嚎鏃堕挓浣胯兘锛屾渶濂戒笉瑕佸叧鎺 - - - - GNSS_BB_enable - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - NOT CHANGE - - - - FUN_TEST_MODE - - NOT CHANGE - - - - - AHB_SYS_CTL6 - - NOT CHANGE - - - - - PLATFORM_ID - - - PROJECT_ID - - - DERIVED_ID - - NOT USE锛孋hange the reset value - - - NOT USE锛孋hange the reset value - - - - MANUFACTURE_ID - - NOT USE锛孋hange the reset value - - - NOT USE锛孋hange the reset value - - - - IMPLEMENTATION_ID - - NOT USE锛孋hange the reset value - - - NOT USE锛孋hange the reset value - - - - - CGM_EN_CTRL - - 鍘烲6绗8bit锛孏NSS_wrap RTC鏃堕挓浣胯兘 - - - NEW锛孏NSS_wrap ADC鏃堕挓浣胯兘 - - - NEW锛孏NSS_wrap bb_pp鏃堕挓浣胯兘 - - - NEW, GNSS_wrap AE_clk浣胯兘淇″彿 - - - NEW锛孏NSS_wrap gnss_clk鏃堕挓浣胯兘 - - - - - GNSS2PSRAM_LPC_CFG - - gnss2psram寮傛妗PC鐨勪娇鑳戒俊鍙 - - - LPC鏀跺埌寮鏃堕挓璇锋眰鍚庯紝绛夊緟cycle鏁帮紝涓鑸繚鎸侀粯璁や笉鎳 - - - LPC鏀跺埌鍏虫椂閽熻姹傚悗锛岀瓑寰卌ycle鏁帮紝涓鑸繚鎸侀粯璁や笉鎳 - - - - GNSS2PSRAM_LPC_STATUS - - LPC鐘舵佷俊鍙凤紝鍙 - - - - GNSS2PSRAM_LPC_FORCE - - LPC鐨刦orce淇″彿锛屽彲浠ュ己鍒跺紑鍏崇粡杩嘗PC鐨勬椂閽 - - - force_ack淇″彿锛屽彧璇 - - - - - - - - - - - - - - - - - - - SOFT_RST - - NEW锛宒ump閫昏緫鐨勮蒋澶嶄綅淇″彿锛屽啓1澶嶄綅 - - - 鍘烲6绗20bit锛孏NSS_wrap鐨勮蒋澶嶄綅锛屽啓1澶嶄綅 - - - 鍘烲6绗19bit锛孯FT妯″潡杞浣嶏紝鍐1澶嶄綅 - - - 鍘烲6绗4bit锛孭PS妯″潡杞浣嶏紝鍐1澶嶄綅 - - - NEW锛孡PC妯″潡杞浣嶏紝鍐1澶嶄綅 - - - NEW锛孯FAD_SPI杞浣嶏紝鍐1澶嶄綅 - - - - - PWR_ON_RSTN_INDEX - - NOT CHANGE锛屽閮ㄤ綆鍣０鏀惧ぇ鍣ㄤ娇鑳戒俊鍙 - - - - - RAM_EMA - - NOT CHANGE - - - NOT USE - - - - - FPGADEBUG - - - - SLEEP_STATUS - - NOT CHANGE - - - - - AUTO_GATE_CTRL0 - - - AUTO_GATE_CTRL1 - - - AUTO_GATE_CTRL2 - - - AUTO_GATE_CTRL3 - - - AUTO_GATE_STATUS0 - - - AUTO_GATE_STATUS1 - - - AUTO_GATE_STATUS2 - - - AUTO_GATE_STATUS3 - - - - LATCH_PULSE_NUM - - GNSS杈撳嚭鐨凴TC_latch涓嶤PU_latch淇″彿鐨勮剦鍐叉嫇瀹介厤缃紝鍙牴鎹悓姝ユ椂閽熼鐜囬厤缃笉鍚岃剦瀹斤紝涔熷彲浠ラ粯璁15 - - - - ADC_IQ_HOLD_SEL - - GNSS hold鏃堕渶瑕佸皢IQ鏁版嵁鍒囨垚0锛岄渶瑕丷F-sys鎻愪緵hold浣胯兘淇″彿锛岃浣胯兘淇″彿鏈夊悓姝ュ拰闈炲悓姝ヤ袱绉嶆柟寮忥紝褰撹bit涓1鐨勬椂鍊欓夐潪鍚屾鏂瑰紡锛0鍗充负鍚屾鍚庝娇鑳戒俊鍙峰皢IQ鍒囨垚0 - - - - ASYNC_BRIDGE_DBG_SINGAL_W - - - ASYNC_BRIDGE_DETECTOR_OVERFLOW - - 寮傛妗verflow鐘舵佷俊鍙凤紝鍙 - - - - GPS_COEXIST_IN - - GNSS_wrap鐨凣PS鍏卞瓨淇″彿 - - - - AXI_REG_SLICE_DS_FORCE - - AXI anti_hang鍔熻兘 - - - AXI anti_hang鍔熻兘锛岄粯璁ら夋嫨dowm_sream_disable_force锛屽啓0琛ㄧず閫夋嫨AXI閫氳矾涓嬫父鐨処SO_EN - - - - AXI_REG_SLICE_DS_FORCE - - GNSS to PSRAM AWQOS config - - - GNSS to PSRAM ARQOS config - - - - AXI_REG_SLICE_DS_FORCE - - AHB Anti_hang err resp en锛宎ctive high锛宖orce to resp err - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cgm_gnss_mtx_sel_cfg clk_mtx_sel - - 0: 26m, 1: 62.5m, 2: 125m, 3: 133m, 4: 158m, 5:167m - - - - - cgm_gnss_bb_pp_sel_cfg clk_bb_pp_sel - - not use - - - - - cgm_gnss_adc_sel_cfg clk_adc_sel - - - - cgm_busy_src_monitor_cfg0 cgm_busy_monitor - - cgm_busy monitor - - - - - - - - - SPI_CFG - - 0: write ; 1 : read - - - 涓ゆ鐩搁偦鎿嶄綔锛孲E鏃犳晥鏃舵渶灏忔椂闂达紝sclk鏃堕挓涓暟鐨勪竴鍗 - - - 璇诲垎棰戠郴鏁帮細4 + FRQ_DIV_RD*2 - - - 璇诲垎棰戠郴鏁帮細4 + FRQ_DIV_WR*2 - - - 鍗婂弻宸ヨ鏁版嵁鏃剁墖閫変俊鍙峰弽鐩镐娇鑳 -0锛氫笉鍙嶅悜锛1锛氬弽鐩 - - - 鍙屽伐妯″紡閫夋嫨锛0锛氬崐锛1锛氬叏 - - - 鎺ュ彈鏁版嵁鏃舵ā寮忛夋嫨 -0锛3绾匡紙鍙敮鎸佸崐鍙屽伐璇伙級锛1锛4绾 - - - SPI鍗婂弻宸ヨ閫夋嫨闂撮殧绗嚑涓猄PI鏃堕挓閲囨牱锛宒efault锛2 - - - 璇绘暟鎹噰鏍锋部 -0锛氱浉鍙嶆部閲囨暟鎹紝涓庡彂閫佹部涓哄弽鐩告部锛堝叏鍙屽伐鏃跺繀椤讳负0锛 -1锛氬悓娌块噰鏁版嵁锛屼笌鍙戦佹部涓哄悓涓娌 - - - 鐗囬変娇鑳芥帶鍒堕夋嫨 -0锛氱墖閫夊湪鏃堕挓涔嬪墠鏈夋晥锛坣ormal锛 -1锛氱墖閫夊湪鏃堕挓涔嬪悗鏈夋晥锛圖IG_RF锛 - - - SPI鏃堕挓鐩镐綅鎺у埗 -0:鏁版嵁閲囨牱鍙戠敓鍦ㄦ椂閽熷鏁版部 -1锛氭暟鎹噰鏍峰彂鐢熷湪鏃堕挓鍋舵暟娌 - - - SPI鏃堕挓鏋佹ф帶鍒 -0锛歋PI鎺ュ彛鍦↖DLE鐘舵佹椂锛屾椂閽熶负浣庣數骞筹紱 -1锛歋PI鎺ュ彛鍦↖DLE鐘舵佹椂锛屾椂閽熶负楂樼數骞筹紱 - - - SPI鐗囬夋瀬鎬ф帶鍒 -0锛歋PI鐗囬変綆鏈夋晥 -1锛歋PI鐗囬夐珮鏈夋晥 - - - SPI鎺ユ敹鏁版嵁闀垮害锛宒efault = 16bit - - - SPI鍙戦佹暟鎹暱搴︼紝default = 32bit - - - - SPI_RXDATA - - - SPI_IMMDATA - - - - SPI_STATUS - - 1锛歋PI姝ｅ湪浼犺緭锛0锛氫紶杈撳畬鎴 - - - - - - - - - - - - - - - - - - - Reserved address for Power Pad control registers - - Power control pin[MS] for power [V_MMC_18_30] - - - Power control pin[MSOUT] for power [V_MMC_18_30] - - - Power control pin[MSEN] for power [V_MMC_18_30] - - - Power control pin[MS] for power [V_LCD_18_33] - - - Power control pin[MSOUT] for power [V_LCD_18_33] - - - Power control pin[MSEN] for power [V_LCD_18_33] - - - Power control pin[MS] for power [VDDIO_18_33] - - - Power control pin[MSOUT] for power [VDDIO_18_33] - - - Power control pin[MSEN] for power [VDDIO_18_33] - - - Power control pin[MS] for power [VSIM0] - - - Power control pin[MSOUT] for power [VSIM0] - - - Power control pin[MSEN] for power [VSIM0] - - - Power control pin[MS] for power [VSIM1] - - - Power control pin[MSOUT] for power [VSIM1] - - - Power control pin[MSEN] for power [VSIM1] - - - Power control pin[MS] for power [VLPVDDIO1833_1] - - - Power control pin[MSOUT] for power [VLPVDDIO1833_1] - - - Power control pin[MSEN] for power [VLPVDDIO1833_1] - - - Power control pin[MS] for power [LPVDDIO_18_33] - - - Power control pin[MSOUT] for power [LPVDDIO_18_33] - - - Power control pin[MSEN] for power [LPVDDIO_18_33] - - - - Global Pin control registers - - - Global Pin control registers - - - Global Pin control registers - - - Global Pin control registers - - - Global Pin control registers - - - Global Pin control registers - - - Pad u_RFDIG_GPIO_7 control - - Function Mode select - 0: rf_gpio7 - 3: lte_gpo_8 - - - - Pad u_RFDIG_GPIO_6 control - - Function Mode select - 0: rf_gpio6 - 3: lte_gpo_7 - - - - Pad u_RFDIG_GPIO_5 control - - Function Mode select - 0: rf_gpio5 - 3: lte_gpo_5 - - - - Pad u_RFDIG_GPIO_4 control - - Function Mode select - 0: rf_gpio4 - 3: lte_gpo_4 - - - - Pad u_RFDIG_GPIO_3 control - - Function Mode select - 0: rf_gpio3 - 3: lte_gpo_3 - - - - Pad u_RFDIG_GPIO_2 control - - Function Mode select - 0: rf_gpio2 - 3: lte_gpo_2 - - - - Pad u_u_RFDIG_GPIO_1 control - - Function Mode select - 0: rffe_sda - 1: rf_gpio1 - 3: lte_gpo_1 - - - - Pad u_RFDIG_GPIO_0 control - - Function Mode select - 0: rffe_sck - 1: rf_gpio0 - 3: lte_gpo_0 - - - - Pad u_KEYIN_4 control - - Function Mode select - 0: keyin_4 - 1: gpio_8 - 2: pwm_0 - 3: pwm_4 - 4: i2c_m2_scl - 6: debug_bus_12 - 7: uart_5_rxd - - - - Pad u_KEYOUT_5 control - - Function Mode select - 0: keyout_5 - 1: gpio_11 - 2: pwm_3 - 3: uart_4_txd - 7: uart_5_rts - - - - Pad u_KEYIN_5 control - - Function Mode select - 0: keyin_5 - 1: gpio_9 - 2: pwm_1 - 3: pwm_5 - 4: i2c_m2_sda - 7: uart_5_txd - - - - Pad u_KEYOUT_4 control - - Function Mode select - 0: keyout_4 - 1: gpio_10 - 2: pwm_2 - 3: uart_4_rxd - 7: uart_5_cts - - - - Pad u_UART_1_RTS control - - Function Mode select - 0: uart_1_rts - 1: pwm_3 - 2: pwm_11 - 3: uart_2_rxd - 4: gpio_15 - - - - Pad u_UART_1_TXD control - - Function Mode select - 0: uart_1_txd - 1: gpio_13 - - - - Pad u_UART_1_RXD control - - Function Mode select - 0: uart_1_rxd - 1: gpio_12 - - - - Pad u_UART_1_CTS control - - Function Mode select - 0: uart_1_cts - 1: gpio_14 - 2: pwm_10 - 3: uart_2_txd - - - - Pad u_GPIO_0 control - - Function Mode select - 0: gpio_0 - 1: spi_2_clk - 3: uart_1_rxd - 4: uart_3_rxd - 5: pwm_8 - 6: debug_clk - 7: uart_2_rxd - - - - Pad u_GPIO_3 control - - Function Mode select - 0: gpio_3 - 1: spi_2_di_1 - 3: uart_1_rts - 4: uart_4_txd - 5: pwm_11 - 6: debug_bus_2 - 7: uart_2_rts - - - - Pad u_GPIO_2 control - - Function Mode select - 0: gpio_2 - 1: spi_2_dio_0 - 3: uart_1_cts - 4: uart_4_rxd - 5: pwm_10 - 6: debug_bus_1 - 7: uart_2_cts - - - - Pad u_GPIO_1 control - - Function Mode select - 0: gpio_1 - 1: spi_2_cs_0 - 3: uart_1_txd - 4: uart_3_txd - 5: pwm_9 - 6: debug_bus_0 - 7: uart_2_txd - - - - Pad u_GPIO_7 control - - Function Mode select - 0: gpio_7 - 1: pwm_2 - 2: i2c_m2_sda - 3: uart_6_txd - 4: uart_3_txd - - - - Pad u_GPIO_6 control - - Function Mode select - 0: gpio_6 - 1: pwm_1 - 2: i2c_m2_scl - 3: uart_6_rxd - 4: uart_3_rxd - - - - Pad u_GPIO_5 control - - Function Mode select - 0: gpio_5 - 1: pwm_0 - 3: uart_5_txd - 4: uart_3_rts - 5: test_clkout - 6: debug_bus_4 - - - - Pad u_GPIO_4 control - - Function Mode select - 0: gpio_4 - 1: spi_2_cs_1 - 3: uart_5_rxd - 4: uart_3_cts - 5: pwm_12 - 6: debug_bus_3 - - - - Pad u_ADI_SDA control - - Function Mode select - 0: ADI_SDA - - - - Pad u_ADI_SCL control - - Function Mode select - 0: ADI_SCL - - - - Pad u_RESETB control - - Function Mode select - 0: RESETB - - - - Pad u_OSC_32K control - - Function Mode select - 0: OSC_32K - - - - Pad u_PMIC_EXT_INT control - - Function Mode select - 0: PMIC_EXT_INT - - - - Pad u_CHIP_PD control - - Function Mode select - 0: CHIP_PD - - - - Pad u_PTEST control - - - Pad u_CLK26M_PMIC control - - Function Mode select - 0: clk26m_pmic - - - - Pad u_SIM_1_RST control - - Function Mode select - 0: sim_1_rst - 1: gpio_32 - 2: pwm_6 - - - - Pad u_SIM_1_DIO control - - Function Mode select - 0: sim_1_dio - 1: gpio_31 - 2: pwm_5 - - - - Pad u_SIM_1_CLK control - - Function Mode select - 0: sim_1_clk - 1: gpio_30 - 2: pwm_4 - - - - Pad u_SIM_0_RST control - - Function Mode select - 0: sim_0_rst - - - - Pad u_SIM_0_DIO control - - Function Mode select - 0: sim_0_dio - - - - Pad u_SIM_0_CLK control - - Function Mode select - 0: sim_0_clk - - - - Pad u_SW_CLK control - - Function Mode select - 0: ap_jtag_tck - 1: gpio_24 - 3: spi_1_clk - 4: sdmmc2_clk - 6: tsx_adc_ch_sel - - - - Pad u_SW_DIO control - - Function Mode select - 0: ap_jtag_tms - 1: gpio_25 - 3: spi_1_cs_0 - 4: sdmmc2_cmd - 6: tsx_adc_clk - - - - Pad u_DEBUG_HOST_TX control - - Function Mode select - 0: ap_jtag_tdo - 1: gpio_27 - 2: debug_host_tx - 3: spi_1_di_1 - 4: sdmmc2_data_1 - 6: osc_adc_clk - - - - Pad u_DEBUG_HOST_RX control - - Function Mode select - 0: ap_jtag_tdi - 1: gpio_26 - 2: debug_host_rx - 3: spi_1_dio_0 - 4: sdmmc2_data_0 - 6: tsx_adc_ch_data - - - - Pad u_DEBUG_HOST_CLK control - - Function Mode select - 0: ap_jtag_trst - 1: gpio_28 - 2: debug_host_clk - 3: spi_1_cs_1 - 4: sdmmc2_data_2 - 6: osc_adc_data - - - - Pad u_CAMERA_RST_L control - - Function Mode select - 0: camera_rst_l - 1: pwm_6 - 2: i2c_m3_scl - 3: gpio_44 - 6: debug_bus_2 - 8: DBG_DO_11 - - - - Pad u_SPI_CAMERA_SCK control - - Function Mode select - 0: spi_camera_sck - 1: pwm_9 - 2: gpio_18 - 3: aud_da_d1 - 6: debug_bus_7 - - - - Pad u_SPI_CAMERA_SI_1 control - - Function Mode select - 0: spi_camera_si_1 - 1: i2c_m2_sda - 2: spi_camera_si_0 - 3: spi_camera_ssn - 6: debug_bus_6 - - - - Pad u_SPI_CAMERA_SI_0 control - - Function Mode select - 0: spi_camera_si_0 - 1: i2c_m2_scl - 2: spi_camera_si_1 - 3: gpio_47 - 6: CTS - 8: DBG_CLK - - - - Pad u_CAMERA_REF_CLK control - - Function Mode select - 0: camera_ref_clk - 1: pwm_8 - 2: gpio_46 - 6: debug_bus_4 - 8: DBG_TRIG - - - - Pad u_CAMERA_PWDN control - - Function Mode select - 0: camera_pwdn - 1: pwm_7 - 2: i2c_m3_sda - 3: gpio_45 - 6: debug_bus_3 - 7: GPADC_IN3 - 8: DBG_DO_12 - - - - Pad u_I2S_SDAT_I control - - Function Mode select - 0: i2s1_sdat_i - 1: pwm_10 - 2: gpio_21 - 3: aud_ad_d0 - 4: i2c_m3_scl - 8: DBG_DO_15 - - - - Pad u_I2S1_SDAT_O control - - Function Mode select - 0: i2s1_sdat_o - 1: pwm_11 - 2: gpio_22 - 3: aud_sclk - 4: i2c_m3_sda - - - - Pad u_I2S1_LRCK control - - Function Mode select - 0: i2s1_lrck - 1: i2c_m3_sda - 2: gpio_20 - 3: aud_ad_sync - 8: DBG_DO_14 - - - - Pad u_I2S1_BCK control - - Function Mode select - 0: i2s1_bck - 1: i2c_m3_scl - 2: gpio_19 - 3: aud_da_d0 - 8: DBG_DO_13 - - - - Pad u_I2S1_MCLK control - - Function Mode select - 0: i2s1_mclk - 1: gpio_46 - - - - Pad u_I2C_M2_SCL control - - Function Mode select - 0: i2c_m2_scl - 1: pwm_4 - 2: gpio_42 - 3: aud_da_sync - 6: debug_bus_0 - 8: DBG_DO_9 - - - - Pad u_I2C_M2_SDA control - - Function Mode select - 0: i2c_m2_sda - 1: pwm_5 - 2: gpio_43 - 3: aud_da_d1 - 6: debug_bus_1 - 8: DBG_DO_10 - - - - Pad u_Nand_sel control - - Function Mode select - 0: Nand_sel - - - - Pad u_KEYOUT_3 control - - Function Mode select - 0: keyout_3 - 1: gpio_35 - 3: i2c_m1_sda - 6: debug_clk - - - - Pad u_KEYOUT_2 control - - Function Mode select - 0: keyout_2 - 1: gpio_34 - 3: i2c_m1_scl - 6: debug_bus_15 - - - - Pad u_KEYOUT_1 control - - Function Mode select - 0: keyout_1 - 1: gpio_33 - 2: uart_6_txd - 3: pwm_7 - 6: debug_bus_14 - - - - Pad u_KEYOUT_0 control - - Function Mode select - 0: keyout_0 - 1: gpio_32 - 2: uart_6_rxd - 3: pwm_6 - 6: debug_bus_13 - - - - Pad u_KEYIN_3 control - - Function Mode select - 0: keyin_3 - 1: gpio_31 - 2: uart_4_txd - 6: debug_bus_11 - - - - Pad u_KEYIN_2 control - - Function Mode select - 0: keyin_2 - 1: gpio_30 - 2: uart_4_rxd - 6: debug_bus_10 - - - - Pad u_KEYIN_1 control - - Function Mode select - 0: keyin_1 - 1: gpio_29 - 2: pwm_15 - 6: debug_bus_9 - - - - Pad u_KEYIN_0 control - - Function Mode select - 0: keyin_0 - 1: gpio_28 - 2: pwm_14 - 6: debug_bus_8 - - - - Pad u_LCD_RSTB control - - Function Mode select - 0: lcd_rstb - 2: gpio_41 - 6: debug_bus_11 - - - - Pad u_LCD_FMARK control - - Function Mode select - 0: lcd_fmark - 1: spi_flash1_sio_3 - 2: gpio_40 - 6: debug_bus_10 - 7: GPADC_IN2 - 8: DBG_DO_8 - - - - Pad u_SPI_LCD_SELECT control - - Function Mode select - 0: spi_lcd_select - 1: spi_flash1_sio_2 - 2: gpio_39 - 6: debug_bus_9 - 8: DBG_DO_7 - - - - Pad u_SPI_LCD_CS control - - Function Mode select - 0: spi_lcd_cs - 1: spi_flash1_sio_1 - 2: gpio_38 - 6: debug_bus_8 - 8: DBG_DO_6 - - - - Pad u_SPI_LCD_CLK control - - Function Mode select - 0: spi_lcd_clk - 1: spi_flash1_sio_0 - 2: gpio_37 - 6: debug_bus_7 - 8: DBG_DO_5 - - - - Pad u_SPI_LCD_SDC control - - Function Mode select - 0: spi_lcd_sdc - 1: spi_flash1_cs - 2: gpio_36 - 6: debug_bus_6 - 7: GPADC_IN1 - 8: DBG_DO_4 - - - - Pad u_SPI_LCD_SIO control - - Function Mode select - 0: spi_lcd_sio - 1: spi_flash1_clk - 2: gpio_35 - 6: debug_bus_5 - 8: DBG_DO_3 - - - - Pad u_SDMMC1_RST control - - Function Mode select - 0: SDMMC1_RST - 1: gpio_36 - - - - Pad u_SDMMC1_DATA_7 control - - Function Mode select - 0: SDMMC1_DATA_7 - 1: gpio_27 - 2: pwm_13 - 3: i2c_m2_sda - 4: spi_1_cs_1 - 5: uart_4_txd - 6: spi_flash1_sio_3 - 7: timestamp_out - 8: dbgio_data7 - - - - Pad u_SDMMC1_DATA_6 control - - Function Mode select - 0: SDMMC1_DATA_6 - 1: gpio_26 - 2: pwm_12 - 3: i2c_m2_scl - 4: spi_1_di_1 - 5: uart_4_rxd - 6: spi_flash1_sio_2 - 7: timestamp_in - 8: dbgio_data6 - - - - Pad u_SDMMC1_DATA_5 control - - Function Mode select - 0: SDMMC1_DATA_5 - 1: gpio_25 - 2: i2c_m1_sda - 3: timestamp_out - 4: spi_1_dio_0 - 5: uart_4_rts - 6: spi_flash1_sio_1 - 7: PPS_OUT - 8: dbgio_data5 - - - - Pad u_SDMMC1_DATA_4 control - - Function Mode select - 0: SDMMC1_DATA_4 - 1: gpio_24 - 2: i2c_m1_scl - 3: timestamp_in - 4: spi_1_cs_0 - 5: uart_4_cts - 6: spi_flash1_sio_0 - 7: Lna_en - 8: dbgio_data4 - - - - Pad u_SDMMC1_DATA_3 control - - Function Mode select - 0: SDMMC1_DATA_3 - 1: gpio_21 - 2: spi_camera_sck - 3: pwm_15 - 4: spi_1_clk - 5: uart_3_txd - 6: spi_flash1_cs - 8: dbgio_data3 - - - - Pad u_SDMMC1_DATA_2 control - - Function Mode select - 0: SDMMC1_DATA_2 - 1: gpio_20 - 2: spi_camera_si_1 - 3: spi_camera_si_0 - 4: spi_2_cs_1 - 5: uart_3_rxd - 6: spi_flash1_clk - 8: dbgio_data2 - - - - Pad u_SDMMC1_DATA_1 control - - Function Mode select - 0: SDMMC1_DATA_1 - 1: gpio_19 - 2: spi_camera_si_0 - 3: spi_camera_si_1 - 4: spi_2_di_1 - 5: uart_5_txd - 6: uart_6_rts - 8: dbgio_data1 - - - - Pad u_SDMMC1_DATA_0 control - - Function Mode select - 0: SDMMC1_DATA_0 - 1: gpio_18 - 2: camera_ref_clk - 3: i2c_m1_sda - 4: spi_2_dio_0 - 5: uart_5_rxd - 6: uart_6_cts - 8: dbgio_data0 - - - - Pad u_SDMMC1_CMD control - - Function Mode select - 0: SDMMC1_CMD - 1: gpio_17 - 2: camera_pwdn - 3: i2c_m1_scl - 4: spi_2_cs_0 - 5: uart_2_txd - 6: uart_6_txd - 8: dbgio_cmd - - - - Pad u_SDMMC1_CLK control - - Function Mode select - 0: SDMMC1_CLK - 1: gpio_16 - 2: camera_rst_l - 3: pwm_14 - 4: spi_2_clk - 5: uart_2_rxd - 6: uart_6_rxd - 8: dbgio_clk - - - - Pad u_UART_2_RTS control - - Function Mode select - 0: uart_2_rts - 1: gpio_34 - 2: uart_2_rxd - 3: i2c_m3_sda - 4: uart_4_txd - - - - Pad u_UART_2_CTS control - - Function Mode select - 0: uart_2_cts - 1: gpio_33 - 2: uart_2_txd - 3: i2c_m3_scl - 4: uart_4_rxd - - - - Pad u_UART_2_TXD control - - Function Mode select - 0: uart_2_txd - 1: i2c_m1_sda - 2: pwm_13 - 3: gpio_32 - 4: uart_3_txd - - - - Pad u_UART_2_RXD control - - Function Mode select - 0: uart_2_rxd - 1: i2c_m1_scl - 2: pwm_12 - 3: gpio_31 - 4: uart_3_rxd - - - - Pad u_I2C_M1_SDA control - - Function Mode select - 0: i2c_m1_sda - 1: gpio_30 - 2: uart_4_txd - 4: rf_gpio8 - - - - Pad u_I2C_M1_SCL control - - Function Mode select - 0: i2c_m1_scl - 1: gpio_29 - 2: uart_4_rxd - 4: rf_gpio9 - - - - Pad u_GPIO_23 control - - Function Mode select - 0: gpio_23 - 1: spi_flash1_sio_3 - 2: pwm_9 - 3: sdmmc2_data_3 - 4: rf_gpio8 - - - - Pad u_GPIO_22 control - - Function Mode select - 0: gpio_22 - 1: spi_flash1_sio_2 - 2: spi_2_cs_1 - 3: sdmmc2_data_2 - 4: rf_gpio9 - 5: osc_adc_data - - - - Pad u_GPIO_21 control - - Function Mode select - 0: gpio_21 - 1: spi_flash1_sio_1 - 2: spi_2_di_1 - 3: sdmmc2_data_1 - 5: osc_adc_clk - - - - Pad u_GPIO_20 control - - Function Mode select - 0: gpio_20 - 1: spi_flash1_sio_0 - 2: spi_2_dio_0 - 3: sdmmc2_data_0 - 4: pwm_15 - 5: tsx_adc_ch_data - - - - Pad u_GPIO_19 control - - Function Mode select - 0: gpio_19 - 1: spi_flash1_cs - 2: spi_2_cs_0 - 3: sdmmc2_cmd - 4: pwm_14 - 5: tsx_adc_clk - - - - Pad u_GPIO_18 control - - Function Mode select - 0: gpio_18 - 1: spi_flash1_clk - 2: spi_2_clk - 3: sdmmc2_clk - 4: pwm_13 - 5: tsx_adc_ch_sel - 6: digrf_strobe_s_o - - - - Pad u_GPIO_17 control - - Function Mode select - 0: gpio_17 - 1: uart_3_rxd - 2: pwm_8 - 3: i2c_m3_sda - 5: PPS_OUT - 6: uart_2_rts - - - - Pad u_GPIO_16 control - - Function Mode select - 0: gpio_16 - 1: uart_3_txd - 2: pwm_7 - 3: i2c_m3_scl - 4: sdmmc2_data_3 - 5: Lna_en - 6: uart_2_cts - - - - Pad u_M_SPI_D_3 control - - Function Mode select - 0: M_SPI_D_3 - - - - Pad u_M_SPI_D_2 control - - Function Mode select - 0: M_SPI_D_2 - - - - Pad u_M_SPI_D_1 control - - Function Mode select - 0: M_SPI_D_1 - - - - Pad u_M_SPI_D_0 control - - Function Mode select - 0: M_SPI_D_0 - - - - Pad u_M_SPI_CS control - - Function Mode select - 0: M_SPI_CS - - - - Pad u_M_SPI_CLK control - - Function Mode select - 0: M_SPI_CLK - - - - - Pad u_RFDIG_GPIO_7 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_6 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_5 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_4 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_3 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_2 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_u_RFDIG_GPIO_1 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RFDIG_GPIO_0 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_4 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_5 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_5 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_4 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_1_RTS control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_1_TXD control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_1_RXD control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_1_CTS control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_0 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_3 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_2 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_1 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_7 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_6 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_5 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_4 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_ADI_SDA control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_ADI_SCL control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_RESETB control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - - Pad u_OSC_32K control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_PMIC_EXT_INT control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_CHIP_PD control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_PTEST control - - - Pad u_CLK26M_PMIC control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_1_RST control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_1_DIO control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_1_CLK control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_0_RST control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_0_DIO control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SIM_0_CLK control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SW_CLK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SW_DIO control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_DEBUG_HOST_TX control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_DEBUG_HOST_RX control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_DEBUG_HOST_CLK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_CAMERA_RST_L control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_CAMERA_SCK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_CAMERA_SI_1 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_CAMERA_SI_0 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - Pad switch control, 1-->analog, 0-->digital - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_CAMERA_REF_CLK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_CAMERA_PWDN control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2S_SDAT_I control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2S1_SDAT_O control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2S1_LRCK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2S1_BCK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2S1_MCLK control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2C_M2_SCL control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2C_M2_SDA control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_Nand_sel control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_3 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_2 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_1 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYOUT_0 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_3 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_2 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_1 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_KEYIN_0 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_LCD_RSTB control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_LCD_FMARK control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_LCD_SELECT control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_LCD_CS control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_LCD_CLK control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_LCD_SDC control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SPI_LCD_SIO control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_RST control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_7 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_6 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_5 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_4 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_3 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_2 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_1 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_DATA_0 control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_CMD control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_SDMMC1_CLK control - - 'drv' control for normal mode - 0: Driven strength 3mA - 1: Driven strength 6mA - 2: Driven strength 9mA - 3: Driven strength 12mA - 4: Driven strength 15mA - 5: Driven strength 18mA - 6: Driven strength 21mA - 7: Driven strength 24mA - 8: Driven strength 27mA - 9: Driven strength 30mA - 10: Driven strength 33mA - 11: Driven strength 36mA - 12: Driven strength 39mA - 13: Driven strength 42mA - 14: Driven strength 45mA - 15: Driven strength 48mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_2_RTS control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_2_CTS control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_2_TXD control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_UART_2_RXD control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2C_M1_SDA control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_I2C_M1_SCL control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_23 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_22 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_21 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_20 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_19 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_18 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_17 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_GPIO_16 control - - 'drv' control for normal mode - 0: Driven strength 2mA - 1: Driven strength 4mA - 2: Driven strength 6mA - 3: Driven strength 8mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_D_3 control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_D_2 control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_D_1 control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_D_0 control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_CS control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - Pad u_M_SPI_CLK control - - 'drv' control for normal mode - 0: Driven strength 4mA - 1: Driven strength 9mA - 2: Driven strength 13mA - 3: Driven strength 18mA - 4: Driven strength 22mA - 5: Driven strength 27mA - 6: Driven strength 32mA - 7: Driven strength 39mA - - - Sub-System deepsleep enable - - - 'wpus' control for normal mode - - - 'se' control for normal mode - - - 'wpu' control for normal mode - - - 'wpdo' control for normal mode - - - 'wpu' control for deepsleep mode - - - 'wpdo' control for deepsleep mode - - - 'ie' control for deepsleep mode - - - 'oe' control for deepsleep mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PWRCTRL_HWEN power domain shutdown/on controled by hardware signal or sofeware register. - - CP power domain control by: -0:software register -1:hardware signal from IDLE_LPS module - - - AP power domain control by: -0:software register -1:hardware signal from IDLE_LPS module - - - - AP_PWR_CTRL Register control AP power domani on/off. - - AP power domain software register control bit -0:off -1:on - - - - CP_PWR_CTRL Register control CP power domani on/off. - - CP power domain software register control bit -0:off -1:on - - - - PUB_PWR_CTRL Register control PUB power domani on/off. PUB power domain whil be shutdown when bit[2:0]=2'b11,otherwise power on. - - PUB power domain poll register bit for CP A5 -0:poll to power on -1:poll to shutdown - - - PUB power domain poll register bit for AP A5 -0:poll to power on -1:poll to shutdown - - - - RF_PWR_CTRL Register control RF power domani on/off. - - RF power domain software register control bit -0:off -1:on - - - - USB_PWR_CTRL Register control USB power domani on/off. - - USB power domain software register control bit -0:off -1:on - - - - LTE_PWR_CTRL Register control LTE power domani on/off. - - LTE power domain software register control bit -0:off -1:on - - - - GNSS_PWR_CTRL Register control GNSS power domani on/off. - - GNSS power domain software register control bit -0:off -1:on - - - - AP_PWR_STAT AP power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - CP power domain state. CP power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - PUB_PWR_STAT PUB power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - RF_PWR_STAT RF power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - USB_PWR_STAT USB power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - LTE_PWR_STAT LTE power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - GNSS_PWR_STAT GNSS power domain state. - - If power state is stable -0:not stable -1:stable - - - Current power state of power domain -0:off -1:on - - - - STATE_DELAY Power domain control state machine delay value between two states. - - Power domain control state machine delay value between two states, counts with 26MHz clock. - - - - PD_M_DELAY Power switch mather chain delay value. - - Power switch mather chain delay value, counts with 26MHz clock. - - - - PD_D_DELAY Power switch daughter chain delay value. - - Power switch daughter chain delay value, counts with 26MHz clock. - - - - PSRAM_HOLD_CTRL Control latch the value of PSRAM IO from PSRAM controller. - - 0:not latch -1:latch - - - - SLP_BYPASS Control bypass the sleep handshake action when shutdown power domain. - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - 0:not bypass -1:bypass - - - - SLP_TIMEOUT_FLAG Flag of power domain sleep handshake action timeout.Write "1" to clear relevant bit. - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - 0:timeout not occur -1:timeout occur - - - - PWRCTRL_INT_EN_AP - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - - PWRCTRL_INT_EN_CP - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - 0:disable irq signal output -1:enable irq signal output - - - - PWRCTRL_SM_STATE The state value of the power domain state machine. - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - 4'h1:CLK_DISA -4'h2:ISO_HOLD -4'h3:RESET -4'h4:PREPON_REQ -4'h5:PWR_OFF -4'h6:PON_REQ -4'h7:ISO_RELEASE -4'h8:RST_RELEASE -4'h9:CLK_ENA -4'ha:PWR_ON -4'hb:PREPOFF_REQ -4'hc:POFF_REQ -4'hd:BUS_HANDSHAKE -others:error state - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LPS_CTRL_AP AP sleep enable register(Enable AP sleep when writing 0x49444c45 to this register, accessed by software only.) - - Enable AP sleep -0:disable -1:enable - - - - AP_SIG_EN signal of low power related enable register - - - ap_pow_on_en ctrl -1:enable -0:disable - - - ap_cg_en ctrl -1:enable -0:disable - - - ap_pd_pll_en ctrl -1:enable -0:disable - - - ap_pd_xtal_en ctrl -1:enable -0:disable - - - ap_chip_pd_en ctrl -1:enable -0:disable - - - - AP_LPS_SIG_TIME low power related time control register - - The time from enable clock to obtain clock - - - The time of PLL from power saving state to output normal clock. - - - The time of OSC circuit from power saving -state to normal state. - - - The time of PMIC boost stabilization. - - - - LPS_CTRL_CP CP sleep enable register(Enable CP sleep when writing 0x49444c45 to this register, accessed by software only.) - - Enable CP sleep -0: disable -1: enable - - - - CP_PM2_STA mark pm2 - - pm2 sta -1:PM2 valid -0:PM2 invalid - - - - CP_SIG_EN signal of low power related enable register - - - cp_pow_on_en ctrl -1:enable -0:disable - - - cp_cg_en ctrl -1:enable -0:disable - - - cp_pd_pll_en ctrl -1:enable -0:disable - - - cp_pd_xtal_en ctrl -1:enable -0:disable - - - cp_chip_pd_en ctrl -1:enable -0:disable - - - - CP_LPS_SIG_TIME low power related time control register - - The time from enable clock to obtain clock - - - The time of PLL from power saving state to output normal clock. - - - The time of OSC circuit from power saving -state to normal state. - - - The time of PMIC boost stabilization. - - - - PM2_OFF_TIME low power related time control register - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - - AON_CLOCK_EN0 low power related time control register - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - - PM2_ON_OFF_TIME low power related time control register - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - Power domain control state machine delay value between two states, counts with 32KHz clock. - - - - AP_PM2_STA mark pm2 - - pm2 sta -1:PM2 valid -0:PM2 invalid - - - - AP_PM2_MODE_EN AP PM2 enable - - AP enable PM2 mode -0:disable PM2 mode -1:enable PM2 mode - - - - AON_SIG_EN AON CTRL signal enable - - - pd_aon_shutdown_d_b ctrl -1:enable -0:disable - - - pd_aon_shutdown_m_b ctrl -1:enable -0:disable - - - pd_aon_mem ctrl -1:enable -0:disable - - - rst_aon_en ctrl -1:enable -0:disable - - - pd_aon_iso ctrl -1:enable -0:disable - - - clk_en_aon ctrl -1:enable -0:disable - - - - SLEEP_PROT_TIME - - The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. - - - - ELIMINATE_JITTER - - Eliminate jitter delay register - - - Emilinate the jitter from awake signal when writing 1 to correspond bits. - - - - AP_LPS_STA - - awake valid -0锛歩nvalid -1锛歷alid - - - AP_POW_ACK sta(ap exit sleep mode) -0锛歅OW_ACK value -1锛歅OW_ACK value - - - AP_LPS end sta -0:not sleep -1:sleep - - - AP_SYS state -0: normal working -1: low power mode - - - - CP_INTEN - - t9_irq enable -1: enable -0: disable - - - t8_irq enable -1: enable -0: disable - - - t7_irq enable -1: enable -0: disable - - - load_irq enable -1: enable -0: disable - - - ap_sys_awk_irq enable -1: enable -0: disable - - - cp_sys_awk_irq enable -1: enable -0: disable - - - tstamp_irq enable -1: enable -0: disable - - - t6_irq enable -1: enable -0: disable - - - t5_irq enable -1: enable -0: disable - - - t4 enable -1: enable -0: disable - - - t3_irq enable -1: enable -0: disable - - - t2_irq enable -1: enable -0: disable - - - t1_irq_enable -1: enable -0: disable - - - p2_irq enable -1: enable -0: disable - - - p1_irq enable -1: enable -0: disable - - - - - CP_INT_STA - - clear cp interrupt state register when writing 1 to correspond bits. - - - - AP_INTEN ap interrupt enable register - - t9_irq enable -1: enable -0: disable - - - t8_irq enable -1: enable -0: disable - - - t7_irq enable -1: enable -0: disable - - - tstamp_irq enable -1: enable -0: disable - - - load_irq enable -1: enable -0: disable - - - ap_sys_awk_irq enable -1: enable -0: disable - - - cp_sys_awk_irq enable -1: enable -0: disable - - - t6_irq enable -1: enable -0: disable - - - t5_irq enable -1: enable -0: disable - - - t4 enable -1: enable -0: disable - - - t3_irq enable -1: enable -0: disable - - - t2_irq enable -1: enable -0: disable - - - t1_irq_enable -1: enable -0: disable - - - p2_irq enable -1: enable -0: disable - - - p1_irq enable -1: enable -0: disable - - - - - AP_INT_STA ap interrupt state - - clear ap interrupt state register when writing 1 to correspond bits. - - - - AP_AWK_EN AP wakeup enable register - - P2_AWK_EN wakeup enable -0: disable -1: enable - - - T6_AWK_EN wakeup enable -0: disable -1: enable - - - T5_AWK_EN wakeup enable -0: disable -1: enable - - - T4_AWK_EN wakeup enable -0: disable -1: enable - - - T3_AWK_EN wakeup enable -0: disable -1: enable - - - T2_AWK_EN wakeup enable -0: disable -1: enable - - - T1_AWK_EN wakeup enable -0: disable -1: enable - - - P1_AWK_EN wakeup enable -0: disable -1: enable - - - AWK23_EN wakeup enable -0: disable -1: enable - - - AWK22_EN wakeup enable -0: disable -1: enable - - - AWK21_EN wakeup enable -0: disable -1: enable - - - AWK20_EN wakeup enable -0: disable -1: enable - - - AWK19_EN wakeup enable -0: disable -1: enable - - - AWK18_EN wakeup enable -0: disable -1: enable - - - AWK17_EN wakeup enable -0: disable -1: enable - - - AWK16_EN wakeup enable -0: disable -1: enable - - - AWK15_EN wakeup enable -0: disable -1: enable - - - AWK14_EN wakeup enable -0: disable -1: enable - - - AWK13_EN wakeup enable -0: disable -1: enable - - - AWK12_EN wakeup enable -0: disable -1: enable - - - AWK11_EN wakeup enable -0: disable -1: enable - - - AWK10_EN wakeup enable -0: disable -1: enable - - - AWK9_EN wakeup enable -0: disable -1: enable - - - AWK8_EN wakeup enable -0: disable -1: enable - - - AWK7_EN wakeup enable -0: disable -1: enable - - - AWK6_EN wakeup enable -0: disable -1: enable - - - AWK5_EN wakeup enable -0: disable -1: enable - - - AWK4_EN wakeup enable -0: disable -1: enable - - - AWK3_EN wakeup enable -0: disable -1: enable - - - AWK2_EN wakeup enable -0: disable -1: enable - - - AWK1_EN wakeup enable -0: disable -1: enable - - - AWK0_EN wakeup enable -0: disable -1: enable - - - - - AP_AWK_ST - - - CP_AWK_EN CP wakeup enable register - - P2_AWK_EN wakeup enable -0: disable -1: enable - - - T6_AWK_EN wakeup enable -0: disable -1: enable - - - T5_AWK_EN wakeup enable -0: disable -1: enable - - - T4_AWK_EN wakeup enable -0: disable -1: enable - - - T3_AWK_EN wakeup enable -0: disable -1: enable - - - T2_AWK_EN wakeup enable -0: disable -1: enable - - - T1_AWK_EN wakeup enable -0: disable -1: enable - - - P1_AWK_EN wakeup enable -0: disable -1: enable - - - AWK23_EN wakeup enable -0: disable -1: enable - - - AWK22_EN wakeup enable -0: disable -1: enable - - - AWK21_EN wakeup enable -0: disable -1: enable - - - AWK20_EN wakeup enable -0: disable -1: enable - - - AWK19_EN wakeup enable -0: disable -1: enable - - - AWK18_EN wakeup enable -0: disable -1: enable - - - AWK17_EN wakeup enable -0: disable -1: enable - - - AWK16_EN wakeup enable -0: disable -1: enable - - - AWK15_EN wakeup enable -0: disable -1: enable - - - AWK14_EN wakeup enable -0: disable -1: enable - - - AWK13_EN wakeup enable -0: disable -1: enable - - - AWK12_EN wakeup enable -0: disable -1: enable - - - AWK11_EN wakeup enable -0: disable -1: enable - - - AWK10_EN wakeup enable -0: disable -1: enable - - - AWK9_EN wakeup enable -0: disable -1: enable - - - AWK8_EN wakeup enable -0: disable -1: enable - - - AWK7_EN wakeup enable -0: disable -1: enable - - - AWK6_EN wakeup enable -0: disable -1: enable - - - AWK5_EN wakeup enable -0: disable -1: enable - - - AWK4_EN wakeup enable -0: disable -1: enable - - - AWK3_EN wakeup enable -0: disable -1: enable - - - AWK2_EN wakeup enable -0: disable -1: enable - - - AWK1_EN wakeup enable -0: disable -1: enable - - - AWK0_EN wakeup enable -0: disable -1: enable - - - - - CP_AWK_ST - - - CP_LPS_STA - - CP AKW valid -0:disvalid -1:valid - - - CP_POW_ACK sta(sleep end) -0锛歀OW -1锛欻IGH - - - CP_LPS end sta -0:don't sleep -1:IDLE end - - - paging awk锛坖ust P1 awk锛 -0:no paging awk -1:paging awk - - - SYS state -0: normal working -1: low power mode - - - - - CP_P1_TIME - - - CP_P2_TIME - - - LPS_T_TIME1 - - - LPS_T_TIME2 - - - LPS_T_TIME3 - - - LPS_T_TIME4 - - - LPS_T_TIME5 - - - LPS_T_TIME6 - - - LOAD_EN - - load_time enable -1:enable -0:disable - - - - LPS_32K_REF 32K reference counter - - - REF_32K_FNL REF_32K CONT clocked register - - - LPS_TPCTRL time stamp register - - 0: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. -1:time stamp loop - - - 1: enable -0: disable - - - - LPS_TP_STA - - 1:tstamp saved -0:nothing - - - - LOAD_TIME - - - MON_SEL - - mon15_sel: -00: select t5_awk -01: select awake[5] -10: select awake[12] -11: select awake[21] - - - mon14_sel: -00: select t4_awk -01: select awake[4] -10: select awake[11] -11: select awake[20] - - - mon13_sel: -00: select t3_awk -01: select awake[3] -10: select awake[10] -11: select awake[19] - - - mon12_sel: -00: select t2_awk -01: select awake[2] -10: select awake[9] -11: select awake[18] - - - mon11_sel: -00: select t1_awk -01: select awake[1] -10: select awake[8] -11: select awake[17] - - - mon10_sel: -00: select p2_int -01: select awake[0] -10: select awake[7] -11: select awake[16] - - - mon9_sel: -00: select p1_awk -01: select chip_pd -10: select awake[6] -11: select awake[15] - - - mon8_sel: -00: select awake[22] -01: select awake[23] -10: select t6_awk -11: select awake[14] - - - mon7_sel: -00: select ap_chip_pd -01: select cp_ship_pd -10: select pd_aon_shutdown_d_b. -11: select awake[13] - - - mon6_sel: -00: select ap_pd_xtal -01: select cp_pd_xtal -10: select pd_aon_shutdown_m_b. -11: select t6_int. - - - mon5_sel: -00: select ap_pd_pll -01: select cp_pd_pll -10: select pd_aon_mem. -11: select t5_int. - - - mon4_sel: -00: select ap_lps_cg -01: select cp_lps_cg -10: select rst_aon_n. -11: select t4_int. - - - mon3_sel: -00: select ap_pow_on_ack -01: select cp_pow_on_ack -10: select pd_aon_iso. -11: select t3_int. - - - mon2_sel: -00: select ap_pow_on -01: select cp_pow_on -10: select clk_en_aon. -11: select t2_int. - - - mon1_sel: -00: select idst_ap -01: select idst_cp. -10: select idst_aon -11: select t1_int - - - mon0_sel: -00: select idct_ap. -01: select idct_cp. -10: select pm2_mode_en. -11: select p1_int - - - - - LPS_RES0 - - - LPS_RES1 - - - LPS_RES2 - - - LPS_RES3 - - - LPS_RES4 - - - LPS_RES5 - - - LPS_RES6 - - - LPS_RES7 - - - LPS_RES8 - - - LPS_RES9 - - - LPS_RES10 - - - LPS_RES11 - - - CP_P1_EN - - paging timer en -1:enable -0:disable - - - - CP_P2_TEN - - awake timer en -1:enable -0:disable - - - - LPS_T1_EN - - target_time en -1:enable -0:disable - - - - LPS_T2_EN - - target_time en -1:enable -0:disable - - - - LPS_T3_EN - - target_time en -1:enable -0:disable - - - - LPS_T4_EN - - target_time en -1:enable -0:disable - - - - LPS_T5_EN - - target_time en -1:enable -0:disable - - - - LPS_T6_EN - - target_time en -1:enable -0:disable - - - - AP_AWK_EN1 - - T9_AWK_EN wakeup enable -0: disable -1: enable - - - T8_AWK_EN wakeup enable -0: disable -1: enable - - - T7_AWK_EN wakeup enable -0: disable -1: enable - - - - - AP_AWK_ST1 - - clear ap wake state register when writing 1 to correspond bits. - - - - CP_AWK_EN1 - - T9_AWK_EN wakeup enable -0: disable -1: enable - - - T8_AWK_EN wakeup enable -0: disable -1: enable - - - T7_AWK_EN wakeup enable -0: disable -1: enable - - - - - CP_AWK_ST1 - - clear ap wake state register when writing 1 to correspond bits. - - - - LPS_T_TIME7 - - - LPS_T_TIME8 - - - LPS_T_TIME9 - - - LPS_T7_EN - - target_time en -1:enable -0:disable - - - - LPS_T8_EN - - target_time en -1:enable -0:disable - - - - LPS_T9_EN - - target_time en -1:enable -0:disable - - - - CP_PM2_MODE_EN CP PM2 enable - - CP enable PM2 mode -0:disable PM2 mode -1:enable PM2 mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - user_gate_force_off - - lps_ahb_ana_wrap3_force_off force clk on, default : 1'b0 - - - lps_ahb_idle_lps_force_off force clk on, default : 1'b0 - - - lps_ahb_pwrctrl_func_force_off force clk on, default : 1'b0 - - - lps_ahb_pwrctrl_intf_force_off force clk on, default : 1'b0 - - - lps_ahb_keypad_osc_force_off force clk on, default : 1'b0 - - - lps_ahb_keypad_always_force_off force clk on, default : 1'b0 - - - lps_ahb_keypad_force_off force clk on, default : 1'b0 - - - lps_ahb_apb_reg_force_off force clk on, default : 1'b0 - - - lps_ahb_gpt1_force_off force clk on, default : 1'b0 - - - lps_ahb_gpio_mod_force_off force clk on, default : 1'b0 - - - lps_ahb_gpio1_force_off force clk on, default : 1'b0 - - - lps_ahb_uart1_force_off force clk on, default : 1'b0 - - - lps_ahb_uart1_always_force_off force clk on, default : 1'b0 - - - lps_ahb_uart1_mod_force_off force clk on, default : 1'b0 - - - lps_ahb_to_aon_force_off force clk on, default : 1'b0 - - - lps_32k_fr_force_off force clk on, default : 1'b0 - - - uart1_bf_div_uart1_always_force_off force clk on, default : 1'b0 - - - uart1_bf_div_uart1_force_off force clk on, default : 1'b0 - - - - user_gate_auto_gate_en - - lps_ahb_ana_wrap3_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_idle_lps_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_pwrctrl_func_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_pwrctrl_intf_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_keypad_osc_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_keypad_always_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_keypad_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_apb_reg_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_gpt1_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_gpio_mod_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_gpio1_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_uart1_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_uart1_always_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_uart1_mod_auto_gate_en auto gate en, default : 1'b1 - - - lps_ahb_to_aon_auto_gate_en auto gate en, default : 1'b1 - - - lps_32k_fr_auto_gate_en auto gate en, default : 1'b1 - - - uart1_bf_div_uart1_always_auto_gate_en auto gate en, default : 1'b1 - - - uart1_bf_div_uart1_auto_gate_en auto gate en, default : 1'b1 - - - - - cgm_uart1_bf_div_sel_cfg - - cgm_uart1_bf_div_sel: clk_uart1_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_26m, default: 2'h1 - - - - - cgm_lps_ahb_sel_cfg - - cgm_lps_ahb_sel: clk_lps_ahb source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_26m, default: 2'h1 - - - - cgm_busy_src_monitor_cfg0 - - cgm_busy_src_monitor0, 0:(cgm_uart1_bf_div_sel_ac == 2) & cgm_busy_uart1_bf_div 1:cgm_busy_lps_ahb_sel_2 & cgm_busy_lps_ahb 2:(cgm_uart1_bf_div_sel_ac == 1) & cgm_busy_uart1_bf_div 3:cgm_busy_lps_ahb_sel_1 & cgm_busy_lps_ahb 4:(cgm_uart1_bf_div_sel_ac == 3) & cgm_busy_uart1_bf_div 5:cgm_busy_lps_ahb_sel_3 & cgm_busy_lps_ahb 6:(cgm_uart1_bf_div_sel_ac == 0) & cgm_busy_uart1_bf_div 7:cgm_busy_lps_32k 8:cgm_busy_lps_ahb_sel_0 & cgm_busy_lps_ahb - - - - - - - - - - - - - - - - - - soft_cnt_done0_cfg - - rc26m_26m_soft_cnt_done counter wait for source stable - - - - pll_wait_sel0_cfg - - rc26m_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control - - - - pll_wait_sw_ctl0_cfg - - rc26m_26m_wait_force_en pll wait's enable sw control - - - - - gate_en_sel0_cfg - - cgm_rtc_32k_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rtc_32k_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rtc_32k_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rtc_32k_lps_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - cgm_rc_26m_lps_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control - - - - gate_en_sw_ctl0_cfg - - cgm_rtc_32k_ap_force_en clock gating enable sw control - - - cgm_rc_26m_ap_force_en clock gating enable sw control - - - cgm_rtc_32k_cp_force_en clock gating enable sw control - - - cgm_rtc_32k_aon_force_en clock gating enable sw control - - - cgm_rc_26m_aon_force_en clock gating enable sw control - - - cgm_rtc_32k_lps_force_en clock gating enable sw control - - - cgm_rc_26m_lps_force_en clock gating enable sw control - - - - monitor_wait_en_status0_cfg - - monitor_wait_en_status , 0:rc26m_26m - - - - monitor_gate_auto_en_status0_cfg - - monitor_gate_auto_en_status , 0:cgm_rtc_32k_ap, 1:cgm_rc_26m_ap, 2:cgm_rtc_32k_cp, 3:cgm_rtc_32k_aon, 4:cgm_rc_26m_aon, 5:cgm_rtc_32k_lps, 6:cgm_rc_26m_lps - - - - - - - - - module enable module enable - - Reserved Enable. Active High; -0 : Disable ; -1 : Enable ; - - - mtx_cfg Enable. Active High; -0 : Disable ; -1 : Enable ; - - - pagespy Enable. Active High; -0 : Disable ; -1 : Enable ; - - - - Soft Reset Soft Reset - - Reserved Soft Reset. Active High; -0 : Keep module in normal mode; -1 : Reset module; - - - mtx_cfg Soft Reset. Active High; -0 : Keep module in normal mode; -1 : Reset module; - - - dmc400 Soft Reset. Active High; -0 : Keep module in normal mode; -1 : Reset module; - - - pagespy Soft Reset. Active High; -0 : Keep module in normal mode; -1 : Reset module; - - - - debug_ctrl debug_ctrl - - - psram sleep ctrl psram sleep ctrl - - half_slp_reg - - - enable - - - force_reg - - - force_en - - - wait_num - - - - psram gate_sel psram gate_sel - - gate_auto_sel - - - - psram gate_force psram gate_force - - gate_force_en - - - - cgm_psram cgm_psram - - cgm_psram_2x_sel - - - cgm_psram_2x_div - - - cgm_psram_1x_div - - - - lpc_ctrl0 lpc_ctrl0 - - pu_num - - - lp_num - - - - lpc_ctrl1 lpc_ctrl1 - - lp_force - - - lp_eb - - - - pub_anti_hang pub_anti_hang - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: enable error response -0: always response OK - - - 1: select fw ID -0: select matrix id - - - - - monitor_clock_status monitor_clock_status - - monitor_cgm_busy_status - - - monitor_gate_en_status - - - - debug_status debug_status - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1: use external resetn -0: use sw/enable generated internal resetn for rxdp - - - 0: clk_dac -1: clk_dac invert - - - 0: clk_adc -1: clk_adc invert - - - 0:no use -1:no use -2:LTE-1.4M -3:LTE-3M -4:LTE-5M -5:LTE-10M -6:LTE-15M -7:LTE-20M -8:no use - - - 0:30.72MHz -1:61.44MHz -2:122.88MHz - - - 0: IF mode -1: ZF mode - - - - - - 0: registers module clk gating enabled; -1: registers module clk always on; -new add for debug, should not config - - - 0: RX CIC1 doesn't work in loft mode; -1: RX CIC1 works in loft mode - - - sw controlled resetn for rxdp -0: assert reset -1: not reset - - - DFE clock shift control. Change in 8910m, when clock_shift enable, only config this bit, no need config rxdp_rc or txdp_rc (deleted) -0: clock shift disabled -1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency - - - clock enable for BB LTE @122.88MHz - - - clock enable for DFE NB/WT/LTE TX - - - clock enable for DFE RX - - - clock enable for DAC - - - clock eanble for ADC - - - - - - Start to load DC value, active high. Before next load, set it low firstly - - - IQ swap in DC module -0: no swap -1. swap - - - Hold DC accumulator calculation in DC calibration mode - - - This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc - - - Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. - - - Load DC value in calibration mode to debug port, only used for debug purpose - - - DC module work mode. -0: DC calibration mode -1: DC cancel mode - - - - - - DC real part value used in cancel mode - - - - - - DC image part value used in cancel mode - - - - - - Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - - Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - - Slow convergence control, work with conv_mode_ct_rg register - - - Fast convergence control, work with conv_mode_ct_rg register - - - Duration time of DC calibration, which is based on sample unit - - - DC convergence loop mode selection. -0: fast -1: slow -2: fast->slow -3: fast->hold - - - - - - load rxdp_gain_ct to DFE. -Write it to 1b'0 before assert it; new add, when [12]=0, need use this bit - - - bypass rxdp_gain_ct_load; new add, -1: direct use [10:0] in static adjust agc gain -0: use [10:0] need load first for dynamic adjust agc gain - - - Gain BB control. [-24db, 47.9375db], step=1/16db; -change the step from 1/8db to 1/16db - - - - - - - Bit [15:0] of RX group delay coefficient 0 - - - - - - Bit [19:16] of RX group delay coefficient 0 - - - - - - Bit [15:0] of RX group delay coefficient 1 - - - - - - Bit [19:16] of RX group delay coefficient 1 - - - - - - Bit [15:0] of RX group delay coefficient 2 - - - - - - Bit [19:16] of RX group delay coefficient 2 - - - - - - Bit [15:0] of RX group delay coefficient 3 - - - - - - 1: LP -0: BP - - - Bit [19:16] of RX group delay coefficient 3 - - - - - - Read rate of DFE ADC FIFO, which depends on RX mode. 8910m move 0x0060[12:7] to here[6:1] -5'h00: GGE -5'h01: NB/WT - - - Write enable of DFE ADC FIFO, active high - - - - - - - Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high - - - - - - Real part of DC value, it is stable when rxdp_dcc_val_reg is high - - - - - - Image part of DC value, it is stable when rxdp_dcc_val_reg is high - - - - - - Data enable of Notch DC -0: disable -1: enable - - - - - - - Coefficient a for real part of Notch DC - - - - - - Coefficient a for image part of Notch DC - - - - - - Coefficient k of Notch DC - - - - - - mrrm bandwidth selection - - - - - - Data enable of Notch H 1st core -0: disable -1: enable - - - Data enable of Notch H 2nd core -0: disable -1: enable - - - - - - Coefficient a for real part of Notch H 1st core - - - - - - Coefficient a for image part of Notch H 1st core - - - - - - Coefficient a for real part of Notch H 2nd core - - - - - - Coefficient a for image part of Notch H 2nd core - - - - - - Coefficient k of Notch H 1st core - - - Coefficient k of Notch H 2nd core - - - - - - Coefficient COEF0 of ACI filter - - - - - - Coefficient COEF1 of ACI filter - - - - - - Coefficient COEF2 of ACI filter - - - - - - Coefficient COEF3 of ACI filter - - - - - - Coefficient COEF4 of ACI filter - - - - - - Coefficient COEF5 of ACI filter - - - - - - Coefficient COEF6 of ACI filter - - - - - - Coefficient COEF7 of ACI filter - - - - - - Coefficient COEF8 of ACI filter - - - - - - Coefficient COEF9 of ACI filter - - - - - - Coefficient COEF10 of ACI filter - - - - - - Coefficient COEF11 of ACI filter - - - - - - Coefficient COEF12 of ACI filter - - - - - - Coefficient COEF13 of ACI filter - - - - - - Coefficient COEF14 of ACI filter - - - - - - Coefficient COEF15 of ACI filter - - - - - - Coefficient COEF16 of ACI filter - - - - - - Coefficient COEF17 of ACI filter - - - - - - Coefficient COEF18 of ACI filter - - - - - - Coefficient COEF19 of ACI filter - - - - - - Coefficient COEF20 of ACI filter - - - - - - Coefficient COEF21 of ACI filter - - - - - - Coefficient COEF22 of ACI filter - - - - - - Coefficient COEF23 of ACI filter - - - - - - Bit [15:0] of frequency offset for Mixer - - - - - - Bit [23:16] of frequency offset for Mixer - - - - - - RSSI3 enable - - - RSSI3 ushift value - - - Outband RSSI enable - - - Inband RSSI enable - - - Outband RSSI ushift value - - - Inband RSSI ushift value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - start inband RSSI max and min measurement - - - - - - timer count[15:0] for max and min measurement report after start - - - - - - timer count[31:16] for max and min measurement report after start - - - - - - start to load max and min measurement report. Before next load, set it low firstly - - - - - - valid of max and min measurement report - - - inband RSSI min value - - - - - - inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high - - - - - - interrupt status to be able to start to load max and min measurement report - - - interrupt mask - - - interrupt clear - - - - - - indication to read instant measurement report - - - - - - valid of instant measurement report - - - - - - inband RSSI instant value - - - - - - start outband RSSI max and min measurement - - - - - - timer count[15:0] for max and min measurement report after start - - - - - - timer count[31:16] for max and min measurement report after start - - - - - - indication to read max and min measurement report - - - - - - valid of max and min measurement report - - - - - - outband RSSI min value - - - - - - outband RSSI max value - - - - - - interrupt status to be able to start to load max and min measurement report - - - interrupt mask - - - interrupt clear - - - - - - indication to read instant measurement report - - - - - - valid of instant measurement report - - - - - - outband RSSI instant value for WD - - - - - - outband RSSI instant value for UP - - - - - - outband RSSI instant value for DN - - - - - - - - - - - - - - Gain_BB - - - Notrch(H) 2nd core - - - Notrch(H) 1st core - - - Deci. HBF1 - - - ACI Filter - - - Group Delay Equ - - - Notch(DC) - - - Mixer - - - RC - - - DC Calib.&Cancel - - - Deci.CIC1 - - - - - - dnhb2 - - - imbc - - - mrrm - - - - - - Gain_BB - - - Notrch(H) 2nd core - - - Notrch(H) 1st core - - - Deci. HBF1 - - - ACI Filter - - - Group Delay Equ - - - Notch(DC) - - - Mixer - - - RC - - - DC Calib.&Cancel - - - Deci.CIC1 - - - - - - dnhb2 - - - imbc - - - mrrm - - - - - - instant value of rxdp_dcc_re, new add for debug - - - - - - instant value of rxdp_dcc_im, new add for debug - - - - - - instant value of rssi_reg_ib_rssi, new add for debug - - - - - - instant value of rssi_reg_wd_ob_rssi, new add for debug - - - - - - instant value of rssi_reg_up_ob_rssi, new add for debug - - - - - - instant value of rssi_reg_dn_ob_rssi, new add for debug - - - - - - - - - - - - - - start RSSI3 max and min measurement - - - - - - timer count[15:0] for max and min measurement report after start - - - - - - timer count[31:16] for max and min measurement report after start - - - - - - start to load max and min measurement report. Before next load, set it low firstly - - - - - - valid of max and min measurement report - - - RSSI3 min value - - - - - - RSSI3 max value, it is stable when rssi_max_min_val_reg_rssi3 is high - - - - - - interrupt status to be able to start to load max and min measurement report - - - interrupt mask - - - interrupt clear - - - - - - indication to read instant measurement report - - - - - - valid of instant measurement report - - - - - - RSSI3 instant value - - - - - - instant value of rssi_reg_rssi3, new add for debug - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it, new add, when [12]=0, need use this bit - - - bypass txdp_wedge_gain_ct_load; new add, 1: direct use [10:0] in static adjust agc gain 0: use [10:0] need load first for dynamic adjust agc gain - - - Gain control of NB/WT TX. [-24db, 47.9375db], step=1/16db; change the step from 1/8db to 1/16db - - - - - - - - - - - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - Amplitude compensation curve of DPD - - - - - - - Coefficient 4 of ACLR filter, new add - - - - - - Coefficient 5 of ACLR filter, new add - - - - - - Coefficient 6 of ACLR filter, new add - - - - - - Coefficient 7 of ACLR filter, new add - - - - - - - - - - resource of clk_dac when test mode. -00: clk_122p88m -01: clk_61p44m -10: clk_30p72m -11: clk_adc_gge_nb - - - enable clk_dac when test mode - - - 0: clk_dac is from function mode -1: clk_dac is from test mode - - - - - - txdp_delay - - - - - - Coefficient 0 of ACLR filter, new add - - - - - - Coefficient 1 of ACLR filter, new add - - - - - - Coefficient 2 of ACLR filter, new add - - - - - - Coefficient 3 of ACLR filter, new add - - - - - - Bit [15:0] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [19:16] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [15:0] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [19:16] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [15:0] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [19:16] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [15:0] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX - - - - - - Bit [19:16] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - no use - - - no use - - - no use - - - - no use - - - no use - - - - - - - - - - - - - - - - - BB TX data loopback to BB RX - - - BB RX IQ swap. -1: swap; -0: normal - - - BB TX IQ swap. -1: swap; -0: normal - - - ADC IQ swap. -1: swap; -0: normal - - - DAC IQ swap. 1: swap; 0: normal - - - BB RX. -0: two's complement -1: offset binary - - - BB TX. -0: two's complement -1: offset binary - - - RF ADC. -0: two's complement -1: offset binary - - - RF DAC. -0: two's complement -1: offset binary - - - - - - instant value of txdp_loft_rssi_err - - - - - - - valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high - - - start to load the result of temper_dout. Before next load, set it low firstly - - - - bandwidth select - - - no use - - - - - - - - temper_dout value - - - - - - clock enable for temper - - - divide mode of clock from analog for Temcomp -0: not divide -1: 1/2 divide -2: 1/4 divide -3: 1/8 divide - - - clock invert for Temcomp -0: clock invert disable -1: clock invert enable - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - instant value of temper_dout - - - - - - - valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high - - - start to load the result of temper_dout. Before next load, set it low firstly - - - - bandwidth select - - - no use - - - - - - - - temper_dout value - - - - - - clock enable for temper - - - divide mode of clock from analog for Temcomp -0: not divide -1: 1/2 divide -2: 1/4 divide -3: 1/8 divide - - - clock invert for Temcomp -0: clock invert disable -1: clock invert enable - - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - Coefficient of filter - - - - - - - instant value of temper_dout - - - - - - - dfe_sw_clkgate_en - - - - - - swap of dfe_monitor[15:8] and dfe_monitor[7:0] - - - dfe_monitor select - - - - - - The offset on DAC real part - - - - - - The offset on DAC image part - - - - - - The DAC real part on test mode - - - - - - The DAC image part on test mode - - - - - - - select of function DAC data or test DAC data -00/01: select function DAC data including sine waveform -10: select test DAC data in txdp -11: select test DAC data in txdp - - - enable sine generation module - - - enable of test DAC data in rxdp - - - select of test DAC data in rxdp - - - enable of test DAC data in txdp - - - select of test DAC data in txdp - - - - - - sine amp - - - - - - sine frequency[15:0] - - - - - - LOFT - - - LOFT - - - sine frequence[22:16] - - - - - - UPHBF(3) - - - UPHBF(2) - - - Group Delay Equ. - - - AMPM of DPD - - - Whole DPD - - - RC - - - Gain - - - CFR - - - UPHBF(1) - - - ACLR LPF - - - ampequ, new add - - - - - - UPHBF(3) - - - UPHBF(2) - - - Group Delay Equ. - - - AMPM of DPD - - - Whole DPD - - - RC - - - Gain - - - CFR - - - UPHBF(1) - - - ACLR LPF - - - ampequ - - - - - - - all zero bits, reserved for ECO - - - - - - all one bits, reserved for ECO - - - - - - all one bits, reserved for ECO - - - - - - - pwr_rf_ushift_rg - - - pwr_rf_start_rg - - - pwr_rf_polar_rg - - - - - - - - - - - - - - - - - - - - - - 1: clk always on, 0: clk gating by hardware - - - - - - 1: clk always on, 0: clk gating by hardware - - - - - - - - - - - - - - - - - - - 1: clk always on, 0: clk gating by hardware - - - - - - determine dac bits position when test mode. -0:[11:0], -1:[12:1], -2:[13:2], -3:[14:3], -4:[15:4] - - - - - - Bit [11:0] of coefficient 0 of ampequ. for NB/LTE/eMTC TX - - - - - - Bit [11:0] of coefficient 1 of ampequ. for NB/LTE/eMTC TX - - - - - - Bit [11:0] of coefficient 2 of ampequ. for NB/LTE/eMTC TX - - - - - - Bit [11:0] of coefficient 3 of ampequ. for NB/LTE/eMTC TX - - - - - - Bit [27:12] of gain for ampequ. for NB/LTE/eMTC TX, must config for all tx, init value 0x400 - - - - - - Bit [11:0] of gain for ampequ. It works with register txdp_ampequ_g_rg - - - - - - read interval for FIFO A, new add change with different rx mode - - - read interval for FIFO B, new add change with different rx mode - - - - - - - FIFO dump full - - - FIFO dump empty - - - FIFO txdp_rc full - - - FIFO txdp_rc empty - - - FIFO rxdp_rc full - - - FIFO rxdp_rc empty - - - FIFO ADC full - - - FIFO ADC empty, this FIFO used between ADC and DFE - - - FIFO B full - - - FIFO B empty, this FIFO used when LVDS RX for adc-dfe-lvds-bb - - - FIFO A full - - - FIFO A empty, this FIFO used when normal RX or LVDS TX for adc-dfe-lvds-bb - - - - - - - clock frequency select when dump FIFO write -0000: clk_122p88m_m -0001: clk_adc -001x: clk_245p76m -01xx: clk_245p76m_m -1xxx: clk_pwd - - - valid width select when dump -00: 1 cycle period (245.76M) -01: 2 cycle period (245.76M) -10: 3 cycle period (245.76M) -11: 4 cycle period (245.76M) - - - enable dump - - - - dump node selection. It works with register sel_clk_dump_w for correct clock. -0: dump RX data from DFE, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref -1: dump TX data from BB, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref -2: dump RXDP data, sel_clk_dump_w can be clk_rxdp/clk_rxdp_m -3: dump TXDP data, sel_clk_dump_w can be clk_txdp/clk_245p76m_m(clk_txdp_m)/clk_pwd -others: dump data from LVDS, sel_clk_dump_w can be can be lvds2dfe_clk - - - - - - Coefficient 8 of ACLR filter, new add - - - - - - Coefficient 9 of ACLR filter, new add - - - - - - Coefficient 10 of ACLR filter, new add - - - - - - Coefficient 11 of ACLR filter, new add - - - - - - Coefficient 12 of ACLR filter, new add - - - - - - Coefficient 13 of ACLR filter, new add - - - - - - Coefficient 14 of ACLR filter, new add - - - - - - Coefficient 15 of ACLR filter, new add - - - - - - Coefficient 16 of ACLR filter, new add - - - - - - Coefficient 17 of ACLR filter, new add - - - - - - Coefficient 18 of ACLR filter, new add - - - - - - Coefficient 19 of ACLR filter, new add - - - - - - Coefficient 20 of ACLR filter, new add - - - - - - Coefficient 21 of ACLR filter, new add - - - - - - Coefficient 22 of ACLR filter, new add - - - - - - Coefficient 23 of ACLR filter, new add - - - - - - Start to load DC value, active high. Before next load, set it low firstly - - - IQ swap in DC module -0: no swap -1. swap - - - Hold DC accumulator calculation in DC calibration mode - - - This register is used. - - - Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. - - - Load DC value in calibration mode to debug port, only used for debug purpose - - - DC module work mode. -0: DC calibration mode -1: DC cancel mode - - - - - - DC real part value used in cancel mode - - - - - - DC image part value used in cancel mode - - - - - - Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - - Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - - Slow convergence control, work with conv_mode_ct_rg register - - - Fast convergence control, work with conv_mode_ct_rg register - - - Duration time of DC calibration, which is based on sample unit - - - DC convergence loop mode selection. -0: fast -1: slow -2: fast->slow -3: fast->hold - - - - - - Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high - - - - - - Real part of DC value, it is stable when pwd_dcc_val_reg is high - - - - - - Image part of DC value, it is stable when pwd_dcc_val_reg is high - - - - - - instant value of rxdp_dcc_re, new add for debug - - - - - - instant value of rxdp_dcc_im, new add for debug - - - - - - - - - - - 1:閫夋嫨LTE BBPLL tuned 122.88M锛0锛氶夋嫨鏅朵綋untuned 26M - - - 杞欢璋冩暣122.88m璁℃暟鍛ㄦ湡鐢熸晥鏃跺埢閫夋嫨0锛氫笅甯ц捣鏁堬紱1锛氬綋甯ц捣鏁 - - - 杞欢璋冩暣122.88m璁℃暟鍛ㄦ湡浣胯兘锛岀敓鏁堟椂鍒诲彲閫 - - - 杞欢璋冩暣122.88M counter璁℃暟鍊间娇鑳斤紝绔嬪嵆鐢熸晥 - - - 杞欢Latch 122.88m counter浣胯兘 - - - GNSS RTC/CPU/EM Latch 122.88m counter浣胯兘 - - - Tuned 122.88M counter璁℃暟娓呴浂 - - - Tuned 122.88M counter璁℃暟浣胯兘 - - - 杞欢latch bitmap wptr鍐欐寚閽堝拰寰幆璁℃暟鍊间娇鑳 - - - GNSS RTC/CPU/EM Latch bitmap wptr鍐欐寚閽堝拰寰幆璁℃暟鍊间娇鑳 - - - 娓呴櫎bitmap寰幆鍒0锛屾竻闄ptr鍐欐寚閽 - - - Bitmap鍔熻兘寮鍏充娇鑳 - - - - - - Bitmap寰幆鍛ㄦ湡璁剧疆锛岄粯璁や负0-127寰幆锛屾渶澶0-255寰幆,Bitmap鍔熻兘鍚姩鍓嶉渶瑕侀厤缃畬姣曪紝鍚姩杩囩▼涓笉鏀寔淇敼 - - - - - - 122.88M璁℃暟涓柇浜х敓鍛ㄦ湡璁剧疆锛岄粯璁や负1ms锛涘鏋滄槸26M锛1ms瀵瑰簲鍊兼槸0x658F - - - - - - 122.88M璁℃暟涓柇浜х敓鍛ㄦ湡璁剧疆锛岄粯璁や负1ms锛涘鏋滄槸26M锛1ms瀵瑰簲鍊兼槸0x0 - - - - - - 杞欢璋冩暣122.88M/26M counter璁℃暟鍊硷紝绔嬪嵆鐢熸晥 - - - - - - 杞欢璋冩暣122.88M/26M counter璁℃暟鍊硷紝绔嬪嵆鐢熸晥 - - - - - - 杞欢璋冩暣122.88M/26M counter璁℃暟鍊硷紝绔嬪嵆鐢熸晥 - - - - - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛屻17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛屻17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - - - - 122.88M/26M counter璁℃暟鍊硷紝GNSS RTC/CPU/EM Latch銆佽蒋浠禠atch浣胯兘鍚庢洿鏂帮紝鍏48bit锛屻17锛0銆戜负1ms璁℃暟寰幆锛屻21锛18銆戜负10ms璁℃暟寰幆锛屻48锛22銆戜负璁℃弧寰幆锛屾牸寮忓悓LTE Frame timer3 - - - - - - - Bitmap wptr鍐欐寚閽堬紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - Bitmap缃綅璁℃暟鍊硷紝杞欢latch浣胯兘鍚庢洿鏂帮紝鍒ゆ柇鍒皏alid涓1鍚庢湁鏁 - - - - - - - LTE-GNSS淇℃伅浜や簰bit瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - Bitmap杞欢缃綅瀵勫瓨鍣紝淇濈暀杞欢浣跨敤 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bandgap trim - - - ISM TXABB LDO output voltage selection -ISM TXABB LDO output voltage control signal -000 0.84V 100 0.96V -001 0.87V 101 0.99V -010 0.9V 110 1.02V -011 0.93V 111 1.05V - - - Top LevelShIft LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol VDD_input -00 1.8V -01 1.5V -10 1.2V -11 1.2V - - - - - - LNA ldo power up - - - LNA ldo fast charge en - - - RX ABB ldo power up - - - RX ABB ldo fast charge en - - - ADC LDO bias enable - - - ADC LDO enable - - - TX filter ldo power up - - - TX filter ldo fast charge en - - - DAC LDO enable - - - DAC LDO fast charge - - - PWDADC LDO bias enable, only used in ditital domain - - - PWDADC LDO enable, only used in digital domain - - - - - - rxpll gro ldo bias en - - - rxpll gro ldo en - - - RXPLL presc ldo power up - - - RXPLL presc ldo fast charge en - - - RXPLL RDAC ldo digital power up - - - RXPLL RDAC ldo vref power up - - - RXPLL RDAC ldo fast charge en - - - RX VCO ldo power up - - - RX VCO ldo fast charge en - - - RX VCO ldo load en - - - RX VCO buffer ldo power up - - - RX VCO buffer ldo fast charge en - - - RX VCO buffer ldo load en - - - RX VCO TC power up - - - RX VCO TC fast charge en - - - - - - txpll gro ldo bias en - - - txpll gro ldo en - - - TXPLL presc ldo power up - - - TXPLL presc ldo fast charge en - - - TXPLL RDAC ldo digital power up - - - TXPLL RDAC ldo vref power up - - - TXPLL RDAC ldo fast charge en - - - TX VCO ldo power up - - - TX VCO ldo fast charge en - - - TX VCO ldo load en - - - TX VCO buffer ldo power up - - - TX VCO buffer ldo fast charge en - - - TX VCO buffer ldo load en - - - TX VCO TC power up - - - TX VCO TC fast charge en - - - - - - Pu of bandgap - - - pu_mdll_bb - - - mdll start up - - - TO AVDDDCXO_18 & AVSS_CLK -pu xdrv buffer - - - - - - rxvco_bias_en - - - rxvco_ibias_en - - - rxvcoh pu - - - rxvcol pu - - - rxvco_pkdet enable - - - pu_rxpll_presc_bb - - - pu_rxpll_gro_bb - - - pu_rxpll_rdac_bb - - - rxpll_gro_rstn_bb - - - rxpll_rdac reset - - - - - - LNA power up - - - lna peak detector enable - - - RX PGA enable - - - rx pga peak detector enable - - - RX PGA DCDC IDAC power up - - - RX filter DCDC IDAC power up - - - RX filter OPA negative reset - - - RX filter enable - - - rx mixer power up - - - tia power up - - - ADC enable - - - ADC enable - - - ADC enable - - - ADC enable - - - ADC reset negative - - - - - - txvco_bias_en - - - txvco_ibias_en - - - txvcoh pu - - - txvcol pu - - - peak detector enable - - - pu_txpll_presc_bb - - - - txpll RDAC power up - - - txpll_gro_rstn_bb - - - txpll RDAC reset - - - - - - TX filter reset negative - - - DAC power up control - - - DAC reset negative - - - TX mixer work on enable - - - TX filter power up control - - - to AVDDRF_18 & AVSS_CLK -txrf power on conrol - - - to AVDDRF_18 & AVSS_CLK -TX PA driver work on enable - - - to AVDDRF_18 & AVSS_CLK -power detector power up - - - PWDADC reset negative - - - PWD PGA power up - - - PWDADC enable - - - PWDADC enable - - - PWDADC enable - - - PWDADC enable - - - PWD reset negative - - - - - - to AVDDRF_18 & AVSS_CLK -power detector power up delay - - - TX filter power up delay - - - to AVDDRF_18 & AVSS_CLK -txrf power on conrol delay - - - - - - Frequency division ratio of loop, -5~10. - - - Dither control enable - - - mdll_band_bit_bb - - - mdll_band_sel_bb - - - Dither control bit - - - mdll_cp_ibit_bb - - - Dither control mode selection - - - - - - Reset voltage control - - - Frequency division 1/2/4 of clock output buffer -01 /1; 10 /2; 11 /4; - - - mdll_refclk_test_en_bb - - - mdll_vctrl_test_en_bb - - - disable_refclk_rxpll_bb - - - disable_refclk_txpll_bb - - - - - - ptat current enable, for tsenadc. -TO AVDDDCXO_18 & AVSS_CLK - - - TO AVDDDCXO_18 & AVSS_CLK - - - - - - - - - - - - - - - - - - - - - - tbd - - - tbd - - - - - tbd - - - - tbd - - - tbd - - - varactor bias reverse seleted - - - - - - - - - tbd - - - tbd - - - - - - tbd - - - rxvco_lcl_div1 - - - rxvco_lcl_div2 - - - rxvco lte en - - - - - - FBDIV LDO VREF TRIM锛岄粯璁ゅ750mV - - - FBDIV LDO VOUT锛岄粯璁ゅ950mV - - - FBDIV LDO闀滃儚鏋佺偣锛1.2V VDD閰2 - - - GRO Master LDO VREF TRIM锛岄粯璁ゅ750mV - - - GRO Master LDO VOUT锛岄粯璁ゅ950mV - - - - - - GRO Master LDO CP TRIM - - - GRO Master Slave LDO VDDRES - - - RDAC DIG LDO VREF TRIM,榛樿鍊750mV - - - RDAC DIG LDO VOUT,榛樿鍊950mV - - - RDAC DIG LDO 闀滃儚鏋佺偣, 1.2V VDD閰2 - - - - - - RDAC VREF LDO VREF TRIM,榛樿鍊750mV - - - RDAC VREF LDO VOUT,榛樿鍊880mV - - - RDAC VREF LDO 闀滃儚鏋佺偣, 1.2V VDD閰2 - - - FBDIV VDDRES - - - - - - <3> 鏍规嵁mdll閫夋嫨slave ldo鏄惁闇瑕佸苟鍏ラ澶栫殑nmos锛宮dll<4锛岄厤缃负1锛沵dll>=4锛岄厤缃负0锛 -<4> rxpll_gro_ldo_in_trim_en - - - - - - [15]mod23_enb聽 聽[14]mod3_dly_more [13:4]clk_sample & clk_dig dly 聽[3:2]pfd姝诲尯鏃堕棿 [1:0]gro mode - - - - - - [1:0]clk_en for tdc cal -[2]鍦╣ro mode3鏃堕夋嫨dn_en=0鎴栬卽p_en鐨勫弽锛 - - - - - - reserved - - - - - - vlow sel, 0~1/3vh, 1~1/5vh 3~1/9vh 7~0 - - - rdac clk edge sel - - - rxpll_fbdiv sdm clk & ndiv load dly,0~dly more - - - rxpll_sdmclk_sel_bb - - - RXPLL open loop enable - - - TBD - - - - - - LNA wifi selection - - - LNA lte hb 1 selection - - - LNA lte hb 2 selection - - - LNA lte mb 1 selection - - - LNA lte mb 2 selection - - - LNA lte mb 3 selection - - - LNA lte mb 4 selection - - - LNA lte mb 5 selection - - - LNA lte gnss selection - - - LNA lte lb 1 selection - - - LNA lte lb 2 selection - - - LNA lte lb 3 selection - - - LNA lte lb 4 selection - - - LNA lte lb 5 selection - - - rxmixer LO signal selection, high for 5g VCO, low for 4g VCO; - - - rxmixer LO signal selection, high for rx VCO, low for tx VCO; - - - - - - lna_power_res_control - - - LNA LDO bypass, work at 1.2V - - - LNA LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol - - - LNA LDO output voltage control signal 000 0.825V; 001 0.85V; 010 0.875; V011 0.9V; 100 0.925V; 101 0.95V; 110 0.975V; 111 1.0V; - - - lna gain0, not used - - - LNA Feedback resistor enable - - - - - - LNA peak detector threshold level control signa - - - tbd - - - tbd - - - LNA peak detector threshold level control signal. - - - LNA input matching capbank tune - - - - - - Lo dc level high mode - - - Lo dc level for lte mode - - - Rin of tia. 00 for 50ohm, 11 for 250ohm - - - Tia bypass mode - - - LNA mixer matching capbank tune high band2 - - - LNA mixer matching capbank tune middle band3 - - - - - - RX ABB LDO output voltage control signal 000 0.825V; 001 0.85V; 010 0.875; V011 0.9V; 100 0.925V; 101 0.95V; 110 0.975V; 111 1.0V; - - - RX ABB LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol - - - Current of pga. 00 for 1.2mA, 11 for 3.5mA, 01 and 10 for 1.8mA. - - - Rs control, 1st pole and 2nd pole control, only valid when pga_blk_mode=1 - - - 鎺у埗琛ュ伩鐢靛澶у皬锛00 for 100f锛01 and 10 for 200f锛11 for 300f - - - 鎺у埗琛ュ伩鐢靛澶у皬锛00 is invalid锛01 and 10 for 150fF锛11 for 300fF. - - - - - - Bw control, 000 for 700KHz, 101 for 10MHz - - - Cf control, 1st pole control, only valid when pga_blk_mode=1 - - - Gsm blokcer mode enable or test model for external control the capacitor and resistor in pga - - - Rpre control, blk fliter bw control, only valid when pga_blk_mode=1 - - - 2nd pole control, only valid when pga_blk_mode=1 - - - Bw tune. 000 for 0.8*bw, 111 for 1.5*bw. - - - - - - 鎺у埗甯﹀锛屽苟tuning甯﹀锛512*40fF - - - tbd - - - tbd - - - LNA peak detector threshold level control signal. - - - - - - time for charge and discharge - - - bias current of the pkd op - - - ldo vout ctrl word - - - pga op vocm ctrl word - - - - - - Dc offset calibration - - - Dc offset calibration - - - - - - Dc offset calibration range - - - - - - aux input for filter enable - - - bandwith selection - - - bandwith tuning - - - IQ swap, not use - - - bandpass mode enable, set 0 - - - center frequency selection (not use) - - - - - - anti_kick_back_filter_bw_control - - - 鎺у埗琛ュ伩鐢靛澶у皬锛00 for 100f锛01 and 10 for 200f锛11 for 300f - - - 鎺у埗琛ュ伩鐢靛澶у皬锛00 is invalid锛01 and 10 for 150fF锛11 for 300fF. - - - RX filter bias current select - - - - - - 甯﹀妗ｄ綅鎺у埗 and tuning - - - 甯﹀妗ｄ綅鎺у埗 and tuning - - - - - - ADC LDO for charge pump output voltage control signal - - - ADC LDO input voltage control signal - - - ADC LDO output voltage control signal - - - - - - Rst time control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - Signal in delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - CLOCK OUT polarity,0:rising edge,1:falling edge - - - Compare time control - - - Loop delay time control - - - MSB compare time control - - - Noise shaping charge set time control - - - Noise shaping enable - - - - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - - - - Ns common mode voltage control - - - Offset control - - - Offset control - - - - Residual compare enable - - - Sample clock delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - STB control - - - ADC vcm calibration - - - - - - common mode voltage control - - - Vrp reference voltage control - - - Vrp control - - - TBD - - - Ns slap control - - - ADC input short for calibration - - - - - - - - - Rst time control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - Signal in delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - CLOCK OUT polarity,0:rising edge,1:falling edge - - - Compare time control - - - Loop delay time control - - - MSB compare time control - - - Noise shaping charge set time control - - - Noise shaping enable - - - - - - Ns slap control - - - Ns common mode voltage control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - Offset control - - - PWDADC input short for calibration - - - - - - Offset control - - - - Residual compare enable - - - Sample clock delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv - - - STB control - - - PWDADC clk selection - - - - - - common mode voltage control - - - Vrp reference voltage control - - - Vrp control - - - PWDADC vcm calibration - - - - - - lna gain control - - - lna bias control - - - LNA common gate bias select. - - - Pga gain control, 11 for 4k Rf, 00 for 0.5k Rf. - - - filter gain selection - - - Rf of lna for impendance matching - - - - - - [4] rxflt_bypass -[3:2] pga_dcoc_ictrl_bit<1:0> -[1:0] flt_dcoc_ictrl_bit<1:0> - - - - - - - - - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - tbd - - - tbd - - - - - tbd - - - - tbd - - - tbd - - - varactor bias reverse seleted - - - - - - - - - tbd - - - tbd - - - - - - tbd - - - txvco_lcl_div1 - - - txvco_lcl_div2 - - - txvco_tx_en_bb - - - txvco_rxlte_en_bb - - - txvco_gnss_en_bb - - - txvco_rx_div1_en_bb - - - txrfdiv_div2_en_bb - - - txrfdiv_div4_en_bb - - - txrfdiv_lte_en_bb - - - txrfdiv_pwd_en_bb - - - - - - FBDIV LDO VREF TRIM锛岄粯璁ゅ750mV - - - FBDIV LDO VOUT锛岄粯璁ゅ950mV - - - FBDIV LDO闀滃儚鏋佺偣锛1.2V VDD閰2 - - - GRO Master LDO VREF TRIM锛岄粯璁ゅ750mV - - - GRO Master LDO VOUT锛岄粯璁ゅ950mV - - - - - - GRO Master LDO CP TRIM - - - GRO Master Slave LDO VDDRES - - - RDAC DIG LDO VREF TRIM,榛樿鍊750mV - - - RDAC DIG LDO VOUT,榛樿鍊950mV - - - RDAC DIG LDO 闀滃儚鏋佺偣, 1.2V VDD閰2 - - - - - - RDAC VREF LDO VREF TRIM,榛樿鍊750mV - - - RDAC VREF LDO VOUT,榛樿鍊880mV - - - RDAC VREF LDO 闀滃儚鏋佺偣, 1.2V VDD閰2 - - - FBDIV VDDRES - - - - - - <3> 鏍规嵁mdll閫夋嫨slave ldo鏄惁闇瑕佸苟鍏ラ澶栫殑nmos锛宮dll<4锛岄厤缃负1锛沵dll>=4锛岄厤缃负0锛 -<4> txpll_gro_ldo_in_trim_en - - - - - - [15]mod23_enb聽 聽[14]mod3_dly_more [13:4]clk_sample & clk_dig dly 聽[3:2]pfd姝诲尯鏃堕棿 [1:0]gro mode - - - - - - [1:0]clk_en for tdc cal -[2]鍦╣ro mode3鏃堕夋嫨dn_en=0鎴栬卽p_en鐨勫弽锛 - - - - - - reserved - - - - - - vlow sel, 0~1/3vh, 1~1/5vh 3~1/9vh 7~0 - - - rdac clk edge sel - - - rxpll_fbdiv sdm clk & ndiv load dly,0~dly more - - - rxpll_sdmclk_sel_bb - - - RXPLL open loop enable - - - TBD - - - - - - 45 degree slice enable - - - 45 degree signal output enable - - - to AVDDRF_18 & AVSS_CLK -driver and mixer slice control - - - to AVDDRF_18 & AVSS_CLK -driver gain setting - - - mixer input rc filter attenuation - - - - - - to AVDDRF_18 & AVSS_CLK -0 deg driver gain compensation setting - - - to AVDDRF_18 & AVSS_CLK -+45 deg driver gain compensation setting - - - to AVDDRF_18 & AVSS_CLK --45 deg driver gain compensation setting - - - to AVDDRF_18 & AVSS_CLK -pad gm current bias tuning - - - - - - to AVDDRF_18 & AVSS_CLK -pad mgtr voltage bias tuning - - - to AVDDRF_18 & AVSS_CLK -pad cascade voltage bias tuning - - - to AVDDRF_18 & AVSS_CLK -output switch size control - - - to AVDDRF_18 & AVSS_CLK -output switch size control - - - to AVDDRF_18 & AVSS_CLK -45 degree load banlance for filter - - - to AVDDRF_18 & AVSS_CLK -attenuation before mixer for band difference - - - to AVDDRF_18 & AVSS_CLK -high band branch1 enable - - - to AVDDRF_18 & AVSS_CLK -high band branch2 enable - - - to AVDDRF_18 & AVSS_CLK -low band branch1 enable - - - to AVDDRF_18 & AVSS_CLK -low band branch2 enable - - - - - - to AVDDRF_18 & AVSS_CLK -frequence selection for different band. - - - to AVDDRF_18 & AVSS_CLK -frequence selection for different band. Ulb - - - driver banlun deQ tuning - - - - - - - - TBD - - - TBD - - - caplatch enable - - - cal_clk edge selection - - - TBD - - - TBD - - - ibias current control - - - TX filter output CM ctrl - - - - - - input high pass freq. control - - - test mode enable - - - filter bandwidth control - - - filter bandwidth tuning control - - - TX filter output buffer current control - - - - - - Vp_diff 00/01锛300mv;10锛600mv;11锛750mv - - - dac_auxout_en_bb - - - dac_iout_en_bb - - - bit[0]:en for tx -bit[1]:en for test - - - 0: negative;1: positive - - - vhigh control, 000:600mv, 001:644mv, 010:692mv, 011:738mv, 100:788mv, 101:835mv, 110:882mv, 111:930mv; - - - dac_core_bit_bb - - - - - - tia input common mode voltage, 00:450mv, 01:550mv, 10:650mv, 11:750mv - - - TBD - - - TBD - - - LDO - - - LDO out voltage control - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - TBD - - - - - - Dc offset calibration rxflt input - - - Dc offset calibration rxflt input - - - - - - - - - - [0] LTE_TX_VCO_DIV_BUF_EN -[1] LTE_TX_VCO_RX_DIV1_EN - - - - - - - - to AVDDRF_18 & AVSS_CLK -power detector mixer gain selection - - - - - - - - - - - - - Pwd pga dc offset calibration - - - pwd_cal_i_done_bb - - - Pwd pga dc offset calibration enable - - - Pwd pga dc offset calibration - - - pwd_cal_q_done_bb - - - Pwd pga dc offset calibration enable - - - - - - TO AVDDDCXO_18 & AVSS_CLK -LDO enable - - - TO AVDDDCXO_18 & AVSS_CLK -LDO fast charge - - - TO AVDDDCXO_18 & AVSS_CLK -TS power up - - - TO AVDDDCXO_18 & AVSS_CLK -Voltage measurement mode - - - TO AVDDDCXO_18 & AVSS_CLK -Voltage measurement mode - - - TO AVDDDCXO_18 & AVSS_CLK -Voltage measurement mode - - - TO AVDDDCXO_18 & AVSS_CLK -Chopper enable - - - TO AVDDDCXO_18 & AVSS_CLK -Chopper clock select - - - TO AVDDDCXO_18 & AVSS_CLK -ADC reference selection - - - TO AVDDDCXO_18 & AVSS_CLK -The SDMADC bias current. 000 is 2uA. - - - - - - TO AVDDDCXO_18 & AVSS_CLK -VBE control, which is used to calibrate the non-linearity of temperature sensor. - - - TO AVDDDCXO_18 & AVSS_CLK -Reset - - - TO AVDDDCXO_18 & AVSS_CLK -TS Test mode 聽power up - - - TO AVDDDCXO_18 & AVSS_CLK -VBE non linearity calibration using another SDMADC - - - TO AVDDDCXO_18 & AVSS_CLK -Biploar core beta dependance calibration - - - TO AVDDDCXO_18 & AVSS_CLK -ADC CLK select. 00 1/8 MCLK; 01 1/4 MCLK; 10 1/2 MCLK; 11 MCLK - - - TO AVDDDCXO_18 & AVSS_CLK -Clk edge selected for MCLK - - - TO AVDDDCXO_18 & AVSS_CLK -Clk edge selected for internal MCLK divider. - - - - - - TO AVDDDCXO_18 & AVSS_CLK -LDO psr improved - - - TO AVDDDCXO_18 & AVSS_CLK -LDO output voltage seltect for 1.5V - - - - - - [0] additional control bit for pwd_pga_cap_bit -[1] ISO signal for clk26m_lp_uart, 0 for isolation, vcore_top domain - - - - - - - - - - - - - - revid - - - - - - TX IF test interface open enable - - - DAC out test interface open enable - - - CLK of PLL test enable - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK -Band gap iref test switch enable - - - TX VCO ldo vref test switch enable - - - TX VCOBUF ldo vref test switch enable - - - RX ABB ldo vref test switch enable - - - RX VCO ldo vref test switch enable - - - RX VCOBUF ldo vref test switch enable - - - txvco_test_en - - - rx_5g_test_en - - - rx_4g_test_en - - - rx_lo_test_en - - - - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - to VDDIO & AVSS_CLK - - - RX PLL RDAC ldo vref test switch enable - - - TX PLL RDAC ldo vref test switch enable - - - ADC INPUT TEST EN - - - rxiq calibration signal divide by 2 enable - - - rxiq calibration signal divide by 4 enable - - - rxiq calibration signal ATT CTRL - - - - - - 0:cal sig from padrv; 1: cal sig from ext pa; - - - - - - - ed ptat current source adjust - - - ed bg current source adjust - - - rxiq calibration signal ATT adjust - - - - - - from AVDDRF_12_RF & AVSS_RF -TX dc cal output I - - - from AVDDRF_12_RF & AVSS_RF -TX dc cal output Q - - - from AVDDRF_12_LNA & AVSS_LNA -LNA peak detector output signal - - - from AVDDRF_12_LNA & AVSS_LNA -LNA peak detector output signal - - - from AVDDRF_12_CLK & AVSS_RXABB -RX PGA peak detector output signal - - - from AVDDRF_12_RX & AVSS_LNA -RX VCO peak detector output - - - from AVDDRF_12_RF & AVSS_RF -TX VCO peak detector output - - - RXPLL lock flag, generated by DLPF; - - - TXPLL lock flag, generated by DLPF; - - - - - - - - - - - - - - - - - TO AVDDDCXO_18 & AVSS_CLK -ADCLDO enable - - - TO AVDDDCXO_18 & AVSS_CLK -LDO output setting - - - TO AVDDDCXO_18 & AVSS_CLK -LDO trim setting(VREF) - - - TO AVDDDCXO_18 & AVSS_CLK -CHOP CLK setting -00:/8192 -01:/4096 -10:/2048 -11:/1024 - - - - - - TO AVDDDCXO_18 & AVSS_CLK -SAMPLE CLK setting -00:/4 -01:/4 -10:/2 -11:/1 - - - TO AVDDDCXO_18 & AVSS_CLK -ADC BIAS setting -00:10uA -01:5uA -10:15uA -11:20uA - - - TO AVDDDCXO_18 & AVSS_CLK -ADC CAPCHOP CK enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC CHOP CK enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC sample edge select: -0:positive edge 1:negative edge - - - TO AVDDDCXO_18 & AVSS_CLK -ADC enable - - - - - - TO AVDDDCXO_18 & AVSS_CLK -ADC input RC enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC offset cancel enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC reset signal, 0 to reset - - - TO AVDDDCXO_18 & AVSS_CLK -ADC input UGBUF enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC_input CM setting - - - TO AVDDDCXO_18 & AVSS_CLK -ADC_output CM setting - - - TO AVDDDCXO_18 & AVSS_CLK -CLK_TSEN_TEST channel select enable: -0: choose CLK path from 1.8V CLK_TSEN_26M -1: choose CLK path from 0.9V CLK_TSEN_TEST - - - TO AVDDDCXO_18 & AVSS_CLK -ADC BIAS setting -00:10uA -01:5uA -10:15uA -11:20uA - - - TO AVDDDCXO_18 & AVSS_CLK -ADC UGBUF CHOP CK enable - - - TO AVDDDCXO_18 & AVSS_CLK -ADC_UGBUF GBW setting - - - - - - TO AVDDDCXO_18 & AVSS_CLK - - - TO AVDDDCXO_18 & AVSS_CLK - - - TO AVDDDCXO_18 & AVSS_CLK - - - TO AVDDDCXO_18 & AVSS_CLK - - - TO AVDDDCXO_18 & AVSS_CLK - - - - - - TO AVDDDCXO_18 & AVSS_CLK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - [0]:pu_xtal from BB;[1]pu xtal from reg - - - - - - 32k gen div step_offset Normal mode - - - 32k gen div step_offset LP mode - - - - - - pu_xtal cycle select 2'b00: 4us; 2'b01:8us; 2'b10:12us; 2'b11:20us - - - - - - - - - - - - enable clk 26m lp uart to lps - - - enable clk 26m lp to analog - - - BBPLL2 ref clk 26m enable - - - BBPLL1 ref clk 26m enable - - - clk_26m_interface enable - - - RFPLL refcal clk 26m - - - pwdadc clk 26m enable - - - xtal_osc_ibit lp mode - - - xtal_osc_ibit normal mode - - - - - - xtal_cfix_bit lp mode - - - xtal_cfix_bit normal mode - - - xtal_fixi_bit lp mode - - - xtal_fixi_bit normal mode - - - - - - xdrv aux1 parameter - - - XTAL parameter - - - xdrv parameter - - - - - - CADC bit lp mode - - - CADC bit normal mode - - - - - - RTC - - - - - - RTC - - - - - - normal mode switch to PSM counter - - - - - - normal mode switch to PSM counter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ細浜х敓涓柇缁檙iscv - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - CP-A5鍐欐瀵勫瓨鍣ㄤ笉浼氫骇鐢熶腑鏂粰riscv锛屼粎鐢ㄤ簬淇℃伅瀛樺偍 - - - - - - - riscv涓柇娓呴櫎bit锛屽啓1娓0 - - - - - - riscv涓柇娓呴櫎bit锛屽啓1娓0 - - - - - - riscv涓柇鐘舵佹寚绀篵it - - - - - - riscv涓柇鐘舵佹寚绀篵it - - - - - - riscv涓柇浣胯兘bit锛岄珮鏈夋晥 - - - - - - riscv涓柇浣胯兘bit锛岄珮鏈夋晥 - - - - - - riscv鍘熷涓柇鐘舵佹寚绀篵it - - - - - - riscv鍘熷涓柇鐘舵佹寚绀篵it - - - - - - riscv涓柇婧愬ご閫夋嫨bit锛岃瑙乺iscv涓柇鍒楄〃 - - - - - - BBPLL1 AFC棰戝亸璋冩暣瀵勫瓨鍣 - - - - - - BBPLL1 AFC棰戝亸璋冩暣瀵勫瓨鍣 - - - BBPLL2 AFC棰戝亸璋冩暣瀵勫瓨鍣 - - - - - - BBPLL2 AFC棰戝亸璋冩暣瀵勫瓨鍣 - - - - - - BBPLL1 AFC璋冩暣浣胯兘bit - - - BBPLL1 AFC璋冩暣浣胯兘bit - - - reserved锛屼笉浣跨敤 - - - reserved锛屼笉浣跨敤 - - - - - - BBPLL1鍒濆棰戝亸 - - - - - - BBPLL1鍒濆棰戝亸 - - - BBPLL2鍒濆棰戝亸 - - - - - - BBPLL2鍒濆棰戝亸 - - - - - - plls1 ldo output. TBD - - - plls1_cpbias_bit_bb - - - plls1_cpc_ibit_bb - - - plls1_cpr_ibit_bb - - - TBD - - - plls1 ldo enable - - - plls1 ldo fast charge enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - [8]:clk fbc inv -[9]:ref clk 52m -[10]:freq update - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RXPLL cal state, ECO - - - - - - - - - - - - - - - plls2 ldo output. TBD - - - plls2_cpbias_bit_bb - - - plls2_cpc_ibit_bb - - - plls2_cpr_ibit_bb - - - TBD - - - plls2 ldo enable - - - plls2 ldo fast charge enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - [8]:clk fbc inv -[9]:ref clk 52m -[10]:freq update - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熺郴鏁 - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熺郴鏁 - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熺郴鏁 - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熺郴鏁 - - - - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熷弽鍚 - - - 閫佺粰妯℃嫙鐨勫垎閰嶆椂閽熶娇鑳絙it - - - - - - - - - - - - - - - - - - sdm rstn - - - sdm input divN offset en - - - sdm dither for frac spur - - - sdm clk inv - - - 0 sel int, 1sel 1bit frac, 2sel 2bit frac. 3sel 3bit frac - - - - - - - - - - - - - - - - - - - - - - afc for vco wait time control - - - 0 for 8bit cband calibration, 3 for 11bit cband calibration - - - afccounter counttime control: -0--2^5/26M 1--2^6/26M -2--2^7/26M 3--2^8/26M - - - a-afc bypass - - - cal top rstn - - - aac bypass - - - vco pkd wait time control: -0--500ns 1--750ns 2--1us 3--1.25us - - - aac cal done vcobias adder control: -0--1 1--2 2--3 3--4 - - - aac cal init delay control,1~1us - - - - - - pll agc rstn - - - pll agc en - - - pll agc counttime control - - - - afc charging delay control, 0~0, 7~3.5us - - - vco calibration start signal - - - - - - - - - - - - - - - - - - - 0 sel a-afc cbank, 1 sel d-afc cbank - - - 0 for auto afc; 1 for manual - - - vco cbank spi - - - - - - 0 for auto aac; 1 for manual - - - vco bias spi - - - 0 for auto ; 1 for manual - - - pll loop open en - - - 0 for auto ; 1 for manual - - - afccounter enable control, high active - - - 0 for auto ; 1 for manual - - - afccounter rst control, high active - - - 0 for auto ; 1 for manual - - - vco peakdetector en - - - - - - a-afc start signal - - - aac start signal - - - aac state - - - cal top state - - - agc cal done signal - - - a-afc cal done signal - - - aac cal done signal - - - cal top cal done signal, same as afc cal done - - - - - - a-afc err min, for debug - - - - - - vco cbank - - - - - - pll loop en - - - afccount en - - - afccount rst - - - vco pkd en - - - vco bias - - - - - - afccount output fot a-afc & agc - - - - - - vco pkd output fot aac - - - - - - - - - - - - - - - - - - sdm rstn - - - sdm input divN offset en - - - sdm dither for frac spur - - - sdm clk inv - - - 0 sel int, 1sel 1bit frac, 2sel 2bit frac. 3sel 3bit frac - - - - - - - - - - - - - - - - - - - - - - afc for vco wait time control - - - 0 for 8bit cband calibration, 3 for 11bit cband calibration - - - afccounter counttime control: -0--2^5/26M 1--2^6/26M -2--2^7/26M 3--2^8/26M - - - a-afc bypass - - - cal top rstn - - - aac bypass - - - vco pkd wait time control: -0--500ns 1--750ns 2--1us 3--1.25us - - - aac cal done vcobias adder control: -0--1 1--2 2--3 3--4 - - - aac cal init delay control: - - - - - - pll agc rstn - - - pll agc en - - - pll agc counttime control - - - - afc charging delay control, 0~0, 7~3.5us - - - vco calibration start signal - - - - - - - - - - - - - - - - - - - 0 sel a-afc cbank, 1 sel d-afc cbank - - - 0 for auto afc; 1 for manual - - - vco cbank spi - - - - - - 0 for auto aac; 1 for manual - - - vco bias spi - - - 0 for auto ; 1 for manual - - - pll loop open en - - - 0 for auto ; 1 for manual - - - afccounter enable control, high active - - - 0 for auto ; 1 for manual - - - afccounter rst control, high active - - - 0 for auto ; 1 for manual - - - vco peakdetector en - - - - - - - - - - - - vco cbank - - - - - - pll loop en - - - afccount en - - - afccount rst - - - vco pkd en - - - vco bias - - - - - - afccount output fot a-afc & agc - - - - - - vco pkd output fot aac - - - - - - peak detector鍔熻兘纭欢妫娴嬪埌adc_en涓1鍚庤嚜鍔ㄦ墦寮锛屼笉闇瑕侀厤缃蒋浠朵娇鑳絙it - - - peak detector涓柇娓呴櫎 - - - peak detector杞欢浣胯兘bit - - - - - - peak detector涓柇鐘舵乥it - - - peak detector淇″彿鏃堕挓鍚屾鍚庣殑鐘舵 - - - peak detector淇″彿鍘熷杈撳叆鐘舵 - - - - - - peak detector涓柇寰幆妫娴嬪懆鏈 - - - peak detector涓柇寰幆妫娴嬪懆鏈 - - - - - - peak detector涓柇寰幆妫娴嬪懆鏈 - - - peak detector涓柇寰幆妫娴嬪懆鏈 - - - - - - peak detector涓柇妫娴嬭Е鍙戝懆鏈 - - - peak detector涓柇妫娴嬭Е鍙戝懆鏈 - - - - - - peak detector涓柇妫娴嬭Е鍙戝懆鏈 - - - peak detector涓柇妫娴嬭Е鍙戝懆鏈 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cmd_mipi_sr[15:0] - - - - - - cmd_mipi_sr[31:16],when write this reg,start the RFFE - - - - - - data_mipi_sr[15:0] - - - - - - data_mipi_sr[31:16] - - - - - - data_out_mipi[15:0] - - - - - - data_out_mipi[31:16] - - - - - - data_valid_byte[3:0] - - - - - - master_busy_mipi_dly - - - cmd_done_status - - - - - - - - - - - DLPF notch bypass status3 -1: notch bypass when the value of dlpf_det_status is less than 3 - - - DLPF sdm bypass - - - DLPF notch bypass status2 -1: notch bypass when the value of dlpf_det_status is less than 2 - - - gro mode tdc cal clk out inverse - - - gro mode phase err clk out inverse - - - gro mode tdc cal reg clk inverse - - - gro mode phase err reg clk inverse - - - DLPF MDLL mode -000: 26x2MHz -001: 26x3MHz -010: 26x4MHz -011: 26x5MHz -100: 26x6MHz -101: 26x7MHz -110: 26x8MHz -111: 26x9MHz - - - DLPF notch bypass - - - DLPF output clock inverse - - - DLPF input clock inverse - - - DLPF lock mode - - - enable DLPF - - - - - - DLPF output direct control - - - DLPF output direct value - - - - - - DLPF afc phase offset - - - - - - DLPF kdco phase offset - - - - - - DLPF gain kp afc - - - - - - DLPF gain ki afc - - - - - - DLPF gain kp 2m - - - - - - DLPF gain ki 2m - - - - - - DLPF gain kp 200k - - - - - - DLPF gain ki 200k - - - - - - DLPF IIR0 gain0[15:0] - - - - - - DLPF IIR0 gain1[15:0] - - - - - - DLPF IIR1 gain0[15:0] - - - - - - DLPF IIR1 gain1[15:0] - - - - - - DLPF IIR1 gain1[16] - - - DLPF IIR1 gain0[16] - - - DLPF IIR0 gain1[16] - - - DLPF IIR0 gain0[16] - - - - - - dlpf_diff_sel value is set to reserved value - - - - - - afc_diff_thr[15:0] - - - - - - afc_diff_thr[31:16] - - - - - - minimum value of afc_cnt_thr is 5 - - - - - - lock_2m_diff_thr[15:0] - - - - - - lock_2m_diff_thr[31:16] - - - - - - minimum value of lock_2m_cnt_thr is 5 - - - - - - lock_200k_diff_thr[15:0] - - - - - - lock_200k_diff_thr[31:16] - - - - - - minimum value of lock_200k_cnt_thr is 5 - - - - - - timer0_cnt[15:0] - - - - - - timer0_cnt[31:16] - - - - - - timer1_cnt[15:0] - - - - - - timer1_cnt[31:16] - - - - - - timer2_cnt[15:0] - - - - - - timer2_cnt[31:16] - - - - - - DLPF capture enable to dump internal values - - - - - - real time afc_code - - - DLPF detect status - - - - - - read time kdco_code - - - - - - captured afc_code - - - - - - captured kdco_code - - - - - - tdc_code - - - - - - dlpf_sum0[15:0] - - - - - - dlpf_sum0[31:16] - - - - - - dlpf_sum0[38:32] - - - - - - iir0_data[15:0] - - - - - - iir0_data[31:16] - - - - - - iir1_data[15:0] - - - - - - iir1_data[31:16] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1: pu_bbpll2 by reg -0: pu_bbpll2 by idle hw - - - 1:瀵勫瓨鍣ㄩ厤缃墦寮BBPLL2 - - - 1:瀵勫瓨鍣ㄩ厤缃墦寮BBPLL1 - - - - - - 1锛氭墦寮clk 26m aux1 - - - 1锛氭墦寮clk 26m tsx adc鏃堕挓 - - - 1锛氭墦寮clk 26m osc adc鏃堕挓 - - - - - - 1锛氬瘎瀛樺櫒閰嶇疆lte rx on锛屼负bitmap妯″潡鍐茬獊浣跨敤锛屽姛鑳藉悓TXRX纭欢閫佸嚭鐨刲te rx on - - - 1锛歭te鎶㈠崰gnss灏勯鎸囩ずbit锛岄佺粰gnss鍚庯紝gnss妯″潡鍐呴儴iq缃0 - - - 1锛歡nss涓柇灞忚斀bit - - - 1锛歡nss adc鏃堕挓閫夋嫨gnss pll 66/33m -0锛歡nss adc鏃堕挓閫夋嫨wifi pll 66/33m锛屽湪LTE绱фユ姠鍗爂nss灏勯鏃讹紝鎵撳紑bbpll1绋冲畾鍚庯紝鏃堕挓鍒囨崲鍒癰bpll1 - - - 1锛歡nss adc浣跨敤wifi pll 66/33m鏃堕挓鍓嶄娇鑳 - - - 1锛歡nss pp鏃堕挓閫夋嫨gnss pll 66/33m -0锛歡nss pp鏃堕挓閫夋嫨wifi pll 66/33m锛屽湪LTE绱фユ姠鍗爂nss灏勯鏃讹紝鎵撳紑bbpll1绋冲畾鍚庯紝鏃堕挓鍒囨崲鍒癰bpll1 - - - 1锛歡nss pp浣跨敤wifi pll 66/33m鏃堕挓鍓嶄娇鑳 - - - 1锛歝apture gnss ae/te鎸囬拡 - - - 1锛氶佺粰LTE鐨処Q婧愬ご缃0 - - - 1锛氶佺粰WIFI鐨処Q婧愬ご缃0 - - - 1锛氶佺粰GNSS鐨処Q婧愬ご缃0 - - - - - - 1:riscv ram鏃堕挓auto gate浣胯兘 - - - 1锛歛on璁块棶rf鐨刟hb async bridge slave绔椂閽焌uto gate浣胯兘 - - - 1锛歛on璁块棶rf鐨刟hb async bridge master绔椂閽焌uto gate浣胯兘 - - - 1锛歛on璁块棶rf鐨刟hb async bridge early response浣胯兘 - - - 1锛歳f璁块棶aon鐨刟hb async bridge slave绔椂閽焌uto gate浣胯兘 - - - 1锛歳f璁块棶aon鐨刟hb async bridge master绔椂閽焌uto gate浣胯兘 - - - 1锛歳f璁块棶aon鐨刟hb async bridge early response浣胯兘 - - - - - - 1锛歱ower detector adc鏃堕挓鍙嶅悜 - - - 1:adda test mode=5,rxdlpf mode, debug data sel dafc and tdc_code -0:adda test mode=5,rxdlpf mode, debug data sel kdco and tdc_code - - - 1:adda test mode=4,txdlpf mode, debug data sel dafc and tdc_code -0:adda test mode=4,txdlpf mode, debug data sel kdco and tdc_code - - - 1锛歰sc娓╁害璁dc鏃堕挓鍙嶅悜 - - - 1锛歵sx娓╁害璁dc鏃堕挓鍙嶅悜 - - - 1锛歳f analog 娴嬭瘯pad杈撳嚭浣胯兘 -0锛歳f analog 娴嬭瘯pad杈撳嚭high-z - - - 1锛歳iscv鎺ユ敹AHB response error灞忚斀 - - - dfe dump鏁版嵁鎴綅閫夋嫨锛 -000锛氬師濮媎fe dump鏁版嵁杈撳嚭 -001锛氫綆4浣嶄涪寮 -001锛氫綆3浣嶄涪寮 -010锛氫綆2浣嶄涪寮 -011锛氫綆1浣嶄涪寮 - - - 1锛歛dc杈撳叆鏃堕挓鍙嶆部 - - - 1锛氳緭鍑虹粰rf analog鐨剅tc鏃堕挓鍙嶆部 - - - 1锛氳緭鍑虹粰rf analog鐨刣ac鏃堕挓鍙嶆部 - - - 1锛氳緭鍑虹粰rf analog鐨刣ac鏃堕挓浣胯兘 - - - - - - 1锛歳xdlpf澶嶄綅 - - - 1锛歵xdlpf澶嶄綅 - - - 1锛歞fe osc temper澶嶄綅 - - - 1锛歞fe tsx temper澶嶄綅 - - - 1锛歞fe pwd澶嶄綅 - - - 1锛歞fe tx閫氶亾澶嶄綅 - - - 1锛歞fe rx閫氶亾澶嶄綅 - - - 1锛歞fe clkrst澶嶄綅 - - - - - - no use - - - 1锛歮ipi鏃堕挓閫夋嫨13m -0锛歮ipi鏃堕挓閫夋嫨26m - - - 1锛歶sid鏀瑰彉鏃跺鍙戜竴鏉rigger鍛戒护 - - - - - - 1锛氶佺粰rf analog鐨刼sc 26m鏃堕挓auto gate浣胯兘 - - - 1锛氶佺粰rf analog鐨則sx 26m鏃堕挓auto gate浣胯兘 - - - 1锛氶佺粰rf analog鐨刡bpll2 122.88m鏃堕挓auto gate浣胯兘 - - - 1锛氶佺粰rf analog鐨刡bpll2 245.76m鏃堕挓auto gate浣胯兘 - - - 1锛氶佺粰rf analog鐨刡bpll1 80m鏃堕挓auto gate浣胯兘 - - - 1锛歛on璁块棶rf閫氳矾鐨凙HB async bridge鏃堕挓auto gate浣胯兘 - - - 1锛歳f璁块棶aon閫氳矾鐨凙HB async bridge鏃堕挓auto gate浣胯兘 - - - 1锛歞fe婧愬ご245.76m鏃堕挓浣胯兘锛宎lways 1 - - - 1锛歳f dig浣跨敤鐨26m鏃堕挓浣胯兘锛宎lways 1 - - - 1锛歳f_dig鐨刟hb鏃堕挓浣胯兘锛宎lways 1 - - - 1锛歛hb鏃堕挓鑷姩鍒囨崲浣胯兘锛屽綋rg_cgm_chb_sel銆1锛0銆戦厤缃夋嫨鍒扮殑鏃堕挓瀵瑰簲PLL婧愬ご鏈墦寮锛宎hb鏃堕挓鑷姩鍒囨崲鍒26m - - - 00锛歞cxo 26m -01锛歸ifi bbpll 80m -10锛歭te bbpll 122.88m -11锛歡nss pll 133m - - - - - - 1锛欰TE妯″紡涓嬬殑tsen bist妯″潡鏃堕挓浣胯兘 - - - 1锛氶佸埌PAD鐨則sx鏃堕挓浣胯兘 - - - 1锛氶佺粰DFE鐨則sx鏃堕挓浣胯兘 - - - 1锛氶佸埌PAD鐨刼sc鏃堕挓浣胯兘 - - - 1锛歞fe osc鏃堕挓婧愬ご浣胯兘 - - - 1锛歞fe adc鏃堕挓婧愬ご浣胯兘 - - - 1锛歞fe pwd鏃堕挓婧愬ご浣胯兘 - - - 1锛歱eak detector鍔熻兘26m鏃堕挓浣胯兘 - - - 1锛歜bpll2 sdm妯″潡26m鏃堕挓浣胯兘 - - - 1锛歜bpll1 sdm妯″潡26m鏃堕挓浣胯兘 - - - 1锛歵xpll calibration妯″潡26m鏃堕挓浣胯兘 - - - 1锛歳xpll calibration妯″潡26m鏃堕挓浣胯兘 - - - 1锛歳f interface reg妯″潡26m鏃堕挓浣胯兘 - - - 1锛歳ffe鎺ュ彛鍜屽姛鑳芥椂閽熶娇鑳 - - - 1锛歳tc鎺ュ彛鏃堕挓浣胯兘 - - - - - - 1锛歳f bitmap妯″潡鏃堕挓浣胯兘 - - - 1锛歸dg妯″潡鏃堕挓浣胯兘 - - - 1锛歵imer妯″潡鏃堕挓浣胯兘 - - - 1锛歳iscv鏃堕挓浣胯兘 - - - 1锛歛on璁块棶rf AHB閫氳矾鏃堕挓浣胯兘 - - - 1锛歳f璁块棶aon AHB閫氳矾鏃堕挓浣胯兘 - - - 1锛歵xdlpf鎺ュ彛鏃堕挓浣胯兘 - - - 1锛歳xdlpf鎺ュ彛鏃堕挓浣胯兘 - - - 1锛歴pi2ahb妯″潡鎺ュ彛鏃堕挓浣胯兘 - - - 1锛歳iscv ram鎺ュ彛鏃堕挓浣胯兘 - - - 1锛歳f interface reg妯″潡ahb鎺ュ彛鏃堕挓浣胯兘 - - - 1锛歞fe妯″潡鎺ュ彛鏃堕挓浣胯兘 - - - 1锛氭荤嚎matrix鏃堕挓浣胯兘 - - - - - - 1锛歳xdlpf gro out2鏃堕挓婧愬ご浣胯兘 - - - 1锛歳xdlpf gro out1鏃堕挓婧愬ご浣胯兘 - - - 1锛歵xdlpf gro out2鏃堕挓婧愬ご浣胯兘 - - - 1锛歵xdlpf gro out1鏃堕挓婧愬ご浣胯兘 - - - 1锛歳xpll sdm鏃堕挓婧愬ご浣胯兘 - - - 1锛歵xpll sdm鏃堕挓婧愬ご浣胯兘 - - - 1锛歭te bbpll sdm鏃堕挓婧愬ご浣胯兘 - - - 1锛歸ifi bbpll sdm鏃堕挓婧愬ご浣胯兘 - - - - - - 1锛歰sc鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宔nable鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歵sx鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宔nable鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歛dc鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宔nable鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歜bpll2鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宭ock鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歜bpll2鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宭ock鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歜bpll1鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宭ock鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歡nss pll鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宭ock鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛歡nss pll鏃堕挓绋冲畾鏃堕棿绛夊緟鍔熻兘bypass -0锛氱‖浠跺垽鏂埌pu鍜宭ock鎷夐珮鍚庤嚜鍔ㄦ墦寮 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - 1锛氳蒋浠朵笉鍙備笌鏃堕挓绋冲畾鏃堕棿鍒ゆ柇锛岀敱纭欢鍐冲畾 - - - - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋wait auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - 1锛氱‖浠禷uto gating浣胯兘 - - - - - - 1锛氬綋auto gate sel=0鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=1鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=2鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=3鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=4鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=5鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=6鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=7鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=8鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=9鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=10鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=11鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=12鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - - - - 1锛氬綋auto gate sel=14鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=15鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=16鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=17鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=18鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=19鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=20鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=21鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=22鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=23鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=24鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=25鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=26鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=27鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - 1锛氬綋auto gate sel=28鏃讹紝杞欢寮哄埗鎵撳紑瀵瑰簲鏃堕挓 - - - - - - 1锛欰TE妯″紡浣跨敤鐨則sen bist妯″潡澶嶄綅 - - - 1锛歜itmap妯″潡澶嶄綅 - - - 1锛歳f璁块棶aon鐨凙HB async bridge澶嶄綅 - - - 1锛歛on璁块棶rf鐨凙HB async bridge澶嶄綅 - - - - - - 1锛歞fe瀵勫瓨鍣ㄦā鍧楀浣 - - - 1锛歳f interface妯″潡clk div澶嶄綅 - - - 1锛歳f interface妯″潡irq handler澶嶄綅 - - - 1锛歳f interface妯″潡peak det澶嶄綅 - - - 1锛歳f interface妯″潡瀵勫瓨鍣ㄥ浣 - - - 1锛歴pi2ahb妯″潡澶嶄綅 - - - 1锛歳iscv璁块棶rf dig rtc鎺ュ彛澶嶄綅 - - - 1锛歳f analog reg妯″潡澶嶄綅 - - - 1锛歳ffe妯″潡澶嶄綅 - - - 1锛歸dg妯″潡澶嶄綅 - - - 1锛歵imer0妯″潡澶嶄綅 - - - 1锛歳xdlpf妯″潡瀵勫瓨鍣ㄥ浣 - - - 1锛歵xdlpf妯″潡瀵勫瓨鍣ㄥ浣 - - - 1锛歳iscv ram妯″潡鎺ュ彛澶嶄綅 - - - 1锛歳iscv妯″潡debug鍔熻兘澶嶄綅 - - - 1锛歳iscv鏍稿浣 - - - - - - 1锛歳fdig gpio杈撳嚭鍊 - - - - - - 1锛歳fidg gpio杈撳叆浣胯兘 - - - - - - 1锛氬綋rg_simc_pa_en=0鏃讹紝PA澶у姛鐜囧彂灏勬椂simc auto gate鍔熻兘杞欢浣胯兘 - - - 1锛欰PC鍙戝皠鍔熺巼瓒呰繃rg_simc_pa_on_th闂ㄩ檺鏃讹紝浜х敓simc auto gate淇″彿閫佺粰simc - - - simc鍔熻兘PA鍙戝皠鍔熺巼闂ㄩ檺 - - - - - - 1锛歴ysctrl妯″潡瀵勫瓨鍣ㄨ蒋澶嶄綅 - - - - - - 1锛氶佺粰rf analog鐨刧ro rst淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛歳f analog閫佺粰dlpf鐨刣lpf rstn淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛氶佺粰rf analog鐨剉co pkdet鍔熻兘鐢盇AFC鏍″噯浜х敓鐨剉co pkdet纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛氶佺粰rf analog鐨刼pen_en淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛氶佺粰rf analog鐨刧ro rst淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛歳f analog閫佺粰dlpf鐨刣lpf rstn淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛氶佺粰rf analog鐨剉co pkdet鍔熻兘鐢盇AFC鏍″噯浜х敓鐨剉co pkdet纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - 1锛氶佺粰rf analog鐨刼pen_en淇″彿鐢盇AFC鏍″噯浜х敓鐨凮PEN_EN纭欢鍐冲畾锛岃蒋浠朵笉鍙備笌 - - - adda娴嬭瘯妯″紡閫夋嫨锛 -000锛歛dc娴嬭瘯妯″紡锛屾暟鎹笉缁忚繃dfe鐩存帴鍒皉am -001锛歛dc娴嬭瘯妯″紡锛屾暟鎹粡杩嘾fe鐩存帴鍒皉am -010锛歞fe dump鏁版嵁鍒皉am -011锛歞ac娴嬭瘯妯″紡 -100锛歵xdlpf娴嬭瘯妯″紡 -101锛歵xdlpf娴嬭瘯妯″紡 -110锛歳xdlpf娴嬭瘯妯″紡 -111锛歳xdlpf娴嬭瘯妯″紡 - - - 1锛氳繘鍏dda娴嬭瘯妯″紡 - - - 1锛歞ac娴嬭瘯妯″紡鏁版嵁浠巖am鑷姩鍙戝嚭涓嶇粡杩嘾fe -0锛歞ac娴嬭瘯妯″紡鏁版嵁浠巖am鍙戝嚭鍚庣粡杩嘾fe - - - 1锛歛dda娴嬭瘯璇诲啓鏁版嵁浣胯兘 - - - 1锛歛dda娴嬭瘯妯″紡澶嶄綅 - - - - - - rfdig gpio杈撳叆淇″彿 - - - - - - rfdig monitor淇″彿瀵勫瓨鍣ㄥ彲璇 - - - - - - wifi agc gain table0锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table1锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table2锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table3锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table4锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table5锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table6锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table7锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table8锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table9锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table10锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table11锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table12锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table13锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table14锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wifi agc gain table15锛岀‖浠舵牴鎹畐lan鍩哄甫杈撳嚭鐨刟uto gac index鑷姩閫夋嫨 - - - - - - wlan鍩哄甫杈撳嚭鐨刟uto gac index锛屽瘎瀛樺櫒鍙 - - - - - - 1锛歐IFI鎺ユ敹妯″紡锛岄佺粰rf analog鐨刟gc gain鐢盿uto gac index閫夋嫨wifi_gain0-15瀵勫瓨鍣紝閫佺粰rf analog鐨剋ifi gain pga/rxflt dccal i/q閫夋嫨瀵勫瓨鍣 -0锛歀TE鍜孏NSS妯″紡锛岄佺粰rf analog鐨刟gc gain銆乸ga/rxflt dccal i/q鐢辫蒋浠堕厤缃 - - - 00锛氶佺粰rf analog鐨刾ga I璺牎鍑嗕俊鍙烽夋嫨瀵勫瓨鍣 -01锛氶佺粰rf analog鐨刾ga I璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine琛ョ爜 -10锛氶佺粰rf analog鐨刾ga I璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine鍘熺爜 -11锛氶佺粰rf analog鐨刾ga I璺牎鍑嗕俊鍙烽夋嫨0 - - - 00锛氶佺粰rf analog鐨刾ga Q璺牎鍑嗕俊鍙烽夋嫨瀵勫瓨鍣 -01锛氶佺粰rf analog鐨刾ga Q璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine琛ョ爜 -10锛氶佺粰rf analog鐨刾ga Q璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine鍘熺爜 -11锛氶佺粰rf analog鐨刾ga Q璺牎鍑嗕俊鍙烽夋嫨0 - - - - - - 閫佺粰rf analog鐨刾ga I璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine琛ヤ笂鍥哄畾offset - - - 閫佺粰rf analog鐨刾ga Q璺牎鍑嗕俊鍙烽夋嫨dfe杈撳嚭鐨刣ac sine琛ヤ笂鍥哄畾offset - - - - - - - - - - - - - - - 缁忚繃ahb clk鑷姩鍒囨崲鍚庣殑ahb freq sel鍊硷紝鍙 - - - 纭寲鐨勪箻娉曞櫒杈撳嚭 - - - - - - 1锛歵xpll gro涓婄數閫夋嫨纭欢鏃跺簭 - - - 1锛歳xpll gro涓婄數閫夋嫨纭欢鏃跺簭 - - - txpll/rxpll gro涓婄數绋冲畾鏃堕棿 - - - - - - LTE2GNSS RX鏃讹細adc_enh_bb_force=0锛屽己鍒跺叧闂瑼DC浣胯兘锛屽嵆adc_enh_bb=0锛沘dc_enh_bb_force=1锛孉DC浣胯兘鎭㈠锛屽彈rg_adc_auto_ctrl_en鎴栬蒋浠跺瘎瀛樺櫒鎺у埗 - - - LTE2GNSS RX鏃讹細adc_clk_enh_bb_force=0锛屽己鍒跺叧闂瑼DC鏃堕挓浣胯兘锛屽嵆adc_clk_enh_bb=0锛沘dc_clk_enh_bb_force=1锛孉DC鏃堕挓浣胯兘鎭㈠锛屽彈rg_adc_auto_ctrl_en鎴栬蒋浠跺瘎瀛樺櫒鎺у埗 - - - 1锛歛dc寮鍏抽夋嫨纭欢鏃跺簭 - - - adc bias鎷夐珮绋冲畾鏃堕棿 - - - - - - adc clk enh鎷夐珮绋冲畾鏃堕棿 - - - - - - 1锛歱wdadc寮鍏抽夋嫨纭欢鏃跺簭 - - - pwdadc bias鎷夐珮绋冲畾鏃堕棿 - - - - - - pwdadc clk enh鎷夐珮绋冲畾鏃堕棿 - - - - - - wifi gain table0瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table0瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table1瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table1瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table2瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table2瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table3瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table3瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table4瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table4瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table5瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table5瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table6瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table6瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table7瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table7瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table8瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table8瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table9瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table9瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table10瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table10瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table11瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table11瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table12瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table12瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table13瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table13瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table14瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table14瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table15瀵瑰簲鐨凲璺痯ga dc鏍″噯琛ュ伩鍊 - - - wifi gain table15瀵瑰簲鐨処璺痯ga dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table0瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table0瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table1瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table1瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table2瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table2瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table3瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table3瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table4瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table4瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table5瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table5瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table6瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table6瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table7瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table7瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table8瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table8瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table9瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table9瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table10瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table10瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table11瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table11瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table12瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table12瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table13瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table13瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table14瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table14瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - wifi gain table15瀵瑰簲鐨凲璺痳xflt dc鏍″噯琛ュ伩鍊 - - - wifi gain table15瀵瑰簲鐨処璺痳xflt dc鏍″噯琛ュ伩鍊 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DLPF notch bypass status3 -1: notch bypass when the value of dlpf_det_status is less than 3 - - - DLPF sdm bypass - - - DLPF notch bypass status2 -1: notch bypass when the value of dlpf_det_status is less than 2 - - - gro mode tdc cal clk out inverse - - - gro mode phase err clk out inverse - - - gro mode tdc cal reg clk inverse - - - gro mode phase err reg clk inverse - - - DLPF MDLL mode -000: 26x2MHz -001: 26x3MHz -010: 26x4MHz -011: 26x5MHz -100: 26x6MHz -101: 26x7MHz -110: 26x8MHz -111: 26x9MHz - - - DLPF notch bypass - - - DLPF output clock inverse - - - DLPF input clock inverse - - - DLPF lock mode - - - enable DLPF - - - - - - DLPF output direct control - - - DLPF output direct value - - - - - - DLPF afc phase offset - - - - - - DLPF kdco phase offset - - - - - - DLPF gain kp afc - - - - - - DLPF gain ki afc - - - - - - DLPF gain kp 2m - - - - - - DLPF gain ki 2m - - - - - - DLPF gain kp 200k - - - - - - DLPF gain ki 200k - - - - - - DLPF IIR0 gain0[15:0] - - - - - - DLPF IIR0 gain1[15:0] - - - - - - DLPF IIR1 gain0[15:0] - - - - - - DLPF IIR1 gain1[15:0] - - - - - - DLPF IIR1 gain1[16] - - - DLPF IIR1 gain0[16] - - - DLPF IIR0 gain1[16] - - - DLPF IIR0 gain0[16] - - - - - - dlpf_diff_sel value is set to reserved value - - - - - - afc_diff_thr[15:0] - - - - - - afc_diff_thr[31:16] - - - - - - minimum value of afc_cnt_thr is 5 - - - - - - lock_2m_diff_thr[15:0] - - - - - - lock_2m_diff_thr[31:16] - - - - - - minimum value of lock_2m_cnt_thr is 5 - - - - - - lock_200k_diff_thr[15:0] - - - - - - lock_200k_diff_thr[31:16] - - - - - - minimum value of lock_200k_cnt_thr is 5 - - - - - - timer0_cnt[15:0] - - - - - - timer0_cnt[31:16] - - - - - - timer1_cnt[15:0] - - - - - - timer1_cnt[31:16] - - - - - - timer2_cnt[15:0] - - - - - - timer2_cnt[31:16] - - - - - - DLPF capture enable to dump internal values - - - - - - real time afc_code - - - DLPF detect status - - - - - - read time kdco_code - - - - - - captured afc_code - - - - - - captured kdco_code - - - - - - tdc_code - - - - - - dlpf_sum0[15:0] - - - - - - dlpf_sum0[31:16] - - - - - - dlpf_sum0[38:32] - - - - - - iir0_data[15:0] - - - - - - iir0_data[31:16] - - - - - - iir1_data[15:0] - - - - - - iir1_data[31:16] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_1 REG_RD_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_1 REG_WR_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_CTRL_ADDR_ARRAY8 BIT_CTRL_ADDR_ARRAY8 - - the addr[32:0] of bit control array8 - - - - BIT_CTRL_ADDR_ARRAY9 BIT_CTRL_ADDR_ARRAY9 - - the addr[32:0] of bit control array9 - - - - BIT_CTRL_ADDR_ARRAY10 BIT_CTRL_ADDR_ARRAY10 - - the addr[32:0] of bit control array10 - - - - BIT_CTRL_ADDR_ARRAY11 BIT_CTRL_ADDR_ARRAY11 - - the addr[32:0] of bit control array11 - - - - BIT_CTRL_ADDR_ARRAY12 BIT_CTRL_ADDR_ARRAY12 - - the addr[32:0] of bit control array12 - - - - BIT_CTRL_ADDR_ARRAY13 BIT_CTRL_ADDR_ARRAY13 - - the addr[32:0] of bit control array13 - - - - BIT_CTRL_ADDR_ARRAY14 BIT_CTRL_ADDR_ARRAY14 - - the addr[32:0] of bit control array14 - - - - BIT_CTRL_ADDR_ARRAY15 BIT_CTRL_ADDR_ARRAY15 - - the addr[32:0] of bit control array15 - - - - BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 - - - BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 - - - BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 - - - BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 - - - BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 - - - BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 - - - BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 - - - BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 - - - BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY8 - - - BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY9 - - - BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY10 - - - BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY11 - - - BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY12 - - - BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY13 - - - BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY14 - - - BIT_CTRL_ARRAY15 BIT_CTRL_ARRAY15 - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 - - - BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 - - - BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 - - - BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 - - - BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 - - - BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 - - - BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 - - - BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_1 REG_RD_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_1 REG_WR_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 - - - BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 - - - BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 - - - BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 - - - BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 - - - BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 - - - BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 - - - BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_1 REG_RD_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_2 REG_RD_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_1 REG_WR_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_2 REG_WR_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_WR_CTRL_ADDR_ARRAY0 BIT_WR_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_WR_CTRL_ADDR_ARRAY1 BIT_WR_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_WR_CTRL_ADDR_ARRAY2 BIT_WR_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_WR_CTRL_ADDR_ARRAY3 BIT_WR_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_WR_CTRL_ADDR_ARRAY4 BIT_WR_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_WR_CTRL_ADDR_ARRAY5 BIT_WR_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_WR_CTRL_ADDR_ARRAY6 BIT_WR_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_WR_CTRL_ADDR_ARRAY7 BIT_WR_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_WR_CTRL_ADDR_ARRAY8 BIT_WR_CTRL_ADDR_ARRAY8 - - the addr[32:0] of bit control array8 - - - - BIT_WR_CTRL_ADDR_ARRAY9 BIT_WR_CTRL_ADDR_ARRAY9 - - the addr[32:0] of bit control array9 - - - - BIT_WR_CTRL_ADDR_ARRAY10 BIT_WR_CTRL_ADDR_ARRAY10 - - the addr[32:0] of bit control array10 - - - - BIT_WR_CTRL_ADDR_ARRAY11 BIT_WR_CTRL_ADDR_ARRAY11 - - the addr[32:0] of bit control array11 - - - - BIT_WR_CTRL_ADDR_ARRAY12 BIT_WR_CTRL_ADDR_ARRAY12 - - the addr[32:0] of bit control array12 - - - - BIT_WR_CTRL_ADDR_ARRAY13 BIT_WR_CTRL_ADDR_ARRAY13 - - the addr[32:0] of bit control array13 - - - - BIT_WR_CTRL_ADDR_ARRAY14 BIT_WR_CTRL_ADDR_ARRAY14 - - the addr[32:0] of bit control array14 - - - - BIT_WR_CTRL_ADDR_ARRAY15 BIT_WR_CTRL_ADDR_ARRAY15 - - the addr[32:0] of bit control array15 - - - - BIT_WR_CTRL_ARRAY0 BIT_WR_CTRL_ARRAY0 - - - BIT_WR_CTRL_ARRAY1 BIT_WR_CTRL_ARRAY1 - - - BIT_WR_CTRL_ARRAY2 BIT_WR_CTRL_ARRAY2 - - - BIT_WR_CTRL_ARRAY3 BIT_WR_CTRL_ARRAY3 - - - BIT_WR_CTRL_ARRAY4 BIT_WR_CTRL_ARRAY4 - - - BIT_WR_CTRL_ARRAY5 BIT_WR_CTRL_ARRAY5 - - - BIT_WR_CTRL_ARRAY6 BIT_WR_CTRL_ARRAY6 - - - BIT_WR_CTRL_ARRAY7 BIT_WR_CTRL_ARRAY7 - - - BIT_WR_CTRL_ARRAY8 BIT_WR_CTRL_ARRAY8 - - - BIT_WR_CTRL_ARRAY9 BIT_WR_CTRL_ARRAY9 - - - BIT_WR_CTRL_ARRAY10 BIT_WR_CTRL_ARRAY10 - - - BIT_WR_CTRL_ARRAY11 BIT_WR_CTRL_ARRAY11 - - - BIT_WR_CTRL_ARRAY12 BIT_WR_CTRL_ARRAY12 - - - BIT_WR_CTRL_ARRAY13 BIT_WR_CTRL_ARRAY13 - - - BIT_WR_CTRL_ARRAY14 BIT_WR_CTRL_ARRAY14 - - - BIT_WR_CTRL_ARRAY15 BIT_WR_CTRL_ARRAY15 - - - - - - - - RESET_SYS_SOFT - - - - - - - - - - - RESET_LPS_SOFT - - - - - - - - - - - EFUSE_POR_READ_DISABLE - - reference "efuse_design_specification.docx" - - - - - LPS_CLK_EN - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - LPS_CLK_AUTO_SEL - - - LPS_CLK_FORCE_EN - - - LPS_CLK_GATE_EN_STATUS - - - LPS_CLK_BUSY_STATUS - - - CFG_CLK_UART1 - - - - - - CFG_CLK_RC26M - - - - - - CFG_DEBUG_BOND_OPTION - - - - - - - - - - - - - - - - - - - - - - CFG_PSRAM_HALF_SLP - - 0: PSRAM macro do not in half-sleep mode when PSRAM controller power-down -1: PSRAM macro in half-sleep mode when PSRAM controller power-down - - - - CFG_LPS_AHB_CLOCK_SEL - - 0:rtc_32k -1:xtal_lp_26m -2:xtal_26m -3:rc_26m - - - - CFG_UART1_CLOCK_SEL - - 0:rtc_32k -1:xtal_lp_2tm -2:xtal_26m -3:rc_26m - - - - CFG_GPT_LITE_CLOCK_SEL - - 0:rtc_32k -1:xtal_lp_2tm -2:xtal_26m -3:rc_26m - - - - CFG_BOOT_MODE - - - - This contains the state of boot mode pins latched during Reset. -bit 0: Force download. -bit 1: EMMC boot. -bit 2: Unused. - - - - CFG_RESET_ENABLE - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - RESET_CAUSE - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - - CFG_PLLS - - 0: select hardware auto control signal -1: select bbpll_pd_force as control signal - - - 0: power-up -1: power-down - - - select hardware control mode:(valid when iispll_clkout_en_sel bit is "0") -0: idle_lps output signal control -1: clock plan signal auto control - - - 0: select hardware auto control signal -1: select iispll_clkout_en_force as control signal - - - 0: disable -1: enable - - - 0: select hardware auto control signal -1: select iispll_pd_force as control signal - - - 0: power-up -1: power-down - - - 0: MPLL clock is not selected in PUB_SYS -1: MPLL clock is secected in PUB_SYS - - - select hardware control mode:(valid when mpll_clkout_en_sel bit is "0") -0: idle_lps output signal control -1: clock plan signal auto control - - - 0: select hardware auto control signal -1: select mpll_clkout_en_force as control signal - - - 0: disable -1: enable - - - 0: select hardware auto control signal -1: select mpll_pd_force as control signal - - - 0: power-up -1: power-down - - - 0: APLL clock is not selected in AP_SYS -1: APLL clock is secected in AP_SYS - - - 0: APLL clock is not selected in CP_SYS -1: APLL clock is secected in CP_SYS - - - 0: APLL clock is not selected in PUB_SYS -1: APLL clock is secected in PUB_SYS - - - 0: APLL clock is not selected in AON_SYS -1: APLL clock is secected in AON_SYS - - - select hardware control mode:(valid when apll_clkout_en_sel bit is "0") -0: idle_lps output signal control -1: clock plan signal auto control - - - 0: select hardware auto control signal -1: select apll_clkout_en_force as control signal - - - 0: disable -1: enable - - - 0: select hardware auto control signal -1: select apll_pd_force as control signal - - - 0: power-up -1: power-down - - - - APLL_WAIT_NUMBER - - From PLL_CLKOUT_EN posedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_PD negedge to PLL_RST negedge,use 26M clock count. - - - - MPLL_WAIT_NUMBER - - From PLL_CLKOUT_EN negedge to PLL_PRECHARGE negedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_PD negedge to PLL_RST negedge,use 26M clock count. - - - - IISMPLL_WAIT_NUMBER - - From PLL_CLKOUT_EN negedge to PLL_PRECHARGE negedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. - - - From PLL_PD negedge to PLL_RST negedge,use 26M clock count. - - - - AON_IRAM_CTRL - - AON_IRAM2 PU_DELAY port value - - - AON_IRAM1 PU_DELAY port value - - - AON_IRAM0 PU_DELAY port value - - - AON_IRAM2 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - AON_IRAM1 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - AON_IRAM0 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - AON_IRAM2 software control: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - AON_IRAM1 software control: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - AON_IRAM0 software control: -00: normal mode -01: retention mode -10: shut-down mode -11: normal mode - - - 1: AON_IRAM2 control by aon_iram2_ctrl_hw[1:0] -0: AON_IRAM2 control by aon_iram2_ctrl_sw - - - 1: AON_IRAM1 control by aon_iram1_ctrl_hw[1:0] -0: AON_IRAM1 control by aon_iram1_ctrl_sw - - - 1: AON_IRAM0 control by aon_iram0_ctrl_hw[1:0] -0: AON_IRAM0 control by aon_iram0_ctrl_sw - - - - IOMUX_G4_FUNC_SEL_LATCH - - This bit will be set to "1" by hardware to latch G4 pad function select when deepsleep, software should write "0" to release after iomux reinitial. - - - - CFG_POR_USB_PHY - - power on reset,reset all state machines, -1: the transmit and receive FSM are reset, -0: the transmit and receive FSM are operational - - - 1: ISO Cell Enable, signals will be gated and output iso value -0: ISO Cell Disable, normal mode - - - Digital in USBPHY Power gating control (large switch), when power up ,need delay 100us after PD_S set to 1'b0; -鈥1鈥: power gating the USB2.0 CORE -鈥0鈥: enable the CORE power - - - Digital in USBPHY Power gating control (small switch) -鈥1鈥: power gating the USB2.0 CORE power -鈥0鈥: enable the CORE power - - - - EFS_POR_READ_BLOCK3 - - - EFS_POR_READ_BLOCK89 - - - RC26M_PU_CTRL - - 鈥1鈥: power up -鈥0鈥: power down - - - 鈥1鈥: hw mode, RC26M PU controlled by "pd_xtal" hardware signal from IDLE_LPS module. -鈥0鈥: sw mode, RC26M PU controlled by "rc26m_pu_sw" register bit. - - - - AON_AHB_LP_CTRL - - 鈥0鈥: xtal_26m -鈥1鈥: rc26m - - - 鈥1鈥: Aon ahb clock auto switch to 26M (bit[5] decide witch clock switch to) when CP_SYS in lightsleep mode(with also bit4 is "1"), and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. -鈥0鈥: Disable. - - - 鈥1鈥: Aon ahb clock auto switch to 26M (bit[5] decide witch clock switch to) when AP_SYS in lightsleep mode(with also bit5 is "1"), and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. -鈥0鈥: Disable. - - - 鈥0鈥: xtal_26m -鈥1鈥: rc26m - - - 鈥1鈥: Aon ahb clock auto switch to RC32K when chip in deepsleep mode, and switch back when wake-up (bit[3] decide witch clock switch back to). Hardware control signal is "pd_pll" from IDLE_LPS module. -鈥0鈥: Disable. - - - 鈥1鈥: Aon ahb clock auto switch to 26M (bit[3] decide witch clock switch to) when chip in deepsleep mode, and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. Hardware control signal is "pow_on" from IDLE_LPS module. -鈥0鈥: Disable. - - - 鈥1鈥: Lps ahb clock auto switch to RC32K when chip in deepsleep mode, and switch back to the clock witch software set(see "CFG_LPS_AHB_CLOCK_SEL" register at address 0x51705030) when wake-up. Hardware control signal is "pd_pll" from IDLE_LPS module. -鈥0鈥: Disable. - - - - USB_UART_SWJ_SHARE_CFG - - 鈥1鈥: uart or swj in use -鈥0鈥: USB in use - - - 鈥1鈥: swj in use(with bit1 also set to "1"). -鈥0鈥: uart in use(with bit1 also set to "1"). - - - - PU_CLK26M_LP_ISO_CFG - - 鈥1鈥: ISO cell no work. -鈥0鈥: ISO work, signal clk_26m_lp clamp to "0". - - - - CFG_IO_DEEP_SLEEP - - 0 : software mode: dslp_io_sys1 and dslp_wp_sys1 signal controlled by bit[2] and bit[3] of this register. -1 : hardware mode: dslp_io_sys1 and dslp_wp_sys1 signal controlled by idst_cp signal of IDLE_LPS module. - - - 0 : software mode: dslp_io_sys0 and dslp_wp_sys0 signal controlled by bit[0] and bit[1] of this register. -1 : hardware mode: dslp_io_sys0 and dslp_wp_sys0 signal controlled by idst_ap signal of IDLE_LPS module. - - - pinmux dslp_wp_sys5 signal control. - - - pinmux dslp_io_sys5 signal control. - - - pinmux dslp_wp_sys4 signal control. - - - pinmux dslp_io_sys4 signal control. - - - pinmux dslp_wp_sys3 signal control. - - - pinmux dslp_io_sys3 signal control. - - - pinmux dslp_wp_sys2 signal control. - - - pinmux dslp_io_sys2 signal control. - - - pinmux dslp_wp_sys1 signal control. - - - pinmux dslp_io_sys1 signal control. - - - pinmux dslp_wp_sys0 signal control. - - - pinmux dslp_io_sys0 signal control. - - - - CFG_LPS_IO_CORE_IE - - - CFG_SIMC_IO - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - 0: sel hardware signal -1: sel software signal - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - software control signal, valid when related sel bit is "1" - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_1 REG_RD_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_2 REG_RD_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_3 REG_RD_CTRL_3 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_1 REG_WR_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_2 REG_WR_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_3 REG_WR_CTRL_3 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 - - - BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 - - - BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 - - - BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 - - - BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 - - - BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 - - - BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 - - - BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 - - - - - - - - REG_RD_CTRL_0 REG_RD_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_1 REG_RD_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_RD_CTRL_2 REG_RD_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_0 REG_WR_CTRL_0 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_1 REG_WR_CTRL_1 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - REG_WR_CTRL_2 REG_WR_CTRL_2 - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - control reg read security attribute: -0: Non security. -1: Security. - - - - BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 - - the addr[32:0] of bit control array0 - - - - BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 - - the addr[32:0] of bit control array1 - - - - BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 - - the addr[32:0] of bit control array2 - - - - BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 - - the addr[32:0] of bit control array3 - - - - BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 - - the addr[32:0] of bit control array4 - - - - BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 - - the addr[32:0] of bit control array5 - - - - BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 - - the addr[32:0] of bit control array6 - - - - BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 - - the addr[32:0] of bit control array7 - - - - BIT_CTRL_ADDR_ARRAY8 BIT_CTRL_ADDR_ARRAY8 - - the addr[32:0] of bit control array8 - - - - BIT_CTRL_ADDR_ARRAY9 BIT_CTRL_ADDR_ARRAY9 - - the addr[32:0] of bit control array9 - - - - BIT_CTRL_ADDR_ARRAY10 BIT_CTRL_ADDR_ARRAY10 - - the addr[32:0] of bit control array10 - - - - BIT_CTRL_ADDR_ARRAY11 BIT_CTRL_ADDR_ARRAY11 - - the addr[32:0] of bit control array11 - - - - BIT_CTRL_ADDR_ARRAY12 BIT_CTRL_ADDR_ARRAY12 - - the addr[32:0] of bit control array12 - - - - BIT_CTRL_ADDR_ARRAY13 BIT_CTRL_ADDR_ARRAY13 - - the addr[32:0] of bit control array13 - - - - BIT_CTRL_ADDR_ARRAY14 BIT_CTRL_ADDR_ARRAY14 - - the addr[32:0] of bit control array14 - - - - BIT_CTRL_ADDR_ARRAY15 BIT_CTRL_ADDR_ARRAY15 - - the addr[32:0] of bit control array15 - - - - BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 - - - BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 - - - BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 - - - BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 - - - BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 - - - BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 - - - BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 - - - BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 - - - BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY8 - - - BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY9 - - - BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY10 - - - BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY11 - - - BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY12 - - - BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY13 - - - BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY14 - - - BIT_CTRL_ARRAY15 BIT_CTRL_ARRAY15 - - - - - - - - port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read channel address miss int enable -1: Enable -0: Disable - - - Port 0 write channel address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read channel address miss int write-clear - - - Port 0 write channel address miss int write-clear - - - - Original interrupt reg %d Original interrupt reg %d - - Port 0 read channel address miss original int -1: Address Miss -0: Normal - - - Port 0 write channel address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg %d Final interrupt reg %d - - Port 0 read channel address miss final int -1: Address Miss -0: Normal - - - Port 0 write channel address miss final int -1: Address Miss -0: Normal - - - - rd 0 sec control rd 0 sec control - - control uart1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control idle_lps_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpio1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control apb_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control keypad_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pwrctrl_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control rtc_timer_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap3_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control lps_ifc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 0 sec control wr 0 sec control - - control uart1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control idle_lps_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpio1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control apb_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control keypad_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pwrctrl_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control rtc_timer_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap3_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control lps_ifc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - id0 first_addr control id0 first_addr control - - - - id0 last_addr control id0 last_addr control - - - - id0 mstid_0 master id control id0 mstid_0 master id control - - - id0 mstid_1 master id control id0 mstid_1 master id control - - - id0 mstid_2 master id control id0 mstid_2 master id control - - - id0 mstid_3 master id control id0 mstid_3 master id control - - - id0 mstid_4 master id control id0 mstid_4 master id control - - - id0 mstid_5 master id control id0 mstid_5 master id control - - - id0 mstid_6 master id control id0 mstid_6 master id control - - - id0 mstid_7 master id control id0 mstid_7 master id control - - - id1 first_addr control id1 first_addr control - - - - id1 last_addr control id1 last_addr control - - - - id1 mstid_0 master id control id1 mstid_0 master id control - - - id1 mstid_1 master id control id1 mstid_1 master id control - - - id1 mstid_2 master id control id1 mstid_2 master id control - - - id1 mstid_3 master id control id1 mstid_3 master id control - - - id1 mstid_4 master id control id1 mstid_4 master id control - - - id1 mstid_5 master id control id1 mstid_5 master id control - - - id1 mstid_6 master id control id1 mstid_6 master id control - - - id1 mstid_7 master id control id1 mstid_7 master id control - - - clk_gate_bypass clk_gate_bypass - - 0: don't response error; 1: response error. - - - clk_gate_bypass - - - - - - - - - port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read channel address miss int enable -1: Enable -0: Disable - - - Port 0 write channel address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read channel address miss int write-clear - - - Port 0 write channel address miss int write-clear - - - - Original interrupt reg %d Original interrupt reg %d - - Port 0 read channel address miss original int -1: Address Miss -0: Normal - - - Port 0 write channel address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg %d Final interrupt reg %d - - Port 0 read channel address miss final int -1: Address Miss -0: Normal - - - Port 0 write channel address miss final int -1: Address Miss -0: Normal - - - - rd 0 sec control rd 0 sec control - - control uart4_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart5_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart6_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sdmmc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control camera_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_ifc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 0 sec control wr 0 sec control - - control uart4_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart5_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart6_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sdmmc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control camera_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_ifc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - id0 first_addr control id0 first_addr control - - - - id0 last_addr control id0 last_addr control - - - - id0 mstid_0 master id control id0 mstid_0 master id control - - - id0 mstid_1 master id control id0 mstid_1 master id control - - - id0 mstid_2 master id control id0 mstid_2 master id control - - - id0 mstid_3 master id control id0 mstid_3 master id control - - - id0 mstid_4 master id control id0 mstid_4 master id control - - - id0 mstid_5 master id control id0 mstid_5 master id control - - - id0 mstid_6 master id control id0 mstid_6 master id control - - - id0 mstid_7 master id control id0 mstid_7 master id control - - - id1 first_addr control id1 first_addr control - - - - id1 last_addr control id1 last_addr control - - - - id1 mstid_0 master id control id1 mstid_0 master id control - - - id1 mstid_1 master id control id1 mstid_1 master id control - - - id1 mstid_2 master id control id1 mstid_2 master id control - - - id1 mstid_3 master id control id1 mstid_3 master id control - - - id1 mstid_4 master id control id1 mstid_4 master id control - - - id1 mstid_5 master id control id1 mstid_5 master id control - - - id1 mstid_6 master id control id1 mstid_6 master id control - - - id1 mstid_7 master id control id1 mstid_7 master id control - - - id2 first_addr control id2 first_addr control - - - - id2 last_addr control id2 last_addr control - - - - id2 mstid_0 master id control id2 mstid_0 master id control - - - id2 mstid_1 master id control id2 mstid_1 master id control - - - id2 mstid_2 master id control id2 mstid_2 master id control - - - id2 mstid_3 master id control id2 mstid_3 master id control - - - id2 mstid_4 master id control id2 mstid_4 master id control - - - id2 mstid_5 master id control id2 mstid_5 master id control - - - id2 mstid_6 master id control id2 mstid_6 master id control - - - id2 mstid_7 master id control id2 mstid_7 master id control - - - id3 first_addr control id3 first_addr control - - - - id3 last_addr control id3 last_addr control - - - - id3 mstid_0 master id control id3 mstid_0 master id control - - - id3 mstid_1 master id control id3 mstid_1 master id control - - - id3 mstid_2 master id control id3 mstid_2 master id control - - - id3 mstid_3 master id control id3 mstid_3 master id control - - - id3 mstid_4 master id control id3 mstid_4 master id control - - - id3 mstid_5 master id control id3 mstid_5 master id control - - - id3 mstid_6 master id control id3 mstid_6 master id control - - - id3 mstid_7 master id control id3 mstid_7 master id control - - - id4 first_addr control id4 first_addr control - - - - id4 last_addr control id4 last_addr control - - - - id4 mstid_0 master id control id4 mstid_0 master id control - - - id4 mstid_1 master id control id4 mstid_1 master id control - - - id4 mstid_2 master id control id4 mstid_2 master id control - - - id4 mstid_3 master id control id4 mstid_3 master id control - - - id4 mstid_4 master id control id4 mstid_4 master id control - - - id4 mstid_5 master id control id4 mstid_5 master id control - - - id4 mstid_6 master id control id4 mstid_6 master id control - - - id4 mstid_7 master id control id4 mstid_7 master id control - - - id5 first_addr control id5 first_addr control - - - - id5 last_addr control id5 last_addr control - - - - id5 mstid_0 master id control id5 mstid_0 master id control - - - id5 mstid_1 master id control id5 mstid_1 master id control - - - id5 mstid_2 master id control id5 mstid_2 master id control - - - id5 mstid_3 master id control id5 mstid_3 master id control - - - id5 mstid_4 master id control id5 mstid_4 master id control - - - id5 mstid_5 master id control id5 mstid_5 master id control - - - id5 mstid_6 master id control id5 mstid_6 master id control - - - id5 mstid_7 master id control id5 mstid_7 master id control - - - clk_gate_bypass clk_gate_bypass - - 0: don't response error; 1: response error. - - - clk_gate_bypass - - - - - - - - - port0 default address, bit 0 ~ 26. port0 default address, bit 0 ~ 26. - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read channel address miss int enable -1: Enable -0: Disable - - - Port 0 write channel address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read channel address miss int write-clear - - - Port 0 write channel address miss int write-clear - - - - Original interrupt reg %d Original interrupt reg %d - - Port 0 read channel address miss original int -1: Address Miss -0: Normal - - - Port 0 write channel address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg %d Final interrupt reg %d - - Port 0 read channel address miss final int -1: Address Miss -0: Normal - - - Port 0 write channel address miss final int -1: Address Miss -0: Normal - - - - rd 0 sec control rd 0 sec control - - control emmc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spi1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control lzma_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_imem_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_busmon_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control apb_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gouda_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_0_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_wd_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer5_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt3_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_clk_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - rd 1 sec control rd 1 sec control - - control spiflash1_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spiflash2_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gouda_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_axidma_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control usb_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control med_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ce_pub_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ce_sec_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 0 sec control wr 0 sec control - - control emmc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spi1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control lzma_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_imem_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_busmon_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control apb_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gouda_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_0_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_wd_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer1_1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control timer5_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt3_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_clk_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 1 sec control wr 1 sec control - - control spiflash1_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spiflash2_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gouda_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ap_axidma_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control usb_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control med_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ce_pub_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ce_sec_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - id0 first_addr control id0 first_addr control - - - - id0 last_addr control id0 last_addr control - - - - id0 mstid_0 master id control id0 mstid_0 master id control - - - id0 mstid_1 master id control id0 mstid_1 master id control - - - id0 mstid_2 master id control id0 mstid_2 master id control - - - id0 mstid_3 master id control id0 mstid_3 master id control - - - id0 mstid_4 master id control id0 mstid_4 master id control - - - id0 mstid_5 master id control id0 mstid_5 master id control - - - id0 mstid_6 master id control id0 mstid_6 master id control - - - id0 mstid_7 master id control id0 mstid_7 master id control - - - id1 first_addr control id1 first_addr control - - - - id1 last_addr control id1 last_addr control - - - - id1 mstid_0 master id control id1 mstid_0 master id control - - - id1 mstid_1 master id control id1 mstid_1 master id control - - - id1 mstid_2 master id control id1 mstid_2 master id control - - - id1 mstid_3 master id control id1 mstid_3 master id control - - - id1 mstid_4 master id control id1 mstid_4 master id control - - - id1 mstid_5 master id control id1 mstid_5 master id control - - - id1 mstid_6 master id control id1 mstid_6 master id control - - - id1 mstid_7 master id control id1 mstid_7 master id control - - - id2 first_addr control id2 first_addr control - - - - id2 last_addr control id2 last_addr control - - - - id2 mstid_0 master id control id2 mstid_0 master id control - - - id2 mstid_1 master id control id2 mstid_1 master id control - - - id2 mstid_2 master id control id2 mstid_2 master id control - - - id2 mstid_3 master id control id2 mstid_3 master id control - - - id2 mstid_4 master id control id2 mstid_4 master id control - - - id2 mstid_5 master id control id2 mstid_5 master id control - - - id2 mstid_6 master id control id2 mstid_6 master id control - - - id2 mstid_7 master id control id2 mstid_7 master id control - - - id3 first_addr control id3 first_addr control - - - - id3 last_addr control id3 last_addr control - - - - id3 mstid_0 master id control id3 mstid_0 master id control - - - id3 mstid_1 master id control id3 mstid_1 master id control - - - id3 mstid_2 master id control id3 mstid_2 master id control - - - id3 mstid_3 master id control id3 mstid_3 master id control - - - id3 mstid_4 master id control id3 mstid_4 master id control - - - id3 mstid_5 master id control id3 mstid_5 master id control - - - id3 mstid_6 master id control id3 mstid_6 master id control - - - id3 mstid_7 master id control id3 mstid_7 master id control - - - id4 first_addr control id4 first_addr control - - - - id4 last_addr control id4 last_addr control - - - - id4 mstid_0 master id control id4 mstid_0 master id control - - - id4 mstid_1 master id control id4 mstid_1 master id control - - - id4 mstid_2 master id control id4 mstid_2 master id control - - - id4 mstid_3 master id control id4 mstid_3 master id control - - - id4 mstid_4 master id control id4 mstid_4 master id control - - - id4 mstid_5 master id control id4 mstid_5 master id control - - - id4 mstid_6 master id control id4 mstid_6 master id control - - - id4 mstid_7 master id control id4 mstid_7 master id control - - - id5 first_addr control id5 first_addr control - - - - id5 last_addr control id5 last_addr control - - - - id5 mstid_0 master id control id5 mstid_0 master id control - - - id5 mstid_1 master id control id5 mstid_1 master id control - - - id5 mstid_2 master id control id5 mstid_2 master id control - - - id5 mstid_3 master id control id5 mstid_3 master id control - - - id5 mstid_4 master id control id5 mstid_4 master id control - - - id5 mstid_5 master id control id5 mstid_5 master id control - - - id5 mstid_6 master id control id5 mstid_6 master id control - - - id5 mstid_7 master id control id5 mstid_7 master id control - - - clk_gate_bypass clk_gate_bypass - - 0: don't response error; 1: response error. - - - clk_gate_bypass - - - - - - - - - port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read channel address miss int enable -1: Enable -0: Disable - - - Port 0 write channel address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read channel address miss int write-clear - - - Port 0 write channel address miss int write-clear - - - - Original interrupt reg %d Original interrupt reg %d - - Port 0 read channel address miss original int -1: Address Miss -0: Normal - - - Port 0 write channel address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg %d Final interrupt reg %d - - Port 0 read channel address miss final int -1: Address Miss -0: Normal - - - Port 0 write channel address miss final int -1: Address Miss -0: Normal - - - - rd 0 sec control rd 0 sec control - - control uart2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart3_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dbg_uart_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aif_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_ifc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dbg_host_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 0 sec control wr 0 sec control - - control uart2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control uart3_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dbg_uart_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aif_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_ifc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dbg_host_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - id0 first_addr control id0 first_addr control - - - - id0 last_addr control id0 last_addr control - - - - id0 mstid_0 master id control id0 mstid_0 master id control - - - id0 mstid_1 master id control id0 mstid_1 master id control - - - id0 mstid_2 master id control id0 mstid_2 master id control - - - id0 mstid_3 master id control id0 mstid_3 master id control - - - id0 mstid_4 master id control id0 mstid_4 master id control - - - id0 mstid_5 master id control id0 mstid_5 master id control - - - id0 mstid_6 master id control id0 mstid_6 master id control - - - id0 mstid_7 master id control id0 mstid_7 master id control - - - id1 first_addr control id1 first_addr control - - - - id1 last_addr control id1 last_addr control - - - - id1 mstid_0 master id control id1 mstid_0 master id control - - - id1 mstid_1 master id control id1 mstid_1 master id control - - - id1 mstid_2 master id control id1 mstid_2 master id control - - - id1 mstid_3 master id control id1 mstid_3 master id control - - - id1 mstid_4 master id control id1 mstid_4 master id control - - - id1 mstid_5 master id control id1 mstid_5 master id control - - - id1 mstid_6 master id control id1 mstid_6 master id control - - - id1 mstid_7 master id control id1 mstid_7 master id control - - - clk_gate_bypass clk_gate_bypass - - 0: don't response error; 1: response error. - - - clk_gate_bypass - - - - - - - - - port0 default address, bit 0 ~ 26. port0 default address, bit 0 ~ 26. - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read channel address miss int enable -1: Enable -0: Disable - - - Port 0 write channel address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read channel address miss int write-clear - - - Port 0 write channel address miss int write-clear - - - - Original interrupt reg %d Original interrupt reg %d - - Port 0 read channel address miss original int -1: Address Miss -0: Normal - - - Port 0 write channel address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg %d Final interrupt reg %d - - Port 0 read channel address miss final int -1: Address Miss -0: Normal - - - Port 0 write channel address miss final int -1: Address Miss -0: Normal - - - - rd 0 sec control rd 0 sec control - - control idle_timer_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_clk_pre_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_clk_core_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aud_2ad_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spi2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control djtag_cfg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control iomux_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dmc400_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control psram_phy_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pagespy_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pub_apb_reg_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dap_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pub_nic_gpv_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - rd 1 sec control rd 1 sec control - - control spinlock_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_sp0_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_sp1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control efuse_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control tzpc_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sys_ctrl_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap1_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control mon_ctrl_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpio2_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c3_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control scc_top_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sysmail_rd_sec rd security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 0 sec control wr 0 sec control - - control idle_timer_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_clk_pre_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aon_clk_core_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control aud_2ad_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control spi2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpt1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control djtag_cfg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control iomux_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dmc400_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control psram_phy_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pagespy_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pub_apb_reg_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control dap_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control pub_nic_gpv_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - wr 1 sec control wr 1 sec control - - control spinlock_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_sp0_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control adi_mst_sp1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control efuse_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control tzpc_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sys_ctrl_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control ana_wrap1_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control mon_ctrl_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control gpio2_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control i2c3_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control scc_top_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - control sysmail_wr_sec wr security attribute: -2'b00: security/non-security can't access -2'b01: security access only -2'b10: non-security access ony -2'b11: security/non-security access - - - - id0 first_addr control id0 first_addr control - - - - id0 last_addr control id0 last_addr control - - - - id0 mstid_0 master id control id0 mstid_0 master id control - - - id0 mstid_1 master id control id0 mstid_1 master id control - - - id0 mstid_2 master id control id0 mstid_2 master id control - - - id0 mstid_3 master id control id0 mstid_3 master id control - - - id0 mstid_4 master id control id0 mstid_4 master id control - - - id0 mstid_5 master id control id0 mstid_5 master id control - - - id0 mstid_6 master id control id0 mstid_6 master id control - - - id0 mstid_7 master id control id0 mstid_7 master id control - - - id1 first_addr control id1 first_addr control - - - - id1 last_addr control id1 last_addr control - - - - id1 mstid_0 master id control id1 mstid_0 master id control - - - id1 mstid_1 master id control id1 mstid_1 master id control - - - id1 mstid_2 master id control id1 mstid_2 master id control - - - id1 mstid_3 master id control id1 mstid_3 master id control - - - id1 mstid_4 master id control id1 mstid_4 master id control - - - id1 mstid_5 master id control id1 mstid_5 master id control - - - id1 mstid_6 master id control id1 mstid_6 master id control - - - id1 mstid_7 master id control id1 mstid_7 master id control - - - id2 first_addr control id2 first_addr control - - - - id2 last_addr control id2 last_addr control - - - - id2 mstid_0 master id control id2 mstid_0 master id control - - - id2 mstid_1 master id control id2 mstid_1 master id control - - - id2 mstid_2 master id control id2 mstid_2 master id control - - - id2 mstid_3 master id control id2 mstid_3 master id control - - - id2 mstid_4 master id control id2 mstid_4 master id control - - - id2 mstid_5 master id control id2 mstid_5 master id control - - - id2 mstid_6 master id control id2 mstid_6 master id control - - - id2 mstid_7 master id control id2 mstid_7 master id control - - - id3 first_addr control id3 first_addr control - - - - id3 last_addr control id3 last_addr control - - - - id3 mstid_0 master id control id3 mstid_0 master id control - - - id3 mstid_1 master id control id3 mstid_1 master id control - - - id3 mstid_2 master id control id3 mstid_2 master id control - - - id3 mstid_3 master id control id3 mstid_3 master id control - - - id3 mstid_4 master id control id3 mstid_4 master id control - - - id3 mstid_5 master id control id3 mstid_5 master id control - - - id3 mstid_6 master id control id3 mstid_6 master id control - - - id3 mstid_7 master id control id3 mstid_7 master id control - - - id4 first_addr control id4 first_addr control - - - - id4 last_addr control id4 last_addr control - - - - id4 mstid_0 master id control id4 mstid_0 master id control - - - id4 mstid_1 master id control id4 mstid_1 master id control - - - id4 mstid_2 master id control id4 mstid_2 master id control - - - id4 mstid_3 master id control id4 mstid_3 master id control - - - id4 mstid_4 master id control id4 mstid_4 master id control - - - id4 mstid_5 master id control id4 mstid_5 master id control - - - id4 mstid_6 master id control id4 mstid_6 master id control - - - id4 mstid_7 master id control id4 mstid_7 master id control - - - id5 first_addr control id5 first_addr control - - - - id5 last_addr control id5 last_addr control - - - - id5 mstid_0 master id control id5 mstid_0 master id control - - - id5 mstid_1 master id control id5 mstid_1 master id control - - - id5 mstid_2 master id control id5 mstid_2 master id control - - - id5 mstid_3 master id control id5 mstid_3 master id control - - - id5 mstid_4 master id control id5 mstid_4 master id control - - - id5 mstid_5 master id control id5 mstid_5 master id control - - - id5 mstid_6 master id control id5 mstid_6 master id control - - - id5 mstid_7 master id control id5 mstid_7 master id control - - - clk_gate_bypass clk_gate_bypass - - 0: don't response error; 1: response error. - - - clk_gate_bypass - - - - - - - - - mst_filter_id0 mst_filter_id0 - - - mst_filter_id1 mst_filter_id1 - - - mst_filter_id2 mst_filter_id2 - - - mst_filter_id3 mst_filter_id3 - - - mst_filter_id4 mst_filter_id4 - - - mst_filter_id5 mst_filter_id5 - - - mst_filter_id6 mst_filter_id6 - - - mst_filter_id7 mst_filter_id7 - - - Interrupt enable reg Interrupt enable reg - - read/write channel address miss int enable -1: Enable -0: Disable - - - - Original interrupt reg Original interrupt reg - - read/write channel address miss original int -1: Address Miss -0: Normal - - - - Interrupt status reg Interrupt status reg - - read/write channel address miss final int -1: Address Miss -0: Normal - - - - Interrupt write-clear reg Interrupt write-clear reg - - read/write channel address miss int write-clear - - - - debug register debug register - - - debug register debug register - - - when miss, latch hauser - - - - response error reg responce error reg - - read/write channel address miss int write-clear - - - - - - - - - mst_filter_id0 mst_filter_id0 - - - mst_filter_id1 mst_filter_id1 - - - mst_filter_id2 mst_filter_id2 - - - mst_filter_id3 mst_filter_id3 - - - mst_filter_id4 mst_filter_id4 - - - mst_filter_id5 mst_filter_id5 - - - mst_filter_id6 mst_filter_id6 - - - mst_filter_id7 mst_filter_id7 - - - Interrupt enable reg Interrupt enable reg - - read/write channel address miss int enable -1: Enable -0: Disable - - - - Original interrupt reg Original interrupt reg - - read/write channel address miss original int -1: Address Miss -0: Normal - - - - Interrupt status reg Interrupt status reg - - read/write channel address miss final int -1: Address Miss -0: Normal - - - - Interrupt write-clear reg Interrupt write-clear reg - - read/write channel address miss int write-clear - - - - debug register debug register - - - debug register debug register - - - when miss, latch hauser - - - - response error reg responce error reg - - read/write channel address miss int write-clear - - - - - - - - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - - clock gate bypass clock gate bypass - - 0: don't response error; 1: response error. - - - clock gate bypass - - - - - Interrupt enable reg Interrupt enable reg - - Port 0 write address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 write address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 write address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 write address miss final int -1: Address Miss -0: Normal - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 read address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 read address miss final int -1: Address Miss -0: Normal - - - - - Debug address register for port 0 write channel Debug address register for port 0 write channel - - Port 0 write channel address, 1K-Byte - - - - Debug id register for port 0 write channel Debug id register for port 0 write channel - - Port 0 write channel id, MSB is prot[1] - - - - Debug address register for port 0 read channel Debug address register for port 0 read channel - - Port 0 read channel address, 1K-Byte - - - - Debug id register for port 0 read channel Debug id register for port 0 read channel - - Port 0 read channel id, MSB is prot[1] - - - - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - - - Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 - - - Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 - - - Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 - - - Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 - - - Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 - - - Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 - - - Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 - - - Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 - - - Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 - - - Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 - - - Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 - - - Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 - - - Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 - - - Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 - - - Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 - - - Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 - - - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 - - - Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 - - - Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 - - - Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 - - - Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 - - - Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 - - - Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 - - - Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 - - - Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 - - - Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 - - - Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 - - - Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 - - - Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 - - - Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 - - - Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 - - - Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 - - - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 - - - Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 - - - Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 - - - Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 - - - Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 - - - Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 - - - Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 - - - Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 - - - Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 - - - Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 - - - Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 - - - Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 - - - Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 - - - Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 - - - Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 - - - Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 - - - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 - - - Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 - - - Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 - - - Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 - - - Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 - - - Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 - - - Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 - - - Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 - - - Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 - - - Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 - - - Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 - - - Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 - - - Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 - - - Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 - - - Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 - - - Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 - - - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 - - - Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 - - - Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 - - - Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 - - - Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 - - - Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 - - - Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 - - - Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 - - - Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 - - - Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 - - - Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 - - - Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 - - - Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 - - - Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 - - - Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 - - - Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 - - - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 - - - Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 - - - Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 - - - Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 - - - Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 - - - Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 - - - Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 - - - Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 - - - Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 - - - Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 - - - Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 - - - Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 - - - Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 - - - Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 - - - Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 - - - Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 - - - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 - - - Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 - - - Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 - - - Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 - - - Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 - - - Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 - - - Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 - - - Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 - - - Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 - - - Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 - - - Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 - - - Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 - - - Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 - - - Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 - - - Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 - - - Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 - - - - - - - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - - clock gate bypass clock gate bypass - - 0: don't response error; 1: response error. - - - clock gate bypass - - - - - Interrupt enable reg Interrupt enable reg - - Port 0 write address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 write address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 write address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 write address miss final int -1: Address Miss -0: Normal - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 read address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 read address miss final int -1: Address Miss -0: Normal - - - - - Debug address register for port 0 write channel Debug address register for port 0 write channel - - Port 0 write channel address, 1K-Byte - - - - Debug id register for port 0 write channel Debug id register for port 0 write channel - - Port 0 write channel id, MSB is prot[1] - - - - Debug address register for port 0 read channel Debug address register for port 0 read channel - - Port 0 read channel address, 1K-Byte - - - - Debug id register for port 0 read channel Debug id register for port 0 read channel - - Port 0 read channel id, MSB is prot[1] - - - - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - - - Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 - - - Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 - - - Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 - - - Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 - - - Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 - - - Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 - - - Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 - - - Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 - - - Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 - - - Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 - - - Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 - - - Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 - - - Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 - - - Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 - - - Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 - - - Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 - - - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 - - - Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 - - - Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 - - - Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 - - - Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 - - - Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 - - - Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 - - - Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 - - - Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 - - - Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 - - - Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 - - - Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 - - - Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 - - - Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 - - - Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 - - - Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 - - - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 - - - Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 - - - Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 - - - Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 - - - Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 - - - Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 - - - Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 - - - Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 - - - Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 - - - Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 - - - Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 - - - Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 - - - Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 - - - Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 - - - Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 - - - Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 - - - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 - - - Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 - - - Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 - - - Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 - - - Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 - - - Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 - - - Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 - - - Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 - - - Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 - - - Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 - - - Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 - - - Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 - - - Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 - - - Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 - - - Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 - - - Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 - - - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 - - - Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 - - - Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 - - - Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 - - - Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 - - - Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 - - - Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 - - - Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 - - - Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 - - - Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 - - - Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 - - - Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 - - - Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 - - - Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 - - - Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 - - - Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 - - - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 - - - Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 - - - Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 - - - Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 - - - Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 - - - Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 - - - Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 - - - Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 - - - Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 - - - Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 - - - Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 - - - Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 - - - Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 - - - Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 - - - Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 - - - Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 - - - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 - - - Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 - - - Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 - - - Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 - - - Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 - - - Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 - - - Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 - - - Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 - - - Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 - - - Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 - - - Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 - - - Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 - - - Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 - - - Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 - - - Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 - - - Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 - - - - - - - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default r address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - default w address 0 register(1K-Byte address, bit 26 ~ bit 10). - - - - - clock gate bypass clock gate bypass - - 0: don't response error; 1: response error. - - - clock gate bypass - - - - - Interrupt enable reg Interrupt enable reg - - Port 0 write address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 write address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 write address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 write address miss final int -1: Address Miss -0: Normal - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 read address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 read address miss final int -1: Address Miss -0: Normal - - - - - Debug address register for port 0 write channel Debug address register for port 0 write channel - - Port 0 write channel address, 1K-Byte - - - - Debug id register for port 0 write channel Debug id register for port 0 write channel - - Port 0 write channel id, MSB is prot[1] - - - - Debug address register for port 0 read channel Debug address register for port 0 read channel - - Port 0 read channel address, 1K-Byte - - - - Debug id register for port 0 read channel Debug id register for port 0 read channel - - Port 0 read channel id, MSB is prot[1] - - - - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - - - Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 - - - Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 - - - Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 - - - Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 - - - Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 - - - Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 - - - Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 - - - Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 - - - Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 - - - Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 - - - Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 - - - Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 - - - Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 - - - Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 - - - Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 - - - Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 - - - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 - - - Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 - - - Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 - - - Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 - - - Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 - - - Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 - - - Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 - - - Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 - - - Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 - - - Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 - - - Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 - - - Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 - - - Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 - - - Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 - - - Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 - - - Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 - - - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 - - - Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 - - - Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 - - - Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 - - - Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 - - - Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 - - - Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 - - - Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 - - - Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 - - - Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 - - - Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 - - - Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 - - - Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 - - - Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 - - - Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 - - - Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 - - - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 - - - Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 - - - Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 - - - Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 - - - Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 - - - Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 - - - Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 - - - Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 - - - Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 - - - Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 - - - Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 - - - Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 - - - Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 - - - Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 - - - Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 - - - Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 - - - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 - - - Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 - - - Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 - - - Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 - - - Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 - - - Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 - - - Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 - - - Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 - - - Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 - - - Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 - - - Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 - - - Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 - - - Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 - - - Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 - - - Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 - - - Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 - - - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 - - - Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 - - - Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 - - - Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 - - - Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 - - - Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 - - - Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 - - - Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 - - - Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 - - - Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 - - - Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 - - - Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 - - - Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 - - - Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 - - - Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 - - - Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 - - - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 - - - Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 - - - Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 - - - Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 - - - Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 - - - Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 - - - Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 - - - Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 - - - Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 - - - Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 - - - Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 - - - Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 - - - Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 - - - Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 - - - Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 - - - Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 - - - - Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 6 Read Master ID select 0~31 Segment 6 Read Master ID select 0~31 - - - Segment 6 Read Master ID select 32~63 Segment 6 Read Master ID select 32~63 - - - Segment 6 Read Master ID select 64~95 Segment 6 Read Master ID select 64~95 - - - Segment 6 Read Master ID select 96~127 Segment 6 Read Master ID select 96~127 - - - Segment 6 Read Master ID select 128~159 Segment 6 Read Master ID select 128~159 - - - Segment 6 Read Master ID select 160~191 Segment 6 Read Master ID select 160~191 - - - Segment 6 Read Master ID select 192~223 Segment 6 Read Master ID select 192~223 - - - Segment 6 Read Master ID select 224~255 Segment 6 Read Master ID select 224~255 - - - Segment 6 Write Master ID select 0~31 Segment 6 Write Master ID select 0~31 - - - Segment 6 Write Master ID select 32~63 Segment 6 Write Master ID select 32~63 - - - Segment 6 Write Master ID select 64~95 Segment 6 Write Master ID select 64~95 - - - Segment 6 Write Master ID select 96~127 Segment 6 Write Master ID select 96~127 - - - Segment 6 Write Master ID select 128~159 Segment 6 Write Master ID select 128~159 - - - Segment 6 Write Master ID select 160~191 Segment 6 Write Master ID select 160~191 - - - Segment 6 Write Master ID select 192~223 Segment 6 Write Master ID select 192~223 - - - Segment 6 Write Master ID select 224~255 Segment 6 Write Master ID select 224~255 - - - - Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 7 Read Master ID select 0~31 Segment 7 Read Master ID select 0~31 - - - Segment 7 Read Master ID select 32~63 Segment 7 Read Master ID select 32~63 - - - Segment 7 Read Master ID select 64~95 Segment 7 Read Master ID select 64~95 - - - Segment 7 Read Master ID select 96~127 Segment 7 Read Master ID select 96~127 - - - Segment 7 Read Master ID select 128~159 Segment 7 Read Master ID select 128~159 - - - Segment 7 Read Master ID select 160~191 Segment 7 Read Master ID select 160~191 - - - Segment 7 Read Master ID select 192~223 Segment 7 Read Master ID select 192~223 - - - Segment 7 Read Master ID select 224~255 Segment 7 Read Master ID select 224~255 - - - Segment 7 Write Master ID select 0~31 Segment 7 Write Master ID select 0~31 - - - Segment 7 Write Master ID select 32~63 Segment 7 Write Master ID select 32~63 - - - Segment 7 Write Master ID select 64~95 Segment 7 Write Master ID select 64~95 - - - Segment 7 Write Master ID select 96~127 Segment 7 Write Master ID select 96~127 - - - Segment 7 Write Master ID select 128~159 Segment 7 Write Master ID select 128~159 - - - Segment 7 Write Master ID select 160~191 Segment 7 Write Master ID select 160~191 - - - Segment 7 Write Master ID select 192~223 Segment 7 Write Master ID select 192~223 - - - Segment 7 Write Master ID select 224~255 Segment 7 Write Master ID select 224~255 - - - - - - - - default r address 0 register(1K-Byte address, bit 22 ~ bit 10). default r address 0 register(1K-Byte address, bit 22 ~ bit 10). - - default r address 0 register(1K-Byte address, bit 22 ~ bit 10). - - - - default w address 0 register(1K-Byte address, bit 22 ~ bit 10). default w address 0 register(1K-Byte address, bit 22 ~ bit 10). - - default w address 0 register(1K-Byte address, bit 22 ~ bit 10). - - - - - clock gate bypass clock gate bypass - - 0: don't response error; 1: response error. - - - clock gate bypass - - - - - Interrupt enable reg Interrupt enable reg - - Port 0 write address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 write address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 write address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 write address miss final int -1: Address Miss -0: Normal - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 read address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 read address miss final int -1: Address Miss -0: Normal - - - - - Debug address register for port 0 write channel Debug address register for port 0 write channel - - Port 0 write channel address, 1K-Byte - - - - Debug id register for port 0 write channel Debug id register for port 0 write channel - - Port 0 write channel id, MSB is prot[1] - - - - Debug address register for port 0 read channel Debug address register for port 0 read channel - - Port 0 read channel address, 1K-Byte - - - - Debug id register for port 0 read channel Debug id register for port 0 read channel - - Port 0 read channel id, MSB is prot[1] - - - - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - - - Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 - - - Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 - - - Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 - - - Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 - - - Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 - - - Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 - - - Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 - - - Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 - - - Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 - - - Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 - - - Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 - - - Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 - - - Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 - - - Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 - - - Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 - - - Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 - - - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 - - - Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 - - - Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 - - - Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 - - - Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 - - - Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 - - - Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 - - - Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 - - - Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 - - - Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 - - - Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 - - - Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 - - - Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 - - - Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 - - - Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 - - - Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 - - - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 - - - Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 - - - Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 - - - Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 - - - Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 - - - Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 - - - Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 - - - Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 - - - Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 - - - Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 - - - Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 - - - Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 - - - Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 - - - Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 - - - Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 - - - Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 - - - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 - - - Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 - - - Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 - - - Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 - - - Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 - - - Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 - - - Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 - - - Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 - - - Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 - - - Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 - - - Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 - - - Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 - - - Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 - - - Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 - - - Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 - - - Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 - - - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 - - - Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 - - - Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 - - - Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 - - - Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 - - - Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 - - - Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 - - - Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 - - - Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 - - - Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 - - - Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 - - - Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 - - - Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 - - - Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 - - - Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 - - - Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 - - - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 - - - Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 - - - Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 - - - Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 - - - Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 - - - Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 - - - Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 - - - Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 - - - Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 - - - Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 - - - Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 - - - Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 - - - Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 - - - Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 - - - Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 - - - Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 - - - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 - - - Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 - - - Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 - - - Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 - - - Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 - - - Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 - - - Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 - - - Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 - - - Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 - - - Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 - - - Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 - - - Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 - - - Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 - - - Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 - - - Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 - - - Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 - - - - - - - - default r address 0 register(1K-Byte address, bit 16 ~ bit 10). default r address 0 register(1K-Byte address, bit 16 ~ bit 10). - - default r address 0 register(1K-Byte address, bit 16 ~ bit 10). - - - - default w address 0 register(1K-Byte address, bit 16 ~ bit 10). default w address 0 register(1K-Byte address, bit 16 ~ bit 10). - - default w address 0 register(1K-Byte address, bit 16 ~ bit 10). - - - - - clock gate bypass clock gate bypass - - 0: don't response error; 1: response error. - - - clock gate bypass - - - - - Interrupt enable reg Interrupt enable reg - - Port 0 write address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 write address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 write address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 write address miss final int -1: Address Miss -0: Normal - - - - Interrupt enable reg Interrupt enable reg - - Port 0 read address miss int enable -1: Enable -0: Disable - - - - Interrupt write-clear reg Interrupt write-clear reg - - Port 0 read address miss int write-clear - - - - Original interrupt reg Original interrupt reg - - Port 0 read address miss original int -1: Address Miss -0: Normal - - - - Final interrupt reg Final interrupt reg - - Port 0 read address miss final int -1: Address Miss -0: Normal - - - - - Debug address register for port 0 write channel Debug address register for port 0 write channel - - Port 0 write channel address, 1K-Byte - - - - Debug id register for port 0 write channel Debug id register for port 0 write channel - - Port 0 write channel id, MSB is prot[1] - - - - Debug address register for port 0 read channel Debug address register for port 0 read channel - - Port 0 read channel address, 1K-Byte - - - - Debug id register for port 0 read channel Debug id register for port 0 read channel - - Port 0 read channel id, MSB is prot[1] - - - - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - Segment default first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - Segment default last address, the actual address should right shift 10-bit (1K-Byte) - - - - Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 - - - Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 - - - Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 - - - Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 - - - Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 - - - Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 - - - Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 - - - Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 - - - Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 - - - Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 - - - Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 - - - Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 - - - Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 - - - Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 - - - Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 - - - Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 - - - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 - - - Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 - - - Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 - - - Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 - - - Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 - - - Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 - - - Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 - - - Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 - - - Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 - - - Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 - - - Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 - - - Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 - - - Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 - - - Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 - - - Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 - - - Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 - - - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 - - - Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 - - - Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 - - - Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 - - - Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 - - - Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 - - - Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 - - - Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 - - - Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 - - - Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 - - - Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 - - - Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 - - - Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 - - - Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 - - - Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 - - - Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 - - - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 - - - Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 - - - Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 - - - Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 - - - Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 - - - Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 - - - Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 - - - Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 - - - Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 - - - Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 - - - Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 - - - Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 - - - Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 - - - Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 - - - Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 - - - Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 - - - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 - - - Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 - - - Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 - - - Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 - - - Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 - - - Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 - - - Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 - - - Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 - - - Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 - - - Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 - - - Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 - - - Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 - - - Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 - - - Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 - - - Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 - - - Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 - - - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 - - - Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 - - - Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 - - - Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 - - - Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 - - - Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 - - - Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 - - - Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 - - - Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 - - - Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 - - - Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 - - - Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 - - - Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 - - - Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 - - - Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 - - - Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 - - - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) - - - - Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 - - - Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 - - - Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 - - - Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 - - - Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 - - - Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 - - - Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 - - - Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 - - - Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 - - - Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 - - - Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 - - - Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 - - - Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 - - - Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 - - - Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 - - - Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 - - - - - - - - rd 0 sec control rd 0 sec control - - control master emmc_rd_sec rd security operation: -00: Non security operation. -01/10: assign to master arprot[1] -11:Security operation - - - control master lzma_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master gouda_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master usb_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - - wr 0 sec control wr 0 sec control - - control master emmc_wr_sec wr security operation: -00: Non security operation. -01/10: assign to master arprot[1] -11:Security operation - - - control master lzma_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master gouda_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master usb_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - - - - - - - rd 0 sec control rd 0 sec control - - control master cp_sys_aon_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master rf_sys_aon_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master dap_aon_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master fdma_aon_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master cp_sys_pub_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - control master gnss_sys_pub_rd_sec rd security operation: -0: Non security operation. -1: Security operation. - - - - wr 0 sec control wr 0 sec control - - control master cp_sys_aon_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master rf_sys_aon_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master dap_aon_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master fdma_aon_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master cp_sys_pub_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - control master gnss_sys_pub_wr_sec wr security operation: -0: Non security operation. -1: Security operation. - - - - - - - - - OTG function address/Powe/TX interrupt register - - EP x TX Interrupt. Signals that the Transmit interrupt has been received from this endpoint - - - Soft Connect. If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit is set by the CPU and tri-stated when this bit is cleared by the CPU. Note: Only valid in Peripheral Mode - - - HS Enable. When set by the CPU, the core will negotiate for High-speed mode when the device is reset by the hub. If not set, the device will only operate in Full-speed mode. - - - HS Mode. When set, this read-only bit indicates High-speed mode successfully negotiated during USB reset. In Peripheral Mode, becomes valid when USB reset completes (as indicated by USB reset interrupt). In Host Mode, becomes valid when Reset bit is cleared. Remains valid for the duration of the session. - - - Reset. This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write from the CPU in Host Mode but Read-Only in Peripheral Mode. - - - Resume. Set by the CPU to generate Resume signaling when the function is in Suspend mode. The CPU should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also automatically set when Resume signaling from the target is detected while the core is suspended. - - - Suspend Mode. In Host mode, this bit is set by the CPU to enter Suspend mode. In Peripheral mode, this bit is set on entry into Suspend mode. It is cleared when the CPU reads the interrupt register, or sets the Resume bit above. - - - Enable Suspend M. Set by the CPU to enable the SUSPENDM output - - - Function address - - - - OTG RX interrupt register/TX interrupt enable register - - EP x TX Interrupt Mask - - - EP x RX Interrupt (x=0 to15)Signals that the Receive interrupt has been received from this endpoint. -0: Masks the Transmit interrupt from the endpoint x -1: The interrupt is allowed - - - - OTG RX interrupt enable/Common USB interrupt register - - VBUS Error Enable.Enables the VBUS interrupt bit in OTG_INTUSB - - - Session Request Enable.Enables the SREQ interrupt bit in OTG_INTUSB - - - Disconnect Enable.Enables the DISCON interrupt bit in OTG_INTUSB - - - Connect Enable.Enables the CONN interrupt bit in OTG_INTUSB - - - Start of Frame Enable.Enables the SOF interrupt bit in OTG_INTUSB - - - Reset/Babble Enable.Enables the RST interrupt bit in OTG_INTUSB - - - Resume Enable.Enables the RES interrupt bit in OTG_INTUSB - - - Suspend Enable.Enables the SUSP interrupt bit in OTG_INTUSB - - - VBUS Error. Set when VBus drops below the VBus Valid threshold during a session. Note: Only valid in Peripheral mode. - - - Session Request. Set when Session Request signaling has been detected. Note: Only valid when the core is A-device. - - - Disconnect.HOST: Set when a device disconnect is detected (HOSTDISCON going high). PERIPHERAL: Set when a session ends. - - - Connect. Set when a device connection is detected (HOSTDISCON signal going low). Note: Only valid in Host mode. - - - Start of Frame.Set when a new frame starts. - - - Reset/Babble -PERIPHERAL: Set when Reset signaling is detected on the USB. HOST: Set when babble condition is detected. - - - Resume. Set when Resume signaling is detected on the bus while the core is in Suspend mode. - - - Suspend. Set when Suspend signaling is detected on the bus. Note: Only valid in Peripheral mode. - - - EP x RX Interrupt Mask (x = 1 to 15) -0: Masks the Receive interrupt from the endpoint x -1: Allows the interrupt - - - - OTG frame number/INDEX/Test Mode register - - Force Host.he Application Software sets this bit to instruct the core to enter Host mode when the Session bit is set, regardless of whether it is connected to any peripheral. The state of the CID input, Host Disconnect and Line State signals are ignored. The core will then remain in Host mode until the Session bit is cleared, even if a device is disconnected, and if the Force_Host bit remains set, will re-enter Host mode the next time the Session bit is set. While in this mode, the status of the HOSTDISCON signal from the PHY may be read from bit 7 of the DevCtl register.The operating speed is determined from the FHS and FFS bits as follows: -00 : Low speed -01 : Full speed -10: High speed -11: undefined - - - FIFO Aceess.The CPU sets this bit to transfer the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO. The bit is cleared automatically. - - - Force full-speed.This bit forces the core into full-speed mode when it receives a USB reset. - - - Force high-speed.This bit forces the core into high-speed mode when it receives a USB reset. - - - Test Packet.The CPU sets this bit to enter the Test_Packet test mode. In this mode, the MUSBMHDRC repetitively transmits on the bus a 53-byte test packet, the form of which is defined in the Universal Serial Bus Specification Revision 2.0, Section 7.1.20. The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before the test mode is entered. -Note: Only valid in high-speed mode - - - Test K-state.The CPU sets this bit to enter the Test_K test mode. In this mode, the MUSBMHDRC transmits a continuous K on the bus. -Note: Only valid in high-speed mode - - - Test J-state.The CPU sets this bit to enter the Test_J test mode. In this mode, the MUSBMHDRC transmits a continuous J on the bus. -Note: Only valid in high-speed mode. - - - Test SE0/NAK.The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode, the MUSBMHDRC remains in High-speed mode but responds to any valid IN token with a NAK. -Note: Only valid in high-speed mode. - - - Endpoint Number.This field programs the current active endpoint - - - Current frame number.Shows the current frame number - - - - EP0 control and status register - - Host:Dis Ping, The CPU writes a 1 to this bit to instruct the core not to issue PING tokens in data and status phases of a high-speed Control transfer (for use with devices that do not respond to PING).. -Device:Reserved - - - Host:Data Toggle Write Enable, The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see Data Toggle bit, below). This bit is automatically cleared once the new value is written. -Device:Reserved - - - Host:Data toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If D10 is high, this bit may be written with the required setting of the data toggle. If D10 is low, any value written to this bit is ignored. -Device:Reserved - - - Host:Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Note: FlushFIFO has no effect unless TxPktRdy or RxPktRdy is set. -Device:Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Note: FlushFIFO has no effect unless TxPktRdy or RxPktRdy is set. - - - Host:NAK Timeout This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLimit0 register. The CPU should clear this bit to allow the endpoint to continue. -Device:Serviced RX Packet Ready. The software sets this bit in order to clear the Rx Packet Ready (RRDY) bit. Writing zero has no effect. -Device:Serviced Setup End. The software sets this bit in order to clear the Setup End (STE) bit. Writing zero has no effect. - - - Host:StatusPkt The CPU sets this bit at the same time as the TxPktRdy or ReqPkt bit is set, to perform a status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is used for the Status Stage transaction. -Device:Send Stall. The software sets this bit to terminate the current transaction. The STALL handshake will be transmitted and after that this bit is cleared automatically. - - - Host:ReqPkt. The CPU sets this bit to request an IN transaction. It is cleared when RxPktRdy is set. -Device:Setup End. This bit will be set when a control transaction ends before the Data End (DE) bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by the software setting the Serviced Setup End (SSE) bit. - - - Host:Error. This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. The CPU should clear this bit. An interrupt is generated when this bit is set. -Device:Data End. The software sets this bit when: -鈥 Setting TRDY for the last data packet. -鈥 Clearing RRDY after unloading the last data packet. -鈥 Setting TRDY for a zero length data packet. This bit is cleared automatically. Writing zero has no effect. - - - Host:SetupPkt The CPU sets this bit, at the same time as the TxPktRdy bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The software should clear this bit. - - - Host:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. -Device:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Host:TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). -Device:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Host:RxPktRdy This bit is set when a data packet has been received. An interrupt is generated (if enabled) when this bit is set. The CPU should clear this bit when the packet has been read from the FIFO. -Device:RX Packet Ready. This bit is set when the data packet is received. An interrupt is generated when RRDY is set (unless disabled). This bit can be cleared by software by setting SRDY bit. - - - Multiple - - - Maximum payload transmitted.Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - - OTG RX bytes received/EP0 type register - - Frames to NAK - - - Operation speed -00: Unused -01: High -10: Full -11: Low - - - EP0 bytes received - - - - OTG core configuration register - - Bulk Pkt Amalgation.When set, the automatic amalgamation of bulk packets is selected - - - Bulk Pkt Spliting.When set, the automatic splitting of bulk packets is selected - - - Big Endian.When set, it indicates Big Endian ordering is selected. - - - High-bandwidth ISO Support.When set to 1 indicates High-bandwidth RX ISO Endpoint Support selected. - - - High-bandwidth ISO Support.When set to 1 indicates High-bandwidth TX ISO Endpoint Support selected. - - - Dynamic FIFO Sizing.When set to 1 indicates Dynamic FIFO Sizing option selected. - - - Soft Connect.When set to 1 indicates Soft Connect/Disconnect option selected. - - - UTMI datawidth -0: 8 bits; -1: 16 bits. - - - - - OTG device control/MISC/TX FIFO size/RX FIFO size register - - Double Packet Buffering. Defines whether the double-packet buffering is set for a selected endpoint. When set, the double-packet buffering is turned on. - - - Endpoint RX FIFO Size. This field defines the RX FIFO size for a selected endpoint (and therefore a maximum packet size that is allowed before any splitting within the FIFO of Bulk/High- Bandwidth packets prior to transmission).RX FIFO Size (Bytes): - - - Double Packet Buffering. Defines whether the double-packet buffering is set for a selected endpoint. When set, the double-packet buffering is turned on. - - - Endpoint TX FIFO Size. This field defines the TX FIFO size for a selected endpoint (and therefore a maximum packet size that is allowed before any splitting within the FIFO of Bulk/High- Bandwidth packets prior to transmission).TX FIFO Size (Bytes): If DPB = 1, the size of the TX FIFO will be twice the size defined in this field. - - - current interrupt is none DMA related. - - - current interrupt is DMA related. - - - B-Device.This bit indicates whether the core is operating as the A-Device or the B-Device. Only valid while a session is in progress. -0: A-Device -1: B-Device -Note: If the core is in Force_Host mode (i.e. a session has been started with OTG_TM.Testmode.FRH = 1), this bit will indicate the state of the HOSTDISCON input signal from the transceiver. - - - Full Speed.Full Speed. This bit is set when a full-speed or high-speed device has been detected being connected to the port. (High-speed devices are distinguished from full-speed by checking for high-speed chirps when the device is reset.) Only valid in Host mode. - - - Low Speed.Low Speed. This bit is set when a low-speed device has been detected being connected to the port. Only valid in Host mode. - - - VBUS.These bits encode the current VBUS level as follows: 00: Below SessionEnd - - - Host Mode.This Read-only bit is set when the core is acting as a Host. - - - Host Request.Host Request. When set, the core will initiate the Host Negotiation when Suspend mode is entered. It is cleared when Host Negotiation is completed. - - - Session.When operating as an A-Device, this bit is set or cleared by the software to start or end a session.When operating as a B-Device, this bit is set/cleared by the core when a session starts/ends. It may also be set by the software to initiate the SRP. When the core is in Suspend mode, the bit may be cleared by the software to perform a software disconnect. - - - - OTG TX/RX FIFO address register - - FIFO Start Address. This field defines the start address of the endpoint FIFO in units of 8 bytes as follows. -13鈥檋000 0000 -13鈥檋001 0008 -13鈥檋002 0010 -鈥︹ 鈥︹ -13鈥檋1FFF FFF8 - - - FIFO Start Address. This field defines the start address of the endpoint FIFO in units of 8 bytes as follows. -13鈥檋000 0000 -13鈥檋001 0008 -13鈥檋002 0010 -鈥︹ 鈥︹ -13鈥檋1FFF FFF8 - - - - - OTG hardware version number register - - Major Version number.Returns 6d02 - - - Minor Version number. Returns 10d000 - - - - - OTG EP/RAM/link/VPLEN INFO register - - VBUS Pulse Length. -Sets the duration of the VBus pulsing charge in units of 546.1 us (the default setting corresponds to 32.77ms). -Note: When working in FS Interface mode, the timer values will be different: units of 682.62 us and the default value of 40.96 ms - - - Connect/Disconnect Delay. Sets the wait to be applied to allow for the user s connect/disconnect filter in units of 533.3ns (the default setting corresponds to 2.667us). Note: When working in FS Interface mode, the timer values will be different: units of 666.63 ns and the default value of 3.33 us - - - ID Pullup Delay. Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms (the default setting corresponds to 52.43ms). Note: When working in FS Interface mode, the timer values will be different: units of 5.46 ms and the default value of 65.54 ms - - - number of DMA channel - - - width of RAM DATA bus - - - number of RX_EP - - - number of TX_EP - - - - OTG HS/FS/LS time buffer register - - Reset All FFs in the XCLK clock domain. When a 1b1 is written to this bit, the XCLK clock domain reset will be asserted within a minimum delay of 7 cycles of the AHB clock. The output NRSTXO will be asynchronously asserted and synchronously de-asserted with respect to XCLK. This register is self clearing and always reads zero. - - - Reset All FFs in the AHB clock domain. When a 1b1 is written to this bit, the AHB clock domain reset will be asserted within a minimum delay of 7 cycles of the AHB clock. The output NRSTO will be asynchronously asserted and synchronously de-asserted with respect to AHB clock. This register is self clearing and always reads zero. - - - LS Time Buffer. Sets for Low-speed transactions the time before EOF to stop beginning new transactions, in units of 1.067 us (the default setting corresponds to 121.6 us). - - - FS Time Buffer. Sets for Full-speed transactions the time before EOF to stop beginning new transactions, in units of 533.3 ns (the default setting corresponds to 63.46 us). - - - HS Time Buffer. Sets for High-speed transactions the time before EOF to stop beginning new transactions, in units of 133.3 ns (the default setting corresponds to 17.07 us) - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG TX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - OTG RX FUNCTION Address/HUB Address/HUB port register - - HUB port number - - - 1= multiple transaction translator -0= single transaction translato - - - The address of hub - - - address of the target function - - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - OTG TX MAXPKTSIZE/CONTROL STATUS register - - Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host: Reserved -Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. - - - Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. - - - Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. - - - Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. -Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. -While D6(ISO)=0, - 鈥1: CPU sets this bit to enable the TX endpoint to do INT transfer - 鈥0: CPU sets this bit to enable the TX endpoint to do BULK transfer - - - Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. - - - Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. -Note: Valid only for Bulk endpoints. -Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. -Note: In anything other than a high-bandwidth transfer, this bit will always return zero. - - - Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. - - - Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. - - - Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. -Note: Setting this bit also clears the Data Toggle. -Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. - - - Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. -Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. -Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. - - - FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. - - - TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. - - - Multiplier.See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX MAXPKTSIZE/CONTROL STATUS register - - Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. -Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. -Note: This bit should not be set for high-bandwidth Isochronous endpoints. - - - Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. -Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. - - - DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. - - - Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. -Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. - - - DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. - - - Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. - - - Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. - - - Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. -Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. - - - Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. - - - Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. -Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. - - - Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. -Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. -Note: This bit has no effect where the endpoint is being used for Isochronous transfers. - - - Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. -Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. - - - Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. -Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. -Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. -Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. -Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. - - - FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. - - - RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. - - - Multiplier. See spec. - - - Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. - - - - OTG RX bytes received counter/transaction control/TX polling interval register - - TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: - 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: - 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. - - - - OTG RX transaction control/polling interval register - - RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. - - - Operating Speed. Operating speed of the target device: 00: Unused -01: High -10: Full -11: Low - - - Protocol. This bit selects the required protocol for the TX endpoint: 00: Control -01: Isochronous -10: Bulk -11: Interrupt - - - Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. - - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX packet count register - - enable the pre-define-RX-data-length - - - RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. - - - - OTG RX/TX double packet buffer disable register - - EPx Receive Double Buffer Disable - - - EPx Receive Double Buffer Disable - - - - OTG chirp timeout control/high-speed resume register - - The delay from the end of High Speed resume signaling to enabling UTM normal operating mode. The default value corresponds to a delay of 3us - - - Configurable Chirp Timeout timer, the default value corresponds to a delay of 1.1ms. - - - - OTG HS BUS TURN around/FIFO timeout check/FIFO timeout count/external control registers - - 1= wait for tx data sent on usb bus - - - 1= set flushFIFO, all rx FIFO pointers, status for MCU&USB -Of each buff will be clear -0 = set flushFIFO,rx pointers, status forr current buff of MCU side will be clear. - - - 1= set flushFIFO, all tx FIFO pointers, status for MCU&USB -Of each buff will be clear -0 = set flushFIFO, tx pointers, status forr current buff of MCU side will be clear. - - - 1= enable OTG SRP protocol -0= disable OTG SRP protocol - - - While HOST_force_en =1 -1= DEVICE mode -0 = HOST mode -(no function if HOST_force_en =0) - - - Setting the mode force host or device,1=SW force enable/0= SW force disable - - - Setting the check number of data in FIFO - - - Setting the period of check data in FIFO - - - Setting the mode of fifochecck - - - adjust the setting of HS bus turn around timing out setting - - - - OTG TX LISTEND interrupt status/enable register - - When 鈥1鈥, the TX_listend_int15 will function - - - When 鈥1鈥, the TX_listend_int14 will function - - - When 鈥1鈥, the TX_listend_int13 will function - - - When 鈥1鈥, the TX_listend_int12 will function - - - When 鈥1鈥, the TX_listend_int11 will function - - - When 鈥1鈥, the TX_listend_int10 will function - - - When 鈥1鈥, the TX_listend_int9 will function - - - When 鈥1鈥, the TX_listend_int8 will function - - - When 鈥1鈥, the TX_listend_int7 will function - - - When 鈥1鈥, the TX_listend_int6 will function - - - When 鈥1鈥, the TX_listend_int5 will function - - - When 鈥1鈥, the TX_listend_int4 will function - - - When 鈥1鈥, the TX_listend_int3 will function - - - When 鈥1鈥, the TX_listend_int2 will function - - - When 鈥1鈥, the TX_listend_int1 will function - - - When TX EP15 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP14 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP13 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP12 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP11 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP10 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP9 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP8 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP7 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP6 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP5 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP4 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP3 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP2 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - When TX EP1 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. - - - - OTG TX LISTEND interrupt clear register - - When 鈥1鈥, the TX_listend_int15 will be cleared - - - When 鈥1鈥, the TX_listend_int14 will be cleared - - - When 鈥1鈥, the TX_listend_int13 will be cleared - - - When 鈥1鈥, the TX_listend_int12 will be cleared - - - When 鈥1鈥, the TX_listend_int11 will be cleared - - - When 鈥1鈥, the TX_listend_int10 will be cleared - - - When 鈥1鈥, the TX_listend_int9 will be cleared - - - When 鈥1鈥, the TX_listend_int8 will be cleared - - - When 鈥1鈥, the TX_listend_int7 will be cleared - - - When 鈥1鈥, the TX_listend_int6 will be cleared - - - When 鈥1鈥, the TX_listend_int5 will be cleared - - - When 鈥1鈥, the TX_listend_int4 will be cleared - - - When 鈥1鈥, the TX_listend_int3 will be cleared - - - When 鈥1鈥, the TX_listend_int2 will be cleared - - - When 鈥1鈥, the TX_listend_int1 will be cleared - - - - OTG endpoint enable register - - When 鈥1鈥, the Endpoint15 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint14 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint13 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint12 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint11 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint10 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint9 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint8 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint7 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint6 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint5 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint4 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint3 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint2 (both TX/RX) will function - - - When 鈥1鈥, the Endpoint1 (both TX/RX) will function - - - - - - - - - global enable global enable control register - - This value requires one-hot or all zero. -[1:0] user channel; [2] train 1 ; [3] : train 2 - - - - - - Funnel overflow flag Funnel overflow flag register - - funnel async fifo empty status - - - funnel overflow flag clear. - - - funnel async fifo full flag - - - - interrupte enable - - fifo_overflow interrupt - - - - interrupte status - - - - dbgio control - - Software reset. -0: work -1: reset - - - Dbgio source clock select -1鈥檋0: 200MHz -1鈥檅1: 140MHz - - - Dbgio ddr mode enable - - - - The max length of data package control register - - "fsm_cut_off_len +1" is the max length of data package between any SYNC & CRC package, keep the value equals to (33N+32) where N is integer or zero. - - - - The max length of data wait cycle register - - "fsm_data_wait_len +1" is the max length of data wait cycle time when gearbox fifo is almost empty - - - - DBGIO PHY DLL CFG DBGIO PHY DLL CFG registers - - Cycles to wait DLL locked signals. - - - write delay cell select -0:use user defined value from CLKDATWR_DLY_VAL -1:use dll generated value which referenced form CLKDATWR_DLY_VAL - - - DLL Clock source selection -0: Select 1x clock -1: Select 2x clock - - - DLL enable signal -0:DLL disable -1:DLL enable - - - DLL clear signal -1:clear DLL - - - Don鈥檛 support in this version - - - DLL output delay value enable - - - DLL start enable signal, this bit should be write to 1鈥檅0 when it is enabled to 1鈥檅1 - - - DLL lock mode: -0: full cycle lock mode -1: half cycle lock mode - - - DLL count initial value, DLL use it as the initial value to count the delay value. - - - DLL change threshold value, DLL update rd/wr/cmd delay line value if the DLL count delta bigger then DLL_CPST_THRESHOLD - - - DLL phase interval , DLL use it as the interval of phase 1 and phase2 - - - OUPUT clock phase select - - - - DBGIO PHY DLL DLY DBGIO PHY DLL DLY registers - - Clock Data Write Line Delay Value -Based Phase is invert of PHY Clock -When DLL_DATWR_CPST_EN is enable, - - - - DBGIO PHY DLL Offset Read DBGIO PHY DLL Offset Read registers - - Clock Data Write Line Delay Invert - - - Data Write Delay offset. The highest bit indicates if it is add or sub. -OFFSET [4]=0: CLKDATWR_DLY_VAL + OFFSET [3:0] -OFFSET [4]=1: CLKDATWR_DLY_VAL 鈥 OFFSET [3:0]. -If DLL_DATWR _CPST_EN==1, the offset is added after the proportion. -E.g. If -Clock cycle (CYC)== 5ns -CLKDATWR _DLY_ VAL (VAL) ==鈥檋40, CLKDATWR_DLY_OFFSET (OFSET) == 鈥榟6, -DLL_CNT(CNT) == 鈥榟20 - it means delay: -(VAL/鈥檋100)*CYC + (CYC * OFSET) / CN = - (鈥榟40/鈥檋100)*5ns + (5ns * 鈥榟6) / 鈥榟20 鈮2.2ns - - - - DBGIO PHY DLL STS0 registers DBGIO PHY DLL STS0 registers - - Reserved for vender asic only - - - Reserved for vender asic only - - - If use DLL, software should wait this value to 1鈥檅1 - - - If use DLL, soft ware should wait DLL_LOCKED to 1鈥檅1 and at that time ,this bit is 1鈥檅0 - - - Reserved for vender asic only - - - Reserved for vender asic only - - - DLL delay cell counts of 1 cycle - - - - DBGIO PHY DLL STS1 DBGIO PHY DLL STS1 registers - - Reserved for vender asic only - - - - DBGIO PHY DLL BACKUP DBGIO PHY DLL BACKUP registers - - Oe_ext_optional( Reserved for vender asic only) - - - Force slice en value( Reserved for vender asic only) - - - Force slice enable( Reserved for vender asic only) - - - Force dll use backup mode value( Reserved for vender asic only) - - - Force dll use backup mode( Reserved for vender asic only) - - - - Which channel be used Which channel be used - - If one channel is used, corresponding bit will be 1, otherwise is 0. - - - - Which channel use source sync mode - - If one channel uses source sync mode, corresponding bit will be 1, otherwise is 0. - - - - Which channel use handshake mode - - If one channel uses handshake mode, corresponding bit will be 1, otherwise is 0. - - - - Which channel use LA mode - - If one channel uses LA mode, corresponding bit will be 1, otherwise is 0. - - - - LA channel sample rate control register - - Sample rate of the LA channel is "(sample_rate + 1) / 16" -This setting can't exceed 0xa, due to the ideal bandwidth limitation. - - - - IP version IP version - - R0p1 - - - - - - - - - - - - - - - - - - - - - - - 鐩戞帶鎺у埗瀵勫瓨鍣 - - Monitor杩愯鍚姩浣 -0锛氬仠姝㈢洃鎺ф垨鐩戞帶宸插畬鎴愩 -1锛氬紑濮嬬洃鎺ф垨鐩戞帶姝ｅ湪杩涜銆 -娉:BUS Monitor鎬诲紑鍏筹紝闄よ繛缁洃鎺фā寮忓锛屽叾浠栫洃鎺фā寮忎笅锛屽綋鐩戞帶瀹屾垚鍚庯紝璇ヤ綅鑷姩娓呴浂銆 - - - - 鐩戞帶鎺у埗瀵勫瓨鍣 - - 鐩戞帶鐗瑰畾鍦板潃娈佃寖鍥村鐨勫啓鎿嶄綔浣胯兘浣 -0锛氫笉浣胯兘锛 -1锛氫娇鑳斤紱 - - - BUSY淇″彿杈撳嚭璁剧疆 -1锛氶殢鐩戞帶鍚姩杈撳嚭 -0锛氫竴鐩磋緭鍑 - - - RBUSY淇″彿杈撳嚭璁剧疆 -1锛氶殢鐩戞帶鍚姩杈撳嚭 -0锛氫竴鐩磋緭鍑 - - - WBUSY淇″彿杈撳嚭璁剧疆 -1锛氶殢鐩戞帶鍚姩杈撳嚭 -0锛氫竴鐩磋緭鍑 - - - 鐩戞帶鐗瑰畾鍦板潃娈佃寖鍥村唴鐨勫啓鎿嶄綔浣胯兘浣 -1锛氬紑鍚姛鑳 -0锛氫笉寮鍚姛鑳 - - - 鐩戞帶璁块棶鍛戒护鏁伴噺杈惧埌璁剧疆鍊 -1锛氬紑鍚姛鑳 -0锛氫笉寮鍚姛鑳 - - - 杩炵画鐩戞帶鍔熻兘锛 -1锛氬紑鍚姛鑳 -0锛氫笉寮鍚姛鑳 - - - 鐩戞帶璁惧畾鏃堕棿娈佃闂噺锛 -1锛氬紑鍚姛鑳 -0锛氫笉寮鍚姛鑳 - - - 鐩戞帶鎬荤嚎閿佹 -1锛氬紑鍚姛鑳 -0锛氫笉寮鍚姛鑳 - - - 鐩戞帶鎬讳腑鏂娇鑳 -0锛氫笉浣胯兘涓柇銆 -1锛氫娇鑳戒腑鏂 -娉細鐩戞帶璁惧畾鏃堕棿娈典笌鐩戞帶璁惧畾璁块棶閲忚繖涓や釜鍔熻兘鍚屾椂寮鍚椂锛屼换浣曚竴涓潯浠惰揪鍒帮紝灏卞仠姝㈡荤嚎璐熻嵎鐨勭洃鎺э紝鎬荤嚎鎸傛涓庣壒瀹氬湴鍧鐗瑰畾鏁版嵁鐨勭洃鎺у姛鑳界収甯革紱 -鐗瑰畾鍦板潃鐨勭洃鎺у姛鑳藉紑鍚椂锛孧ON_M0_ADDR_WID淇濈暀鐨勬槸绗竴娆℃潯浠惰Е鍙戠殑ID鍙凤紱鐩戞帶鐗瑰畾鍦板潃鑼冨洿鍐呬笌鐩戞帶鐗瑰畾鍦板潃鑼冨洿澶栫殑鍔熻兘涓嶈兘閮戒娇鑳斤紱褰撶洃鎺х壒瀹氬湴鍧鑼冨洿鍐呯殑鍔熻兘浣胯兘鍚庯紝浠讳綍璁块棶鍥涙璁惧畾鍦板潃娈电殑鍐欐搷浣滈兘浼氳Е鍙戜腑鏂紱褰撶洃鎺х壒瀹氬湴鍧鑼冨洿澶栫殑鍔熻兘浣胯兘鍚庯紝浠讳綍璁块棶鍥涙璁惧畾鍦板潃娈典互澶栫殑DDR鍦板潃锛0x0-0x1fff_ffff锛夊啓鎿嶄綔閮戒細瑙﹀彂涓柇锛屽嵆鐩戞帶鍦板潃娈佃寖鍥村鐨勫姛鑳藉彧闄愪簬DDR鐨勫湴鍧锛屽瘎瀛樺櫒鐨勫湴鍧涓嶅湪鐩戞帶涔嬪唴锛涘鏋滅洃鎺х殑鍦板潃娈靛皯浜庡洓娈碉紝闇灏嗗洓娈靛湴鍧瀵勫瓨鍣ㄥ潎閰嶉綈鍏紝澶氫綑鐨勫湴鍧瀵勫瓨鍣ㄦ闇涓庡墠闈换涓鏈夋晥鍦板潃閰嶇疆鐩稿悓鍊笺 -杩炵画鐩戞帶鍔熻兘浣胯兘鍚庯紝姣忛殧璁惧畾鏃堕棿娈典骇鐢熶竴涓腑鏂紝骞剁户缁洃鎺э紱鈥滆繛缁洃鎺у姛鑳解濅笌鈥滅洃鎺ц瀹氭椂闂存璁块棶閲忊濅袱涓姛鑳藉彧鑳芥敮鎸佷竴涓 - - - - 鐩戞帶鎺у埗瀵勫瓨鍣 - - - 璁块棶鍛戒护闄愬畾瀵勫瓨鍣 - - - 涓柇浣胯兘瀵勫瓨鍣 - - MASTER0璁块棶璁惧畾鍦板潃娈典腑鏂娇鑳 -0锛氫笉浣胯兘涓柇銆 -1锛氫娇鑳戒腑鏂 - - - 璁块棶鍛戒护鏁拌揪鍒拌瀹氭暟鐩腑鏂娇鑳 -0锛氫笉浣胯兘涓柇銆 -1锛氫娇鑳戒腑鏂 - - - 璁℃暟鏃堕棿鍒拌揪璁惧畾鍊间腑鏂娇鑳 -0锛氫笉浣胯兘涓柇銆 -1锛氫娇鑳戒腑鏂 - - - LOCK涓柇浣胯兘 -0锛氫笉浣胯兘涓柇銆 -1锛氫娇鑳戒腑鏂 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 鐩戞帶璁惧畾鏃堕棿娈垫ā寮忎笅锛岀洃鎺ф椂闂寸粨鏉熶腑鏂 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER0璁块棶鐗瑰畾鍦板潃娈典腑鏂 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER4璇昏闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇 - - - MASTER4鍐欒闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER3璇昏闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER3鍐欒闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER2璇昏闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER2鍐欒闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER1璇昏闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER1鍐欒闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER0璇昏闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER0鍐欒闂懡浠よ揪鍒版寚瀹氭暟涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - 杩炵画鐩戞帶妯″紡涓嬶紝璁惧畾鏃堕棿鍒拌揪涓柇 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER4鎬荤嚎閿佹 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER3鎬荤嚎閿佹 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER2鎬荤嚎閿佹 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER1鎬荤嚎閿佹 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - MASTER0鎬荤嚎閿佹 -0锛氭棤涓柇銆 -1锛氭湁涓柇銆 - - - - MASTER0鐩戞帶绗竴娈佃捣濮嬪湴鍧瀵勫瓨鍣 - - - MASTER0鍐欑壒瀹氬湴鍧娈垫椂ID鍙峰瘎瀛樺櫒 - - - MASTER0鐩戞帶绗竴娈佃捣濮嬪湴鍧瀵勫瓨鍣 - - 鍐欑壒瀹氬湴鍧娈电殑ID鍙 -娉: MON_START_ADDR, MON_END_ADDR涓や釜瀵勫瓨鍣ㄧ敤浜庤缃甅ASTER0鐩戞帶鍦板潃娈电殑璧峰鍜岀粨鏉熷湴鍧;锛屽叾涓捣濮嬪湴鍧搴旇澶т簬绛変簬缁撴潫鍦板潃锛涘綋MASTER0璁块棶璇ュ湴鍧娈垫椂,ADDR_INT浼氱疆浣,濡傛灉璇ヤ腑鏂娇鑳藉垯浜х敓涓柇 - - - - - 鎬荤嚎鎸傛鏃堕棿瀵勫瓨鍣 - - 鎬荤嚎鎸傛鍒ゅ畾鏃堕棿 -娉細涓涓闂瀵勫瓨鍣ㄧ殑璁惧畾鏃堕棿鍐呮湭瀹屾垚璁块棶锛屽嵆璁ゅ畾涓烘荤嚎鎸傛 - - - - 閫氶亾0璇诲懡浠よ鏁板櫒 - - - 閫氶亾0璇绘暟鎹鏁板櫒 - - - 閫氶亾0璇绘暟鎹鏁板櫒 - - - 閫氶亾0鍐欐暟鎹鏁板櫒 - - - 閫氶亾1璇诲懡浠よ鏁板櫒 - - - 閫氶亾1璇绘暟鎹鏁板櫒 - - - 閫氶亾1璇绘暟鎹鏁板櫒 - - - 閫氶亾1鍐欐暟鎹鏁板櫒 - - - 閫氶亾2璇诲懡浠よ鏁板櫒 - - - 閫氶亾2璇绘暟鎹鏁板櫒 - - - 閫氶亾2璇绘暟鎹鏁板櫒 - - - 閫氶亾2鍐欐暟鎹鏁板櫒 - - - 閫氶亾3璇诲懡浠よ鏁板櫒 - - - 閫氶亾3璇绘暟鎹鏁板櫒 - - - 閫氶亾3璇绘暟鎹鏁板櫒 - - - 閫氶亾3鍐欐暟鎹鏁板櫒 - - - 閫氶亾4璇诲懡浠よ鏁板櫒 - - - 閫氶亾4璇绘暟鎹鏁板櫒 - - - 閫氶亾4璇绘暟鎹鏁板櫒 - - - 閫氶亾4鍐欐暟鎹鏁板櫒 - - - MASTER0鐩戞帶绗簩娈佃捣濮嬪湴鍧瀵勫瓨鍣 - - - MASTER0鐩戞帶绗簩娈电粨鏉熷湴鍧瀵勫瓨鍣 - - - MASTER0鐩戞帶绗笁娈佃捣濮嬪湴鍧瀵勫瓨鍣 - - - MASTER0鐩戞帶绗笁娈电粨鏉熷湴鍧瀵勫瓨鍣 - - - MASTER0鐩戞帶绗洓娈佃捣濮嬪湴鍧瀵勫瓨鍣 - - - MASTER0鐩戞帶绗洓娈电粨鏉熷湴鍧瀵勫瓨鍣 - - - MASTER0鍐欑壒瀹氬湴鍧娈典簨浠跺彂鐢熸椂鐨勫湴鍧瀵勫瓨鍣 - - - - - - - - - - phy initial complete configuration - - - phy enable - - - - - clk_ag_rd enable - - - clk_ag_wr enable - - - clk_ag enable - - - clk_fg enable - - - all clk enable - - - - - software configure axi channel slave port cwakeup - - - software configure axi channel master port cwakeup - - - low power interface m0 ch or all ch select - - - - - burst length 256byte limit for freq of 26m,52m and 109m - - - wb955 128byte wrapper limit - - - winbond memory sample rwds time - - - psram is winbond memory 64Mb or 256Mb - - - psram dq width x8 or x16 select - - - psram is ap memory 256Mb or not select - - - psram is winbond hyperbus or not select - - - - - winbond memory mr write data - - - - - - not use - - - - - This bit indicates ad slice 1 cpst is in IDLE status. - - - This bit indicates ad slice 0 cpst is in IDLE status. - - - - - phy input data - - - - - - This field indicates the cycles to wait the DLL lock internal signals - - - This bit use to clear dll error automaticly - - - This field is the sum of the delay cells from phase1 to phase2. - - - This field is the threshold to start one compensation - - - This bit enables the DLL. - - - select input clock of dll for ad slice - - - This bit write 1 to clear ad slice - - - This bit is used to enable automatic compensation when all bank auto refresh. - - - This bit is used to start compensation one time. - - - This bit enables the DLL compensation. - - - This bit enables DLL automatically clear when in low power state - - - This field is to reset DLL - - - - - This field is set if DLL error happens - - - This field indicates DLL is locked or not - - - This fields show the state of DLL FSM - - - This bit indicates ad slice 0 cpst is in IDLE status. - - - This field indicate the count of delay cells for one clk_dmc cycle - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field controls delay value of CEN output delay line - - - This field controls delay value of CLK output delay line - - - - - This field controls delay value of D3 output delay line - - - This field controls delay value of D2 output delay line - - - This field controls delay value of D1 output delay line - - - This field controls delay value of D0 output delay line - - - - - This field controls delay value of D7 output delay line - - - This field controls delay value of D6 output delay line - - - This field controls delay value of D5 output delay line - - - This field controls delay value of D4 output delay line - - - - - This field controls delay value of D3 input delay line - - - This field controls delay value of D2 input delay line - - - This field controls delay value of D1 input delay line - - - This field controls delay value of D0 input delay line - - - - - This field controls delay value of D7 input delay line - - - This field controls delay value of D6 input delay line - - - This field controls delay value of D5 input delay line - - - This field controls delay value of D4 input delay line - - - - - This field controls delay value of DQS input delay line - - - This field controls delay value of DQM input delay line - - - This field controls delay value of DQS output delay line - - - - - dll max count for frequency set 3 - - - dll max count for frequency set 2 - - - dll max count for frequency set 1 - - - dll max count for frequency set 0 - - - - - dll min count for frequency set 3 - - - dll min count for frequency set 2 - - - dll min count for frequency set 1 - - - dll min count for frequency set 0 - - - - - This field controls IO source of CS -0:from psram internal logic -1:from register - - - This field controls IO source of CLK -0:from psram internal logic -1:from register - - - This field controls IO source of DQS -0:from psram internal logic -1:from register - - - This field controls IO source of DQM -0:from psram internal logic -1:from register - - - This field controls IO source of D7 -0:from psram internal logic -1:from register - - - This field controls IO source of D6 -0:from psram internal logic -1:from register - - - This field controls IO source of D5 -0:from psram internal logic -1:from register - - - This field controls IO source of D4 -0:from psram internal logic -1:from register - - - This field controls IO source of D3 -0:from psram internal logic -1:from register - - - This field controls IO source of D2 -0:from psram internal logic -1:from register - - - This field controls IO source of D1 -0:from psram internal logic -1:from register - - - This field controls IO source of D0 -0:from psram internal logic -1:from register - - - - - This field controls IO source of CS ie -0:from psram internal logic -1:from register - - - This field controls IO source of CLK ie -0:from psram internal logic -1:from register - - - This field controls IO source of DQS ie -0:from psram internal logic -1:from register - - - This field controls IO source of DQM ie -0:from psram internal logic -1:from register - - - This field controls IO source of D7 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D6 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D5 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D4 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D3 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D2 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D1 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D0 ie -0:from psram internal logic -1:from register - - - - - This field controls IO source of CS oe -0:from psram internal logic -1:from register - - - This field controls IO source of CLK oe -0:from psram internal logic -1:from register - - - This field controls IO source of DQS oe -0:from psram internal logic -1:from register - - - This field controls IO source of DQM oe -0:from psram internal logic -1:from register - - - This field controls IO source of D7 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D6 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D5 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D4 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D3 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D2 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D1 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D0 oe -0:from psram internal logic -1:from register - - - - - This field set value of CEN IO output - - - This field set value of CLK IO output - - - This field set value of DQS IO output - - - This field set value of DQM IO output - - - This field set value of D7 IO output - - - This field set value of D6 IO output - - - This field set value of D5 IO output - - - This field set value of D4 IO output - - - This field set value of D3 IO output - - - This field set value of D2 IO output - - - This field set value of D1 IO output - - - This field set value of D0 IO output - - - - - not use - - This field indicates the cycles to wait the DLL lock internal signals - - - This bit use to clear dll error automaticly - - - This field is the sum of the delay cells from phase1 to phase2. - - - This field is the threshold to start one compensation - - - This bit enables the DLL. - - - select input clock of dll for ad slice - - - This bit write 1 to clear ad slice - - - This bit is used to enable automatic compensation when all bank auto refresh. - - - This bit is used to start compensation one time. - - - This bit enables the DLL compensation. - - - This bit enables DLL automatically clear when in low power state - - - This field is to reset DLL - - - - not use - - This field is set if DLL error happens - - - This field indicates DLL is locked or not - - - This fields show the state of DLL FSM - - - This bit indicates ad slice 0 cpst is in IDLE status. - - - This field indicate the count of delay cells for one clk_dmc cycle - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field enables the delay line to be compensated automatically by DLL - - - This field enables to plus or to minus the offset value when DLL CPST, -0: Plus offset -1: Minus offset - - - This fields are used to set the offset quarter delay value of DLL CPST - - - This field indicate the quarter count of delay - - - This field controls quarter delay value of delay line - - - This fields are used to set the offset delay value of DLL CPST - - - This field indicate the raw count of delay - - - This field controls delay value of delay line - - - - - This field controls delay value of CEN output delay line - - - This field controls delay value of CLK output delay line - - - - - This field controls delay value of D3 output delay line - - - This field controls delay value of D2 output delay line - - - This field controls delay value of D1 output delay line - - - This field controls delay value of D0 output delay line - - - - - This field controls delay value of D7 output delay line - - - This field controls delay value of D6 output delay line - - - This field controls delay value of D5 output delay line - - - This field controls delay value of D4 output delay line - - - - - This field controls delay value of D3 input delay line - - - This field controls delay value of D2 input delay line - - - This field controls delay value of D1 input delay line - - - This field controls delay value of D0 input delay line - - - - - This field controls delay value of D7 input delay line - - - This field controls delay value of D6 input delay line - - - This field controls delay value of D5 input delay line - - - This field controls delay value of D4 input delay line - - - - - This field controls delay value of DQS input delay line - - - This field controls delay value of DQM input delay line - - - This field controls delay value of DQS output delay line - - - - not use - - dll max count for frequency set 3 - - - dll max count for frequency set 2 - - - dll max count for frequency set 1 - - - dll max count for frequency set 0 - - - - - dll min count for frequency set 3 - - - dll min count for frequency set 2 - - - dll min count for frequency set 1 - - - dll min count for frequency set 0 - - - - - This field controls IO source of CS -0:from psram internal logic -1:from register - - - This field controls IO source of CLK -0:from psram internal logic -1:from register - - - This field controls IO source of DQS -0:from psram internal logic -1:from register - - - This field controls IO source of DQM -0:from psram internal logic -1:from register - - - This field controls IO source of D7 -0:from psram internal logic -1:from register - - - This field controls IO source of D6 -0:from psram internal logic -1:from register - - - This field controls IO source of D5 -0:from psram internal logic -1:from register - - - This field controls IO source of D4 -0:from psram internal logic -1:from register - - - This field controls IO source of D3 -0:from psram internal logic -1:from register - - - This field controls IO source of D2 -0:from psram internal logic -1:from register - - - This field controls IO source of D1 -0:from psram internal logic -1:from register - - - This field controls IO source of D0 -0:from psram internal logic -1:from register - - - - - This field controls IO source of CS ie -0:from psram internal logic -1:from register - - - This field controls IO source of CLK ie -0:from psram internal logic -1:from register - - - This field controls IO source of DQS ie -0:from psram internal logic -1:from register - - - This field controls IO source of DQM ie -0:from psram internal logic -1:from register - - - This field controls IO source of D7 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D6 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D5 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D4 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D3 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D2 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D1 ie -0:from psram internal logic -1:from register - - - This field controls IO source of D0 ie -0:from psram internal logic -1:from register - - - - - This field controls IO source of CS oe -0:from psram internal logic -1:from register - - - This field controls IO source of CLK oe -0:from psram internal logic -1:from register - - - This field controls IO source of DQS oe -0:from psram internal logic -1:from register - - - This field controls IO source of DQM oe -0:from psram internal logic -1:from register - - - This field controls IO source of D7 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D6 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D5 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D4 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D3 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D2 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D1 oe -0:from psram internal logic -1:from register - - - This field controls IO source of D0 oe -0:from psram internal logic -1:from register - - - - - This field set value of CEN IO output - - - This field set value of CLK IO output - - - This field set value of DQS IO output - - - This field set value of DQM IO output - - - This field set value of D7 IO output - - - This field set value of D6 IO output - - - This field set value of D5 IO output - - - This field set value of D4 IO output - - - This field set value of D3 IO output - - - This field set value of D2 IO output - - - This field set value of D1 IO output - - - This field set value of D0 IO output - - - - - - This field use to select clkdmem_out -0:clkdmem_out invert -1:clkdmem_out - - - - - This field use to select f0/f1/f2/f3 register - - - - - This field use to select dqs ie delay cycle - - - - - This field use to select dqs oe delay cycle - - - - - This field use to select dqs out delay cycle - - - - - This field use to select dqs gate delay cycle - - - - - This field use to select data ie delay cycle - - - - - This field use to select data oe delay cycle - - - - - This field use to select dqs ie delay cycle - - - - - This field use to select dqs oe delay cycle - - - - - This field use to select dqs out delay cycle - - - - - This field use to select dqs gate delay cycle - - - - - This field use to select data ie delay cycle - - - - - This field use to select data oe delay cycle - - - - - This field use to select dqs ie delay cycle - - - - - This field use to select dqs oe delay cycle - - - - - This field use to select dqs out delay cycle - - - - - This field use to select dqs gate delay cycle - - - - - This field use to select data ie delay cycle - - - - - This field use to select data oe delay cycle - - - - - This field use to select dqs ie delay cycle - - - - - This field use to select dqs oe delay cycle - - - - - This field use to select dqs out delay cycle - - - - - This field use to select dqs gate delay cycle - - - - - This field use to select data ie delay cycle - - - - - This field use to select data oe delay cycle - - - - - This field use to select dll in saturate mode - - - This field use to select dll in half mode - - - This field use to select dll in x1 or x2 clk mode - - - - - dll counts setting for fast lock - - - indicate the count of dll state - - - This field is used to configure DLL searching start value - - - - - This field use to select dll in saturate mode - - - This field use to select dll in half mode - - - This field use to select dll in x1 or x2 clk mode - - - - - dll counts setting for fast lock - - - indicate the count of dll state - - - This field is used to configure DLL searching start value - - - - - This field use to select dll in saturate mode - - - This field use to select dll in half mode - - - This field use to select dll in x1 or x2 clk mode - - - - - dll counts setting for fast lock - - - indicate the count of dll state - - - This field is used to configure DLL searching start value - - - - - This field use to select dll in saturate mode - - - This field use to select dll in half mode - - - This field use to select dll in x1 or x2 clk mode - - - - - dll counts setting for fast lock - - - indicate the count of dll state - - - This field is used to configure DLL searching start value - - - - - - This field use to set psram memory burst - - - - - This field use to set rcd timing - - - - - This field use to set rddata_en timing - - - - - This field use to set phywrlat timing - - - - - This field use to set cph_wr timing - - - - - This field use to set cph_rd_optm timing - - - This field use to set cph_rd timing - - - - - This field use to set cmd data oe extend cycle - - - This field use to set wdata oe extend cycle - - - - - This field use to set dqs oe extend cycle - - - - - This field use to set xphs timing - - - - - This field use to set rddata valid sync cycle - - - - - This field use to set rddata late cycle - - - - - This field use to set rddata early cycle - - - - - This field use to set winbond reset rp cycle - - - This field use to set winbond reset rh cycle - - - - - not use - - This field use to enable dmc read gate training - - - This field use to enable phy read gate training - - - This field use to enable dmc read data eye training - - - This field use to enable phy read data eye training - - - This field use to enable dmc write training - - - This field use to enable phy write training - - - This field use to define type3 max number of cycles of idle time on DFI control - - - This field use to define type2 max number of cycles of idle time on DFI control - - - This field use to define type1 max number of cycles of idle time on DFI control - - - This field use to define type0 max number of cycles of idle time on DFI control - - - This field use to select phyupd type - - - This field use to enable phy-initiated update - - - - - record read memory register data enable - - - - read memory register data0 - - - read memory register data1 - - - - - ads1 read command send int enable - - - ads1 write command send int enable - - - ads1 mr read command send int enable - - - ads1 mr write command send int enable - - - ads1 reset command send int enable - - - ads0 read command send int enable - - - ads0 write command send int enable - - - ads0 mr read command send int enable - - - ads0 mr write command send int enable - - - ads0 reset command send int enable - - - ads1 rddata timeout int enable - - - ads0 rddata timeout int enable - - - ads1 dll unlock int enable - - - ads0 dll unlock int enable - - - - - ads1 read command send int clear - - - ads1 write command send int clear - - - ads1 mr read command send int clear - - - ads1 mr write command send int clear - - - ads1 reset command send int clear - - - ads0 read command send int clear - - - ads0 write command send int clear - - - ads0 mr read command send int clear - - - ads0 mr write command send int clear - - - ads0 reset command send int clear - - - ads1 rddata timeout int clear - - - ads0 rddata timeout int clear - - - ads1 dll unlock int clear - - - ads0 dll unlock int clear - - - - - ads1 read command send int status - - - ads1 write command send int status - - - ads1 mr read command send int status - - - ads1 mr write command send int status - - - ads1 reset command send int status - - - ads0 read command send int status - - - ads0 write command send int status - - - ads0 mr read command send int status - - - ads0 mr write command send int status - - - ads0 reset command send int status - - - ads1 rddata timeout int status - - - ads0 rddata timeout int status - - - ads1 dll unlock int status - - - ads0 dll unlock int status - - - - - ads1 dll unlock cnt clear - - - ads0 dll unlock cnt clear - - - - - ads0 dll unlock cnt overflow status - - - ads0 dll unlock cnt value - - - - - ads1 dll unlock cnt overflow status - - - ads1 dll unlock cnt value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Interrupt flag Register0 - - - Interrupt flag Register0 - - - Interrupt mask Register0 - - - Interrupt mask Register1 - - - 涓柇灞忚斀缃1瀵勫瓨鍣0 - - - 涓柇灞忚斀缃1瀵勫瓨鍣1 - - - 涓柇灞忚斀娓0瀵勫瓨鍣0 - - - 涓柇灞忚斀娓0瀵勫瓨鍣1 - - - 鍏ㄥ眬涓柇灞忚斀瀵勫瓨鍣 - - Global interrupt enable BIT -0锛欼nterrupt is decided by corresponding mask bit -1锛歁aks all Interrupt - - - - 涓柇閫夋嫨瀵勫瓨鍣0 - - - 涓柇閫夋嫨瀵勫瓨鍣1 - - - - IRQ涓柇鐘舵佸瘎瀛樺櫒 - - - IRQ涓柇鐘舵佸瘎瀛樺櫒 - - - IRQ涓柇婧愬瘎瀛樺櫒 - - IRQ interrupt source code -0000000锛欼RQ0 -0000001锛欼RQ1 -0000010锛欼RQ2 -鈥︹ -0111111锛欼RQ63 - - - - IRQ涓柇鎺у埗瀵勫瓨鍣 - - Clear interrupt status bit -0锛歯o operation -1锛歝lear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low - - - - FIQ涓柇鐘舵佸瘎瀛樺櫒 - - - FIQ涓柇鐘舵佸瘎瀛樺櫒 - - - FIQ涓柇婧愬瘎瀛樺櫒 - - fiq interrupt source code -0000000锛欶IQ0 -0000001锛欶IQ1 -0000010锛欶IQ2 -鈥︹ -0111111锛欶IQ63 - - - - FIQ涓柇鎺у埗瀵勫瓨鍣 - - Clear interrupt status bit -0锛歯o operation -1锛歝lear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - 涓柇浼樺厛绾ч厤缃瘎瀛樺櫒 - - Interrupt prio -0锛欼nterrupt prio 0 -1锛欼nterrupt prio 1 -鈥︹ -7锛欼nterrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - - - - - - - general used register security visit enable -0锛歴ecurity -1锛歶nsecurity - - - response error stop function enable -0锛歟nable -1锛歞isable - - - the number of outstanding that can be send out -0: 2 -1: 3 -2: 4 - - - multe-channel transport priority mode control -0: there is no priority in the channels, using polling to DMA data -1: smaller channel number has high-priority.high-priority move data before low-priority channels - - - interrupt control bit -0: no interruption occurs when all logical channels finish -1: interruption occurs when all logical channels finish - - - the control bit of logical channel transport finish -0: don't stop all the channel,or automatically clear after setting -1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared - - - - - in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. - - - - - stop status -0: not finish -1: finish - - - the channel number of the final transmission -0000: channel 0 just finished the transmission -0001: channel 1 just finished the transmission -0010: channel 2 just finished the transmission -鈥︹ -1011: channel 11 just finished the transmission -others: nonentity - - - - - 閫昏緫閫氶亾浼犺緭鍋滄涓柇鐘舵佷綅 -0锛氶昏緫閫氶亾浼犺緭鍋滄涓柇鏈骇鐢 -1锛氶昏緫閫氶亾浼犺緭鍋滄浜х敓涓 - - - channel 11 interrupts state -0: the channel 11 has not been interrupted, or the interrupt bit has been cleared -1: channel 11 is interrupted - - - channel 10 interrupts state -0: the channel 10 has not been interrupted, or the interrupt bit has been cleared -1: channel 10 is interrupted - - - channel 9 interrupts state -0: the channel 9 has not been interrupted, or the interrupt bit has been cleared -1: channel 9 is interrupted - - - channel 8 interrupts state -0: the channel 8 has not been interrupted, or the interrupt bit has been cleared -1: channel 8 is interrupted - - - channel 7 interrupts state -0: the channel 7 has not been interrupted, or the interrupt bit has been cleared -1: channel 7 is interrupted - - - channel 6 interrupts state -0: the channel 6 has not been interrupted, or the interrupt bit has been cleared -1: channel 6 is interrupted - - - channel 5 interrupts state -0: the channel 5 has not been interrupted, or the interrupt bit has been cleared -1: channel 5 is interrupted - - - channel 4 interrupts state -0: the channel 4 has not been interrupted, or the interrupt bit has been cleared -1: channel 4 is interrupted - - - channel 3 interrupts state -0: the channel 3 has not been interrupted, or the interrupt bit has been cleared -1: channel 3 is interrupted - - - channel 2 interrupts state -0: the channel 2 has not been interrupted, or the interrupt bit has been cleared -1: channel 2 is interrupted - - - channel 1 interrupts state -0: the channel 1 has not been interrupted, or the interrupt bit has been cleared -1: channel 1 is interrupted - - - channel 0 interrupts state -0: the channel 0 has not been interrupted, or the interrupt bit has been cleared -1: channel 0 is interrupted - - - - - state of IRQ 23 generate requests of moving data -0: IRQ 23 does not generate requests of moving data -1: IRQ 23 generate requests of moving data - - - state of IRQ 22 generate requests of moving data -0: IRQ 22 does not generate requests of moving data -1: IRQ 22 generate requests of moving data - - - state of IRQ 21 generate requests of moving data -0: IRQ 21 does not generate requests of moving data -1: IRQ 21 generate requests of moving data - - - state of IRQ 20 generate requests of moving data -0: IRQ 20 does not generate requests of moving data -1: IRQ 20 generate requests of moving data - - - state of IRQ 19 generate requests of moving data -0: IRQ 19 does not generate requests of moving data -1: IRQ 19 generate requests of moving data - - - state of IRQ 18 generate requests of moving data -0: IRQ 18 does not generate requests of moving data -1: IRQ 18 generate requests of moving data - - - state of IRQ 17 generate requests of moving data -0: IRQ 17 does not generate requests of moving data -1: IRQ 17 generate requests of moving data - - - state of IRQ 16 generate requests of moving data -0: IRQ 16 does not generate requests of moving data -1: IRQ 16 generate requests of moving data - - - state of IRQ 15 generate requests of moving data -0: IRQ 15 does not generate requests of moving data -1: IRQ 15 generate requests of moving data - - - state of IRQ 14 generate requests of moving data -0: IRQ 14 does not generate requests of moving data -1: IRQ 14 generate requests of moving data - - - state of IRQ 13 generate requests of moving data -0: IRQ 13 does not generate requests of moving data -1: IRQ 13 generate requests of moving data - - - state of IRQ 12 generate requests of moving data -0: IRQ 12 does not generate requests of moving data -1: IRQ 12 generate requests of moving data - - - state of IRQ 11 generate requests of moving data -0: IRQ 11 does not generate requests of moving data -1: IRQ 11 generate requests of moving data - - - state of IRQ 10 generate requests of moving data -0: IRQ 10 does not generate requests of moving data -1: IRQ 10 generate requests of moving data - - - state of IRQ 9 generate requests of moving data -0: IRQ 9 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 8 generate requests of moving data -0: IRQ 8 does not generate requests of moving data -1: IRQ 8 generate requests of moving data - - - state of IRQ 7 generate requests of moving data -0: IRQ 7 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 6 generate requests of moving data -0: IRQ 6 does not generate requests of moving data -1: IRQ 6 generate requests of moving data - - - state of IRQ 5 generate requests of moving data -0: IRQ 5 does not generate requests of moving data -1: IRQ 5 generate requests of moving data - - - state of IRQ 4 generate requests of moving data -0: IRQ 4 does not generate requests of moving data -1: IRQ 4 generate requests of moving data - - - state of IRQ 3 generate requests of moving data -0: IRQ 3 does not generate requests of moving data -1: IRQ 3 generate requests of moving data - - - state of IRQ 2 generate requests of moving data -0: IRQ 2 does not generate requests of moving data -1: IRQ 2 generate requests of moving data - - - state of IRQ 1 generate requests of moving data -0: IRQ 1 does not generate requests of moving data -1: IRQ 1 generate requests of moving data - - - state of IRQ 0 generate requests of moving data -0: IRQ 0 does not generate requests of moving data -1: IRQ 0 generate requests of moving data - - - - - state of ACK 23 generate requests of moving data -0: ACK 23 does not generate requests of moving data -1: ACK 23 generate requests of moving data - - - state of ACK 22 generate requests of moving data -0: ACK 22 does not generate requests of moving data -1: ACK 22 generate requests of moving data - - - state of ACK 21 generate requests of moving data -0: ACK 21 does not generate requests of moving data -1: ACK 21 generate requests of moving data - - - state of ACK 20 generate requests of moving data -0: ACK 20 does not generate requests of moving data -1: ACK 20 generate requests of moving data - - - state of ACK 19 generate requests of moving data -0: ACK 19 does not generate requests of moving data -1: ACK 19 generate requests of moving data - - - state of ACK 18 generate requests of moving data -0: ACK 18 does not generate requests of moving data -1: ACK 18 generate requests of moving data - - - state of ACK 17 generate requests of moving data -0: ACK 17 does not generate requests of moving data -1: ACK 17 generate requests of moving data - - - state of ACK 16 generate requests of moving data -0: ACK 16 does not generate requests of moving data -1: ACK 16 generate requests of moving data - - - state of ACK 15 generate requests of moving data -0: ACK 15 does not generate requests of moving data -1: ACK 15 generate requests of moving data - - - state of ACK 14 generate requests of moving data -0: ACK 14 does not generate requests of moving data -1: ACK 14 generate requests of moving data - - - state of ACK 13 generate requests of moving data -0: ACK 13 does not generate requests of moving data -1: ACK 13 generate requests of moving data - - - state of ACK 12 generate requests of moving data -0: ACK 12 does not generate requests of moving data -1: ACK 12 generate requests of moving data - - - state of ACK 11 generate requests of moving data -0: ACK 11 does not generate requests of moving data -1: ACK 11 generate requests of moving data - - - state of ACK 10 generate requests of moving data -0: ACK 10 does not generate requests of moving data -1: ACK 10 generate requests of moving data - - - state of ACK 9 generate requests of moving data -0: ACK 9 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 8 generate requests of moving data -0: ACK 8 does not generate requests of moving data -1: ACK 8 generate requests of moving data - - - state of ACK 7 generate requests of moving data -0: ACK 7 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 6 generate requests of moving data -0: ACK 6 does not generate requests of moving data -1: ACK 6 generate requests of moving data - - - state of ACK 5 generate requests of moving data -0: ACK 5 does not generate requests of moving data -1: ACK 5 generate requests of moving data - - - state of ACK 4 generate requests of moving data -0: ACK 4 does not generate requests of moving data -1: ACK 4 generate requests of moving data - - - state of ACK 3 generate requests of moving data -0: ACK 3 does not generate requests of moving data -1: ACK 3 generate requests of moving data - - - state of ACK 2 generate requests of moving data -0: ACK 2 does not generate requests of moving data -1: ACK 2 generate requests of moving data - - - state of ACK 1 generate requests of moving data -0: ACK 1 does not generate requests of moving data -1: ACK 1 generate requests of moving data - - - state of ACK 0 generate requests of moving data -0: ACK 0 does not generate requests of moving data -1: ACK 0 generate requests of moving data - - - - - REQ 7鎼暟璇锋眰鐘舵 -000锛歊EQ 7鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 7浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 7浜х敓7娆℃惉鏁拌姹 - - - REQ 6鎼暟璇锋眰鐘舵 -000锛歊EQ 6鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 6浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 6浜х敓7娆℃惉鏁拌姹 - - - REQ 5鎼暟璇锋眰鐘舵 -000锛歊EQ 5鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 5浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 5浜х敓7娆℃惉鏁拌姹 - - - REQ 4鎼暟璇锋眰鐘舵 -000锛歊EQ 4鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 4浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 4浜х敓7娆℃惉鏁拌姹 - - - REQ 3鎼暟璇锋眰鐘舵 -000锛歊EQ 3鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 3浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 3浜х敓7娆℃惉鏁拌姹 - - - REQ 2鎼暟璇锋眰鐘舵 -000锛歊EQ 2鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 2浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 2浜х敓7娆℃惉鏁拌姹 - - - REQ 1鎼暟璇锋眰鐘舵 -000锛歊EQ 1鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 1浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 1浜х敓7娆℃惉鏁拌姹 - - - REQ 0鎼暟璇锋眰鐘舵 -000锛歊EQ 0鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 0浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 0浜х敓7娆℃惉鏁拌姹 - - - - - REQ 11鎼暟璇锋眰鐘舵 -000锛歊EQ 11鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 11浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 11浜х敓7娆℃惉鏁拌姹 - - - REQ 10鎼暟璇锋眰鐘舵 -000锛歊EQ 10鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 10浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 10浜х敓7娆℃惉鏁拌姹 - - - REQ 9鎼暟璇锋眰鐘舵 -000锛歊EQ 9鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 9浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 9浜х敓7娆℃惉鏁拌姹 - - - REQ 0鎼暟璇锋眰鐘舵 -000锛歊EQ 8鏈骇鐢熸惉鏁拌姹 -001锛歊EQ 8浜х敓1娆℃惉鏁拌姹 -鈥︹ -111锛歊EQ 8浜х敓7娆℃惉鏁拌姹 - - - - - channel 11 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 10 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 9 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 8 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 7 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 6 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 5 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 4 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 3 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 2 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 1 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 0 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0锛歞isable -1锛歟nable - - - security visit -0锛歴ecurity -1锛歶nsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -鈥︹ -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -鈥︹ -01111: IRQ15 trigger transmission -鈥︹ -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - response error interrupt flag -0锛歶nset -1锛歴et - - - response error status -0锛歶nset -1锛歴et - - - data linked list is paused -0: not paused -1: paused - - - the linked list is completed -0: not completed -1: completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - scatter-gather pause - - - the number of scatter-gather transfers completed -0x0000: 0 -鈥︹ -0xFFFF: 65535 times - - - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -鈥︹ -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - scatter-gather function enable -0: disable -1: enable - - - - AXIDMA 鍚勯氶亾杩愯浣嶇疆浣嶅瘎瀛樺櫒 - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - AXIDMA 鍚勯氶亾杩愯浣嶆竻闄ゅ瘎瀛樺櫒 - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - - - - F8 妯″潡涓婅閰嶇疆瀵勫瓨鍣 - - F8绠楁硶绫诲瀷鍜屽彧鍋氭惉鏁伴夋嫨锛 -000锛氬彧鎼暟锛屼笉鍋氬姞瑙ｅ瘑 -001锛欰ES鍔犺В瀵嗭紝骞舵惉鏁 -010锛歴now3G鍔犺В瀵嗭紝骞舵惉鏁 -011锛歾uc鍔犺В瀵嗭紝骞舵惉鏁 -100锛欿asumi鍔犺В瀵嗭紝骞舵惉鏁 -101-111锛歊eversed - - - F8绠楁硶涓柇浣胯兘浣 -0锛欶8 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝涓嶄骇鐢熶腑鏂紱 -1锛欶8 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝浜х敓涓柇 - - - F8绠楁硶鍚姩鎺у埗浣 -0锛氫笉鍚姩F8 绠楁硶锛屾垨瀹屾垚鍚庤嚜鍔ㄦ竻闆讹紱 -1锛氬惎鍔‵8绠楁硶 - - - - F8涓婅group棣栧湴鍧瀵勫瓨鍣 - - - F8涓婅group涓暟瀵勫瓨鍣 - - - F8涓婅鐘舵佸瘎瀛樺櫒 - - 0锛欶8绠楁硶/鎼暟锛屾湭瀹屾垚鎴栨湭寮濮 -1锛欶8绠楁硶/鎼暟锛屽凡瀹屾垚 - - - - F8 妯″潡涓嬭閰嶇疆瀵勫瓨鍣 - - F8绠楁硶绫诲瀷鍜屽彧鍋氭惉鏁伴夋嫨锛 -000锛氬彧鎼暟锛屼笉鍋氬姞瑙ｅ瘑 -001锛欰ES鍔犺В瀵嗭紝骞舵惉鏁 -010锛歴now3G鍔犺В瀵嗭紝骞舵惉鏁 -011锛歾uc鍔犺В瀵嗭紝骞舵惉鏁 -100锛欿asumi鍔犺В瀵嗭紝骞舵惉鏁 -101-111锛歊eversed - - - F8绠楁硶涓柇浣胯兘浣 -0锛欶8 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝涓嶄骇鐢熶腑鏂紱 -1锛欶8 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝浜х敓涓柇 - - - F8绠楁硶鍚姩鎺у埗浣 -0锛氫笉鍚姩F8 绠楁硶锛屾垨瀹屾垚鍚庤嚜鍔ㄦ竻闆讹紱 -1锛氬惎鍔‵8绠楁硶 - - - - F8涓嬭group棣栧湴鍧瀵勫瓨鍣 - - - F8涓嬭group涓暟瀵勫瓨鍣 - - - F8涓嬭鐘舵佸瘎瀛樺櫒 - - 0锛欶8绠楁硶/鎼暟锛屾湭瀹屾垚鎴栨湭寮濮 -1锛欶8绠楁硶/鎼暟锛屽凡瀹屾垚 - - - - F9閰嶇疆瀵勫瓨鍣 - - AXI鍐檕utstanding鑳藉姏璁剧疆,涓嶈兘閰嶇疆涓2鈥榖11 - - - AXI璇籵utstanding鑳藉姏璁剧疆,涓嶈兘閰嶇疆涓2鈥榖11 - - - F9绠楁硶绫诲瀷閫夋嫨锛 -00锛欰ES瀹屾暣鎬х畻娉 -01锛欰ES瀹屾暣鎬х畻娉 -10锛歴now3G瀹屾暣鎬х畻娉 -11锛歾uc瀹屾暣鎬х畻娉 - - - F9绠楁硶涓柇浣胯兘浣 -0锛欶9 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝涓嶄骇鐢熶腑鏂紱 -1锛欶9 绠楁硶/鎼暟鍦ㄦ暣涓鍧梘roup缁撴潫鍚庯紝浜х敓涓柇 - - - F9绠楁硶鍚姩鎺у埗浣 -0锛氫笉鍚姩F9 绠楁硶锛屾垨瀹屾垚鍚庤嚜鍔ㄦ竻闆讹紱 -1锛氬惎鍔‵9绠楁硶 - - - - F9 group棣栧湴鍧瀵勫瓨鍣 - - - F9鐘舵佸瘎瀛樺櫒 - - 0锛欶9鏈畬鎴愭垨鏈紑濮 -1锛欶9宸插畬鎴 - - - - F9 缁撴灉瀵勫瓨鍣 - - - F8 淇′护閰嶇疆瀵勫瓨鍣 - - F8绠楁硶绫诲瀷鍜屽彧鍋氭惉鏁伴夋嫨锛 -000锛氬彧鎼暟锛屼笉鍋氬姞瑙ｅ瘑 -001锛欰ES鍔犺В瀵嗭紝骞舵惉鏁 -010锛歴now3G鍔犺В瀵嗭紝骞舵惉鏁 -011锛歾uc鍔犺В瀵嗭紝骞舵惉鏁 -100锛欿asumi鍔犺В瀵嗭紝骞舵惉鏁 -101-111锛歊eversed - - - F8绠楁硶涓柇浣胯兘浣 -0锛欶8 淇′护鍔犺В瀵嗗崟娆roup瀹屾垚鍚庯紝涓嶄骇鐢熶腑鏂紱 -1锛欶8 淇′护鍔犺В瀵嗗崟娆roup瀹屾垚鍚庯紝浜х敓涓柇 - - - F8绠楁硶鍚姩鎺у埗浣 -0锛氫笉鍚姩F8 绠楁硶锛屾垨瀹屾垚鍚庤嚜鍔ㄦ竻闆讹紱 -1锛氬惎鍔‵8绠楁硶 - - - - F8淇′护group棣栧湴鍧瀵勫瓨鍣 - - - F8淇′护鐘舵佸瘎瀛樺櫒 - - 0锛欶8淇′护鏈畬鎴愭垨鏈紑濮 -1锛欶8淇′护宸插畬鎴 - - - - 鐘舵佹寚绀哄瘎瀛樺櫒 - - 0锛欶9淇′护鏈畬鎴愭垨鏈紑濮 -1锛欶9淇′护宸插畬鎴 - - - 0锛欶8淇′护鏈畬鎴愭垨鏈紑濮 -1锛欶8淇′护宸插畬鎴 - - - 0锛欶8涓婅鏈畬鎴愭垨鏈紑濮 -1锛欶8涓婅宸插畬鎴 - - - 0锛欶8涓嬭鏈畬鎴愭垨鏈紑濮 -1锛欶8涓嬭宸插畬鎴 - - - - - - - - - CP sleep enable register(Enable CP sleep when writing 0x49444c45 to this register, accessed by software only.) - - Enable CP sleep -0: disable -1: enable - - - - AP sleep enable register(Auto cleared by hardware after the system awakup) - - Enable AP sleep(Auto cleared to be 0 when the system is awaked) -0: disable -1: enable - - - - System sleep enable register - - Enable AP sleep -0: disable -1: enable - - - Enable CP sleep -0: disable -1: enable - - - - Slssp counter wrap value. - - - WCN lp enable register - - Default value when the enable bit was disabled. - - - Enable bit of wcn idle_cg -0: disable -1: enable - - - Enable bit of wcn pd_pll -0: disable -1: enable - - - Enable bit of wcn pd_xtal -0: disable -1: enable - - - Enable bit of wcn chip_pd -0: disable -1: enable - - - - Timer sleep enable (writing 0x49444c45 to this register to enable timer sleep.) - - Enable Timer sleep(Auto clear to be 0 when timer is awaked) -0: disable -1: enable - - - - Sleep threshold register - - Threshold register M1: -when the signal pow_on_ack is low, both gsm and lte timer are sleeped, and the difference between current ref_32k counter -and sleep wrap value is larger than this register, system sleep state machine can shift to SLP state. - - - Threshold register M2: -when idct_sys1 and idct_sys2 are set to be1, the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP_PRE state. - - - - Take over TCU enable register - - Enable mode(TCU suspend and this bits are clear to be 0 when take over is started) -00: disbale or already release TCU. -01: take over TCU immediately -10: take over at gsm frame interrupt. -11: no effect. - - - - Restart TCU register - - restart TCU when gsm counter reach this register - - - restart mode(this bits clear to be 0 when TCU restarts) -00: disable -01: restart TCU immediately -10: restart TCU when gsm frame interrupt occurred. -11: restart TCU when gsm framc equal to TC_END_FRAMC. - - - - TIMER wakeup register - - Timer wakeup enable(software accessed only) -0: disable -1: enable - - - - Lp_pu_done register - - TCU restart enable(software accessed only) -Output to the port gsm_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. - - - - gsm frame interrupt enable set register - - gsm_frame_irq enable -1: enable -0: disable - - - - gsm frame interrupt state register - - cleared by writing 1 to correspond bit - - - - LTEM1 frame interrupt enable register - - ltem1_frame3_irq enable -1: enable -0: disable - - - ltem1_frame2_irq enable -1: enable -0: disable - - - ltem1_frame1_irq enable -1: enable -0: disable - - - - LTEM1 interrupt state register - - cleared by writing 1 to correspond bit - - - - LTEM2 frame interrupt enable register - - ltem2_frame3_irq enable -1: enable -0: disable - - - ltem2_frame2_irq enable -1: enable -0: disable - - - ltem2_frame1_irq enable -1: enable -0: disable - - - - LTEM2 interrupt state register - - cleared by writing 1 to correspond bit - - - - IDLE state register - - ltem3 timer state -0: running at 122.88M -1: running at 32K - - - NB timer state -0: running at 61.44M -1: running at 32K - - - H circuit state -0: not work -1: at wok - - - ltem2 timer state -0: running at 122.88M -1: running at 32K - - - ltem1 timer state -0: running at 122.88M -1: running at 32K - - - GSM timer state -0: running at 26M -1: running at 32K - - - SYS state -0: normal working -1: low power mode - - - - H circuit control register - - Runtime of H circuit, the length is 2^h_run_time(number of 32k clocks) - - - Automatic computing mode enable(loop computing until disabled) -0: disable -1: enable - - - Invocation pattern(compute only one time, automatic clear to be 0 when finished.) -0: disable -1: enable - - - - H value register - - The length of sys clock in 2^h_run_time 32k cycles - - - - H value register - - The cycles number of 26M in 2^h_run_time 32k cycles - - - - H value register - - The cycles number of 122.88M in of 2^h_run_time 32k cycles - - - - wakeup enable register - - signal nb_lp_pu_reach wakeup enable -0: disable -1: enable - - - signal gsm_lp_pu_reach wakeup enable -0: disable -1: enable - - - sofware wakeup enable -0: disable -1: enable - - - OSW2 wakeup enable -0: disable -1: enable - - - OSW1 wakeup enable -0: disable -1: enable - - - pad_gpio1 wakeup enable -0: disable -1: enable - - - uart3_irq wakeup enable -0: disable -1: enable - - - pad_uart3_rxd wakeup enable -0: disable -1: enable - - - gpt2_irq wakeup enable -0: disable -1: enable - - - mailbox_irq wakeup enable -0: disable -1: enable - - - gpio2_irq wakeup enable -0: disable -1: enable - - - uart2_irq wakeup enable -0: disable -1: enable - - - pad_uart2_rxd wakeup enable -0: disable -1: enable - - - pmic_irq wakeup enable -0: disable -1: enable - - - usb_irq wakeup enable -0: disable -1: enable - - - pad_uart1_rxd wakeup enable -0: disable -1: enable - - - Uart1_irq wakeup enable -0: disable -1: enable - - - Gpio1_irq wakeup enable -0: disable -1: enable - - - Keyboard wakeup enable -0: disable -1: enable - - - gpt1_irq wakeup enable -0: disable -1: enable - - - Pad_gpio6 wakeup enable -0: disable -1: enable - - - - wakeup state(can be cleared by writing 1 to correspond bits) - - pow_dfe_ack state -0: pow_dfe_ack is 0 when system exit IDLE -1: pow_dfe_ack is 1 when system exit IDLE - - - Threshold M1 state -1: pow_ack not meet threshold M1 or pow_ack not feedback in sleep period -0: meet threshold M1 - - - pow_ack state -0: pow_ack is 0 when system exit IDLE -1: pow_ack is 1 when system exit IDLE - - - system exit idle state -0: sys not enter idle -1: sys enter idle state - - - IDLE sleep wakeup state -0: awaked before the sleep warp time -1: awaked at the sleep warp time - - - Signal nb_lp_pu_reach wakeup state -0: this signal not generated -1: this signal generated - - - Signal gsm_lp_pu_reach wakeup state -0: this signal not generated -1: this signal generated - - - software wakeup state -0: software wakeupup signal not generated -1: software wakeupup system. - - - OSW2 wakeup state -0: this signal not generated -1: this signal generated - - - OSW1 wakeup state -0: this signal not generated -1: this signal generated - - - AWK15 wakeup state -0: this signal not generated -1: this signal generated - - - AWK14 wakeup state -0: this signal not generated -1: this signal generated - - - AWK13 wakeup state -0: this signal not generated -1: this signal generated - - - AWK12 wakeup state -0: this signal not generated -1: this signal generated - - - AWk11 wakeup state -0: this signal not generated -1: this signal generated - - - AWk10 wakeup state -0: this signal not generated -1: this signal generated - - - AWK9 wakeup state -0: this signal not generated -1: this signal generated - - - AWK8 wakeup state -0: this signal not generated -1: this signal generated - - - AWK7 wakeup state -0: this signal not generated -1: this signal generated - - - AWK6 wakeup state -0: this signal not generated -1: this signal generated - - - AWK5 wakeup state -0: this signal not generated -1: this signal generated - - - AWK4 wakeup state -0: this signal not generated -1: this signal generated - - - AWk3 wakeup state -0: this signal not generated -1: this signal generated - - - AWk2 wakeup state -0: this signal not generated -1: this signal generated - - - AWK1 wakeup state -0: this signal not generated -1: this signal generated - - - AWK0 wakeup state -0: this signal not generated -1: this signal generated - - - - software wakeup signal - - 0: not effect -1: wakeup system -(accessed by software only, this bit shold clear bu software when system is awaked.) - - - - OSW1 TIMER enable - - 1: enable -0: disable - - - osw1 wrap value - - - - OSW1 Timer current value - - - IDLE GSM frame register - - - IDLE LTEM1frame register - - Number of frames ltem1 sleeped. - - - Number of sub-frames ltem1 sleeped. - - - - IDLE LTEM2 frame register - - Number of frames ltem2 sleeped - - - Number of sub-frames ltem2 sleeped. - - - - IDLE LTE frame length register - - LTE sleep frame length, suggest keep the default value. - - - - IDLE LTE sub-frame length register - - LTE sleep sub-frame length, suggest keep -the default value. - - - - signal of low power related enable register - - Idle_cg_en enable -1: enable. -0: disable. - - - Pd_pll_en enable -1: enable -0: disable - - - pd_xtal_en enable -1: enable. -0: disable. - - - chip_pd_en enable -1: enable. -0: disable. - - - - low power related time control register - - The time from enable clock to obtain clock - - - The time of PLL from power saving state to output normal clock. - - - The time of OSC circuit from power saving -state to normal state. - - - The time of PMIC boost stabilization. - - - - 32K reference counter - - - cp interrupt enable register - - em_latch_irq enable -1: enable -0: disable - - - cpu_latch_irq enable -1: enable -0: disable - - - rtc_latch_irq enable -1: enable -0: disable - - - load_end_irq enable -1: enable -0: disable - - - timer_idle_irq enable -1: enable -0: disable - - - target_irq enable -1: enable -0: disable - - - nb_pu_reach_irq enable -1: enable -0: disable - - - nb_tc_end_irq enable -1: enable -0: disable - - - nb_tc_start_irq enable -1: enable -0: disable - - - sys_awk _irq enable -1: enable -0: disable - - - Timer_awk_irq_enable -1: enable -0: disable - - - gsm_pu_reach_irq enable -1: enable -0: disable - - - gsm_tc_end_irq enable -1: enable -0: disable - - - gsm_tc_start_irq enable -1: enable -0: disable - - - osw1_irq enable -1: enable -0: disable - - - tstamp_irq enable -1: enable -0: disable - - - idle_frame_irq enable -1: enable -0: disable - - - idle_h_irq enable -1: enable -0: disable - - - layout_irq enable -1: enable -0: disable - - - - cp interrupt enable set register - - set cp interrupt enable register when writing 1 to correspond bits. - - - - cp interrupt enable clear register - - clear cp interrupt enable register when writing 1 to correspond bits. - - - - cp interrupt state - - clear interrupt state register when writing 1 to correspond bits. - - - - ap interrupt enable register - - em_latch_irq enable -1: enable -0: disable - - - cpu_latch_irq enable -1: enable -0: disable - - - rtc_latch_irq enable -1: enable -0: disable - - - load_end_irq enable -1: enable -0: disable - - - timer_idle_irq enable -1: enable -0: disable - - - target_irq enable -1: enable -0: disable - - - nb_pu_reach_irq enable -1: enable -0: disable - - - sys_awk _irq enable -1: enable -0: disable - - - Timer_awk_irq_enable -1: enable -0: disable - - - gsm_pu_reach_irq enable -1: enable -0: disable - - - osw2_irq enable -1: enable -0: disable - - - - ap interrupt enable set register - - set ap interrupt enable register when writing 1 to correspond bits. - - - - ap interrupt enable clear register - - clear ap interrupt enable register when writing 1 to correspond bits. - - - - ap interrupt state - - clear ap interrupt state register when writing 1 to correspond bits. - - - - LTEM1 high-level frame number register - - Ltem1 high-level frame number value - - - - - LTE-M1 frame number - - - LTE-M1 sub-frame number - - - - LTE-M1 frame offset register - - frame adjust time -0: adjust at next frame interrupt -1: adjust frame immetiately - - - frame adjust direction -0: postive -1: negative - - - LTE-M1 frame offest value -(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) - - - - LTE-M1 high-level frame read register - - LTE-M1 high-level frame value - - - - LTE-M1 frame read register - - LTE-M1 radio frame value - - - LTE-M1 sub-frame value - - - - LTE-M1 counter - - LTE-M1 counter value - - - - LTE-M1 frame length register - - LTE-M1 frame length - - - - LTE-M1 frame length adjust register - - adjust time -0: adjust immetiately -1: adjust at next ltem frame interrupt - - - LTE-M1 adjuste frame length. -current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. - - - - LTE-M1 radio frame value time stamp register - - LTE-M1 high-level frame value time stamp register - - - - LTE-M1 sub-frame time stamp register - - LTE-M1 frame stamp value - - - - LTE-M1 counter time stamp register - - LTE-M1 stamp counter - - - - LTE-M2 high-level frame register - - LTE-M2 high-level frame value - - - - - LTE-M2 radio frame value - - - LTE-M2 sub-frame value - - - - LTE-M2 frame offset adjust register - - adjust time. -0: adjust at next frame interrupt -1: adjust frame immetiately - - - adjust direction -0: postive -1: negative - - - Frame offest value(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value at the time of frame interrupt genereted. otherwise write b-1 into this register then current frame minus this value at the time of frame interrupt generated.) - - - - LTE-M2 high-level frame read register - - LTE-M2 super read frame value - - - - LTE-M2 frame read register - - LTE-M2 radio frame read value - - - LTE-M2 sub-frame read value - - - - LTE-M counter - - LTE-M counter - - - - LTE-M2 frame length - - LTE-M2 frame length value - - - - LTE-M2 frame length adjust register - - adjust time -0: adjust immetiately -1: adjust at next ltem frame interrupt - - - LTE-M2 adjuste frame length. -current Ltem frame length load the register when write happens,then backed the LFRAML at the time of lte frame interrupt occurred. - - - - LTE-M2 radio frame time stamp register - - LTE-M2 high-level frame time stamp register - - - - LTE-M2 sub-frame time stamp register - - LTE-M2 frame stamp value - - - - LTE-M2 counter time stamp register - - LTE-M2 stamp counter - - - - GSM frame register - - GSM frame value - - - - GSM frame offset adjust register - - adjust direction -0: postive -1: negative - - - frame offest value -(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 into this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) - - - - GSM frame overflow register - - GSM frame overflow value - - - - LTE-M high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - LTE-M frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - LTE-M counter locked register - - LTE-M couner locked value - - - - LTE-M high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - LTE-M frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - LTE-M counter locked register - - LTE-M counter locked value - - - - GSM frame lock register - - GSM frame locked value - - - - GSM counter lock register - - GSM counter locked value - - - - time stamp register - - lock signal -000: ltem1 frame interrupt. -001: ltem2 frame interrupt. -010: gsm frame interrupt. -011: negative of 32k clock. -100: nb frame interrput. -others: gsm frame interrupt. - - - lock way -00: disable lock -01: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. -10: time stamp when lock signal comes after that bit 5 and 4 clear to be 0. -11: time stamp loop - - - 1: time stamp immediately. -0: not effect - - - - current task planning time register - - - task planning time register - - Layoutt register descending unit. -15鈥檋0000: 1 -15鈥檋0001: 2 -15鈥檋0002: 3 -鈥︹ -15鈥檋7fff: 32768 - - - Layout count time selection -0: ltem1 timer -1: ltem2 timer - - - task planning -1: start task planing -0: end timing -(The control bit is clear automatically after the timer is finished, and the software can be clear to bestop counting.) - - - - LTEM1 frame interrupt delay register 1 - - LTE-M1 frame interrupt delay, take ltem1_framc as a reference. - - - - LTEM1 frame interrupt delay register 2 - - LTE-M1 frame interrupt delay, take ltem1_framc as a reference. - - - - LTEM2 frame interrupt delay register 1 - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - LTEM2 frame interrupt delay register 2 - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - sub-frame interrupt enable register - - Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. - - - - TIMER enable register - - GNSS_LTE-M timer enable -0: disable -1: enable - - - NB timer enable -0: disable -1: enable - - - LTE-M timer enable -0: disable -1: enable -(note: this timer is the reference lte timer.) - - - GSM timer enable -0: disable -1: enable - - - LTE-M2 timer enable -0: disable -1: enable - - - LTE-M1 timer enable -0: disable -1: enable - - - - IDLE frame interrupt state register(can be clear by writing 1 to correspond bit) - - GNSS_LTE-M frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - NB frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - reference lte frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - GSM frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - LTE-M2 frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - LTE-M1 frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - - IDLE LTE-M1 frame configuration register - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt frame number -interrupt occurred when current frame reach this register. - - - - IDLE LTE-M2 frame configuration register - - enable(this bit is cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register. - - - - IDLE GSM frame configuration register - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_GSM - - - - IDLE REF_LTE frame configuration register - - - IDLE REF LTE frame enable register - - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - - REF_LTE frame register - - - REF_LTE frame locked register - - - REF_LTE counter locked register - - reference lte counter locked value - - - - REF_32K CONT clocked register - - - REF_LTE counter register - - reference lte counter - - - - GSM frame length - - GSM frame length value - - - - OSW2 configuration register - - 1: enable OSW2 timer -0: disable - - - OSW2 Timing start value - - - - OSW2 counter register - - - IDLE GSM frame interrupt counter setting register - - IDLE GSM frame interrupt generated when GSM frame counter reach GSM_FRAME_GSM and GSM counter equal to this register. - - - - LTEM1 interrupt delay setting register 3 - - LTE-M1 frame interrupt delay, -take ltem1_framc as a reference. - - - - LTEM2 interrupt delay setting register 3 - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - idle time select register - - 1: select pd_xtal, 0: select chip_pd - - - - IDLE time register - - - H value register - - The cycles number of 26M in 2^h_run_time 32k cycles - - - - H value register - - The cycles number of 122.88M in of 2^h_run_time 32k cycles - - - - Take over NB TCU enable register - - Enable mode(NB TCU suspend and this bits are cleared by hardware when take over started) -00: disbale or already release TCU. -01: take over TCU immediately -10: take over at gsm frame interrupt. -11: no effect. - - - - Restart NB TCU register - - restart TCU when gsm counter reach this register - - - restart mode(this bits cleared when TCU restarts) -00: disable -01: restart TCU immediately -10: restart TCU when gsm frame interrupt occurred. -11: restart TCU when gsm framc equal to TC_END_FRAMC. - - - - Nb_lp_pu_done register - - TCU restart enable(accessed by software only.) -Output to the port nb_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. - - - - H value register - - The cycles number of 61.44M in the length of 2^h_run_time 32k cycles - - - - H value register - - The cycles number of 61.44M in the length of 2^h_run_time 32k cycles - - - - IDLE NB frame register - - - NB frame interrupt enable register - - nb_frame_irq enable -1: enable -0: disable - - - - NB frame interrupt state register - - cleared by writing 1 to correspond bit - - - - NB frame register - - NB frame value - - - - NB frame length - - NB frame length value - - - - NB frame offset adjust register - - adjust direction -0: postive -1: negative - - - frame offest value -(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b- 1 to this register then current frame minus this value when frame interrupt occurred.) - - - - NB frame overflow register - - NB frame overflow value - - - - NB frame lock register - - NB frame locked value - - - - NB counter lock register - - NB counter locked value - - - - IDLE NB frame configuration register - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_NB - - - - IDLE NB frame interrupt counter setting register - - IDLE NB frame interrupt generated when NB frame counter reach IDLE_FRAME_NB and NB counter equal to this register. - - - - wakeup enable set register - - set wakeup enable register by writing 1 to correspond bits. - - - - wakeup enable clear register - - clear wakeup enable register by writing 1 to correspond bits. - - - - GSM framc read register - - Read enable register. -This bit should be set first when read the value of GSM counter, then rd_enable bit cleared by hardware after locked the GSM counter. - - - GSM framc - - - - NB framc read register - - Read enable register. -This bit should be set first when read the value of NB counter, then rd_enable bit cleared by hardware after locked the NB counter. - - - NB framc - - - - Eliminate jitter configuration register - - Eliminate jitter delay register - - - Emilinate the jitter from awake signal when writing 1 to correspond bits. - - - - - GGE low power Scheme selection signal -0: use RDA8909 LP Scheme -1: use IDLE module of LP Scheme - - - - - NB low power Scheme selection signal -0: use RDA8909 LP Scheme -1: use IDLE module of LP Scheme - - - - - 1:disbale PLL -0:enable PLL - - - 1:disable PLL -0:enbale PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - - - set corresponding bits of PD_PLL_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - clean corresponding bits of PD_PLL_SW -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit6 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit5 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit4 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit3 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit2 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit1 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit0 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - - - set corresponding bits of PD_PLL_SEL -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - clean corresponding bits of PD_PLL_SEL -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - - - set corresponding bits of IDLE_CG_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - clean corresponding bits of IDLE_CG_SW -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit6 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit5 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit4 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit3 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit2 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit1 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit0 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - - - set corresponding bits of IDLE_CG_SEL -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - clean corresponding bits of IDLE_CG_SEL -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - 1:control the RF_DIG enter in IDLE -0:control the RF_DIG exit to the IDLE - - - - - select the hardware signal or software register to control the RF_DIG enter in or extit to IDLE model. -1:software register(RF_IDLE_ENABLE_SW) -0:hardware signal( pow_on signal invert of IDLE module) - - - - IDLE moduel reserved register 0 - - - IDLE moduel reserved register 1 - - - IDLE moduel reserved register 2 - - - IDLE moduel reserved register 3 - - - IDLE moduel reserved register 4 - - - IDLE moduel reserved register 5 - - - IDLE moduel reserved register 6 - - - IDLE moduel reserved register 7 - - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - - - UART module reset control: -0: reset锛 -1: reset release銆 - - - UART module clock control: -0: disable锛 -1: enable銆 - - - - - PSRAM IO LATCH: -0: release PSRAM PAD -1: no release PSRAM PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after PSRAM initialization when AP wake-up from deep sleep. - - - LPDDR IO LATCH: -0: release LPDDR PAD -1: no release LPDDR PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after LPDDR initialization when AP wake-up from deep sleep. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDLE moduel reserved register 8 - - - IDLE moduel reserved register 9 - - - IDLE moduel reserved register 10 - - - IDLE moduel reserved register 11 - - - - - - - - - - - - - - mon15_sel: -00: select nb_en. -01: select awk_sys_valid. -10: select awake[7]. -11: select target_timer_stat[1]. - - - mon14_sel: -00: select gsm_en. -01: select wcn_chip_pd. -10: select awake[6]. -11: select target_timer_stat[0]. - - - mon13_sel: -00: select wake_timer. -01: select wcn_pd_xtal. -10: select awake[5]. -11: select target_timer_enable. - - - mon12_sel: -00: select timer_en_nb. -01: select wcn_pd_pll. -10: select awake[4]. -11: select nb_frame_int. - - - mon11_sel: -00: select timer_en_gsm. -01: select wcn_idle_cg. -10: select awake[3]. -11: nb_lp_pu_done. - - - mon10_sel: -00: select timer_en_ltem2. -01: select nb_en_sel. -10: select awake[2]. -11: select nb_lp_sf_slowrunning. - - - mon9_sel: -00: select timer_en_ltem1. -01: select gsm_en_sel. -10: select awake[1]. -11: select nb_fint. - - - mon8_sel: -00: select idst_nb_timer. -01: select idle_chip_pd. -10: select awake[0]. -11: select gsm_frame_int. - - - mon7_sel: -00: select idst_gsm_timer -01: select idle_pd_xtal. -10: select awk_self. -11: gsm_lp_pu_done. - - - mon6_sel: -00: select idst_ltem2_timer. -01: select idle_pd_pll. -10: select idst_gsm_ltem_timer. -11: select gsm_lp_sf_slowrunning. - - - mon5_sel: -00: select idst_ltem1_timer. -01: select idle_idle_cg. -10: select awk_gsm_ltem_timner. -11: select gsm_fint. - - - mon4_sel: -00: select idct_nb_timer. -01: select pow_on. -10: select idst_sys. -11: select rstctrl_uart. - - - mon3_sel: -00: select idct_gsm_timer. -01: select idct_sys_valid. -10: select nb_lp_pu_reach. -11: select clken_uart. - - - mon2_sel: -00: select idct_ltem2_timer. -01: select idct_ap. -10: select gsm_lp_pu_reach. -11: select psram_latch_reg. - - - mon1_sel: -00: select idct_ltem1_timer -01: select idct_cp. -10: select osw2_awk -11: select lpddr_latch_reg - - - mon0_sel: -00: select idct_timer. -01: select ltem1_fint. -10: select osw1_awk. -11: select ltem2_fint - - - - set corresponding bits of MON_SEL -0:Invariance of corresponding bits -1:set corresponding bits - - - clear corresponding bits of MON_SEL -0:Invariance of corresponding bits -1:clear corresponding bits - - - Interrupt generated when the reference 32K counter reach to this register value. - - - - 1: disable target timer. -0: enable - - - - The locked value of reference 32K when interrupt generated. - - - - Indicat the state of target timer in 32K clock domain - - - Indicate the state of target timer in 122.88M clock domain - - - - - 0:SLOW_CLK and system clk selected by software bit conrtol -1:SLOW_CLK and system clk select by hareware signal control - - - - - 0:SLOW_CLK selected(between 26M and 32k) by software bit control -1:SLOW_CLK selected(between 26M and 32k) by hareware signal control - - - - - The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. - - - - - change H_VAL's time -1:pd_xtal -0:chip_pd - - - - - 1:tstamp_i[1] -0:tstamp_i[0] - - - 1:perip tstamp -0:inner tstamp - - - 1:tstamp saved -0:nothing - - - - LTE-M framl ref adjust register - - adjust direction -0: postive -1: negative - - - - - LTE-M framl abs adjust register - - adjust direction -0: postive -1: negative - - - - - - - LTE-M framl ref adjust register - - adjust direction -0: postive -1: negative - - - - - LTE-M framl abs adjust register - - adjust direction -0:postive -1:negative - - - - - LTE-M1 LOAD change register - - 0:load_timer from lps -1:TP load - - - - LTE-M2 LOAD change register - - 0:load_timer from lps -1:TP load - - - - sub-frame interrupt enable register - - Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. - - - - sub-frame interrupt enable register - - 1:enable -0:disable - - - 1:enable -0:disable - - - 1:enable -0:disable - - - - GNSS_CAPTURE_LTE-M1 high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS_CAPTURE_LTE-M1 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS_CAPTURE_LTE-M1 counter locked register - - LTE-M couner locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS_CAPTURE_LTE-M1 high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS_CAPTURE_LTE-M1 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS_CAPTURE_LTE-M1 counter locked register - - LTE-M couner locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS_CAPTURE_LTE-M1 high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS_CAPTURE_LTE-M1 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS_CAPTURE_LTE-M1 counter locked register - - LTE-M couner locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS_CAPTURE_LTE-M1 high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS_CAPTURE_LTE-M1 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS_CAPTURE_LTE-M1 counter locked register - - LTE-M couner locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - GNSS CAPTURE LTE-M2 high-level frame lock register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - GNSS CAPTURE LTE-M2 frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - GNSS CAPTURE LTE-M2 counter locked register - - LTE-M counter locked value - - - - LTE-M3 LOAD change register - - - - IDLE LTEM3 frame register - - Number of frames ltem3 sleeped - - - Number of sub-frames ltem3 sleeped. - - - - LTEM3 frame interrupt enable register - - ltem3_frame3_irq enable -1: enable -0: disable - - - ltem3_frame2_irq enable -1: enable -0: disable - - - ltem3_frame1_irq enable -1: enable -0: disable - - - - LTEM3 interrupt state register - - cleared by writing 1 to correspond bit - - - - LTEM3 high-level frame number register - - LTEM3 high-level frame number value - - - - - LTE-M3 frame number - - - LTE-M3 sub-frame number - - - - LTE-M3 frame offset register - - frame adjust time -0: adjust at next frame interrupt -1: adjust frame immetiately - - - frame adjust direction -0: postive -1: negative - - - LTE-M3 frame offest value -(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) - - - - LTE-M3 high-level frame read register - - LTE-M3 high-level frame value - - - - LTE-M3 frame read register - - LTE-M3 radio frame value - - - LTE-M3 sub-frame value - - - - LTE-M3 counter - - LTE-M3 counter value - - - - LTE-M3 frame length register - - LTE-M3 frame length - - - - LTE-M3 frame length adjust register - - adjust time -0: adjust immetiately -1: adjust at next ltem frame interrupt - - - LTE-M3 adjuste frame length. -current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. - - - - LTE-M3 radio frame value time stamp register - - LTE-M3 high-level frame value time stamp register - - - - LTE-M3 sub-frame time stamp register - - LTE-M3 frame stamp value - - - - LTE-M3 counter time stamp register - - LTE-M3 stamp counter - - - - LTE-M framl ref adjust register - - adjust direction -0: postive -1: negative - - - - - LTE-M framl abs adjust register - - adjust direction -0: postive -1: negative - - - - - LTEM3 frame interrupt delay register 1 - - LTE-M3 frame interrupt delay, take ltem2_framc as a reference. - - - - LTEM3 frame interrupt delay register 2 - - LTE-M3 frame interrupt delay, take ltem3_framc as a reference. - - - - LTEM1 interrupt delay setting register 3 - - LTE-M3 frame interrupt delay, -take ltem3_framc as a reference. - - - - sub-frame interrupt enable register - - Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. - - - - LTE-M high-level frame locked register - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - LTE-M frame locked register - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - LTE-M counter locked register - - LTE-M couner locked value - - - - IDLE LTE-M3 frame configuration register - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt frame number -interrupt occurred when current frame reach this register. - - - - - - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗0鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗1鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗2鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗3鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗4鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗5鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗6鏍圭洃鎺т俊鍙烽佸嚭 - - - - - 鐢ㄤ簬閫夋嫨鍚勪釜瀛愮郴缁熶腑鐨勭洃鎺т俊鍙峰苟閫氳繃绗7鏍圭洃鎺т俊鍙烽佸嚭 - - - - - monitor_o[0]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[1]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[2]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[3]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[4]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[5]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[6]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - monitor_o[7]閫夋嫨锛 -3'h0: 瀛愮郴缁0 -3'h1: 瀛愮郴缁1 -3'h2: 瀛愮郴缁2 -3'h3: 瀛愮郴缁3 -3'h4: 瀛愮郴缁4 -3'h5: 瀛愮郴缁5 -3'h6: 瀛愮郴缁6 -3'h7: 瀛愮郴缁7 - - - - - 鐩戞帶浣胯兘 -1锛氫娇鑳界洃鎺 -0锛氫笉浣胯兘鐩戞帶 - - - - - monitor output signal value. - - - - - - - - - power domain shutdown/on controled by hardware signal or sofeware register. - - - sysmail0 interrupt bit set register - - - sysmail0 interrupt clean register - - - sysmail0 interrupt mask register - - - sysmail0 interrupt status register - - - sysmail0 interrupt mask status register - - - - sysmail1 Interrupt generate register - - - sysmail1 interrupt bit set register - - - sysmail1 interrupt clean register - - - sysmail1 interrupt mask register - - - sysmail1 interrupt status register - - - sysmail1 interrupt mask status register - - - - sysmail2 Interrupt generate register - - - sysmail2 interrupt bit set register - - - sysmail2 interrupt clean register - - - sysmail2 interrupt mask register - - - sysmail2 interrupt status register - - - sysmail2 interrupt mask status register - - - - sysmail3 Interrupt generate register - - - sysmail3 interrupt bit set register - - - sysmail3 interrupt clean register - - - sysmail3 interrupt mask register - - - sysmail3 interrupt status register - - - sysmail3 interrupt mask status register - - - - sysmail4 Interrupt generate register - - - sysmail4 interrupt bit set register - - - sysmail4 interrupt clean register - - - sysmail4 interrupt mask register - - - sysmail4 interrupt status register - - - sysmail4 interrupt mask status register - - - - sysmail5 Interrupt generate register - - - sysmail5 interrupt bit set register - - - sysmail5 interrupt clean register - - - sysmail5 interrupt mask register - - - sysmail5 interrupt status register - - - sysmail5 interrupt mask status register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACK鍋忕Щ绱㈠紩 - - ACK鍋忕Щ绱㈠紩 - - - - RI鐨凪CS鍋忕Щ绱㈠紩 - - RI鐨凪CS鍋忕Щ绱㈠紩 - - - - CQI鐨凪CS鍋忕Щ绱㈠紩 - - CQI鐨凪CS鍋忕Щ绱㈠紩 - - - - 鍒濆浼犺緭鍧楀ぇ灏忔暟鎹噺瀵勫瓨鍣 - - PUSCH妯″潡浣胯兘鏃惰〃绀篜USCH浼犺緭鍧楀ぇ灏忥紝鍗充紶杈撳潡CRC娣诲姞鍓嶇殑鏁版嵁閲忥紝鍗曚綅涓篵it - - - - 浼犺緭鍧楀ぇ灏忔暟鎹噺瀵勫瓨鍣 - - PUSCH妯″潡浣胯兘鏃惰〃绀篜USCH浼犺緭鍧楀ぇ灏忥紝鍗充紶杈撳潡CRC娣诲姞鍓嶇殑鏁版嵁閲忥紝鍗曚綅涓篵it - - - - 璋冨埗鏂瑰紡瀵勫瓨鍣 - - 00锛欱PSK -01锛歈PSK -10锛16QAM -11锛64QAM - - - - 鍐椾綑鐗堟湰鍙 - - 鍐椾綑鐗堟湰鍙 - - - - PUSCH鍙婂垵浼燩USCH鍗犵敤鐨勫甫瀹斤紙瀛愯浇娉釜鏁帮級 - - 鍒濅紶PUSCH鍗犵敤鐨勫甫瀹斤紙瀛愯浇娉釜鏁帮級 - - - 褰撳墠PUSCH鍗犵敤鐨勫甫瀹斤紙瀛愯浇娉釜鏁帮級 - - - - PUSCH鍙婂垵浼燩USCH鍗犵敤鐨勭鍙蜂釜鏁 - - RU涓暟 - - - 鍒濅紶PUSCH鍗犵敤绗﹀彿鏁帮細瀵逛簬CAT1/CATM锛 -琛ㄧず1涓瓙甯у崰鐢ㄧ殑PUSCH DATA鐨勭鍙蜂釜 -鏁帮紱瀵逛簬CAT-NB锛岃〃绀1涓猂U鍗犵敤鐨勭鍙蜂釜鏁 - - - 褰撳墠PUSCH鍗犵敤绗﹀彿鏁帮細瀵逛簬CAT1/CATM锛岃〃绀1涓瓙甯у崰鐢ㄧ殑 -PUSCH DATA鐨勭鍙蜂釜鏁帮紱瀵逛簬CAT-NB锛 -琛ㄧず1涓猂U鍗犵敤鐨勭鍙蜂釜鏁 - - - - CQI淇℃伅姣旂壒鏁版嵁瀵勫瓨鍣 - - - CQI淇℃伅姣旂壒鏁版嵁瀵勫瓨鍣 - - - CQI淇℃伅姣旂壒鏁版嵁鍙婃瘮鐗归暱搴﹀瘎瀛樺櫒 - - 缂栫爜鍓岰QI淇℃伅鏈灏忔瘮鐗归暱搴 - - - 缂栫爜鍓岰QI淇℃伅姣旂壒闀垮害锛屾渶澶т负65 - - - 缂栫爜鍓岰QI淇℃伅姣旂壒浣64 - - - - RI淇℃伅姣旂壒鏁版嵁鍙婃瘮鐗归暱搴﹀瘎瀛樺櫒 - - 缂栫爜鍓峈I淇℃伅姣旂壒闀垮害 - - - 缂栫爜鍓峈I淇℃伅 - - - - ACK淇℃伅姣旂壒鏁版嵁鍙婃瘮鐗归暱搴﹀瘎瀛樺櫒 - - 缂栫爜鍓岮CK淇℃伅姣旂壒闀垮害锛屾渶澶т负4 - - - 缂栫爜鍓岮CK淇℃伅 - - - - ACK缂栫爜澶嶇敤缁戝畾閫夋嫨鍙婃壈鐮佸簭鍒楁寚绀哄瘎瀛樺櫒 - - 0锛欶DD鎴朤DD鐨凥ARQ-ACK澶嶇敤妯″紡 -1锛歍DD鐨凥ARQ-ACK缁戝畾妯″紡 - - - TDD HARQ-ACK缁戝畾妯″紡鏃讹紝鎵扮爜搴忓垪鐨勯夋嫨绱㈠紩鍊 - - - - PUCCH鏍煎紡瀵勫瓨鍣 - - PUCCH鏍煎紡 -000~010锛歊ESERVED -011锛氭牸寮2 -100锛氭牸寮2a -101锛氭牸寮2b -110~111锛歊ESERVED - - - - U鍜孶閫嗗瘎瀛樺櫒 - - U閫嗙殑鍊 - - - U鍊 - - - - CV瀵勫瓨鍣 - - CV鍊 - - - - 鐢熸垚GOLD搴忓垪鏃剁浜屼釜搴忓垪鐨勫垵濮嬪煎瘎瀛樺櫒 - - 鐢熸垚GOLD搴忓垪鏃讹紝绗簩涓簭鍒楃殑鍒濆鍊 - - - - 鎺у埗瀵勫瓨鍣 - - 1锛氫娇鑳絇USCH妯″潡杩愮畻瀹屾瘯鍚庣‖浠跺惎鍔║LDFT妯″潡 -0锛氫笉浣胯兘PUSCH妯″潡杩愮畻瀹屾瘯鍚庣‖浠跺惎鍔║LDFT妯″潡 - - - 00锛氬惎鍔≒USCH杩愮畻 -01锛氬惎鍔≒UCCH UCI缂栫爜鍔犳壈杩愮畻 -10锛氬惎鍔≒RACH杩愮畻 -11锛氬惎鍔∟PUSCH鏍煎紡1锛圢PUSCH鏍煎紡2涓嶈皟鐢≒USCH IP锛 - - - 涓嶧UNC_SEL鑱斿悎閰嶇疆锛岄夋嫨PUSCH UCI鎴朠UCCH UCI锛孎UNC_SEL涓衡00鈥欐椂閫夋嫨PUSCH UCI锛孎UNC_SEL涓衡01鈥欐椂閫夋嫨PUCCH UCI锛 -0锛氫笉鍚姩UCI缂栫爜杩愮畻 -1锛氬惎鍔║CI缂栫爜杩愮畻 - - - PUSCH_BUFFER涓璏EM搴忓彿鎸囩ず -00锛歅USCH_BUF1锛 -01锛歅USCH_BUF2锛 -10锛歅USCH_BUF3锛 -11锛歅RACH_BUF锛 - - - 0锛氫笉鍚姩PUSCH_BUFFER鍔熻兘锛 -1锛氬惎鍔≒USCH_BUFFER鍔熻兘锛 - - - PRACH涓璟C搴忓垪闀垮害鎸囩ず -0锛歓C搴忓垪闀垮害涓139锛 -1锛歓C搴忓垪闀垮害涓839锛 - - - 0锛歅USCH涓殑CRC涓嶅杈撳叆鏁版嵁杩涜Byte鍙嶈浆 -1锛歅USCH涓殑CRC瀵硅緭鍏ユ暟鎹繘琛孊yte鍙嶈浆 - - - 0锛歀TE妯″紡涓嬫ā鍧椾腑鏂笉浣胯兘 -1锛歀TE妯″紡涓嬫ā鍧椾腑鏂娇鑳 - - - 0锛氫笉鍚姩PUSCH鐨勪俊閬撳姞鎵 -1锛氬惎鍔≒USCH鐨勪俊閬撳姞鎵 - - - 0锛氫笉鍚姩PUSCH鐨勪俊閬撲氦缁 -1锛氬惎鍔≒USCH鐨勪俊閬撲氦缁 - - - 0锛氫笉鍚姩PUSCH鐨凾urbo缂栫爜鍜岄熺巼鍖归厤 -1锛氬惎鍔≒USCH鐨凾urbo缂栫爜鍜岄熺巼鍖归厤 - - - 0锛氫笉鍚姩PUSCH鐨凜RC -1锛氬惎鍔≒USCH鐨凜RC - - - 0锛氫笉鍚姩鍔熻兘妯″潡锛圠TE妯″紡锛 -1锛氬惎鍔ㄥ姛鑳芥ā鍧楋紙LTE妯″紡锛 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 涓柇鏍囧織 -0锛氬姛鑳芥ā鍧楁湭瀹屾垚 -1锛氬姛鑳芥ā鍧楀畬鎴愶紝涓柇鎸囩ず - - - - PUCCH format2/2a/2b UCI缂栫爜鍔犳壈缁撴灉 - - PUCCH format2/2a/2b UCI缂栫爜鍔犳壈缁撴灉 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CTRL绯荤粺鍙傛暟瀵勫瓨鍣 - - Schedule SIB1 BR R13锛圥BML浣胯兘鏃堕渶瑕侀厤缃級 - - - PHICH resource锛圥BML浣胯兘鏃堕渶瑕侀厤缃級 - - - PHICH duration锛圥BML浣胯兘鏃堕渶瑕侀厤缃級 - - - 涓婅甯﹀鎸囩ず锛 -0锛1.4Mhz -1锛3Mhz锛 -2锛5Mhz锛 -3锛10Mhz锛 -4锛15Mhz锛 -5锛20Mhz -6~7锛氶鐣欙紙淇濇姢鎴愰厤缃5锛 - - - Ng鐨勬寚绀猴細 -0锛1/6 -1锛1/2 -2锛1 -3锛2 - - - 浼犺緭妯″紡锛 -1~:9锛歵m1,tm2,鈥,tm9 - - - TDD妯″紡鏃讹紝鐗规畩瀛愬抚閰嶇疆锛0~9锛堟棤鏁堜繚 -鎶ゆ垚9锛 - - - 涓婁笅琛岄厤缃細0~6锛堟棤鏁堜繚鎶ゆ垚6锛 - - - 甯﹀鎸囩ず锛 -0锛1.4Mhz -1锛3Mhz锛 -2锛5Mhz锛 -3锛10Mhz锛 -4锛15Mhz锛 -5锛20Mhz -6~7锛氶鐣欙紙淇濇姢鎴愰厤缃5锛 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 -2锛4鍙戝皠澶╃嚎 -3锛氶鐣欙紙淇濇姢鎴愰厤缃2锛 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - FDD鎴朤DD鎸囩ず锛 -0锛歍DD -1锛欶DD - - - - CTRL灏忓尯ID瀵勫瓨鍣 - - 灏忓尯ID锛0~503 - - - - CTRL绯荤粺鍙傛暟瀵勫瓨鍣 - - 涓婅甯﹀鎸囩ず锛 -0锛1.4Mhz -1锛3Mhz锛 -2锛5Mhz锛 -3锛10Mhz锛 -4锛15Mhz锛 -5锛20Mhz -6~7锛氶鐣欙紙淇濇姢鎴愰厤缃5锛 - - - Ng鐨勬寚绀猴細 -0锛1/6 -1锛1/2 -2锛1 -3锛2 - - - 浼犺緭妯″紡锛 -1~:9锛歵m1,tm2,鈥,tm9 - - - TDD妯″紡鏃讹紝鐗规畩瀛愬抚閰嶇疆锛0~9锛堟棤鏁堜繚鎶ゆ垚9锛 - - - 涓婁笅琛岄厤缃細0~6锛堟棤鏁堜繚鎶ゆ垚6锛 - - - 甯﹀鎸囩ず锛 -0锛1.4Mhz -1锛3Mhz锛 -2锛5Mhz锛 -3锛10Mhz锛 -4锛15Mhz锛 -5锛20Mhz -6~7锛氶鐣欙紙淇濇姢鎴愰厤缃5锛 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 -2锛4鍙戝皠澶╃嚎 -3锛氶鐣欙紙淇濇姢鎴愰厤缃2锛 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - FDD鎴朤DD鎸囩ず锛 -0锛歍DD -1锛欶DD - - - - CTRL灏忓尯ID瀵勫瓨鍣 - - MBSFN ID锛0~255 -灏忓尯ID锛0~503 - - - - RA-RNTI/TEMP-C-RNTI瀵勫瓨鍣 - - Temp-C-RNTI - - - RA_RNTI - - - - C-RNTI/SPS-C-RNTI瀵勫瓨鍣 - - SPS_RNTI - - - C_RNTI - - - - TPC-PUCCH-RNTI/TPC-PUSCH-RNTI瀵勫瓨鍣 - - TPC-PUCSH-RNTI - - - TPC-PUCCH-RNTI - - - - G_RNTI瀵勫瓨鍣 - - G_RNTI - - - - CSI鐨凴S鍒嗗竷閰嶇疆瀵勫瓨鍣0 - - 绗2缁勬椂鍩熶笂锛屼竴涓狿RB鐨凜SI-RS鐨勫垎甯冩寚 -绀猴紝鍚孋SIRS_GROUP1銆 - - - 绗1缁勬椂鍩熶笂锛屼竴涓狿RB鐨凜SI-RS鐨勫垎甯冩寚 -绀猴紝绗0姣旂壒鍒11姣旂壒鍒嗗埆鎸囩ずPRB涓璕E#0 -鍒癛E#11銆傚鏋滅0姣旂壒涓1琛ㄧずRE#0涓 -CSI-RS锛屽弽涔嬪垯鍚︺ - - - - CSI鐨凴S鍒嗗竷閰嶇疆瀵勫瓨鍣1 - - 瀛愬抚鍐呭惈CSI-RS鐨凮FDM绗﹀彿瀵逛笟鍔1锛圥DSCH涓氬姟锛夌殑澶勭悊鎸囩ず銆侼orm-CP鏃讹紝24鍒30姣旂壒鍒嗗埆琛ㄧずOFDM#5銆6銆8銆9銆10銆12鍜13锛汦xt-CP鏃讹紝24鍒29姣旂壒鍒嗗埆琛ㄧずOFDM#4銆5銆7銆8銆10鍜11锛涗互Norm-CP鐨勭24姣旂壒杩涜璇存槑锛屽鏋滀负1琛ㄧずOFDM#5涓婅涓氬姟1涓轰笉瀛樺湪锛涘鏋滀负0琛ㄧずOFDM#5涓婁笟鍔1鐨勬暟鎹簲閬垮紑CSI-RS鎵鍗犵殑瀛愯浇娉綅缃 - - - 绗4缁勬椂鍩熶笂锛屼竴涓狿RB鐨凜SI-RS鐨勫垎甯冩寚绀猴紝鍚孋SIRS_GROUP1銆 - - - 绗3缁勬椂鍩熶笂锛屼竴涓狿RB鐨凜SI-RS鐨勫垎甯冩寚绀猴紝鍚孋SIRS_GROUP1銆 - - - - PMI閰嶇疆瀵勫瓨鍣 - - PMI 鐮佹湰闄愬埗闆(codebookSubsetRestriction)锛 -0锛歅MI琛ㄥ搴攂it鐨勮闇瑕佽绠 -1锛歅MI琛ㄥ搴攂it鐨勮涓嶉渶瑕佽绠 - - - - PDCCH閰嶇疆瀵勫瓨鍣 - - 姣忎釜BIT鍒嗗竷鏍囪瘑锛 -Bit0:1涓狾FDM绗﹀彿CFI -Bit1:2涓狾FDM绗﹀彿CFI -Bit2:3涓狾FDM绗﹀彿CFI -Bit3:4涓狾FDM绗﹀彿CFI -0锛氭棤鏁 -1锛氭湁鏁 - - - - PHICH閰嶇疆瀵勫瓨鍣 - - HI鐨凮FDM鏉′欢閫夋嫨锛0~3 - - - PHICH1浣胯兘锛 -0锛氫娇鑳 -1锛氫笉浣胯兘 - - - PHICH1搴忓垪鍙凤細0~7 - - - PHICH1缁勫彿锛0~99 - - - PHICH0浣胯兘锛 -0锛氫娇鑳 -1锛氫笉浣胯兘 - - - PHICH0搴忓垪鍙凤細0~7 - - - PHICH0缁勫彿锛0~99 - - - - PDCCH閰嶇疆瀵勫瓨鍣 - - UE绌洪棿DCI绗簩涓暱搴︼細max57 - - - UE绌洪棿DCI绗竴涓暱搴︼細max57 - - - COMM绌洪棿DCI绗簩涓暱搴︼細max57 - - - COMM绌洪棿DCI绗竴涓暱搴︼細max57 - - - DCILEN閫夋嫨锛 -0锛氱‖浠惰〃鏍 -1锛氳蒋浠堕厤缃 - - - PUSCH澧炲己浣胯兘锛 -0锛欴CI0 -1锛欴CI0C - - - CSI闀垮害閫夋嫨锛 -0锛1 -1锛2 - - - 澶╃嚎閫夋嫨浣胯兘锛 -0锛氬ぉ绾块夋嫨涓嶄娇鑳 -1锛氬ぉ绾块夋嫨浣胯兘 - - - SRS婵娲伙細 -0锛氭棤DCI涓璖RS_REQ鍩 -1锛氭湁DCI涓璖RS_REQ鍩 - - - PDCCH鐩叉涓暟锛 -0:1 -1:2 -2:3 -3:4 -鈥 -7锛8 - - - - PDSCH 鈥揅/RA/T鐩稿叧杈撳叆淇℃伅瀵勫瓨鍣 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - PDSCH -SI鐩稿叧杈撳叆淇℃伅瀵勫瓨鍣 - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - 鍐椾綑鐗堟湰锛0~3 - - - 浼犺緭鍧楅暱搴︼細max2216 - - - - PDSCH -PAGING鐩稿叧杈撳叆淇℃伅瀵勫瓨鍣 - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - 鍐椾綑鐗堟湰锛0~3 - - - 浼犺緭鍧楅暱搴︼細max2216 - - - - CTRL甯у彿瀵勫瓨鍣 - - 瓒呭抚鍙凤細0~65535 - - - 鏃犵嚎甯у彿:0~1023 - - - 瀛愬抚鍙:0~9 - - - - DATA甯у彿瀵勫瓨鍣 - - 瓒呭抚鍙凤細0~65535 - - - 鏃犵嚎甯у彿:0~1023 - - - 瀛愬抚鍙:0~9 - - - - LDTC CTRL涓氬姟閰嶇疆瀵勫瓨鍣 - - SC-N-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SC-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - G-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - TPC-PUCCH-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - TPC-PUSCH-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - Temp-C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SPS-C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RA-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - P-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SI-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - LDTC DATA涓氬姟閰嶇疆瀵勫瓨鍣 - - SC-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - G-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - Temp-C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SPS-C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - C-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RA-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - P-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SI-RNTI浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - LDTC CTRL鎺у埗瀵勫瓨鍣 - - SINR DMA瑙﹀彂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PMI DMA瑙﹀彂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SINR涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PMI涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PDCCH涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PBCH涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - MBMS瀛愬抚鎸囩ず锛 -0锛氶潪MBMS瀛愬抚 -1锛歁BMS瀛愬抚 - - - CTRL QFQT涔掍箵閫夋嫨锛 -0锛氱1鍧椾箳 -1锛氱2鍧椾箵 -2锛氱3鍧 - - - PBCH璁＄畻鐨勮捣濮嬶細 -0锛氶潪璧峰 -1锛氳捣濮 - - - SINR浣胯兘锛 -0锛氫娇鑳 -1锛氫笉浣胯兘 - - - PMI璁＄畻浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - HI璁＄畻浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PDCCH浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PBCH浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - LDTC DATA鎺у埗瀵勫瓨鍣 - - PDSCH DMA瑙﹀彂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - PDSCH涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - DATA QFQT涔掍箵閫夋嫨锛 -0锛氱1鍧椾箳 -1锛氱2鍧椾箵 -2锛氱3鍧 - - - CSIRS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - SI鐨凥QBUF閫夋嫨锛 -0锛氶夋嫨HQBUF0 -1锛氶夋嫨HQBUF1 - - - PDSCH璁＄畻鐨勮捣濮嬶細 -0锛氶潪璧峰 -1锛氳捣濮 - - - PDS璁＄畻鐨勮捣濮嬶細 -0锛氶潪璧峰 -1锛氳捣濮 - - - PDSCH浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - LDTC CTRL鍚姩瀵勫瓨鍣 - - 鍚姩LDTC妯″潡锛 -0锛氫笉鍚姩鎴栬呭凡缁忓惎鍔ㄥ苟娓呴櫎 -1锛氬惎鍔 - - - - LDTC DATA鍚姩瀵勫瓨鍣 - - 鍚姩LDTC妯″潡锛 -0锛氫笉鍚姩鎴栬呭凡缁忓惎鍔ㄥ苟娓呴櫎 -1锛氬惎鍔 - - - - CTRL鏍囧織瀵勫瓨鍣 - - DCI褰撳墠瀛愬抚妫鍑烘湁鏁堟爣璇嗭細 -0锛氭棤DCI妫鍑猴紱 -1锛氬搴旀瘮鐗圭殑DCI褰撳墠瀛愬抚妫鍑烘湁鏁 - - - MIB褰撳墠瀛愬抚妫鍑烘湁鏁堟爣璇嗭細 -0锛氭棤MIB妫鍑猴紱 -1锛氬搴旀瘮鐗圭殑MIB褰撳墠瀛愬抚妫鍑烘湁鏁 - - - SINR瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - PMI瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - PDCCH瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - PBCH瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - - DATA鏍囧織瀵勫瓨鍣 - - PAGING璇戠爜缁撴灉鏁版嵁锛堝惈CRC鏍￠獙浣嶏級锛屽叏闆舵爣蹇楋細 -0锛氭暟鎹笉涓哄叏闆 -1锛氭暟鎹负鍏ㄩ浂 - - - PAGING璇戠爜CRC鏍囧織锛 -0锛欳RC鏍￠獙姝ｇ‘ -1锛欳RC鏍￠獙閿欒 - - - SI璇戠爜缁撴灉鏁版嵁锛堝惈CRC鏍￠獙浣嶏級锛屽叏闆舵爣蹇楋細 -0锛氭暟鎹笉涓哄叏闆 -1锛氭暟鎹负鍏ㄩ浂 - - - SI璇戠爜CRC鏍囧織锛 -0锛欳RC鏍￠獙姝ｇ‘ -1锛欳RC鏍￠獙閿欒 - - - PDSCH 璇戠爜缁撴灉鏁版嵁锛堝惈CRC鏍￠獙浣嶏級锛屽叏闆舵爣蹇楋細 -0锛氭暟鎹笉涓哄叏闆 -1锛氭暟鎹负鍏ㄩ浂 - - - PDSCH 璇戠爜CRC鏍囧織锛 -0锛欳RC鏍￠獙姝ｇ‘ -1锛欳RC鏍￠獙閿欒 - - - PDSCH瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - - BUF鎸囩ず瀵勫瓨鍣 - - FH鐨刣ata浣跨敤鎸囩ず锛 -0锛氫娇鐢‵H0 -1锛氫娇鐢‵H1 - - - FH鐨刢trl浣跨敤鎸囩ず锛 -0锛氫娇鐢‵H0 -1锛氫娇鐢‵H1 - - - DSCHOUT浣跨敤鎸囩ず锛 -0锛氫娇鐢―SCHOUT0 -1锛氫娇鐢―SCHOUT1 - - - FFTBUF浣跨敤鎸囩ず锛 -0锛氫娇鐢‵FTBUF0 -1锛氫娇鐢‵FTBUF1 - - - - ALG_COMM_PARA閫氱敤鍙傛暟瀵勫瓨鍣 - - PDCCH褰掍竴鍖栫瓥鐣ラ棬闄愪釜鏁 - - - G鐨凲鍊艰皟鏁村洜瀛愶細 -0锛歈15 -1锛歈16 -鈥 -7锛歈22 - - - HQ 鍚堝苟鏂瑰紡閫夋嫨锛 -0锛欳C鍚堝苟 -1锛欼R鍚堝苟 - - - HQ BUF鐨勬瘮鐗逛綅瀹界殑澶у皬锛 -0锛4bit -1锛6bit - - - SD浣跨敤G鎴栬卬oise杩涜淇″彿妫娴嬭绠楋細 -0锛氱敤noise璁＄畻 -1锛氱敤GM鐭╅樀 - - - PMI/PWR瀛愬甫瀹藉甫閫夋嫨锛 -0锛氬皬甯﹀ -1锛氬ぇ甯﹀ -鍏蜂綋瑙佷笅琛ㄦ弿杩 - - - CTCG璧峰浣嶇疆閫夋嫨锛 -0锛氫粠OFDM4(鍖呮嫭OFDM4)鍓嶆湁鏁圕RS涓烘牱鏈 -1锛氫粠OFDM8(鍖呮嫭OFDM8)鍓嶆湁鏁圕RS涓烘牱鏈 - - - CRS G鐨勯暱搴﹂夋嫨锛 -0锛1PRB -1锛2PRB - - - CRS棰戝煙浼拌婊戝姩绐楅暱锛3鎴6 PRB锛 -0锛3PRB -1锛6PRB - - - UE RS鏃讹紝澶勭悊PRB鐨勪釜鏁帮紝鍙栧间负1,3 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - CHE棰戝煙鍙傛暟瀵勫瓨鍣 - - 涔樼疮鍔犲悗鐢16bit鏁版嵁鎴彇涓10bit鏁版嵁鐨勬埅鍙栨柟寮忛夋嫨 -0锛氭寜鎺ュ彛瀵勫瓨鍣ㄩ厤缃洿鎺ユ埅浣 -1锛氭渶澶у煎綊涓鍖栨埅浣 - - - 涔樼疮鍔犲悗鐢16bit鏁版嵁鎴彇涓10bit鏁版嵁鐨勬瘮鐗归夋嫨锛 -0x0锛氭埅鍙栭夋嫨15~6 -0x1锛氭埅鍙栭夋嫨14~5 -0x2锛氭埅鍙栭夋嫨13~4 -0x3锛氭埅鍙栭夋嫨12~3 -0x4锛氭埅鍙栭夋嫨11~2 -0x5锛氭埅鍙栭夋嫨10~1 -0x6锛氭埅鍙栭夋嫨9~0 -鍏朵粬锛歳eserved锛屼笉鍙厤缃 - - - 涔樼疮鍔犲悗鎴彇16bit鏁版嵁鐨勬瘮鐗归夋嫨锛 -0x0锛氭埅鍙栭夋嫨28~13 -0x1锛氭埅鍙栭夋嫨27~12 -0x2锛氭埅鍙栭夋嫨26~11 -0x3锛氭埅鍙栭夋嫨25~10 -0x4锛氭埅鍙栭夋嫨24~9 -0x5锛氭埅鍙栭夋嫨23~8 -0x6锛氭埅鍙栭夋嫨22~7 -0x7锛氭埅鍙栭夋嫨21~6 -0x8锛氭埅鍙栭夋嫨20~5 -0x9锛氭埅鍙栭夋嫨19~4 -0xa锛氭埅鍙栭夋嫨18~3 -0xb锛氭埅鍙栭夋嫨17~2 -0xc锛氭埅鍙栭夋嫨16~1 -0xd锛氭埅鍙栭夋嫨15~0 -鍏朵粬锛歊eserved - - - - CHE鏃跺煙鍙傛暟瀵勫瓨鍣 - - 鏃跺煙浼拌涔樼疮鍔犲悗鎴彇姣旂壒閫夋嫨锛 -0x0锛氭埅鍙栭夋嫨25~10 -0x1锛氭埅鍙栭夋嫨24~9 -0x2锛氭埅鍙栭夋嫨23~8 -0x3锛氭埅鍙栭夋嫨22~7 -0x4锛氭埅鍙栭夋嫨21~6 -0x5锛氭埅鍙栭夋嫨20~5 -0x6锛氭埅鍙栭夋嫨19~4 -0x7锛氭埅鍙栭夋嫨18~3 -0x8锛氭埅鍙栭夋嫨17~2 -0x9锛氭埅鍙栭夋嫨16~1 -0xa锛氭埅鍙栭夋嫨15~0 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it[99:96]琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it[99:96]琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it[99:96]琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it[99:96]琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - - 璧勬簮鍗犵敤淇℃伅瀵勫瓨鍣 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it[99:96]琛ㄧず涓嶅悓鐨刾rb锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - 鐮佹湰绱㈠紩瀵勫瓨鍣 - - 瀛愬甫8鐨勭爜鏈储寮 - - - 瀛愬甫7鐨勭爜鏈储寮 - - - 瀛愬甫6鐨勭爜鏈储寮 - - - 瀛愬甫5鐨勭爜鏈储寮 - - - 瀛愬甫4鐨勭爜鏈储寮 - - - 瀛愬甫3鐨勭爜鏈储寮 - - - 瀛愬甫2鐨勭爜鏈储寮 - - - 瀛愬甫1鐨勭爜鏈储寮 - - - - 鐮佹湰绱㈠紩瀵勫瓨鍣 - - 瀛愬甫16鐨勭爜鏈储寮 - - - 瀛愬甫15鐨勭爜鏈储寮 - - - 瀛愬甫14鐨勭爜鏈储寮 - - - 瀛愬甫13鐨勭爜鏈储寮 - - - 瀛愬甫12鐨勭爜鏈储寮 - - - 瀛愬甫11鐨勭爜鏈储寮 - - - 瀛愬甫10鐨勭爜鏈储寮 - - - 瀛愬甫9鐨勭爜鏈储寮 - - - - 鐮佹湰绱㈠紩瀵勫瓨鍣 - - 瀛愬甫24鐨勭爜鏈储寮 - - - 瀛愬甫23鐨勭爜鏈储寮 - - - 瀛愬甫22鐨勭爜鏈储寮 - - - 瀛愬甫21鐨勭爜鏈储寮 - - - 瀛愬甫20鐨勭爜鏈储寮 - - - 瀛愬甫19鐨勭爜鏈储寮 - - - 瀛愬甫18鐨勭爜鏈储寮 - - - 瀛愬甫17鐨勭爜鏈储寮 - - - - 鐮佹湰绱㈠紩瀵勫瓨鍣 - - 瀛愬甫25鐨勭爜鏈储寮 - - - - CRS鑾峰緱鐨勫甯︿俊鍙峰姛鐜囧瘎瀛樺櫒 - - - CRS鑾峰緱鐨勫甯﹀櫔澹板姛鐜囧瘎瀛樺櫒 - - - CRS鑾峰緱鐨勫甯︿俊鍙峰姛鐜嘇GC瀵勫瓨鍣 - - 鎺ユ敹澶╃嚎1涓奀RS鑾峰緱鐨勫甯︿俊鍙峰姛鐜嘇GC - - - - CRS鑾峰緱鐨勫甯﹀櫔澹板姛鐜嘇GC瀵勫瓨鍣 - - 鎺ユ敹澶╃嚎1涓奀RS鑾峰緱鐨勫甯﹀櫔澹板姛鐜嘇GC - - - - DATA鎴綅鍥犲瓙瀵勫瓨鍣0 - - PDCCH鐨勬埅浣嶆柟寮忥細 -0锛氬浐瀹氭埅浣 -1锛氭寜鐓ф渶澶у煎姩鎬佹埅浣 - - - PBCH鐨勬埅浣嶆柟寮忥細 -0锛氬浐瀹氭埅浣 -1锛氭寜鐓т笅闈㈠潎鍊艰寖鍥村姩鎬佹埅浣 - - - 鎴綅鑼冨洿鍊1 - - - 鎴綅鑼冨洿鍊0 - - - - DATA鎴綅鍥犲瓙瀵勫瓨鍣2 - - PDSCH鐨勬埅浣嶆柟寮忥細 -0锛氬浐瀹氭埅浣 -1锛氭寜鐓т笅闈㈠潎鍊艰寖鍥村姩鎬佹埅浣 - - - 鎴綅鑼冨洿鍊0 - - - - DATA鎴綅鍥犲瓙瀵勫瓨鍣3 - - 鎴綅鑼冨洿鍊2 - - - 鎴綅鑼冨洿鍊1 - - - - DATA鎴綅鍥犲瓙瀵勫瓨鍣4 - - 鎴綅鑼冨洿鍊4 - - - 鎴綅鑼冨洿鍊3 - - - - DATA璋冩暣鍥犲瓙(CRS)瀵勫瓨鍣0 - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃湁CELL RS鏃讹紝瀵筪ata璋冩暣 - - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃棤CELL RS鏃讹紝瀵筪ata璋冩暣 - - - - DATA璋冩暣鍥犲瓙(URS)瀵勫瓨鍣1 - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃湁CELL RS鏃讹紝瀵筪ata璋冩暣 - - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃棤CELL RS鏃讹紝瀵筪ata璋冩暣 - - - - DATA璋冩暣鍥犲瓙(URS)瀵勫瓨鍣2 - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃湁CELL RS鏃讹紝瀵筪ata璋冩暣 - - - 鍊硷紝鐢ㄤ簬褰揙FDM绗﹀彿涓婃棤CELL RS鏃讹紝瀵筪ata璋冩暣 - - - - CTRL鍣０鍊煎瘎瀛樺櫒 - - - CTRL鍣０缁濆AGC鍊 - - 鍣０缁濆AGC鍊硷紙鏈夌鍙凤級 - - - - CTRL鍣０闂ㄩ檺瀵勫瓨鍣 - - 鍣０闂ㄩ檺锛圥DCCH銆丳BCH锛 - - - - DATA鍣０鍊煎瘎瀛樺櫒 - - - DATA鍣０缁濆AGC鍊 - - 鍣０缁濆AGC鍊硷紙鏈夌鍙凤級 - - - - DATA鍣０闂ㄩ檺瀵勫瓨鍣 - - 鍣０闂ㄩ檺锛堣緟涓氬姟锛 - - - 鍣０闂ㄩ檺锛堜富涓氬姟锛 - - - - SDOUT鎴綅鍥犲瓙PBCH杈撳嚭瀵勫瓨鍣0 - - PDCCH鎴綅INDX鍊 - - - PBCH鎴綅INDX鍊3 - - - PBCH鎴綅INDX鍊2 - - - PBCH鎴綅INDX鍊1 - - - PBCH鎴綅INDX鍊0 - - - - SDOUT鎴綅鍥犲瓙PDSCH杈撳嚭瀵勫瓨鍣0 - - 鎴綅INDX鍊7 - - - 鎴綅INDX鍊6 - - - 鎴綅INDX鍊5 - - - 鎴綅INDX鍊4 - - - 鎴綅INDX鍊3 - - - 鎴綅INDX鍊2 - - - 鎴綅INDX鍊1 - - - 鎴綅INDX鍊0 - - - - SDOUT鎴綅鍥犲瓙PDSCH杈撳嚭瀵勫瓨鍣1 - - 鎴綅INDX鍊15 - - - 鎴綅INDX鍊14 - - - 鎴綅INDX鍊13 - - - 鎴綅INDX鍊12 - - - 鎴綅INDX鍊11 - - - 鎴綅INDX鍊10 - - - 鎴綅INDX鍊9 - - - 鎴綅INDX鍊8 - - - - SDOUT鎴綅鍥犲瓙PDSCH杈撳嚭瀵勫瓨鍣2 - - 鎴綅INDX鍊23 - - - 鎴綅INDX鍊22 - - - 鎴綅INDX鍊21 - - - 鎴綅INDX鍊20 - - - 鎴綅INDX鍊19 - - - 鎴綅INDX鍊18 - - - 鎴綅INDX鍊17 - - - 鎴綅INDX鍊16 - - - - SDOUT鎴綅鍥犲瓙PDSCH杈撳嚭瀵勫瓨鍣3 - - 鎴綅INDX鍊31 - - - 鎴綅INDX鍊30 - - - 鎴綅INDX鍊29 - - - 鎴綅INDX鍊28 - - - 鎴綅INDX鍊27 - - - 鎴綅INDX鍊26 - - - 鎴綅INDX鍊25 - - - 鎴綅INDX鍊24 - - - - SDOUT鎴綅鍥犲瓙PDSCH杈撳嚭瀵勫瓨鍣4 - - 鎴綅INDX鍊34 - - - 鎴綅INDX鍊33 - - - 鎴綅INDX鍊32 - - - - HARQBUF瀛樺偍鍗犵敤鎸囩ず瀵勫瓨鍣 - - 绗15鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗14鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗13鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗12鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗11鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗10鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗9鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗8鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗7鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗6鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗5鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗4鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗3鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗2鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗1鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - 绗0鍧桯ARQBUFFER瀛樺偍鐘舵佹寚绀 -0:璇ュ潡璧勬簮宸茬粡琚噴鏀撅紱 -1:璇ュ潡璧勬簮姝ｅ湪琚崰鐢紱 - - - - HARQBUF瀛樺偍杩涚▼鎸囩ず0瀵勫瓨鍣 - - 绗7鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗6鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗5鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗4鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗3鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗2鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗1鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗0鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - - HARQBUF瀛樺偍杩涚▼鎸囩ず1瀵勫瓨鍣 - - 绗15鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗14鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗13鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗12鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗11鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗10鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗9鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - 绗8鍧桯ARQBUFFER瀛樺偍杩涚▼鎸囩ず:0~15 - - - - TURBO鍙傛暟瀵勫瓨鍣 - - 褰掍竴鍖栭夋嫨锛64QAM -0锛2鍊嶅潎鍊 -1锛氭渶澶у - - - 褰掍竴鍖栭夋嫨锛16QAM -0锛2鍊嶅潎鍊 -1锛氭渶澶у - - - 褰掍竴鍖栭夋嫨锛歈PSK -0锛2鍊嶅潎鍊 -1锛氭渶澶у - - - 绉讳綅浣胯兘锛64QAM -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 绉讳綅浣胯兘锛16QAM -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 绉讳綅浣胯兘锛歈PSK -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 绉讳綅杩唬娆℃暟2 - - - 绉讳綅杩唬娆℃暟1 - - - 鏈澶ц瘧鐮佽凯浠ｆ鏁板噺1 -锛堟渶澶ц瘧鐮佹鏁颁负9锛夛細0~8 - - - - TURBO杩唬娆℃暟杈撳嚭瀵勫瓨鍣 - - PAG瀹為檯杩唬娆℃暟-1 - - - SI瀹為檯杩唬娆℃暟-1 - - - PDS绗簩鍧楀疄闄呰凯浠ｆ鏁-1 - - - PDS绗竴鍧楀疄闄呰凯浠ｆ鏁-1 - - - - VIT鍙傛暟瀵勫瓨鍣 - - 鎺╃爜浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - CRC绫诲瀷锛 -0锛欳RC16 -1锛欳RC24A - - - DMA瑙﹀彂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 涓柇浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - VIT杩唬娆℃暟 -0:1 -1:2 -2:3 -3:4 - - - - VIT FA閰嶇疆瀵勫瓨鍣 - - 鎺╃爜 - - - PDCCH鐨刦alse alarm浣胯兘 - - - PDCCH鐨刦alse alarm鐨勯噸鏋勫樊寮傜櫨鍒嗘瘮闂ㄩ檺(U8Q7) - - - - VIT鍗曠嫭璋冪敤闀垮害瀵勫瓨鍣 - - VIT闀垮害 - - - - VIT鍗曠嫭璋冪敤鍚姩瀵勫瓨鍣 - - VIT鍚姩锛 -0锛氫笉鍚姩鎴栬呭畬鎴 -1锛氬惎鍔 - - - - VIT鏍囧織瀵勫瓨鍣 - - VIT CRC璇戠爜缁撴灉鏁版嵁锛堝惈CRC鏍￠獙浣嶏級锛屽叏闆舵爣蹇楋細 -0锛氭暟鎹笉涓哄叏闆 -1锛氭暟鎹负鍏ㄩ浂 - - - VIT CRC鏍￠獙姝ｇ‘瀹屾垚鏍囧織锛 -0锛氭纭 -1锛氶敊璇 - - - PBCH瀹屾垚鏍囧織锛 -0锛氭棤涓柇 -1锛氫腑鏂 - - - - VIT FA杈撳嚭瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - CFICH杈撳嚭瀵勫瓨鍣 - - CFI杈撳嚭鐨勫硷細 -1~4锛1.4M鍥哄畾鍔犱簡1鍚庣殑缁撴灉锛 - - - - PHICH杈撳嚭瀵勫瓨鍣 - - HI1杈撳嚭鐨勫 - - - HI0杈撳嚭鐨勫 - - - - 杞欢杈撳叆CTRL瀵勫瓨鍣 - - - 杞欢杈撳叆DATA瀵勫瓨鍣 - - - 杞欢杈撳嚭CTRL瀵勫瓨鍣 - - - 杞欢杈撳嚭DATA瀵勫瓨鍣 - - - PDSCH閲嶅娆℃暟瀵勫瓨鍣 - - PDSCH 绗15涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗14涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗13涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗12涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗11涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗10涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗9涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗8涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗7涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗6涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗5涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗4涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗3涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗2涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗1涓繘绋嬮噸浼犳鏁版寚绀 - - - PDSCH 绗0涓繘绋嬮噸浼犳鏁版寚绀 - - - - SI閲嶅娆℃暟瀵勫瓨鍣 - - SI绗1涓繘绋嬮噸浼犳鏁版寚绀 - - - SI绗0涓繘绋嬮噸浼犳鏁版寚绀 - - - - PBCH閲嶅娆℃暟瀵勫瓨鍣 - - PBCH閲嶄紶娆℃暟鎸囩ず - - - - 杩愯鏃堕棿鎺у埗瀵勫瓨鍣 - - 杩愯鏃堕棿鎺у埗瀵勫瓨鍣 - - - - ABIS浣胯兘閰嶇疆瀵勫瓨鍣 - - 閭诲尯2澶╃嚎骞叉壈鐨勬儏鍐甸夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - 閭诲尯1澶╃嚎骞叉壈鐨勬儏鍐甸夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - 鏈嶅姟灏忓尯澶╃嚎閫夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - MultiCell璁＄畻浣胯兘 -0锛歋ingalCell -1锛歁ultiCell - - - ABIS绉讳綅鍥犲瓙鏂瑰紡閫夋嫨锛 -0锛氶夋嫨杞欢閰嶇疆 -1锛氶夋嫨DLFFT鐩存帴浼犻 - - - ABIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D PDSCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D MPDCCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D PBCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - ABIS灏忓尯閰嶇疆瀵勫瓨鍣 - - 妫娴嬪埌骞叉壈閭诲尯鐨勪釜鏁帮細 -00锛0涓共鎵伴偦鍖 -01锛1涓共鎵伴偦鍖 -10锛2涓共鎵伴偦鍖 -鍏朵粬锛氶粯璁0涓共鎵伴偦鍖 - - - 骞叉壈閭诲尯2鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯1鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯2 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯1 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯2 CELL ID鍊 - - - 骞叉壈閭诲尯1 CELL ID鍊 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒1 - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒2 - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - ABIS骞叉壈绉讳綅瀵勫瓨鍣 - - ABIS骞叉壈绫诲瀷3锛堥偦鍖1+2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷2锛堥偦鍖2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷1锛堥偦鍖1锛夌Щ浣嶅 - - - - ABIS浣胯兘閰嶇疆瀵勫瓨鍣 - - 閭诲尯2澶╃嚎骞叉壈鐨勬儏鍐甸夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - 閭诲尯1澶╃嚎骞叉壈鐨勬儏鍐甸夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - 鏈嶅姟灏忓尯澶╃嚎閫夋嫨锛 -0锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛歱ort0鍜宲ort1閮藉共鎵帮紱鍙戝皠澶╃嚎鏁颁负4鐨勬儏鍐典笅锛歱ort0銆乸ort1銆乸ort2銆乸ort3閮藉共鎵 -1锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort0骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort0銆乸ort2銆乸ort3閮藉共鎵 -2锛氬彂灏勫ぉ绾挎暟涓2鐨勬儏鍐典笅锛氬彧鏈塸ort1骞叉壈锛涘彂灏勫ぉ绾挎暟涓4鐨勬儏鍐典笅锛歱ort1銆乸ort2銆乸ort3閮藉共鎵 - - - ABIS绉讳綅鍥犲瓙鏂瑰紡閫夋嫨锛 -0锛氶夋嫨杞欢閰嶇疆 -1锛氶夋嫨DLFFT鐩存帴浼犻 - - - ABIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D PDSCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D MPDCCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ABIS鐨凷D PBCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - ABIS灏忓尯閰嶇疆瀵勫瓨鍣 - - 妫娴嬪埌骞叉壈閭诲尯鐨勪釜鏁帮細 -00锛0涓共鎵伴偦鍖 -01锛1涓共鎵伴偦鍖 -10锛2涓共鎵伴偦鍖 -鍏朵粬锛氶粯璁0涓共鎵伴偦鍖 - - - 骞叉壈閭诲尯2鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯2鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯2 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯1 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯2 CELL ID鍊 - - - 骞叉壈閭诲尯1 CELL ID鍊 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - ABIS骞叉壈绉讳綅瀵勫瓨鍣 - - ABIS骞叉壈绫诲瀷3锛堥偦鍖1+2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷2锛堥偦鍖2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷1锛堥偦鍖1锛夌Щ浣嶅 - - - - REIS閰嶇疆瀵勫瓨鍣 - - REIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - REIS鐨凬UM涓暟 - - - - REIS浣嶇疆瀵勫瓨鍣0 - - REIS1鐨勭Щ浣嶆寚绀 - - - REIS1鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS0鐨勭Щ浣嶆寚绀 - - - REIS0鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣1 - - REIS3鐨勭Щ浣嶆寚绀 - - - REIS3鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS2鐨勭Щ浣嶆寚绀 - - - REIS2鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣2 - - REIS5鐨勭Щ浣嶆寚绀 - - - REIS5鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS4鐨勭Щ浣嶆寚绀 - - - REIS4鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣3 - - REIS7鐨勭Щ浣嶆寚绀 - - - REIS7鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS6鐨勭Щ浣嶆寚绀 - - - REIS6鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - RBIS鍙傛暟瀵勫瓨鍣 - - 鍙戝皠澶╃嚎鏁颁负2鐨勬儏鍐典笅锛孉BIS鍒ゅ喅鐨凱ORT閫夋嫨锛 -0锛氫娇鐢╬ort0 -1锛氫娇鐢╬ort1 - - - RBIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RBIS鐨凷D PDSCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RBIS鐨凷D MPDCCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RBIS鐨凷D PBCH娓呴浂浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RBIS浣跨敤鐩存帴浣嶇疆鎸囩ず锛 -0锛氫笉浣跨敤鐩存帴浣嶇疆 -1锛氫娇鐢ㄧ洿鎺ヤ綅缃 - - - RBIS妫娴嬩釜鏁帮細 -0锛1 -1锛2 -2锛3 -3锛4 -4锛5 - - - RBIS鐨勭洿鎺ヤ綅缃 - - - RBIS鍥犲瓙 - - - - RBIS妫娴嬪埌骞叉壈鎵鍦ㄤ綅缃緭鍑哄瘎瀛樺櫒0 - - RBIS妫娴嬪嚭鐨勫共鎵颁綅缃細0~99 - - - RBIS妫娴嬪嚭鐨勫共鎵颁綅缃細0~99 - - - RBIS妫娴嬪嚭鐨勫共鎵颁綅缃細0~99 - - - RBIS妫娴嬪嚭鐨勫共鎵颁綅缃細0~99 - - - - RBIS妫娴嬪埌骞叉壈鎵鍦ㄤ綅缃緭鍑哄瘎瀛樺櫒1 - - RBIS妫娴嬪嚭鐨勫共鎵颁綅缃細0~99 - - - - RBIS妫娴嬪埌鍧囧艰緭鍑哄瘎瀛樺櫒 - - - RBIS妫娴嬪埌鍧囧艰緭鍑哄瘎瀛樺櫒 - - RBIS妫娴嬪嚭鐨勬渶澶у - - - - 鍔犳潈鍊煎瘎瀛樺櫒 - - PBML浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 闇瑕佷慨姝ｇ殑LLR淇℃伅闀垮害 - - - 闇瑕佷慨姝ｇ殑LLR淇℃伅璧峰浣嶇疆 - - - LLR淇鍔犳潈鍊硷細 -0~255 - - - - 鎺у埗閾捐矾鐘舵佽緭鍑哄瘎瀛樺櫒 - - 鎺у埗閾捐矾鐘舵佽緭鍑哄瘎瀛樺櫒 - - - - 鏁版嵁閾捐矾鐘舵佽緭鍑哄瘎瀛樺櫒 - - 鏁版嵁閾捐矾鐘舵佽緭鍑哄瘎瀛樺櫒 - - - - CTRL甯у彿杈撳嚭瀵勫瓨鍣 - - 瓒呭抚鍙凤細0~65535 - - - 鏃犵嚎甯у彿锛0~1023 - - - 瀛愬抚鍙凤細0~9 - - - - DATA甯у彿杈撳嚭瀵勫瓨鍣 - - 瓒呭抚鍙凤細0~65535 - - - 鏃犵嚎甯у彿锛0~1023 - - - 瀛愬抚鍙凤細0~9 - - - - PDSCH HARQIN瀵勫瓨鍣 - - 涓讳笟鍔B0鍦℉ARQIN MEM0鐨勯暱搴 - - - 涓讳笟鍔B0鍦℉ARQIN MEM0鐨勮捣濮 - - - - PDSCH HARQIN瀵勫瓨鍣 - - 涓讳笟鍔B0鐨勬婚暱搴 - - - 涓讳笟鍔B0鍦℉ARQIN MEM1鐨勮捣濮 - - - - PDSCH HARQIN瀵勫瓨鍣 - - 涓讳笟鍔B1鍦℉ARQIN MEM0鐨勯暱搴 - - - 涓讳笟鍔B1鍦℉ARQIN MEM0鐨勮捣濮 - - - - PDSCH HARQIN瀵勫瓨鍣 - - 涓讳笟鍔B1鐨勬婚暱搴 - - - 涓讳笟鍔B1鍦℉ARQIN MEM1鐨勮捣濮 - - - - SI HARQIN瀵勫瓨鍣 - - SI涓氬姟CB1鍦℉ARQIN MEM0鐨勯暱搴 - - - SI涓氬姟CB1鍦℉ARQIN MEM0鐨勮捣濮 - - - - SI HARQIN瀵勫瓨鍣 - - SI涓氬姟CB1鐨勬婚暱搴 - - - SI涓氬姟CB1鍦℉ARQIN MEM1鐨勮捣濮 - - - - PAGING HARQIN瀵勫瓨鍣 - - PAGING涓氬姟CB1鍦℉ARQIN MEM0鐨勯暱搴 - - - PAGING涓氬姟CB1鍦℉ARQIN MEM0鐨勮捣濮 - - - - PAGING HARQIN瀵勫瓨鍣 - - PAGING涓氬姟CB1鐨勬婚暱搴 - - - PAGING涓氬姟CB1鍦℉ARQIN MEM1鐨勮捣濮 - - - - ABIS骞叉壈绉讳綅杈撳嚭瀵勫瓨鍣 - - ABIS骞叉壈绫诲瀷3锛堥偦鍖1+2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷2锛堥偦鍖2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷1锛堥偦鍖1锛夌Щ浣嶅 - - - - ABIS骞叉壈绉讳綅杈撳嚭瀵勫瓨鍣 - - ABIS骞叉壈绫诲瀷3锛堥偦鍖1+2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷2锛堥偦鍖2锛夌Щ浣嶅 - - - ABIS骞叉壈绫诲瀷1锛堥偦鍖1锛夌Щ浣嶅 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 灏忓尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 灏忓尯鏃跺欢闂ㄩ檺鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯鐩稿鏈尯鏃跺欢闂ㄩ檺鍊硷紙鍗曚綅TS锛 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DCI0杈撳嚭瀵勫瓨鍣1 - - - DCI0杈撳嚭瀵勫瓨鍣2 - - - DCI0鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI0 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI0 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI1A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI0 -1:DCI1 -2:DCI1A -3:DCI1B -4:DCI1C -5:DCI1D -6:DCI2 -7:DCI2A -8:DCI2B -9:DCI2C -10:DCI3/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI0 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI0 淇℃伅瀵勫瓨鍣3 - - DCI0C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI2/DCI2A/DCI2B/DCI2C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI0鐨勫惊鐜Щ浣嶆寚绀 - - - DCI0鐨凜QI鎸囩ず - - - DCI2/DCI2A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI0銆丏CI1A銆丏CI2B TDD銆丏CI2C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI1D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI0 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI0 淇℃伅瀵勫瓨鍣5 - - - DCI0 淇℃伅瀵勫瓨鍣6 - - - DCI0 淇℃伅瀵勫瓨鍣7 - - - DCI0 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI0 淇℃伅瀵勫瓨鍣9 - - - DCI0 淇℃伅瀵勫瓨鍣10 - - - DCI0 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI1杈撳嚭瀵勫瓨鍣1 - - - DCI1杈撳嚭瀵勫瓨鍣2 - - - DCI1鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI1 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI1 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI1A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI1 -1:DCI1 -2:DCI1A -3:DCI1B -4:DCI1C -5:DCI1D -6:DCI2 -7:DCI2A -8:DCI2B -9:DCI2C -10:DCI3/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI1 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI1 淇℃伅瀵勫瓨鍣3 - - DCI1C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI2/DCI2A/DCI2B/DCI2C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI1鐨勫惊鐜Щ浣嶆寚绀 - - - DCI1鐨凜QI鎸囩ず - - - DCI2/DCI2A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI1銆丏CI1A銆丏CI2B TDD銆丏CI2C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI1D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI1 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI1 淇℃伅瀵勫瓨鍣5 - - - DCI1 淇℃伅瀵勫瓨鍣6 - - - DCI1 淇℃伅瀵勫瓨鍣7 - - - DCI1 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI1 淇℃伅瀵勫瓨鍣9 - - - DCI1 淇℃伅瀵勫瓨鍣10 - - - DCI1 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI2杈撳嚭瀵勫瓨鍣1 - - - DCI2杈撳嚭瀵勫瓨鍣2 - - - DCI2鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI2 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI2 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI2A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI2 -1:DCI2 -2:DCI2A -3:DCI2B -4:DCI2C -5:DCI2D -6:DCI2 -7:DCI2A -8:DCI2B -9:DCI2C -10:DCI3/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI2 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI2 淇℃伅瀵勫瓨鍣3 - - DCI2C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI2/DCI2A/DCI2B/DCI2C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI2鐨勫惊鐜Щ浣嶆寚绀 - - - DCI2鐨凜QI鎸囩ず - - - DCI2/DCI2A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI2銆丏CI2A銆丏CI2B TDD銆丏CI2C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI2D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI2 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI2 淇℃伅瀵勫瓨鍣5 - - - DCI2 淇℃伅瀵勫瓨鍣6 - - - DCI2 淇℃伅瀵勫瓨鍣7 - - - DCI2 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI2 淇℃伅瀵勫瓨鍣9 - - - DCI2 淇℃伅瀵勫瓨鍣10 - - - DCI2 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI3杈撳嚭瀵勫瓨鍣1 - - - DCI3杈撳嚭瀵勫瓨鍣2 - - - DCI3鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI3 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI3 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI3A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI3 -1:DCI3 -2:DCI3A -3:DCI3B -4:DCI3C -5:DCI3D -6:DCI3 -7:DCI3A -8:DCI3B -9:DCI3C -10:DCI3/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI3 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI3 淇℃伅瀵勫瓨鍣3 - - DCI3C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI3/DCI3A/DCI3B/DCI3C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI3鐨勫惊鐜Щ浣嶆寚绀 - - - DCI3鐨凜QI鎸囩ず - - - DCI3/DCI3A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI3銆丏CI3A銆丏CI3B TDD銆丏CI3C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI3D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI3 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI3 淇℃伅瀵勫瓨鍣5 - - - DCI3 淇℃伅瀵勫瓨鍣6 - - - DCI3 淇℃伅瀵勫瓨鍣7 - - - DCI3 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI3 淇℃伅瀵勫瓨鍣9 - - - DCI3 淇℃伅瀵勫瓨鍣10 - - - DCI3 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI4杈撳嚭瀵勫瓨鍣1 - - - DCI4杈撳嚭瀵勫瓨鍣2 - - - DCI4鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI4 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI4 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI4A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI4 -1:DCI4 -2:DCI4A -3:DCI4B -4:DCI4C -5:DCI4D -6:DCI4 -7:DCI4A -8:DCI4B -9:DCI4C -10:DCI4/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI4 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI4 淇℃伅瀵勫瓨鍣3 - - DCI4C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI4/DCI4A/DCI4B/DCI4C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI4鐨勫惊鐜Щ浣嶆寚绀 - - - DCI4鐨凜QI鎸囩ず - - - DCI4/DCI4A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI4銆丏CI4A銆丏CI4B TDD銆丏CI4C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI4D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI4 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI4 淇℃伅瀵勫瓨鍣5 - - - DCI4 淇℃伅瀵勫瓨鍣6 - - - DCI4 淇℃伅瀵勫瓨鍣7 - - - DCI4 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI4 淇℃伅瀵勫瓨鍣9 - - - DCI4 淇℃伅瀵勫瓨鍣10 - - - DCI4 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI5杈撳嚭瀵勫瓨鍣1 - - - DCI5杈撳嚭瀵勫瓨鍣2 - - - DCI5鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI5 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI5 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI5A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI5 -1:DCI5 -2:DCI5A -3:DCI5B -4:DCI5C -5:DCI5D -6:DCI5 -7:DCI5A -8:DCI5B -9:DCI5C -10:DCI5/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI5 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI5 淇℃伅瀵勫瓨鍣3 - - DCI5C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI5/DCI5A/DCI5B/DCI5C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI5鐨勫惊鐜Щ浣嶆寚绀 - - - DCI5鐨凜QI鎸囩ず - - - DCI5/DCI5A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI5銆丏CI5A銆丏CI5B TDD銆丏CI5C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI5D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI5 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI5 淇℃伅瀵勫瓨鍣5 - - - DCI5 淇℃伅瀵勫瓨鍣6 - - - DCI5 淇℃伅瀵勫瓨鍣7 - - - DCI5 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI5 淇℃伅瀵勫瓨鍣9 - - - DCI5 淇℃伅瀵勫瓨鍣10 - - - DCI5 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI6杈撳嚭瀵勫瓨鍣1 - - - DCI6杈撳嚭瀵勫瓨鍣2 - - - DCI6鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI6 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI6 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI6A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI6 -1:DCI6 -2:DCI6A -3:DCI6B -4:DCI6C -5:DCI6D -6:DCI6 -7:DCI6A -8:DCI6B -9:DCI6C -10:DCI6/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI6 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI6 淇℃伅瀵勫瓨鍣3 - - DCI6C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI6/DCI6A/DCI6B/DCI6C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI6鐨勫惊鐜Щ浣嶆寚绀 - - - DCI6鐨凜QI鎸囩ず - - - DCI6/DCI6A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI6銆丏CI6A銆丏CI6B TDD銆丏CI6C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI6D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI6 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI6 淇℃伅瀵勫瓨鍣5 - - - DCI6 淇℃伅瀵勫瓨鍣6 - - - DCI6 淇℃伅瀵勫瓨鍣7 - - - DCI6 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI6 淇℃伅瀵勫瓨鍣9 - - - DCI6 淇℃伅瀵勫瓨鍣10 - - - DCI6 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI7杈撳嚭瀵勫瓨鍣1 - - - DCI7杈撳嚭瀵勫瓨鍣2 - - - DCI7鍔熺巼瀵勫瓨鍣 - - DCI鍔熺巼 - - - - DCI7 LLR瀵勫瓨鍣 - - DCI false alarm杞俊鎭负0鐨勪釜鏁 - - - DCI false alarm鐨勮緭鍑洪噸鏋勫樊寮備釜鏁 - - - - DCI7 淇℃伅瀵勫瓨鍣1 - - 澶╃嚎閫夋嫨锛 -0锛氬ぉ绾0 -1锛氬ぉ绾1 - - - DCI7A涓嬶細 -0锛氶潪ORDER -1锛歄RDER - - - SPS-C-RNTI鎸囩ず锛 -0锛氭巿鏉 -1锛氭縺娲 -2锛氶噴鏀 -3锛氭棤鏁 - - - DCI鏍煎紡绫诲瀷锛 -0:DCI7 -1:DCI7 -2:DCI7A -3:DCI7B -4:DCI7C -5:DCI7D -6:DCI7 -7:DCI7A -8:DCI7B -9:DCI7C -10:DCI7/3A - - - 妫鍑篋CI 鎵鐢ㄧ殑RNTI鎸囩ず锛 -0锛歊NTI0锛歋I-RNTI锛 -1锛歊NTI1锛歅-RNTI锛 -2锛歊NTI2锛歊A-RNTI锛 -3锛歊NTI3锛欳-RNTI锛 -4锛歊NTI4锛歋PS-RNTI锛 -5锛歊NTI5锛歍-RNTI锛 -6锛歊NTI6锛歍PCS-RNTI锛 -7锛歊NTI7锛歍PCC-RNTI -8锛歊NTI8锛欸-RNTI -9锛歊NTI9锛歋C-RNTI -10锛歊NTI10锛歋C-N-RNTI - - - 妫鍑篋CI鏄湪COMM杩樻槸UE绌洪棿妫鍑猴細 -0锛氬叕鍏辩┖闂 -1锛歎E绌洪棿 - - - 妫鍑篋CI鏁版嵁鐨勮捣濮嬪湴鍧(index:0~23) - - - 妫鍑篋CI鎵鍦ㄧ殑L绛夌骇鎸囩ず锛 -000锛歀=1; -001锛歀=2; -010锛歀=4; -011锛歀=8; -100锛歀=12; -101锛歀=16; -110锛歀=24; - - - 妫鍑篋CI 闀垮害(max38) - - - - DCI7 淇℃伅瀵勫瓨鍣2 - - 閫夋嫨浣跨敤涓婃姤鐨凱MI锛岃繕鏄夋嫨浣跨敤DCI涓嬪彂鐨凱MI锛 -0锛氶夋嫨浣跨敤DCI涓嬪彂鐨凱MI -1锛氶夋嫨浣跨敤涓婃姤鐨凱MI - - - HARQ杩涚▼:0~15 - - - 棰勭紪鐮佹寚绀猴細tx2:0~3锛宼x4:0~15 - - - 浼犺緭鏂规锛 -0锛氬崟澶╃嚎 -1锛氬彂灏勫垎闆 -2锛氱┖闂村鐢 -3锛歅ORT7 -4锛歅ORT8 -5锛歅ORT5 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛氶泦涓紡 -1锛氬垎甯冨紡 - - - Nscid鐨勫(UE涓氬姟鍔犳壈鐢)锛0~1 - - - 鍐椾綑鐗堟湰锛0~3 - - - 璋冨埗鏍煎紡锛 -0:QPSK -1:16QAM -2:64QAM - - - 浼犺緭鍧楅暱搴︼細max12216 - - - - DCI7 淇℃伅瀵勫瓨鍣3 - - DCI7C涓殑閲嶅娆℃暟鎸囩ず - - - 璋冨埗缂栫爜鏂规 - - - DCI7/DCI7A/DCI7B/DCI7C锛2鐮佸瓧婵娲绘爣蹇楋細 -0锛1鐮佸瓧婵娲 -1锛2鐮佸瓧婵娲 - - - DCI7鐨勫惊鐜Щ浣嶆寚绀 - - - DCI7鐨凜QI鎸囩ず - - - DCI7/DCI7A锛歍B鍒癈W鐨勬槧灏勬槸鍚︿氦鍙夋槧灏勶細 -0锛氭甯告槧灏 -1锛氫氦缁囨槧灏 - - - SRS璇锋眰锛 -SRQ楂樺眰閰嶇疆浜嗙殑鎯呭喌涓嬶細DCI7銆丏CI7A銆丏CI7B TDD銆丏CI7C TDD - - - 鏂版暟鎹弽杞寚绀 - - - DCI7D POWER OFFSET - - - DAI鍩 - - - 鍔熸帶鍙傛暟 - - - - DCI7 淇℃伅瀵勫瓨鍣4 - - 濉厖鍩 - - - 璧勬簮鍒嗛厤绫诲瀷锛 -0锛歍YPE0 -1锛歍YPE1 - - - Type0鐨勮烦棰戞爣蹇楁寚绀 - - - Type0/Type1鐨勮祫婧愬潡鍒嗛厤RBA - - - - DCI7 淇℃伅瀵勫瓨鍣5 - - - DCI7 淇℃伅瀵勫瓨鍣6 - - - DCI7 淇℃伅瀵勫瓨鍣7 - - - DCI7 淇℃伅瀵勫瓨鍣8 - - 鍓0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - DCI7 淇℃伅瀵勫瓨鍣9 - - - DCI7 淇℃伅瀵勫瓨鍣10 - - - DCI7 淇℃伅瀵勫瓨鍣11 - - - - 鍚0.5ms璧勬簮bitmap鎸囩ず锛氬搴攂it琛ㄧず涓嶅悓鐨刾rb[99:96]锛屾瘡涓猙it鐨勬剰涔夊涓嬶細 -0锛氭煇涓猵rb涓嶅崰鐢 -1锛氭煇涓猵rb鍗犵敤 - - - - - - - - - - - - - - - - - - MIB0杈撳嚭瀵勫瓨鍣1 - - MIB0鐨勫 - - - - MIB0INFO瀵勫瓨鍣 - - MIB 瀛愬抚淇℃伅 - - - - MIB1杈撳嚭瀵勫瓨鍣1 - - MIB1鐨勫 - - - - MIB1INFO瀵勫瓨鍣 - - MIB 瀛愬抚淇℃伅 - - - - MIB2杈撳嚭瀵勫瓨鍣1 - - MIB2鐨勫 - - - - MIB2INFO瀵勫瓨鍣 - - MIB 瀛愬抚淇℃伅 - - - - MIB3杈撳嚭瀵勫瓨鍣1 - - MIB3鐨勫 - - - - MIB3INFO瀵勫瓨鍣 - - MIB 瀛愬抚淇℃伅 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 甯у彿閰嶇疆瀵勫瓨鍣 - - CATM妯″紡涓婥ELL RS鍔熺巼璁＄畻鏄惁鍖呭惈OFDM0锛 -0锛氫笉鍖呭惈OFDM0 -1锛氬寘鍚玂FDM0 - - - FFT杩愮畻姣忕骇褰掍竴鍖栨ā寮忛夋嫨锛 -0锛氶《婊℃楂樹綅褰掍竴鍖 -1锛氶《婊℃渶楂樹綅褰掍竴鍖 - - - 0锛欶FT杩愮畻姣忕骇褰掍竴鍖栦笉浣胯兘锛孎FT鍊掓暟绗簩绾ф埅浣嶄娇鑳斤紱 -1锛欶FT杩愮畻姣忕骇褰掍竴鍖栦娇鑳斤紝FFT鍊掓暟绗簩绾ф埅浣嶄笉浣胯兘锛 - - - 0锛欴LFFT瑙﹀彂LDTC1鎴朙DTC鎺у埗淇″彿 -1锛欴LFFT涓嶈Е鍙慙DTC1鎴朙DTC鎺у埗淇″彿 - - - 1锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇浣胯兘锛堝埌TXRX鐨勪腑鏂紝姣忎釜OFDM绗﹀彿杈撳叆鏁版嵁鎼暟瀹屾垚鍚庡彂鍑猴級 -0锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇涓嶄娇鑳 - - - 0:涓诲崱閫夋嫨 -1:杈呭崱閫夋嫨 - - - 绯荤粺甯у彿锛屽彇鍊艰寖鍥0~1023 - - - 瀛愬抚甯у彿锛屽彇鍊艰寖鍥0~9 - - - - CAT1妯″紡RS鎺у埗瀵勫瓨鍣 - - CELL RS鍔熺巼鏈澶у&AGC鍊艰緭鍑洪夋嫨锛 -000锛氶夋嫨绗竴濂楄緭鍑哄瘎瀛樺櫒 -001锛氶夋嫨绗簩濂楄緭鍑哄瘎瀛樺櫒 -010锛氶夋嫨绗笁濂楄緭鍑哄瘎瀛樺櫒 -011锛氶夋嫨绗洓濂楄緭鍑哄瘎瀛樺櫒 -100锛氶夋嫨绗簲濂楄緭鍑哄瘎瀛樺櫒 -鍏朵粬锛氶粯璁ら夋嫨绗竴濂 - - - CAT1妯″紡涓婥ELL RS鍔熺巼璁＄畻鏄惁鍖呭惈OFDM0锛 -0锛氫笉鍖呭惈OFDM0 -1锛氬寘鍚玂FDM0 - - - MBMS涓氬姟瀛愬抚绫诲瀷閫夋嫨锛 -2鈥檅00锛歁BMS涓氬姟瀛愬抚涓病鏈塁ELLRS淇℃伅鐨勭鍙 -2鈥檅01锛歁BMS涓氬姟瀛愬抚涓湁1涓狢ELLRS淇℃伅鐨勭鍙 -2鈥檅10锛歁BMS涓氬姟瀛愬抚涓湁2涓狢ELLRS淇℃伅鐨勭鍙 -2鈥檅11锛氱‖浠朵細榛樿涓00鏉ヨ繘琛屽鐞 - - - 0锛歁BMS涓氬姟瀛愬抚涓嶄娇鑳 -1锛歁BMS涓氬姟瀛愬抚浣胯兘 - - - CELLID搴忓彿鎸囩ず - - - CP绫诲瀷鎸囩ず锛 -0锛歂ORM CP -1锛欵X CP - - - CELLRS PORT绫诲瀷鎸囩ず锛 -2鈥檅00锛歱ort0 -2鈥檅01锛歱ort0/1 -2鈥檅10锛歱ort0/1/2/3 -2鈥檅11锛氫繚鐣欙紝褰揅ELLPORT_SEL閰嶇疆涓2鈥檅11锛氱‖浠朵細榛樿涓2鈥檅00锛坧rot0锛夋潵杩涜澶勭悊 - - - UERS PORT绫诲瀷鎸囩ず锛 -0锛歱ort5 -1锛歱ort7/8 - - - 0锛欳ELLRS鎶藉彇涓嶄娇鑳 -1锛欳ELLRS鎶藉彇浣胯兘 - - - 0锛歎ERS鎶藉彇涓嶄娇鑳 -1锛歎ERS鎶藉彇浣胯兘 - - - - CAT1妯″紡CSIRS鍙傛暟瀵勫瓨鍣 - - 鑻S绫诲瀷涓篊SIRS锛屽垯鎸囩ずCSIRS BITMAP淇℃伅 - - - 鎸囩ずCSIRS鎶藉彇鏃剁浜屼釜CSIRS淇℃伅鐨凮FDM绗﹀彿 - - - 鎸囩ずCSIRS鎶藉彇鏃剁涓涓狢SIRS淇℃伅鐨凮FDM绗﹀彿 - - - - CAT1妯″紡AGC鍙傛暟瀵勫瓨鍣 - - MBMS涓氬姟瀛愬抚鏃堕潪鍚獵ELLRS淇℃伅鐨凮FDM绗﹀彿鐨勮緭鍏GC鍊 - - - 闈濵BMS涓氬姟瀛愬抚鏃惰緭鍏GC鍊兼垨MBMS涓氬姟瀛愬抚鏃跺惈CELLRS淇℃伅鐨凮FDM绗﹀彿鐨勮緭鍏GC鍊 - - - - DLFFT鎺у埗鍙傛暟瀵勫瓨鍣 - - 0锛歅BCH鎶藉彇涓嶄娇鑳 -1锛歅BCH鎶藉彇浣胯兘 - - - 0锛欳SIRS鎶藉彇涓嶄娇鑳 -1锛欳SIRS鎶藉彇浣胯兘 - - - - CAT1妯″紡绯荤粺鍙傛暟瀵勫瓨鍣 - - 绯荤粺甯﹀PRB绱㈠紩鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -111锛氶粯璁6prb - - - 涓婁笅琛岄厤姣旓紝鍙栧艰寖鍥0~6 - - - 0锛歍DD MODE -1锛欶DD MODE - - - 鐗规畩瀛愬抚閰嶇疆 锛屽彇鍊艰寖鍥 0~9 - - - - CAT1妯″紡FFT鍊掓暟绗簩绾чケ鍜岄棬闄愬弬鏁板瘎瀛樺櫒 - - FFT鍊掓暟绗簩绾у垽楗卞拰鐨勯棬闄愪釜鏁板硷紙鍜岀郴缁熷甫瀹芥湁鍏筹級锛岃寖鍥0~4096 - - - - CATM/NB妯″紡绯荤粺鍙傛暟閰嶇疆瀵勫瓨鍣 - - NBIOT鏃讹紝鎸囩ずNB鎵鍦ㄧ殑PRB浣嶇疆锛屽彇鍊艰寖鍥0~5 - - - CP绫诲瀷鎸囩ず锛 -0锛氭櫘閫欳P -1锛氭墿灞旵P - - - 涓婁笅琛岄厤姣旓紝鍙栧艰寖鍥0~6 - - - 0锛歍DD MODE -1锛欶DD MODE - - - 鐗规畩瀛愬抚閰嶇疆 锛屽彇鍊艰寖鍥 0~9 - - - - CATM/NB妯″紡RS鎶藉彇閰嶇疆瀵勫瓨鍣 - - CELL RS鍔熺巼鏈澶у&AGC鍊艰緭鍑洪夋嫨锛 -000锛氶夋嫨绗竴濂楄緭鍑哄瘎瀛樺櫒 -001锛氶夋嫨绗簩濂楄緭鍑哄瘎瀛樺櫒 -010锛氶夋嫨绗笁濂楄緭鍑哄瘎瀛樺櫒 -011锛氶夋嫨绗洓濂楄緭鍑哄瘎瀛樺櫒 -100锛氶夋嫨绗簲濂楄緭鍑哄瘎瀛樺櫒 -鍏朵粬锛氶粯璁ら夋嫨绗竴濂 - - - 0锛歂B妯″紡鏃舵娊鍙朜RS淇″彿 -1锛歂B妯″紡鏃舵娊鍙朇RS淇″彿 - - - 琛ㄧずCELLRS鎴朜RS鐨処D搴忓彿鍊 - - - CELLRS鎴朜RS PORT绫诲瀷鎸囩ず锛 -2鈥檅00锛歱ort0 -2鈥檅01锛歱ort0/1 -2鈥檅10锛歱ort0/1/2/3 -2鈥檅11锛氶粯璁や负2鈥檅10澶勭悊 - - - - CATM/NB妯″紡闆堕閰嶇疆瀵勫瓨鍣 - - 绐勫甫甯﹀鏄惁鍖呭惈闆堕鐐规寚绀猴細 -0锛氫笉鍖呭惈闆堕鐐癸紙鍖呭惈闆朵綅缃級 -1锛氬寘鍚浂棰戠偣锛堣烦寮闆朵綅缃級 - - - - CATM妯″紡AGC鍙傛暟瀵勫瓨鍣 - - CATM妯″紡杈撳叆AGC鍊 - - - - ABIS鍙傛暟閰嶇疆瀵勫瓨鍣 - - 0锛氫紶缁橪DTC1鐨凩LR绉讳綅鍊间负0 -1锛氫紶缁橪DTC1鐨凩LR绉讳綅鍊间负鍘嗗彶鍊 - - - CTCG璧峰浣嶇疆閫夋嫨锛 -0锛氫粠OFDM4(鍖呮嫭OFDM4)鍓嶆湁鏁圕RS涓烘牱鏈 -1锛氫粠OFDM8(鍖呮嫭OFDM8)鍓嶆湁鏁圕RS涓烘牱鏈 - - - 妫娴嬪埌骞叉壈閭诲尯鐨勪釜鏁帮細 -00锛0涓共鎵伴偦鍖 -01锛1涓共鎵伴偦鍖 -10锛2涓共鎵伴偦鍖 -鍏朵粬锛氶粯璁0涓共鎵伴偦鍖 - - - 骞叉壈閭诲尯2鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯1鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯2 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯1 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯2 CELL ID鍊 - - - 骞叉壈閭诲尯1 CELL ID鍊 - - - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - CRS绗﹀彿涓庨潪CRS绗﹀彿鍔熺巼姣斿煎瘎瀛樺櫒 - - - ABIS寮濮嬫悳绱㈠共鎵扮殑璧峰OFDM绗﹀彿鏁帮紙鍙栧艰寖鍥0~13锛 - - - CRS绗﹀彿涓庨潪CRS绗﹀彿鍔熺巼姣斿 - - - - 鍣０鍔熺巼鍊煎瘎瀛樺櫒 - - - 鍣０AGC鍊煎瘎瀛樺櫒 - - 杈撳叆鍣０鍔熺巼AGC鍊 - - - - 妯″潡宸ヤ綔妯″紡閫夋嫨瀵勫瓨鍣 - - 0锛氶夋嫨DLFFT_INFO_OUT1杈撳嚭 -1锛氶夋嫨DLFFT_INFO_OUT2杈撳嚭 - - - DLFFT INFO淇℃伅杈撳叆 - - - 0锛氬抚涓庡抚涔嬮棿姣旇緝CRS_POW_MAX鍊煎ぇ灏忓苟杈撳嚭POW鏈澶у煎拰瀵瑰簲AGC鍊 -1锛氬抚涓庡抚涔嬮棿涓嶆瘮杈僀RS_POW_MAX鍊煎ぇ灏忥紝鍙緭鍑哄綋鍓嶅抚鐨凱OW鏈澶у煎拰瀵瑰簲AGC鍊 - - - 0锛歋OFT_IRT鍔熻兘涓嶄娇鑳 -1锛歋OFT_IRT鍔熻兘浣胯兘 - - - 00锛欳AT1妯″紡 -01锛欳ATM妯″紡 -10锛歂B-IOT妯″紡 -11锛氶粯璁AT1妯″紡 - - - - FFT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~18bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~19bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~20bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~21bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~22bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~23bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~24bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~25bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~26bit - - - - 甯у彿閰嶇疆瀵勫瓨鍣 - - ATM妯″紡涓婥ELL RS鍔熺巼璁＄畻鏄惁鍖呭惈OFDM0锛 -0锛氫笉鍖呭惈OFDM0 -1锛氬寘鍚玂FDM0 - - - FFT杩愮畻姣忕骇褰掍竴鍖栨ā寮忛夋嫨锛 -0锛氶《婊℃楂樹綅褰掍竴鍖 -1锛氶《婊℃渶楂樹綅褰掍竴鍖 - - - 0锛欶FT杩愮畻姣忕骇褰掍竴鍖栦笉浣胯兘锛孎FT鍊掓暟绗簩绾ф埅浣嶄娇鑳斤紱 -1锛欶FT杩愮畻姣忕骇褰掍竴鍖栦娇鑳斤紝FFT鍊掓暟绗簩绾ф埅浣嶄笉浣胯兘锛 - - - 0锛欴LFFT瑙﹀彂LDTC1鎴朙DTC鎺у埗淇″彿 -1锛欴LFFT涓嶈Е鍙慙DTC1鎴朙DTC鎺у埗淇″彿 - - - 1锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇浣胯兘锛堝埌TXRX鐨勪腑鏂紝姣忎釜OFDM绗﹀彿杈撳叆鏁版嵁鎼暟瀹屾垚鍚庡彂鍑猴級 -0锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇涓嶄娇鑳 - - - 0:涓诲崱閫夋嫨 -1:杈呭崱閫夋嫨 - - - 绯荤粺甯у彿锛屽彇鍊艰寖鍥0~1023 - - - 瀛愬抚甯у彿锛屽彇鍊艰寖鍥0~9 - - - - CAT1妯″紡RS鎺у埗瀵勫瓨鍣 - - CELL RS鍔熺巼鏈澶у&AGC鍊艰緭鍑洪夋嫨锛 -000锛氶夋嫨绗竴濂楄緭鍑哄瘎瀛樺櫒 -001锛氶夋嫨绗簩濂楄緭鍑哄瘎瀛樺櫒 -010锛氶夋嫨绗笁濂楄緭鍑哄瘎瀛樺櫒 -011锛氶夋嫨绗洓濂楄緭鍑哄瘎瀛樺櫒 -100锛氶夋嫨绗簲濂楄緭鍑哄瘎瀛樺櫒 -鍏朵粬锛氶粯璁ら夋嫨绗竴濂 - - - CELL RS鍔熺巼璁＄畻鏄惁鍖呭惈OFDM0锛 -0锛氫笉鍖呭惈OFDM0 -1锛氬寘鍚玂FDM0 - - - MBMS涓氬姟瀛愬抚绫诲瀷閫夋嫨锛 -2鈥檅00锛歁BMS涓氬姟瀛愬抚涓病鏈塁ELLRS淇℃伅鐨勭鍙 -2鈥檅01锛歁BMS涓氬姟瀛愬抚涓湁1涓狢ELLRS淇℃伅鐨勭鍙 -2鈥檅10锛歁BMS涓氬姟瀛愬抚涓湁2涓狢ELLRS淇℃伅鐨勭鍙 -2鈥檅11锛氱‖浠朵細榛樿涓00鏉ヨ繘琛屽鐞 - - - 0锛歁BMS涓氬姟瀛愬抚涓嶄娇鑳 -1锛歁BMS涓氬姟瀛愬抚浣胯兘 - - - CELLID搴忓彿鎸囩ず - - - CP绫诲瀷鎸囩ず锛 -0锛歂ORM CP -1锛欵X CP - - - CELLRS PORT绫诲瀷鎸囩ず锛 -2鈥檅00锛歱ort0 -2鈥檅01锛歱ort0/1 -2鈥檅10锛歱ort0/1/2/3 -2鈥檅11锛氫繚鐣欙紝褰揅ELLPORT_SEL閰嶇疆涓2鈥檅11锛氱‖浠朵細榛樿涓2鈥檅00锛坧rot0锛夋潵杩涜澶勭悊 - - - UERS PORT绫诲瀷鎸囩ず锛 -0锛歱ort5 -1锛歱ort7/8 - - - 0锛欳ELLRS鎶藉彇涓嶄娇鑳 -1锛欳ELLRS鎶藉彇浣胯兘 - - - 0锛歎ERS鎶藉彇涓嶄娇鑳 -1锛歎ERS鎶藉彇浣胯兘 - - - - CAT1妯″紡CSIRS鍙傛暟瀵勫瓨鍣 - - 鑻S绫诲瀷涓篊SIRS锛屽垯鎸囩ずCSIRS BITMAP淇℃伅 - - - 鎸囩ずCSIRS鎶藉彇鏃剁浜屼釜CSIRS淇℃伅鐨凮FDM绗﹀彿 - - - 鎸囩ずCSIRS鎶藉彇鏃剁涓涓狢SIRS淇℃伅鐨凮FDM绗﹀彿 - - - - CAT1妯″紡AGC鍙傛暟瀵勫瓨鍣 - - MBMS涓氬姟瀛愬抚鏃堕潪鍚獵ELLRS淇℃伅鐨凮FDM绗﹀彿鐨勮緭鍏GC鍊 - - - 闈濵BMS涓氬姟瀛愬抚鏃惰緭鍏GC鍊兼垨MBMS涓氬姟瀛愬抚鏃跺惈CELLRS淇℃伅鐨凮FDM绗﹀彿鐨勮緭鍏GC鍊 - - - - DLFFT鎺у埗鍙傛暟瀵勫瓨鍣 - - 0锛歅BCH鎶藉彇涓嶄娇鑳 -1锛歅BCH鎶藉彇浣胯兘 - - - 0锛欳SIRS鎶藉彇涓嶄娇鑳 -1锛欳SIRS鎶藉彇浣胯兘 - - - - CAT1妯″紡绯荤粺鍙傛暟瀵勫瓨鍣 - - 绯荤粺甯﹀PRB绱㈠紩鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -111锛氶粯璁6prb - - - 涓婁笅琛岄厤姣旓紝鍙栧艰寖鍥0~6 - - - 0锛歍DD MODE -1锛欶DD MODE - - - 鐗规畩瀛愬抚閰嶇疆 锛屽彇鍊艰寖鍥 0~9 - - - - CAT1妯″紡FFT鍊掓暟绗簩绾чケ鍜岄棬闄愬弬鏁板瘎瀛樺櫒 - - FFT鍊掓暟绗簩绾у垽楗卞拰鐨勯棬闄愪釜鏁板硷紙鍜岀郴缁熷甫瀹芥湁鍏筹級锛岃寖鍥0~4096 - - - - CATM/NB妯″紡绯荤粺鍙傛暟閰嶇疆瀵勫瓨鍣 - - NBIOT鏃讹紝鎸囩ずNB鎵鍦ㄧ殑PRB浣嶇疆锛屽彇鍊艰寖鍥0~5 - - - CP绫诲瀷鎸囩ず锛 -0锛氭櫘閫欳P -1锛氭墿灞旵P - - - 涓婁笅琛岄厤姣旓紝鍙栧艰寖鍥0~6 - - - 0锛歍DD MODE -1锛欶DD MODE - - - 鐗规畩瀛愬抚閰嶇疆 锛屽彇鍊艰寖鍥 0~9 - - - - CATM/NB妯″紡RS鎶藉彇閰嶇疆瀵勫瓨鍣 - - CELL RS鍔熺巼鏈澶у&AGC鍊艰緭鍑洪夋嫨锛 -000锛氶夋嫨绗竴濂楄緭鍑哄瘎瀛樺櫒 -001锛氶夋嫨绗簩濂楄緭鍑哄瘎瀛樺櫒 -010锛氶夋嫨绗笁濂楄緭鍑哄瘎瀛樺櫒 -011锛氶夋嫨绗洓濂楄緭鍑哄瘎瀛樺櫒 -100锛氶夋嫨绗簲濂楄緭鍑哄瘎瀛樺櫒 -鍏朵粬锛氶粯璁ら夋嫨绗竴濂 - - - 0锛歂B妯″紡鏃舵娊鍙朜RS淇″彿 -1锛歂B妯″紡鏃舵娊鍙朇RS淇″彿 - - - 琛ㄧずCELLRS鎴朜RS鐨処D搴忓彿鍊 - - - CELLRS鎴朜RS PORT绫诲瀷鎸囩ず锛 -2鈥檅00锛歱ort0 -2鈥檅01锛歱ort0/1 -2鈥檅10锛歱ort0/1/2/3 -2鈥檅11锛氶粯璁や负2鈥檅10澶勭悊 - - - - CATM/NB妯″紡闆堕閰嶇疆瀵勫瓨鍣 - - 绐勫甫甯﹀鏄惁鍖呭惈闆堕鐐规寚绀猴細 -0锛氫笉鍖呭惈闆堕鐐癸紙鍖呭惈闆朵綅缃級 -1锛氬寘鍚浂棰戠偣锛堣烦寮闆朵綅缃級 - - - - CATM妯″紡AGC鍙傛暟瀵勫瓨鍣 - - CATM妯″紡杈撳叆AGC鍊 - - - - ABIS鍙傛暟閰嶇疆瀵勫瓨鍣 - - 0锛氫紶缁橪DTC1鐨凩LR绉讳綅鍊间负0 -1锛氫紶缁橪DTC1鐨凩LR绉讳綅鍊间负鍘嗗彶鍊 - - - CTCG璧峰浣嶇疆閫夋嫨锛 -0锛氫粠OFDM4(鍖呮嫭OFDM4)鍓嶆湁鏁圕RS涓烘牱鏈 -1锛氫粠OFDM8(鍖呮嫭OFDM8)鍓嶆湁鏁圕RS涓烘牱鏈 - - - 妫娴嬪埌骞叉壈閭诲尯鐨勪釜鏁帮細 -00锛0涓共鎵伴偦鍖 -01锛1涓共鎵伴偦鍖 -10锛2涓共鎵伴偦鍖 -鍏朵粬锛氶粯璁0涓共鎵伴偦鍖 - - - 骞叉壈閭诲尯2鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯1鍙戝皠澶╃嚎鏁帮細 -00锛1port -01锛2port -10锛4port -鍏朵粬锛氶粯璁1port - - - 骞叉壈閭诲尯2 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯1 绯荤粺甯﹀鍊硷細 -000锛6prb -001锛15prb -010锛25prb -011锛50prb -100锛75prb -101锛100prb -鍏朵粬锛氶粯璁6prb - - - 骞叉壈閭诲尯2 CELL ID鍊 - - - 骞叉壈閭诲尯1 CELL ID鍊 - - - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯1鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊煎瘎瀛樺櫒 - - 骞叉壈閭诲尯2鐩稿鏈尯鏃跺欢鍊硷紙鍗曚綅TS锛 - - - - CRS绗﹀彿涓庨潪CRS绗﹀彿鍔熺巼姣斿煎瘎瀛樺櫒 - - ABIS LLR淇鍊硷紙鍙栧艰寖鍥-8~8锛 - - - ABIS寮濮嬫悳绱㈠共鎵扮殑璧峰OFDM绗﹀彿鏁帮紙鍙栧艰寖鍥0~13锛 - - - CRS绗﹀彿涓庨潪CRS绗﹀彿鍔熺巼姣斿 - - - - 鍣０鍔熺巼鍊煎瘎瀛樺櫒 - - - 鍣０AGC鍊煎瘎瀛樺櫒 - - 鍣０AGC鍊 - - - - 妯″潡宸ヤ綔妯″紡閫夋嫨瀵勫瓨鍣 - - 0锛氶夋嫨DLFFT_INFO_OUT1杈撳嚭 -1锛氶夋嫨DLFFT_INFO_OUT2杈撳嚭 - - - DLFFT INFO淇℃伅杈撳叆 - - - 0锛氬抚涓庡抚涔嬮棿姣旇緝CRS_POW_MAX鍊煎ぇ灏忓苟杈撳嚭POW鏈澶у煎拰瀵瑰簲AGC鍊 -1锛氬抚涓庡抚涔嬮棿涓嶆瘮杈僀RS_POW_MAX鍊煎ぇ灏忥紝鍙緭鍑哄綋鍓嶅抚鐨凱OW鏈澶у煎拰瀵瑰簲AGC鍊 - - - 0锛歋OFT_IRT鍔熻兘涓嶄娇鑳 -1锛歋OFT_IRT鍔熻兘浣胯兘 - - - 00锛欳AT1妯″紡 -01锛欳ATM妯″紡 -10锛歂B-IOT妯″紡 -11锛氶粯璁AT1妯″紡 - - - - FFT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~18bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~19bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~20bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~21bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~22bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~23bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~24bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~25bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~26bit - - - - DLFFT涓柇浣胯兘鎺у埗瀵勫瓨鍣 - - 1锛氬鐢ㄩ敊璇腑鏂3浣胯兘 -0锛氬鐢ㄩ敊璇腑鏂3涓嶄娇鑳 - - - 1锛氬鐢ㄩ敊璇腑鏂2浣胯兘 -0锛氬鐢ㄩ敊璇腑鏂2涓嶄娇鑳 - - - 1锛欼DDET Online&Offline鍐茬獊閿欒涓柇浣胯兘 -0锛欼DDET Online&Offline鍐茬獊閿欒涓柇涓嶄娇鑳 - - - 1锛歊XCAPT閿欒涓柇浣胯兘 -0锛歊XCAPT閿欒涓柇涓嶄娇鑳 - - - 1锛歊F鏃犳暟鎹腑鏂娇鑳 -0锛歊F鏃犳暟鎹腑鏂笉浣胯兘 - - - 1锛氭娴嬩笂琛孯F椹卞姩閰嶇疆寮傚父涓柇浣胯兘 -0锛氭娴嬩笂琛孯F椹卞姩閰嶇疆寮傚父涓柇涓嶄娇鑳 - - - 1锛氭娴嬩笅琛孯F椹卞姩閰嶇疆寮傚父涓柇浣胯兘 -0锛氭娴嬩笅琛孯F椹卞姩閰嶇疆寮傚父涓柇涓嶄娇鑳 - - - 1锛氭娴婻F灏戞敹鏁版嵁涓柇浣胯兘 -0锛氭娴婻F灏戞敹鏁版嵁涓柇涓嶄娇鑳 - - - 1锛氭娴婻F澶氭敹鏁版嵁涓柇浣胯兘 -0锛氭娴婻F澶氭敹鏁版嵁涓柇涓嶄娇鑳 - - - 1锛欰XIDMA涓柇浣胯兘锛堥佺粰 -AXIDMA锛孌LFFT鐨勬渶鍚庝竴涓 -OFDM瀹屾垚鍚庡彂鍑猴級 -0锛欰XIDMA涓柇涓嶄娇鑳 - - - 1锛欴LFFT璁块棶TXRX or LDTC or LDTC1瀛樺偍鍣‥RROR涓柇浣胯兘 -0锛欴LFFT璁块棶TXRX or LDTCor LDTC1瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 - - - 1锛欴LFFT涓柇浣胯兘锛堝埌鏍哥殑涓柇锛屾渶鍚庝竴涓狾FDM瀹屾垚鍚庡彂鍑猴級 -0锛欴LFFT涓柇涓嶄娇鑳 - - - 1锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇浣胯兘锛堝埌TXRX鐨勪腑鏂紝姣忎釜OFDM绗﹀彿杈撳叆鏁版嵁鎼暟瀹屾垚鍚庡彂鍑猴級 -0锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇涓嶄娇鑳 - - - - CATM/NB妯″紡FFT鍊掓暟绗簩绾чケ鍜岄棬闄愬弬鏁板瘎瀛樺櫒 - - FFT鍊掓暟绗簩绾у垽楗卞拰鐨勯棬闄愪釜鏁板硷紝鑼冨洿0~4096 - - - - 妯″潡鍚姩瀵勫瓨鍣 - - 0: CATM/NB妯″紡鏈ā鍧椾笉鍚姩 -1: CATM/NB妯″紡鏈ā鍧楀惎鍔 - - - 0: CAT1妯″紡鏈ā鍧椾笉鍚姩 -1: CAT1妯″紡鏈ā鍧楀惎鍔 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 1锛氬鐢ㄩ敊璇腑鏂3鏍囧織缃綅 -0锛氬鐢ㄩ敊璇腑鏂3鏍囧織鏈疆浣 - - - 1锛氬鐢ㄩ敊璇腑鏂2鏍囧織缃綅 -0锛氬鐢ㄩ敊璇腑鏂2鏍囧織鏈疆浣 - - - 1锛欼DDET Online&Offline鍐茬獊閿欒涓柇鏍囧織缃綅 -0锛欼DDET Online&Offline鍐茬獊閿欒涓柇鏍囧織鏈疆浣 - - - 1锛歊XCAPT閿欒涓柇鏍囧織缃綅 -0锛歊XCAPT閿欒涓柇鏍囧織鏈疆浣 - - - 1锛歁EASPWR閿欒涓柇鏍囧織缃綅 -0锛 MEASPWR閿欒涓柇鏍囧織鏈疆浣 - - - 1锛歊F鏃犳暟鎹腑鏂爣蹇楃疆浣 -0锛歊F鏃犳暟鎹腑鏂爣蹇楁湭缃綅 - - - 1锛歋D璁块棶DLFFT瀛樺偍鍣ㄩ敊璇腑鏂爣蹇楃疆浣 -0锛歋D璁块棶DLFFT瀛樺偍鍣ㄩ敊璇腑鏂爣蹇楁湭缃綅 - - - 1锛欳OEFF璁块棶LDTC涓柇鏍囧織缃綅 -0锛欳OEFF璁块棶LDTC涓柇鏍囧織鏈疆浣 - - - 1锛欳OEFF璁块棶LDTC1涓柇鏍囧織缃綅 -0锛欳OEFF璁块棶LDTC1涓柇鏍囧織鏈疆浣 - - - 1锛氫笂琛孯F椹卞姩閰嶇疆寮傚父涓柇鏍囧織缃綅 -0锛氫笂琛孯F椹卞姩閰嶇疆寮傚父涓柇鏍囧織鏈疆浣 - - - 1锛氫笅琛孯F椹卞姩閰嶇疆寮傚父涓柇鏍囧織缃綅 -0锛氫笅琛孯F椹卞姩閰嶇疆寮傚父涓柇鏍囧織鏈疆浣 - - - 1锛歊F灏戞敹鏁版嵁涓柇鏍囧織缃綅 -0锛歊F灏戞敹鏁版嵁涓柇鏍囧織鏈疆浣 - - - 1锛歊F澶氭敹鏁版嵁涓柇鏍囧織缃綅 -0锛歊F澶氭敹鏁版嵁涓柇鏍囧織鏈疆浣 - - - 1锛欰XIDMA涓柇鏍囧織缃綅锛堥佺粰AXIDMA锛孌LFFT鐨勬渶鍚庝竴涓狾FDM瀹屾垚鍚庡彂鍑猴級 -0锛欰XIDMA涓柇鏈疆浣 - - - 1锛氬啓CSI瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氬啓CSI瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - 1锛氬啓MMSE瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氬啓MMSE瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - 1锛氬啓LDTC瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氬啓LDTC瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - 1锛氳TXRX瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氳TXRX瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - 1锛欴LFFT涓柇鏍囧織缃綅锛堝埌鏍哥殑涓柇鏍囧織锛屾渶鍚庝竴涓狾FDM瀹屾垚鍚庤繘琛岀疆浣嶏級 -0锛欴LFFT涓柇鏍囧織鏈疆浣 - - - 1锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇鏍囧織缃綅锛堝埌TXRX鐨勪腑鏂爣蹇楋紝姣忎釜OFDM 绗﹀彿杈撳叆鏁版嵁鎼暟瀹屾垚鍚庤繘琛岀疆浣嶏級 -0锛欴LFFT杈撳叆鎼暟瀹屾垚涓柇鏍囧織鏈疆浣 - - - - OFDM绗﹀彿璁℃暟瀵勫瓨鍣 - - 鎸囩ず褰撳墠鐨凮FDM绗﹀彿鏁帮紝鑼冨洿0~13 - - - - 涓昏緟鍗¤緭鍑哄瘎瀛樺櫒 - - DLFFT INFO淇℃伅杈撳嚭 2 - - - DLFFT INFO淇℃伅杈撳嚭 1 - - - 0锛氫富鍗″畬鎴 -1锛氳緟鍗″畬鎴 - - - - ABIS骞叉壈绫诲瀷1绉讳綅鍊艰緭鍑哄瘎瀛樺櫒 - - ABIS骞叉壈绫诲瀷1锛堥偦鍖1锛夌Щ浣嶅 - - - - ABIS骞叉壈绫诲瀷2绉讳綅鍊艰緭鍑哄瘎瀛樺櫒 - - ABIS骞叉壈绫诲瀷2锛堥偦鍖2锛夌Щ浣嶅 - - - - ABIS骞叉壈绫诲瀷3绉讳綅鍊艰緭鍑哄瘎瀛樺櫒 - - ABIS骞叉壈绫诲瀷3锛堥偦鍖1+2锛夌Щ浣嶅 - - - - CELLRS鍔熺巼鏈澶у艰緭鍑哄瘎瀛樺櫒 - - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭瀵勫瓨鍣 - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭鍊 - - - - CELLRS鍔熺巼鏈澶у艰緭鍑哄瘎瀛樺櫒 - - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭瀵勫瓨鍣 - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭鍊 - - - - CELLRS鍔熺巼鏈澶у艰緭鍑哄瘎瀛樺櫒 - - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭瀵勫瓨鍣 - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭鍊 - - - - CELLRS鍔熺巼鏈澶у艰緭鍑哄瘎瀛樺櫒 - - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭瀵勫瓨鍣 - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭鍊 - - - - CELLRS鍔熺巼鏈澶у艰緭鍑哄瘎瀛樺櫒 - - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭瀵勫瓨鍣 - - CELLRS鍔熺巼鏈澶у糀GC杈撳嚭鍊 - - - - 妯″潡鐘舵佹満杈撳嚭瀵勫瓨鍣 - - - TXRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑哄瘎瀛樺櫒1 - - OFDM 7鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 6鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 5鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 4鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 3鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 2鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 1鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 0鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - - TXRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑哄瘎瀛樺櫒1 - - OFDM 13鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 12鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 11鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 10鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 9鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - OFDM 8鐨凾XRX妯″潡褰掍竴鍖栧洜瀛愯緭鍑 - - - - TXRX妯″潡SOFT IRT鍥犲瓙杈撳嚭瀵勫瓨鍣 - - TXRX妯″潡SOFT IRT鍥犲瓙1杈撳嚭 - - - TXRX妯″潡SOFT IRT鍥犲瓙0杈撳嚭 - - - - OFDM绗﹀彿璁℃暟瀵勫瓨鍣 - - ASSERT鍙戠敓鏃堕噰鍒扮殑TXRX_ENABLE淇″彿鍊 - - - ASSERT鍙戠敓鏃跺綋鍓嶇殑OFDM绗﹀彿鏁帮紝鑼冨洿0~13 - - - - 鐘舵佹満杈撳嚭瀵勫瓨鍣 - - - ABIS瀹炴椂璁＄畻鏍囧織瀵勫瓨鍣 - - 0锛欰BIS褰撳墠甯ф棤娉曞畬鎴怢LR_OUT3瀹炴椂璁＄畻 -1锛欰BIS褰撳墠甯у畬鎴怢LR_OUT3瀹炴椂璁＄畻 - - - 0锛欰BIS褰撳墠甯ф棤娉曞畬鎴怢LR_OUT2瀹炴椂璁＄畻 -1锛欰BIS褰撳墠甯у畬鎴怢LR_OUT2瀹炴椂璁＄畻 - - - 0锛欰BIS褰撳墠甯ф棤娉曞畬鎴怢LR_OUT1瀹炴椂璁＄畻 -1锛欰BIS褰撳墠甯у畬鎴怢LR_OUT1瀹炴椂璁＄畻 - - - - - - - - - 鍚姩瀵勫瓨鍣 - - Coeff杈撳嚭鑷砿eas浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Coeff杈撳嚭鑷砽dtc\ldtc1浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Coeff杈撳嚭鑷砽dtc\ldtc1 buf閫夋嫨浣 -00锛氳緭鍑簂dtc buf1 -01锛氳緭鍑簂dtc buf2 -10锛氳緭鍑簂dtc buf3 -11锛氭棤鏁堝 - - - CAT1鍜孋ATM妯″紡閫夋嫨 -0锛欳ATM妯 -1锛欳AT1妯 - - - 蹇熻緭鍑烘ā寮 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - Port閫夋嫨浣 -0锛氶夋嫨Port78 -1锛氶夋嫨Port5 - - - 涓柇浣胯兘淇″彿锛 -0锛歈FQT涓柇涓嶄娇鑳 -1锛歈FQT涓柇浣胯兘 - - - 妯″紡閫夋嫨锛 -0: NCP -1: ECP - - - 妯″潡浣胯兘淇″彿锛 -0: QFQT妯″潡涓嶄娇鑳 -1: QFQT妯″潡浣胯兘 - - - - 涓柇鐘舵佸瘎瀛樺櫒 - - 璇诲啓buf鍐茬獊鐨勬潵婧 -00锛氭潵鑷猯dtc buf1 -01锛氭潵鑷猯dtc buf2 -10锛氭潵鑷猯dtc buf3 -11锛氭潵鑷猰eas buf - - - 鍐茬獊鏍囧織 - - - 涓柇鐘舵 -0: 鏈畬鎴愮郴鏁扮煩闃垫眰閫 -1: 瀹屾垚绯绘暟鐭╅樀姹傞 - - - - QF鍙傛暟閰嶇疆瀵勫瓨鍣(鍦ㄩ厤缃甉T_CONF涔嬪墠杩涜閰嶇疆) - - 绯荤粺甯﹀閫夋嫨 -000: 6PRB -001: 15PRB -010: 25PRB -011: 50PRB -100: 75PRB -101: 100PRB -Others: RESERVED 6PRB - - - 淇″櫔姣 - - - 淇￠亾绫诲瀷 -00: EPA -01: EVA -10: ETU -11: RESERVED EPA - - - - QT鍙傛暟閰嶇疆瀵勫瓨鍣(鍦ㄩ厤缃甉F_CONF涔嬪悗杩涜閰嶇疆) - - 澶氭櫘鍕掑 -00锛5 -01锛70 -10锛300 -11: 850 - - - TDD銆丗DD妯″紡閫夋嫨 -0锛歍DD -1锛欶DD - - - 淇″櫔姣 - - - 鐗规畩瀛愬抚鎸囩ず -0000锛歋S0 -0001锛歋S1 -0010锛歋S2 -0011锛歋S3 -0100锛歋S4 -0101锛歋S5 -0110锛歋S6 -0111锛歋S7 -1000锛歋S8 -1001锛歋S9 - - - - 杞欢杈撳叆瀵勫瓨鍣 - - 杞欢杈撳叆瀵勫瓨鍣 - - - - 杞欢杈撳嚭瀵勫瓨鍣 - - 杞欢杈撳嚭瀵勫瓨鍣 - - - - - - - - - 妯″潡浣胯兘瀵勫瓨鍣 - - 涓婅瀹氭椂鐢佃矾浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 涓嬭瀹氭椂鐢佃矾浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - - RAM鍦板潃鏄犲皠瀵勫瓨鍣 - - 涓婅RAM3锛堟寚浠AM锛夌殑鍋忕Щ鍦板潃 -锛圧AM3璧峰鍦板潃涓256+鍋忕Щ鍦板潃锛 - - - 涓婅RAM2锛圫PI RAM锛夌殑璧峰鍦板潃 - - - 涓嬭RAM3锛堟寚浠AM锛夌殑鍋忕Щ鍦板潃 -锛圧AM3璧峰鍦板潃涓256+鍋忕Щ鍦板潃锛 - - - 涓嬭RAM2锛圫PI RAM锛夌殑璧峰鍦板潃 - - - - GPO绔嬪嵆璧锋晥瀵勫瓨鍣 - - 涓婁笅琛屼娇鑳芥帶鍒堕夋嫨 -1锛氭湰娆℃搷浣滀负涓婅鎺у埗 -0锛氭湰娆℃搷浣滀负涓嬭鎺у埗 - - - SPI閫夋嫨鎺у埗 -1锛氭湰娆″彂閫佹暟鎹负SPI -0锛氭湰娆″彂閫佹暟鎹负GPO - - - SPI璇诲啓鎺у埗 -1锛氭湰娆PI鎿嶄綔涓鸿鎿嶄綔 -0锛氭湰娆PI鎿嶄綔涓哄啓鎿嶄綔 - - - 鎺у埗灏勯鑺墖鐨勭洿鎺ョ嚎 - - - - 鐩存帴鍙戦佺殑RFSPI鏁版嵁瀵勫瓨鍣 - - - SPI 鎺у埗瀵勫瓨鍣 - - 涓ゆ鐩搁偦SPI鎿嶄綔锛孲EN鏃犳晥闇瑕佷繚璇佺殑鏈灏忔椂闂达紙SCLK鏃堕挓涓暟鐨勪竴鍗婏級 - - - SPI璇绘椂閽熶骇鐢熷垎棰戠郴鏁版帶鍒讹細 -000锛4 -001锛6锛坉efault锛 -010锛8 -011锛10 -100锛12 -101锛14 -110锛16 -111锛18 - - - SPI鍐欐椂閽熶骇鐢熷垎棰戠郴鏁版帶鍒讹細 -000锛4 -001锛6锛坉efault锛 -010锛8 -011锛10 -100锛12 -101锛14 -110锛16 -111锛18 - - - 鍗婂弻宸ヨ鏁版嵁鏃剁墖閫変俊鍙峰弽鐩镐娇鑳斤紙鍖呮嫭4-W锛3-W鍒剁殑鍗婂弻宸ヨ锛 -0锛氫笉鍙嶇浉 -1锛氬弽鐩 - - - 鍙屽伐妯″紡閫夋嫨锛堟浣嶄粎鍦 17bit閫変负4绾垮埗鏃舵湁鏁堬級 -0锛氬崐鍙屽伐 -1锛氬叏鍙屽伐 - - - SPI鎺ユ敹鏁版嵁鏃舵ā寮忛夋嫨浣嶏細 -0锛3绾挎ā寮忥紙鍙敮鎸佸崐鍙屽伐璇伙級锛 -1锛4绾挎ā寮忥紱 - - - SPI鍗婂弻宸ヨ鏁版嵁鏃堕夋嫨闂撮殧绗嚑涓猄PI閲囨牱鏃堕挓鐨勬暟鎹湁鏁 -00:0涓椂閽 -01:1涓椂閽 -10:2涓椂閽 -11:3涓椂閽 - - - 璇绘暟鎹噰鏍锋部 -0锛氱浉鍙嶆部閲囨暟鎹紝涓庡彂閫佹部涓虹浉鍙嶆部锛堝叏鍙屽伐鏃跺繀椤讳负0锛 -1锛氬悓娌块噰鏁版嵁锛屼笌鍙戦佹部涓哄悓涓涓部 - - - 鐗囬変娇鑳芥帶鍒堕夋嫨 -0锛氱墖閫夊湪鏃堕挓涔嬪墠鏈夋晥锛圢ormal SPI锛 -1锛氱墖閫夊湪鏃堕挓涔嬪悗鏈夋晥锛圖igRF SPI锛 - - - SPI鏃堕挓鐩镐綅鎺у埗锛 -0: 鏁版嵁閲囨牱鍙戠敓鍦ㄦ椂閽熺殑濂囨暟娌匡紱 -锛堝閮ㄨ姱鐗囧湪濂囨暟娌块噰鏁帮紝1寮濮嬭鏁帮級; -1: 鏁版嵁閲囨牱鍙戠敓鍦ㄦ椂閽熺殑鍋舵暟娌匡紱 -锛堝閮ㄨ姱鐗囧湪鍋舵暟娌块噰鏁帮級; - - - SPI鏃堕挓鏋佹ф帶鍒讹細 -0: SPI鎺ュ彛鍦↖DLE鐘舵佹椂锛屾椂閽熶负浣庣數骞筹紱 -1: SPI鎺ュ彛鍦↖DLE鐘舵佹椂锛屾椂閽熶负楂樼數骞筹紱 - - - SPI鐗囬夋瀬鎬ф帶鍒讹細 -0: SPI鐗囬変綆鏈夋晥锛 -1: SPI鐗囬夐珮鏈夋晥 - - - SPI鎺ユ敹鏁版嵁闀垮害锛堝彧鍖呮嫭鏁版嵁浣嶏級锛 -00000: 1-bits -00001: 2-bits -鈥........... -11111: 32-bits - - - SPI鍙戦佹暟鎹暱搴︼細锛堝寘鎷鍐欐瘮鐗广佸湴鍧浣嶅拰鏁版嵁浣嶏級锛 -00000: 1-bits -00001: 2-bits -鈥........... -11111: 32-bits - - - - SPI 鎺ユ敹鏁版嵁瀵勫瓨鍣 - - - DEBUG瀵勫瓨鍣 - - 涓婅瀹氭椂閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 涓婅绂佹鎻掗槦閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 0锛歊AM鍦板潃瓒呯晫閿欒鏈彂鐢 -1锛歊AM鍦板潃瓒呯晫閿欒宸插彂鐢 - - - 0锛氬畾鏃舵椂闂磋秴闄愰敊璇湭鍙戠敓 -1锛氬畾鏃舵椂闂磋秴闄愰敊璇凡鍙戠敓 -锛堝瓙甯у彿涓嶆槸0xf涓斿ぇ浜0xA锛 - - - 涓婅RAM璇诲湴鍧 - - - 涓嬭瀹氭椂閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 涓嬭绂佹鎻掗槦閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 0锛歊AM鍦板潃瓒呯晫閿欒鏈彂鐢 -1锛歊AM鍦板潃瓒呯晫閿欒宸插彂鐢 - - - 0锛氬畾鏃舵椂闂磋秴闄愰敊璇湭鍙戠敓 -1锛氬畾鏃舵椂闂磋秴闄愰敊璇凡鍙戠敓 -锛堝瓙甯у彿涓嶆槸0xf涓斿ぇ浜0xA锛 - - - 涓嬭RAM璇诲湴鍧 - - - - RF GPO control register - - - RFAD甯ч暱鎺у埗瀵勫瓨鍣 - - 绂佹鎻掗槦鏈哄埗浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 涓婅甯ч暱浣胯兘 - - - 涓嬭甯ч暱浣胯兘 - - - RFAD甯ч暱鍊 - - - - 涓婅瀹氭椂閿欒鏃禙RAMC鍊煎瘎瀛樺櫒 - - 涓婅瀹氭椂閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 涓婅瀹氭椂閿欒鏃禙RAMC鍊 - - - - 涓婅瀹氭椂閿欒鏃跺畾鏃舵椂闂村瘎瀛樺櫒 - - 涓婅瀹氭椂閿欒鏃跺畾鏃朵簨浠跺湴鍧 - - - 涓婅瀹氭椂閿欒鏃跺畾鏃舵椂闂村 - - - - 涓嬭瀹氭椂閿欒鏃禙RAMC鍊煎瘎瀛樺櫒 - - 涓嬭瀹氭椂閿欒鏍囪瘑 -1锛氭湁閿欒 -0锛氭棤閿欒 - - - 涓嬭瀹氭椂閿欒鏃禙RAMC鍊 - - - - 涓嬭瀹氭椂閿欒鏃跺畾鏃舵椂闂村瘎瀛樺櫒 - - 涓嬭瀹氭椂閿欒鏃跺畾鏃朵簨浠跺湴鍧 - - - 涓嬭瀹氭椂閿欒鏃跺畾鏃舵椂闂村 - - - - 瀹氭椂閿欒鏃禙RAML鍊肩姸鎬佸瘎瀛樺櫒 - - 涓婅瀹氭椂閿欒鏃禙RAML鍊 - - - 涓嬭瀹氭椂閿欒鏃禙RAML鍊 - - - - 涓婅绂佹鎻掗槦閿欒鐘舵佸瘎瀛樺櫒 - - 涓婅鎻掗槦閿欒鏃跺畾鏃朵簨浠跺湴鍧 - - - 涓婅鎻掗槦閿欒鏃禙RAMC鍊 - - - - 涓嬭绂佹鎻掗槦閿欒鐘舵佸瘎瀛樺櫒 - - 涓嬭鎻掗槦閿欒鏃跺畾鏃朵簨浠跺湴鍧 - - - 涓嬭鎻掗槦閿欒鏃禙RAMC鍊 - - - - - 涓嬭瀛樺偍鍣 - - - - 涓婅瀛樺偍鍣 - - - - - - - - DFT/IDFT鎺у埗瀵勫瓨鍣 - - 0锛欰NTI_DROP鍔熻兘涓嶄娇鑳 -1锛欰NTI_DROP鍔熻兘浣胯兘 - - - ANTI_DROP鍔熻兘鎴綅鍥犲瓙: -0锛氬彸绉8bit -1锛氬彸绉7bit - - - DFT/IDFT鐐规暟閫夋嫨鐨刬ndex锛0~43鍒嗗埆鎸囩ず44绉嶇偣鏁帮紝index涓庡疄闄呯偣鏁扮殑瀵瑰簲鍏崇郴濡備笅琛ㄨ鏄 锛堜笉鍙厤缃叾浠栧硷級 - - - 00: BPSK璋冨埗鏂瑰紡 -01: QPSK璋冨埗鏂瑰紡 -10: 16QAM璋冨埗鏂瑰紡 -11: 64QAM璋冨埗鏂瑰紡 - - - 0锛欴FT/IDFT鍔熻兘涓嶄娇鑳 -1锛欴FT/IDFT鍔熻兘浣胯兘 - - - 0锛歅USCH璋冨埗鍔熻兘涓嶄娇鑳 -1锛歅USCH璋冨埗鍔熻兘浣胯兘 - - - 0: 閫夋嫨DFT杩愮畻 -1: 閫夋嫨IDFT杩愮畻 - - - - PUCCH璋冨埗杈撳叆鏁版嵁瀵勫瓨鍣 - - PUCCH璋冨埗杈撳叆鏁版嵁d(n) - - - - SRS璧勬簮鏄犲皠鍙傛暟閰嶇疆瀵勫瓨鍣 - - SRS濉浂闂撮殧鎸囩ず锛 -0锛氭瘡2涓瓙杞芥尝濉1涓浂锛 -1锛氭瘡4涓瓙杞芥尝濉3涓浂锛 - - - 璧峰瀛愯浇娉綅缃紙姊抽娇浣嶇疆锛夛紝鍙栧艰寖鍥达細 -00锛0锛 -01锛1锛 -10锛2锛 -11锛3锛 - - - SRS棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - - SRS鐨刏C搴忓垪闀垮害瀵勫瓨鍣 - - 0锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓1涓 -1锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓2涓 - - - 绗簩涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 绗竴涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 鍙彂SRS锛堢壒娈婂瓙甯э級鏃讹紝瀛愬抚璧峰鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - SRS鐨刏C搴忓垪闀垮害鍊 - - - - PUCCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - 0锛歍X婊ゆ尝涓嶄娇鑳 -1锛歍X婊ゆ尝浣胯兘 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃2 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃1 - - - 绗簩涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - 绗竴涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - - PUSCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - PUSCH鏄犲皠鍒嗛厤绫诲瀷锛 -0锛氳祫婧愭槧灏0.5ms锛 -1锛氳祫婧愭槧灏1ms锛 - - - 绗簩娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗竴娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣1 - - PUSCH DMRS姝ｄ氦鐮佺储寮曞彇鍙嶆爣蹇椾綅锛 -1锛氬彇鍙 -0锛氫笉鍙栧弽 - - - PUSCH/PUCCH绗﹀彿鎵撳瓟澶勭悊鎸囩ず锛 -0000锛歯ormal -0001锛歵ype0_shortend -0010锛歵ype1_shortend -0011锛歵ype2_shortend -0100锛歵ype3_shortend -0101锛歵ype4_shortend -0110锛歵ype5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1锛歶鍊艰烦鍙 -0锛歶鍊间笉璺冲彉 - - - 1锛歷鍊艰烦鍙 -0锛歷鍊间笉璺冲彉 - - - 杩炵画涓や釜鍙戦佸抚瑕嗙洊TA閮ㄥ垎绱㈠紩鍊硷紝鍙栧艰寖鍥0~32 - - - dmrsValue鍙傝冧俊鍙疯В璋冪殑寰幆鍋忕Щ鍊硷紝鍙栧艰寖鍥0~7 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣2 - - SRS鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - PUSCH/PUCCH/PRACH鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣3 - - PUCCH鏍煎紡1/1a/1b鐨勮祫婧愮储寮曞硷紝鍙栧艰寖鍥0~4095 - - - SRS寰幆绉讳綅鍊 - - - 瀵笴AT1/CATM/CAT-NB瀛愯浇娉15kHz锛屾瘡娆¤皟鐢ㄥ搴1ms鍐2涓椂闅欙紝璇ュ弬鏁拌〃绀哄瓙甯у彿锛涘CAT-NB瀛愯浇娉3.75kHz锛屾瘡娆¤皟鐢ㄥ搴2ms鍐1涓椂闅欙紝璇ュ弬鏁拌〃绀烘椂闅欏彿 - - - 鏃犵嚎甯у彿锛屽彇鍊艰寖鍥0~1023 - - - - OFDM OFFSET閰嶇疆瀵勫瓨鍣 - - 鏈鍚庝竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - 绗竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - - 涓柇浣胯兘瀵勫瓨鍣 - - 0锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 -1锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 - - - 1锛欰XIDMA涓柇浣胯兘 -0锛欰XIDMA涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿13涓柇浣胯兘 -0锛歄FDM绗﹀彿13涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿12涓柇浣胯兘 -0锛歄FDM绗﹀彿12涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿11涓柇浣胯兘 -0锛歄FDM绗﹀彿11涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿10涓柇浣胯兘 -0锛歄FDM绗﹀彿10涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿9涓柇浣胯兘 -0锛歄FDM绗﹀彿9涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿8涓柇浣胯兘 -0锛歄FDM绗﹀彿8涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿7涓柇浣胯兘 -0锛歄FDM绗﹀彿7涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿6涓柇浣胯兘 -0锛歄FDM绗﹀彿6涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿5涓柇浣胯兘 -0锛歄FDM绗﹀彿5涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿4涓柇浣胯兘 -0锛歄FDM绗﹀彿4涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿3涓柇浣胯兘 -0锛歄FDM绗﹀彿3涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿2涓柇浣胯兘 -0锛歄FDM绗﹀彿2涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿1涓柇浣胯兘 -0锛歄FDM绗﹀彿1涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿0涓柇浣胯兘 -0锛歄FDM绗﹀彿0涓柇鏈娇鑳 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 1锛歄FDM绗﹀彿13涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿13涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿12涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿12涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿11涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿11涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿10涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿10涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿9涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿9涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿8涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿8涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿7涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿7涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿6涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿6涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿5涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿5涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿4涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿4涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿3涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿3涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿2涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿2涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿1涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿1涓柇鏍囧織鏈疆浣 - - - 1锛歄FDM绗﹀彿0涓柇鏍囧織缃綅 -0锛歄FDM绗﹀彿0涓柇鏍囧織鏈疆浣 - - - 1锛氳pusch瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氳pusch瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - 1锛氬啓txrx瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楃疆浣 -0锛氬啓txrx瀛樺偍鍣ㄦ椂閽熷紑鍚け璐ユ爣蹇楁湭缃綅 - - - - OFDM绗﹀彿濉浂鍙戦佸瘎瀛樺櫒 - - 鎸囩ず濉浂鍙戦佺殑OFDM绗﹀彿鏁帮細 -14鈥檅0锛氭病鏈夊～闆跺彂閫 -14鈥檅1锛氱鍙0濉浂鍙戦 -14鈥檅11锛氱鍙0锛1濉浂鍙戦 -14鈥檅111锛氱鍙0锛1锛2濉浂鍙戦 -鈥︹ - - - - DFT/IDFT&FFT/IFFT鎺у埗瀵勫瓨鍣 - - 0锛氳蒋浠舵湭瑙﹀彂ULDFT鍚姩 -1锛氳蒋浠惰Е鍙慤LDFT鍚姩 - - - 0锛歎LDFT鍚姩妯″紡涓鸿蒋浠惰Е鍙 -1锛歎LDFT鍚姩妯″紡涓篜USCH妯″潡瑙﹀彂 - - - 0锛氬惎绐椾笉浣胯兘 -1锛氬惎绐椾娇鑳 - - - 0锛歋RS浜х敓涓嶄娇鑳 -1锛歋RS浜х敓浣胯兘 - - - 0锛欶FT杈撳叆MEM娓呴浂鍔熻兘涓嶄娇鑳 -1锛欶FT杈撳叆MEM娓呴浂鍔熻兘浣胯兘 - - - 1锛氶夋嫨IFFT杩愮畻 -0锛氶夋嫨FFT杩愮畻 - - - 1锛欶FT/IFFT杩愮畻浣胯兘 -0锛欶FT/IFFT杩愮畻涓嶄娇鑳 - - - 0锛氬姛鐜囪皟鏁翠笉浣胯兘 -1锛氬姛鐜囪皟鏁翠娇鑳 - - - 鎸囩ずPRACH鏍煎紡绫诲瀷锛 -000锛歅RACH鏍煎紡0 -001锛歅RACH鏍煎紡1 -010锛歅RACH鏍煎紡2 -011锛歅RACH鏍煎紡3 -100锛歅RACH鏍煎紡4 -鍏朵粬锛氫繚鐣 - - - 鎸囩ずPUCCH鏍煎紡绫诲瀷锛 -000锛歅UCCH鏍煎紡1 -001锛歅UCCH鏍煎紡1a -010锛歅UCCH鏍煎紡1b -011锛歅UCCH鏍煎紡2 -100锛歅UCCH鏍煎紡2a -101锛歅UCCH鏍煎紡2b -鍏朵粬锛氫繚鐣 - - - 0锛歂PUSCH format 1 -1锛歂PUSCH format2 - - - 鎸囩ずOFDM绗﹀彿鐨勪釜鏁 - - - 0锛欴ATADRIVE涓嶄娇鑳 -1锛欴ATADRIVE浣胯兘 - - - 鎸囩ずUL_DFT璇籔USCH BUFFER鍧楅夋嫨锛 -00锛歅USCH BUFFER1 -01锛歅USCH BUFFER2 -10锛歅USCH BUFFER3 -11锛歅USCH PRA_BUF - - - 鎸囩ず涓婅淇￠亾鍙戦佹ā寮 -000锛歅USCH -001锛歅UCCH -010锛歅RACH -011锛歋RS -100锛歂PUSCH -101锛歂PRACH -鍏朵粬锛氫繚鐣 - - - FFT/IFFT鐐规暟閫夋嫨 -111锛氫繚鐣欙紙涓嶅彲閰嶏級 -110锛氫繚鐣欙紙涓嶅彲閰嶏級 -101锛氫繚鐣欙紙涓嶅彲閰嶏級 -100锛2048鐐 -011锛1024鐐 -010锛512鐐 -001锛256鐐 -000锛128鐐 - - - 0: 涓柇涓嶄娇鑳 -1: 涓柇浣胯兘 - - - - SRS鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - PUSCH/PUCCH/PRACH鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - NPUSCH鍙傛暟瀵勫瓨鍣 - - NPUSCH褰撳墠閲嶅浼犺緭鐨勭鍑犳锛屽彇鍊艰寖鍥0~127 - - - 瀛愯浇娉釜鏁帮細 -00锛1涓瓙杞芥尝 -01锛3涓瓙杞芥尝 -10锛6涓瓙杞芥尝 -11锛12涓瓙杞芥尝 - - - NPUSCH 鐨勮捣濮嬪瓙杞芥尝浣嶇疆锛屽彇鍊艰寖鍥0~47 - - - 褰撳墠浼犺緭鐨勭鍑犱釜Nslots鍗曚綅锛屽彇鍊艰寖鍥1~160 - - - 0: 3.75KHz -1: 15KHz - - - - NPUSCH DMRS鍙傛暟瀵勫瓨鍣 - - 棣栦釜RU鐨勯涓椂闅欏彿锛屽彇鍊艰寖鍥0~19 - - - 鐢ㄤ簬瀛愯浇娉釜鏁颁负1鐢熸垚DMRS鏃讹紝琛ㄧず绗嚑涓椂闅欙紝鍙栧艰寖鍥0~20480 - - - BASE_SEQ_NEXT鍊硷紝鍙栧艰寖鍥0~30 - - - CYCLIC_SHIFT鍊硷紝鍙栧艰寖鍥0~3 - - - - NPRACH鍙傛暟瀵勫瓨鍣 - - t鍊硷紝鍙栧艰寖鍥0~128 - - - frequency location of the first sub-carrier allocated to NPRACH锛 -000锛歠requency location涓0锛 -001锛歠requency location涓2锛 -010锛歠requency location涓12 -011锛歠requency location涓18 -100锛歠requency location涓24 -101锛歠requency location涓34 -110锛歠requency location涓36 -111锛氶粯璁や负0 - - - being the subcarrier selected by the MAC layer from 锛屽彇鍊艰寖鍥0-47 - - - - FFT/IFFT杈撳叆杈撳嚭鏁版嵁鎺у埗鍙婂弬鏁板瘎瀛樺櫒 - - 閲囨牱婊ゆ尝鍣ㄨ緭鍑烘埅鍙栭夋嫨 - - - 璁＄畻缁勮烦棰戝弬鏁帮紝鍙栧艰寖鍥0~29 - - - PUCCH鏍煎紡2/2a/2b鐨勮祫婧愮储寮曞硷紝鍙栧艰寖鍥0~1184 - - - 鍙傝冧俊鍙风殑寰幆鍋忕Щ鍙傛暟鍊硷紝鍙栧艰寖鍥0~7 - - - 鎸囩ずCP绫诲瀷锛 -0锛氭櫘閫欳P -1锛氭墿灞旵P - - - 0锛歍DD mode -1锛欶DD mode - - - 1: 浣胯兘鎸夊湴鍧浣嶅弽搴忚緭鍏ユ暟鎹紝鎸夋嫾鎺ュソ鐨勯『搴忚緭鍑烘暟鎹 -0: 姝ｅ父杈撳叆杈撳嚭鏁版嵁 - - - - ID閰嶇疆瀵勫瓨鍣 - - NCS鍜孶鎵闇鐨凣OLD搴忓垪鏃跺垵濮嬪糃_INI鐨勮绠楁ā寮忛夋嫨锛 -1锛歩f no value for or is configured by higher layers or the PUSCH transmission corresponds to a Random Access Response Grant or a retransmission of the same transport block as part of the contention based random access procedure -0锛歰therwise - - - NCS_U_GOLD_MODE涓1鏃讹紝琛ㄧず + 鐨勫硷紝鍙栧艰寖鍥0~532锛汵CS_U_GOLD_MODE涓0鏃讹紝琛ㄧず楂樺眰鎵閰 鐨勫硷紝鍙栧艰寖鍥0~509锛 - - - NCS_U_GOLD_MODE涓1鏃讹紝琛ㄧず + 鐨勫硷紝鍙栧艰寖鍥0~532锛汵CS_U_GOLD_MODE涓0鏃讹紝琛ㄧず楂樺眰鎵閰 鐨勫硷紝鍙栧艰寖鍥0~509锛 - - - 灏忓尯ID鍊硷紝鍙栧艰寖鍥0~503 - - - - PUCCH铏氭嫙ID瀵勫瓨鍣 - - RS浣跨敤鐨勮櫄鎷烮D - - - - PUCCH璧勬簮鏄犲皠閰嶇疆瀵勫瓨鍣 - - nCsAn娣峰悎璧勬簮鍧楀唴鏍煎紡1/1a/1b浣跨敤寰幆绉讳綅鏁帮紝鍙栧艰寖鍥0~7 - - - CE_mode鎸囩ず锛 -0锛欳E_modeA -1锛欳E_modeB - - - 绱㈠紩鍊硷細 -00锛 涓1 -01锛 涓2 -10锛 涓3 -11锛氬彇00鍊硷紝 涓1 - - - cqiNrb PUCCH鏍煎紡2/2a/2b鍗犵敤璧勬簮鍧楁暟锛屽彇鍊艰寖鍥0~98 - - - - 绯荤粺甯﹀閰嶇疆瀵勫瓨鍣 - - CAT1妯″紡涓 涓婅绯荤粺甯﹀绱㈠紩鍊硷細 -000锛氱郴缁熷甫瀹戒负6PRB -001锛氱郴缁熷甫瀹戒负15PRB -010锛氱郴缁熷甫瀹戒负25PRB -011锛氱郴缁熷甫瀹戒负50PRB -100锛氱郴缁熷甫瀹戒负75PRB -101锛氱郴缁熷甫瀹戒负100PRB -鍏朵粬锛氶粯璁ょ郴缁熷甫瀹戒负6PRB - - - - 鍙傛暟浼犻掑瘎瀛樺櫒 - - 0锛欴MA鎺у埗鏈ā鍧楀惎鍔ㄤ笉浣胯兘 -1锛欴MA鎺у埗鏈ā鍧楀惎鍔ㄤ娇鑳 - - - 0: 杞欢鍙傛暟閰嶇疆鏈粨鏉 -1: 杞欢鍙傛暟閰嶇疆缁撴潫 - - - - 杞欢鏆傚仠鍜屽仠姝㈢‖浠堕厤缃瘎瀛樺櫒 - - SW_PAUSE_EN=1鏃讹紝杞欢鏆傚仠纭欢鐨凮FDM绗﹀彿搴忓彿锛 -14`b0锛氫笉鏆傚仠 -14`b1锛歄FDM绗﹀彿0鏆傚仠 -14`b11锛歄FDM绗﹀彿0銆1鏆傚仠 -14`b111锛歄FDM绗﹀彿0銆1銆2鏆傚仠 -鈥︹ - - - SW_PAUSE_EN=1鏃讹紝杞欢鏆傚仠纭欢鐨勭瓥鐣ラ夋嫨锛 -0锛歋W_PAUSE_OFDM璁剧疆鐨凮FDM绗﹀彿鐨勪箣鍓嶆殏鍋 -1锛歋W_PAUSE_OFDM璁剧疆鐨凮FDM绗﹀彿鐨勪箣鍚庢殏鍋 - - - 杞欢鏆傚仠纭欢浣胯兘淇″彿锛 -0锛氳蒋浠舵殏鍋滅‖浠朵笉浣胯兘 -1锛氳蒋浠舵殏鍋滅‖浠朵娇鑳 - - - 杞欢绔嬪嵆鏆傚仠浣胯兘淇″彿锛 -0锛氳蒋浠剁珛鍗虫殏鍋滅‖浠朵笉浣胯兘 -1锛氳蒋浠剁珛鍗虫殏鍋滅‖浠朵娇鑳 - - - 杞欢鍋滄纭欢浣胯兘淇″彿锛 -0锛氳蒋浠跺仠姝㈢‖浠朵笉浣胯兘 -1锛氳蒋浠跺仠姝㈢‖浠朵娇鑳斤紝纭欢瀹屾垚褰撳墠OFDM澶勭悊鍚庯紝鍋滄褰撳墠瀛愬抚鐨勬搷浣 - - - - 杞欢鏆傚仠鏍囧織瀵勫瓨鍣 - - 杞欢鏆傚仠纭欢鏍囧織淇″彿锛 -0锛氳蒋浠舵湭鎴愬姛鏆傚仠纭欢 -1锛氳蒋浠舵垚鍔熸殏鍋滅‖浠 - - - 杞欢鍋滄纭欢鏍囧織淇″彿锛 -0锛氳蒋浠舵湭鎴愬姛鍋滄纭欢 -1锛氳蒋浠舵垚鍔熷仠姝㈢‖浠 - - - - DFT/IDFT鎺у埗瀵勫瓨鍣 - - 0锛欰NTI_DROP鍔熻兘涓嶄娇鑳 -1锛欰NTI_DROP鍔熻兘浣胯兘 - - - ANTI_DROP鍔熻兘鎴綅鍥犲瓙: -0锛氬彸绉8bit -1锛氬彸绉7bit - - - DFT/IDFT鐐规暟閫夋嫨鐨刬ndex锛0~43鍒嗗埆鎸囩ず44绉嶇偣鏁帮紝index涓庡疄闄呯偣鏁扮殑瀵瑰簲鍏崇郴濡備笅琛ㄨ鏄 锛堜笉鍙厤缃叾浠栧硷級 - - - 00: BPSK璋冨埗鏂瑰紡 -01: QPSK璋冨埗鏂瑰紡 -10: 16QAM璋冨埗鏂瑰紡 -11: 64QAM璋冨埗鏂瑰紡 - - - 0锛欴FT/IDFT鍔熻兘涓嶄娇鑳 -1锛欴FT/IDFT鍔熻兘浣胯兘 - - - 0锛歅USCH璋冨埗鍔熻兘涓嶄娇鑳 -1锛歅USCH璋冨埗鍔熻兘浣胯兘 - - - 0: 閫夋嫨DFT杩愮畻 -1: 閫夋嫨IDFT杩愮畻 - - - - PUCCH璋冨埗杈撳叆鏁版嵁瀵勫瓨鍣 - - PUCCH璋冨埗杈撳叆鏁版嵁d(n) - - - - SRS璧勬簮鏄犲皠鍙傛暟閰嶇疆瀵勫瓨鍣 - - SRS濉浂闂撮殧鎸囩ず锛 -0锛氭瘡2涓瓙杞芥尝濉1涓浂锛 -1锛氭瘡4涓瓙杞芥尝濉3涓浂锛 - - - 璧峰瀛愯浇娉綅缃紙姊抽娇浣嶇疆锛夛紝鍙栧艰寖鍥达細 -00锛0锛 -01锛1锛 -10锛2锛 -11锛3锛 - - - SRS棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - - SRS鐨刏C搴忓垪闀垮害瀵勫瓨鍣 - - 0锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓1涓 -1锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓2涓 - - - 绗簩涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 绗竴涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 鍙彂SRS锛堢壒娈婂瓙甯э級鏃讹紝瀛愬抚璧峰鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - SRS鐨刏C搴忓垪闀垮害鍊 - - - - PUCCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - 0锛歍X婊ゆ尝涓嶄娇鑳 -1锛歍X婊ゆ尝浣胯兘 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃2 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃1 - - - 绗簩涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - 绗竴涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - - PUSCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - PUSCH鏄犲皠鍒嗛厤绫诲瀷锛 -0锛氳祫婧愭槧灏0.5ms锛 -1锛氳祫婧愭槧灏1ms锛 - - - 绗簩娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗竴娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣1 - - PUSCH/PUCCH绗﹀彿鎵撳瓟澶勭悊鎸囩ず锛 -0000锛歯ormal -0001锛歵ype0_shortend -0010锛歵ype1_shortend -0011锛歵ype2_shortend -0100锛歵ype3_shortend -0101锛歵ype4_shortend -0110锛歵ype5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1锛歶鍊艰烦鍙 -0锛歶鍊间笉璺冲彉 - - - 1锛歷鍊艰烦鍙 -0锛歷鍊间笉璺冲彉 - - - 杩炵画涓や釜鍙戦佸抚瑕嗙洊TA閮ㄥ垎绱㈠紩鍊硷紝鍙栧艰寖鍥0~32 - - - dmrsValue鍙傝冧俊鍙疯В璋冪殑寰幆鍋忕Щ鍊硷紝鍙栧艰寖鍥0~7 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣2 - - SRS鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - PUSCH/PUCCH/PRACH鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣3 - - PUCCH鏍煎紡1/1a/1b鐨勮祫婧愮储寮曞硷紝鍙栧艰寖鍥0~4095 - - - SRS寰幆绉讳綅鍊 - - - 瀵笴AT1/CATM/CAT-NB瀛愯浇娉15kHz锛屾瘡娆¤皟鐢ㄥ搴1ms鍐2涓椂闅欙紝璇ュ弬鏁拌〃绀哄瓙甯у彿锛涘CAT-NB瀛愯浇娉3.75kHz锛屾瘡娆¤皟鐢ㄥ搴2ms鍐1涓椂闅欙紝璇ュ弬鏁拌〃绀烘椂闅欏彿 - - - 鏃犵嚎甯у彿锛屽彇鍊艰寖鍥0~1023 - - - - OFDM OFFSET閰嶇疆瀵勫瓨鍣 - - 鏈鍚庝竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - 绗竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - - 涓柇浣胯兘瀵勫瓨鍣 - - 0锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 -1锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 - - - 1锛欰XIDMA涓柇浣胯兘 -0锛欰XIDMA涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿13涓柇浣胯兘 -0锛歄FDM绗﹀彿13涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿12涓柇浣胯兘 -0锛歄FDM绗﹀彿12涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿11涓柇浣胯兘 -0锛歄FDM绗﹀彿11涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿10涓柇浣胯兘 -0锛歄FDM绗﹀彿10涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿9涓柇浣胯兘 -0锛歄FDM绗﹀彿9涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿8涓柇浣胯兘 -0锛歄FDM绗﹀彿8涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿7涓柇浣胯兘 -0锛歄FDM绗﹀彿7涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿6涓柇浣胯兘 -0锛歄FDM绗﹀彿6涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿5涓柇浣胯兘 -0锛歄FDM绗﹀彿5涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿4涓柇浣胯兘 -0锛歄FDM绗﹀彿4涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿3涓柇浣胯兘 -0锛歄FDM绗﹀彿3涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿2涓柇浣胯兘 -0锛歄FDM绗﹀彿2涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿1涓柇浣胯兘 -0锛歄FDM绗﹀彿1涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿0涓柇浣胯兘 -0锛歄FDM绗﹀彿0涓柇鏈娇鑳 - - - - OFDM绗﹀彿濉浂鍙戦佸瘎瀛樺櫒 - - 鎸囩ず濉浂鍙戦佺殑OFDM绗﹀彿鏁帮細 -14鈥檅0锛氭病鏈夊～闆跺彂閫 -14鈥檅1锛氱鍙0濉浂鍙戦 -14鈥檅11锛氱鍙0锛1濉浂鍙戦 -14鈥檅111锛氱鍙0锛1锛2濉浂鍙戦 -鈥︹ - - - - DFT/IDFT&FFT/IFFT鎺у埗瀵勫瓨鍣 - - 0锛氳蒋浠舵湭瑙﹀彂ULDFT鍚姩 -1锛氳蒋浠惰Е鍙慤LDFT鍚姩 - - - 0锛歎LDFT鍚姩妯″紡涓鸿蒋浠惰Е鍙 -1锛歎LDFT鍚姩妯″紡涓篜USCH妯″潡瑙﹀彂 - - - 0锛氬惎绐椾笉浣胯兘 -1锛氬惎绐椾娇鑳 - - - 0锛歋RS浜х敓涓嶄娇鑳 -1锛歋RS浜х敓浣胯兘 - - - 0锛欶FT杈撳叆MEM娓呴浂鍔熻兘涓嶄娇鑳 -1锛欶FT杈撳叆MEM娓呴浂鍔熻兘浣胯兘 - - - 1锛氶夋嫨IFFT杩愮畻 -0锛氶夋嫨FFT杩愮畻 - - - 1锛欶FT/IFFT杩愮畻浣胯兘 -0锛欶FT/IFFT杩愮畻涓嶄娇鑳 - - - 0锛氬姛鐜囪皟鏁翠笉浣胯兘 -1锛氬姛鐜囪皟鏁翠娇鑳 - - - 鎸囩ずPRACH鏍煎紡绫诲瀷锛 -000锛歅RACH鏍煎紡0 -001锛歅RACH鏍煎紡1 -010锛歅RACH鏍煎紡2 -011锛歅RACH鏍煎紡3 -100锛歅RACH鏍煎紡4 -鍏朵粬锛氫繚鐣 - - - 鎸囩ずPUCCH鏍煎紡绫诲瀷锛 -000锛歅UCCH鏍煎紡1 -001锛歅UCCH鏍煎紡1a -010锛歅UCCH鏍煎紡1b -011锛歅UCCH鏍煎紡2 -100锛歅UCCH鏍煎紡2a -101锛歅UCCH鏍煎紡2b -鍏朵粬锛氫繚鐣 - - - 0锛歂PUSCH format 1 -1锛歂PUSCH format2 - - - 鎸囩ずOFDM绗﹀彿鐨勪釜鏁 - - - 0锛欴ATADRIVE涓嶄娇鑳 -1锛欴ATADRIVE浣胯兘 - - - 鎸囩ずUL_DFT璇籔USCH BUFFER鍧楅夋嫨锛 -00锛歅USCH BUFFER1 -01锛歅USCH BUFFER2 -10锛歅USCH BUFFER3 -11锛歅USCH PRA_BUF - - - 鎸囩ず涓婅淇￠亾鍙戦佹ā寮 -000锛歅USCH -001锛歅UCCH -010锛歅RACH -011锛歋RS -100锛歂PUSCH -101锛歂PRACH -鍏朵粬锛氫繚鐣 - - - FFT/IFFT鐐规暟閫夋嫨 -111锛氫繚鐣欙紙涓嶅彲閰嶏級 -110锛氫繚鐣欙紙涓嶅彲閰嶏級 -101锛氫繚鐣欙紙涓嶅彲閰嶏級 -100锛2048鐐 -011锛1024鐐 -010锛512鐐 -001锛256鐐 -000锛128鐐 - - - 0: 涓柇涓嶄娇鑳 -1: 涓柇浣胯兘 - - - - SRS鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - PUSCH/PUCCH/PRACH鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - NPUSCH鍙傛暟瀵勫瓨鍣 - - NPUSCH褰撳墠閲嶅浼犺緭鐨勭鍑犳锛屽彇鍊艰寖鍥0~127 - - - 瀛愯浇娉釜鏁帮細 -00锛1涓瓙杞芥尝 -01锛3涓瓙杞芥尝 -10锛6涓瓙杞芥尝 -11锛12涓瓙杞芥尝 - - - NPUSCH 鐨勮捣濮嬪瓙杞芥尝浣嶇疆锛屽彇鍊艰寖鍥0~47 - - - 褰撳墠浼犺緭鐨勭鍑犱釜Nslots鍗曚綅锛屽彇鍊艰寖鍥1~160 - - - 0: 3.75KHz -1: 15KHz - - - - NPUSCH DMRS鍙傛暟瀵勫瓨鍣 - - 棣栦釜RU鐨勯涓椂闅欏彿锛屽彇鍊艰寖鍥0~19 - - - 鐢ㄤ簬瀛愯浇娉釜鏁颁负1鐢熸垚DMRS鏃讹紝琛ㄧず绗嚑涓椂闅欙紝鍙栧艰寖鍥0~20480 - - - BASE_SEQ_CURR鍊硷紝鍙栧艰寖鍥0~30 - - - CYCLIC_SHIFT鍊硷紝鍙栧艰寖鍥0~3 - - - - NPRACH鍙傛暟瀵勫瓨鍣 - - t鍊硷紝鍙栧艰寖鍥0~128 - - - frequency location of the first sub-carrier allocated to NPRACH锛 -000锛歠requency location涓0锛 -001锛歠requency location涓2锛 -010锛歠requency location涓12 -011锛歠requency location涓18 -100锛歠requency location涓24 -101锛歠requency location涓34 -110锛歠requency location涓36 -111锛氶粯璁や负0 - - - being the subcarrier selected by the MAC layer from 锛屽彇鍊艰寖鍥0-47 - - - - DFT/IDFT鎺у埗瀵勫瓨鍣 - - 0锛欰NTI_DROP鍔熻兘涓嶄娇鑳 -1锛欰NTI_DROP鍔熻兘浣胯兘 - - - ANTI_DROP鍔熻兘鎴綅鍥犲瓙: -0锛氬彸绉8bit -1锛氬彸绉7bit - - - DFT/IDFT鐐规暟閫夋嫨鐨刬ndex锛0~43鍒嗗埆鎸囩ず44绉嶇偣鏁帮紝index涓庡疄闄呯偣鏁扮殑瀵瑰簲鍏崇郴濡備笅琛ㄨ鏄 锛堜笉鍙厤缃叾浠栧硷級 - - - 00: BPSK璋冨埗鏂瑰紡 -01: QPSK璋冨埗鏂瑰紡 -10: 16QAM璋冨埗鏂瑰紡 -11: 64QAM璋冨埗鏂瑰紡 - - - 0锛欴FT/IDFT鍔熻兘涓嶄娇鑳 -1锛欴FT/IDFT鍔熻兘浣胯兘 - - - 0锛歅USCH璋冨埗鍔熻兘涓嶄娇鑳 -1锛歅USCH璋冨埗鍔熻兘浣胯兘 - - - 0: 閫夋嫨DFT杩愮畻 -1: 閫夋嫨IDFT杩愮畻 - - - - PUCCH璋冨埗杈撳叆鏁版嵁瀵勫瓨鍣 - - PUCCH璋冨埗杈撳叆鏁版嵁d(n) - - - - SRS璧勬簮鏄犲皠鍙傛暟閰嶇疆瀵勫瓨鍣 - - SRS濉浂闂撮殧鎸囩ず锛 -0锛氭瘡2涓瓙杞芥尝濉1涓浂锛 -1锛氭瘡4涓瓙杞芥尝濉3涓浂锛 - - - 璧峰瀛愯浇娉綅缃紙姊抽娇浣嶇疆锛夛紝鍙栧艰寖鍥达細 -00锛0锛 -01锛1锛 -10锛2锛 -11锛3锛 - - - SRS棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴涓猄RS绗﹀彿棰戝煙鏄犲皠璧峰浣嶇疆 - - - - SRS鐨刏C搴忓垪闀垮害瀵勫瓨鍣 - - 0锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓1涓 -1锛氬彂閫佺壒娈婂瓙甯ф椂锛孲RS绗﹀彿涓暟涓2涓 - - - 绗簩涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 绗竴涓猄RS鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - 鍙彂SRS锛堢壒娈婂瓙甯э級鏃讹紝瀛愬抚璧峰鍙戦佺殑OFDM绗﹀彿浣嶇疆 - - - SRS鐨刏C搴忓垪闀垮害鍊 - - - - PUCCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - 0锛歍X婊ゆ尝涓嶄娇鑳 -1锛歍X婊ゆ尝浣胯兘 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃2 - - - 绐勫甫鍦ㄧ郴缁熷甫瀹藉唴鐨勮捣濮嬩綅缃1 - - - 绗簩涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - 绗竴涓椂闅橮UCCH鏄犲皠璧峰浣嶇疆 - - - - PUSCH璧勬簮鏄犲皠鍙傛暟瀵勫瓨鍣 - - PUSCH鏄犲皠鍒嗛厤绫诲瀷锛 -0锛氳祫婧愭槧灏0.5ms锛 -1锛氳祫婧愭槧灏1ms锛 - - - 绗簩娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗竴娈礟USCH棰戝煙鏄犲皠闀垮害鍊 - - - 绗簩娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - 绗竴娈礟USCH棰戝煙鏄犲皠璧峰浣嶇疆 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣1 - - PUSCH/PUCCH绗﹀彿鎵撳瓟澶勭悊鎸囩ず锛 -0000锛歯ormal -0001锛歵ype0_shortend -0010锛歵ype1_shortend -0011锛歵ype2_shortend -0100锛歵ype3_shortend -0101锛歵ype4_shortend -0110锛歵ype5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1锛歶鍊艰烦鍙 -0锛歶鍊间笉璺冲彉 - - - 1锛歷鍊艰烦鍙 -0锛歷鍊间笉璺冲彉 - - - 杩炵画涓や釜鍙戦佸抚瑕嗙洊TA閮ㄥ垎绱㈠紩鍊硷紝鍙栧艰寖鍥0~32 - - - dmrsValue鍙傝冧俊鍙疯В璋冪殑寰幆鍋忕Щ鍊硷紝鍙栧艰寖鍥0~7 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣2 - - SRS鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - PUSCH/PUCCH/PRACH鐨勫皬鏁癆PC锛 锛夎皟鏁村洜瀛 - - - - 纭寲璁＄畻鍙傛暟閰嶇疆瀵勫瓨鍣3 - - PUCCH鏍煎紡1/1a/1b鐨勮祫婧愮储寮曞硷紝鍙栧艰寖鍥0~4095 - - - SRS寰幆绉讳綅鍊 - - - 瀵笴AT1/CATM/CAT-NB瀛愯浇娉15kHz锛屾瘡娆¤皟鐢ㄥ搴1ms鍐2涓椂闅欙紝璇ュ弬鏁拌〃绀哄瓙甯у彿锛涘CAT-NB瀛愯浇娉3.75kHz锛屾瘡娆¤皟鐢ㄥ搴2ms鍐1涓椂闅欙紝璇ュ弬鏁拌〃绀烘椂闅欏彿 - - - 鏃犵嚎甯у彿锛屽彇鍊艰寖鍥0~1023 - - - - OFDM OFFSET閰嶇疆瀵勫瓨鍣 - - 鏈鍚庝竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - 绗竴涓狾FDM绗﹀彿鐨刼ffset鍊 - - - - 涓柇浣胯兘瀵勫瓨鍣 - - 0锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 -1锛歎LDFT璁块棶TXRX鎴朠USCH瀛樺偍鍣‥RROR涓柇涓嶄娇鑳 - - - 1锛欰XIDMA涓柇浣胯兘 -0锛欰XIDMA涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿13涓柇浣胯兘 -0锛歄FDM绗﹀彿13涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿12涓柇浣胯兘 -0锛歄FDM绗﹀彿12涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿11涓柇浣胯兘 -0锛歄FDM绗﹀彿11涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿10涓柇浣胯兘 -0锛歄FDM绗﹀彿10涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿9涓柇浣胯兘 -0锛歄FDM绗﹀彿9涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿8涓柇浣胯兘 -0锛歄FDM绗﹀彿8涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿7涓柇浣胯兘 -0锛歄FDM绗﹀彿7涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿6涓柇浣胯兘 -0锛歄FDM绗﹀彿6涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿5涓柇浣胯兘 -0锛歄FDM绗﹀彿5涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿4涓柇浣胯兘 -0锛歄FDM绗﹀彿4涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿3涓柇浣胯兘 -0锛歄FDM绗﹀彿3涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿2涓柇浣胯兘 -0锛歄FDM绗﹀彿2涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿1涓柇浣胯兘 -0锛歄FDM绗﹀彿1涓柇鏈娇鑳 - - - 1锛歄FDM绗﹀彿0涓柇浣胯兘 -0锛歄FDM绗﹀彿0涓柇鏈娇鑳 - - - - OFDM绗﹀彿濉浂鍙戦佸瘎瀛樺櫒 - - 鎸囩ず濉浂鍙戦佺殑OFDM绗﹀彿鏁帮細 -14鈥檅0锛氭病鏈夊～闆跺彂閫 -14鈥檅1锛氱鍙0濉浂鍙戦 -14鈥檅11锛氱鍙0锛1濉浂鍙戦 -14鈥檅111锛氱鍙0锛1锛2濉浂鍙戦 -鈥︹ - - - - DFT/IDFT&FFT/IFFT鎺у埗瀵勫瓨鍣 - - 0锛氳蒋浠舵湭瑙﹀彂ULDFT鍚姩 -1锛氳蒋浠惰Е鍙慤LDFT鍚姩 - - - 0锛歎LDFT鍚姩妯″紡涓鸿蒋浠惰Е鍙 -1锛歎LDFT鍚姩妯″紡涓篜USCH妯″潡瑙﹀彂 - - - 0锛氬惎绐椾笉浣胯兘 -1锛氬惎绐椾娇鑳 - - - 0锛歋RS浜х敓涓嶄娇鑳 -1锛歋RS浜х敓浣胯兘 - - - 0锛欶FT杈撳叆MEM娓呴浂鍔熻兘涓嶄娇鑳 -1锛欶FT杈撳叆MEM娓呴浂鍔熻兘浣胯兘 - - - 1锛氶夋嫨IFFT杩愮畻 -0锛氶夋嫨FFT杩愮畻 - - - 1锛欶FT/IFFT杩愮畻浣胯兘 -0锛欶FT/IFFT杩愮畻涓嶄娇鑳 - - - 0锛氬姛鐜囪皟鏁翠笉浣胯兘 -1锛氬姛鐜囪皟鏁翠娇鑳 - - - 鎸囩ずPRACH鏍煎紡绫诲瀷锛 -000锛歅RACH鏍煎紡0 -001锛歅RACH鏍煎紡1 -010锛歅RACH鏍煎紡2 -011锛歅RACH鏍煎紡3 -100锛歅RACH鏍煎紡4 -鍏朵粬锛氫繚鐣 - - - 鎸囩ずPUCCH鏍煎紡绫诲瀷锛 -000锛歅UCCH鏍煎紡1 -001锛歅UCCH鏍煎紡1a -010锛歅UCCH鏍煎紡1b -011锛歅UCCH鏍煎紡2 -100锛歅UCCH鏍煎紡2a -101锛歅UCCH鏍煎紡2b -鍏朵粬锛氫繚鐣 - - - 0锛歂PUSCH format 1 -1锛歂PUSCH format2 - - - 鎸囩ずOFDM绗﹀彿鐨勪釜鏁 - - - 0锛欴ATADRIVE涓嶄娇鑳 -1锛欴ATADRIVE浣胯兘 - - - 鎸囩ずUL_DFT璇籔USCH BUFFER鍧楅夋嫨锛 -00锛歅USCH BUFFER1 -01锛歅USCH BUFFER2 -10锛歅USCH BUFFER3 -11锛歅USCH PRA_BUF - - - 鎸囩ず涓婅淇￠亾鍙戦佹ā寮 -000锛歅USCH -001锛歅UCCH -010锛歅RACH -011锛歋RS -100锛歂PUSCH -101锛歂PRACH -鍏朵粬锛氫繚鐣 - - - FFT/IFFT鐐规暟閫夋嫨 -111锛氫繚鐣欙紙涓嶅彲閰嶏級 -110锛氫繚鐣欙紙涓嶅彲閰嶏級 -101锛氫繚鐣欙紙涓嶅彲閰嶏級 -100锛2048鐐 -011锛1024鐐 -010锛512鐐 -001锛256鐐 -000锛128鐐 - - - 0: 涓柇涓嶄娇鑳 -1: 涓柇浣胯兘 - - - - SRS鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - PUSCH/PUCCH/PRACH鐨凢FT鎴綅鍥犲瓙鍙傛暟瀵勫瓨鍣 - - FFT绗崄涓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗崄绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗節绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竷绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗叚绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簲绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗洓绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗笁绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗簩绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - FFT绗竴绾ф埅浣嶅洜瀛愭寚绀猴細 -2鈥檅00锛氭埅鍙25~14bit -2鈥檅01锛氭埅鍙26~15bit -2鈥檅10锛氭埅鍙27~16bit -2鈥檅11锛氭埅鍙28~17bit - - - - NPUSCH鍙傛暟瀵勫瓨鍣 - - NPUSCH褰撳墠閲嶅浼犺緭鐨勭鍑犳锛屽彇鍊艰寖鍥0~127 - - - 瀛愯浇娉釜鏁帮細 -00锛1涓瓙杞芥尝 -01锛3涓瓙杞芥尝 -10锛6涓瓙杞芥尝 -11锛12涓瓙杞芥尝 - - - NPUSCH 鐨勮捣濮嬪瓙杞芥尝浣嶇疆锛屽彇鍊艰寖鍥0~47 - - - 褰撳墠浼犺緭鐨勭鍑犱釜Nslots鍗曚綅锛屽彇鍊艰寖鍥1~160 - - - 0: 3.75KHz -1: 15KHz - - - - NPUSCH DMRS鍙傛暟瀵勫瓨鍣 - - 棣栦釜RU鐨勯涓椂闅欏彿锛屽彇鍊艰寖鍥0~19 - - - 鐢ㄤ簬瀛愯浇娉釜鏁颁负1鐢熸垚DMRS鏃讹紝琛ㄧず绗嚑涓椂闅欙紝鍙栧艰寖鍥0~20480 - - - BASE_SEQ_CURR鍊硷紝鍙栧艰寖鍥0~30 - - - CYCLIC_SHIFT鍊硷紝鍙栧艰寖鍥0~3 - - - - NPRACH鍙傛暟瀵勫瓨鍣 - - t鍊硷紝鍙栧艰寖鍥0~128 - - - frequency location of the first sub-carrier allocated to NPRACH锛 -000锛歠requency location涓0锛 -001锛歠requency location涓2锛 -010锛歠requency location涓12 -011锛歠requency location涓18 -100锛歠requency location涓24 -101锛歠requency location涓34 -110锛歠requency location涓36 -111锛氶粯璁や负0 - - - being the subcarrier selected by the MAC layer from 锛屽彇鍊艰寖鍥0-47 - - - - 鐘舵佹満鍙瀵勫瓨鍣 - - TXRX PING瀛樺偍鍣ㄧ┖婊℃寚绀 -1锛氬瓨鍌ㄥ櫒婊 -0锛氬瓨鍌ㄥ櫒绌 - - - TXRX PANG瀛樺偍鍣ㄧ┖婊℃寚绀 -1锛氬瓨鍌ㄥ櫒婊 -0锛氬瓨鍌ㄥ櫒绌 - - - 瀛愬抚绾х姸鎬佹満鎸囩ず - - - 绗﹀彿绾х姸鎬佹満鎸囩ず - - - - OFDM绗﹀彿璁℃暟鍙瀵勫瓨鍣 - - OFDM绗﹀彿璁℃暟锛屽彇鍊艰寖鍥0~13 - - - - ASSERT鐘舵佹満鍙瀵勫瓨鍣 - - ASSERT TXRX PING瀛樺偍鍣ㄧ┖婊℃寚绀 -1锛氬瓨鍌ㄥ櫒婊 -0锛氬瓨鍌ㄥ櫒绌 - - - ASSERT TXRX PANG瀛樺偍鍣ㄧ┖婊℃寚绀 -1锛氬瓨鍌ㄥ櫒婊 -0锛氬瓨鍌ㄥ櫒绌 - - - ASSERT瀛愬抚绾х姸鎬佹満鎸囩ず - - - ASSERT绗﹀彿绾х姸鎬佹満鎸囩ず - - - - OFDM绗﹀彿璁℃暟鍙瀵勫瓨鍣 - - ASSERT OFDM绗﹀彿璁℃暟锛屽彇鍊艰寖鍥0~13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 鍙戦佸畬鎴怲RACE涓柇鏍囧織 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - 鎺ユ敹瀹屾垚TRACE涓柇鏍囧織 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - 鍙戦佸畬鎴愪腑鏂爣蹇 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - 鍙戦佺鍙蜂腑鏂爣蹇 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - 鎺ユ敹瀹屾垚涓柇鏍囧織 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - 鎺ユ敹绗﹀彿涓柇鏍囧織 -0锛氭涓柇鏈骇鐢 -1锛氭涓柇浜х敓 - - - - 涓柇灞忚斀瀵勫瓨鍣 - - 鍙戦佸畬鎴怲RACE灞忚斀浣 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - 鎺ユ敹瀹屾垚TRACE灞忚斀浣 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - 鍙戦佸畬鎴愪腑鏂睆钄戒綅 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - 鍙戦佺鍙蜂腑鏂睆钄戒綅 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - 鎺ユ敹瀹屾垚涓柇灞忚斀浣 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - 鎺ユ敹绗﹀彿涓柇灞忚斀浣 -0锛氫笉灞忚斀姝や腑鏂 -1锛氬睆钄芥涓柇 - - - - OFDM涓柇鏍囧織浣嶅瘎瀛樺櫒 - - 0锛氫笅琛孫FDM绗﹀彿14涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿14涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿13涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿13涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿12涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿12涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿11涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿11涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿10涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿10涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿9涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿9涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿8涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿8涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿7涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿7涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿6涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿6涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿5涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿5涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿4涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿4涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿3涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿3涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿2涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿2涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿1涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿1涓柇浜х敓 - - - 0锛氫笅琛孫FDM绗﹀彿0涓柇鏈骇鐢 -1锛氫笅琛孫FDM绗﹀彿0涓柇浜х敓 - - - - 鎺ユ敹绗﹀彿涓柇浣胯兘瀵勫瓨鍣 - - 绗﹀彿绾т腑鏂娇鑳戒俊鍙凤紙姝ゆ瘮鐗逛负1鏃讹紝绗﹀彿绾т腑鏂娇鑳芥湁鏁堬紱鍙嶄箣锛岀鍙风骇涓柇浣胯兘鏃犳晥锛夛細 -0锛氫腑鏂笉浣胯兘 -1锛氫腑鏂娇鑳 - - - 0锛氭渶鍚庝竴涓狾FDM绗﹀彿涓柇涓嶄娇鑳 -1锛氭渶鍚庝竴涓狾FDM绗﹀彿涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿14涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿14涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿13涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿13涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿12涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿12涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿11涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿11涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿10涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿10涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿9涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿9涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿8涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿8涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿7涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿7涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿6涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿6涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿5涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿5涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿4涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿4涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿3涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿3涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿2涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿2涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿1涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿1涓柇浣胯兘 - - - 0锛歄FDM绗﹀彿0涓柇涓嶄娇鑳 -1锛歄FDM绗﹀彿0涓柇浣胯兘 - - - - 绯荤粺绾ч厤缃瘎瀛樺櫒 - - 鎺ユ敹DCOC鍊煎熀鍑嗛夋嫨 -1锛氳蒋浠堕厤缃熀鍑嗗 -0锛氭寜绗﹀彿璁＄畻鍩哄噯鍊 - - - 0锛氭帴鏀舵暟鎹渶楂樻瘮鐗逛笉缈昏浆 -1锛氭帴鏀舵暟鎹渶楂樻瘮鐗圭炕杞 - - - 0锛氬彂閫佹暟鎹渶楂樻瘮鐗逛笉缈昏浆 -1锛氬彂閫佹暟鎹渶楂樻瘮鐗圭炕杞 - - - DFE妯″紡浣胯兘淇″彿 -0锛氶潪DFE妯″紡 -1锛欴FE妯″紡 - - - 绐勫甫妯″紡浣胯兘淇″彿 -0锛氶潪绐勫甫妯″紡 -1锛氱獎甯︽ā寮 - - - CAT1妯″紡浣胯兘淇″彿 -0锛氶潪CAT1妯″紡 -1锛欳AT1妯″紡 - - - - 绔嬪嵆鍋滄閰嶇疆瀵勫瓨鍣 - - 涓婅绔嬪嵆鍋滄鍔熻兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 涓嬭绔嬪嵆鍋滄鍔熻兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - - 鎺ユ敹鍏ㄥ眬閰嶇疆瀵勫瓨鍣 - - SOFT AFC 鍔熻兘浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RSSI璁＄畻绐楅暱 -1锛氬崐涓鍙风殑data娈 -0锛氫竴涓鍙风殑data娈 - - - RSSI 鍊煎瓨鍌ㄤ綅缃夋嫨 -0: 瀛樺偍鍦≧SSI_MAX1 -1: 瀛樺偍鍦≧SSI_MAX2 -2: 瀛樺偍鍦≧SSI_MAX3 -3: 瀛樺偍鍦≧SSI_MAX4 -4: 瀛樺偍鍦≧SSI_MAX5 -Other:涓嶅彲閰嶇疆 - - - 鍗婂甫婊ゆ尝璁＄畻浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - OTDOA閫氳矾浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - offset浣跨敤绫诲瀷鏍囪瘑鎸囩ず -1锛歊X浣跨敤offset鍊艰繘琛宑p闀垮害璋冩暣锛屽苟浼犲肩粰鐩稿叧妯″潡锛 -0锛氫娇鐢╫ffset浣欐暟鍊间紶缁欑浉鍏虫ā鍧楋紱 - - - 1锛欼DDET閫氳矾浣胯兘 -0锛欼DDET閫氳矾涓嶄娇鑳 - - - 涓嶥LFFT浜や簰鏈哄埗浣胯兘鎺у埗锛堜笅琛 DATA_DRIVE鏈哄埗锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 00锛氭櫘閫欳P -01锛氭墿灞旵P -10锛氭棤CP锛堜粎鐢ㄤ簬IDDET鍦烘櫙锛 - - - 鍗婂甫FIR涔樼疮鍔犲悗姣旂壒閫夋嫨锛 -4鈥檋0锛33-22 -4鈥檋1锛32-21 -4鈥檋2锛31-20 -4鈥檋3锛30-19 -4鈥檋4锛29-18 -4鈥檋5锛28-17 -4鈥檋6锛27-16 -4鈥檋7锛26-15 -4鈥檋8锛25-14 -4鈥檋9锛24-13 -4鈥檋a锛23-12 -4鈥檋b锛22-11 -4鈥檋c锛21-10 -4鈥檋d锛20-9 -4鈥檋e锛19-8 -4鈥檋f锛18-7 - - - 鎺ユ敹TRACE鍔熻兘浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 浣欐暟浼0鏍囪瘑锛坢easpwr/dlfft offset锛夛細 -1锛氫紶0锛 -0锛氭牴鎹畂ffset鍜宱ffset_ctrl_flag锛屼紶浣欐暟 - - - 娴嬮噺浠诲姟浣胯兘鎺у埗 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹閫氳矾褰掍竴鍖栬绠椾娇鑳 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹鍧囧艰绠椾娇鑳斤細 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹閫氳矾鏁版嵁缁熻浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - RSSI璁＄畻浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 鍏ㄥ眬鎺ユ敹閫氳矾浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 鎺ユ敹棣栦釜OFDM绗﹀彿闀垮害淇鍊 - - 鎺ユ敹棣栦釜OFDM绗﹀彿闀垮害淇鍊 - - - - SOFT AFC璋冩暣鍥犲瓙瀵勫瓨鍣 - - AFC杞欢棰戝亸璋冩暣浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - AFC杞欢棰戝亸璋冩暣鍥犲瓙 -锛堝洜瀛愭湁姝ｈ礋锛屾闀10hz锛岋級 - - - - RSSI MAX鍙傛暟瀵勫瓨鍣 - - 涓嬩竴娆℃帴鏀剁殑鏍囧織 -1锛氫笅娆℃帴鏀舵爣蹇椾娇鑳 -0锛氫笅娆℃帴鏀舵爣蹇椾笉浣胯兘 -锛堢‖浠跺湪AD_ON涓婂崌娌挎竻0锛 - - - RSSI鏈澶у兼竻闄ゆ爣蹇楋紙纭欢绔嬪嵆娓0锛 -1锛氭竻闄ゆ爣蹇椾娇鑳 -0锛氭竻闄ゆ爣蹇椾笉浣胯兘 - - - 璁＄畻RSSI鏈澶у肩殑璧风偣绗﹀彿鍙风爜 - - - - 鎺ユ敹褰掍竴鍖栭厤缃瘎瀛樺櫒 - - 鎸囩ず褰撳墠鎺ユ敹浣跨敤绗嚑涓渶澶у兼潵杩涜褰掍竴鍖栨搷浣 -閰嶇疆鑼冨洿1~5 - - - - 鎺ユ敹楗卞拰鏁板煎瘎瀛樺櫒 - - 楗卞拰鏁版渶澶у -褰撴瘮杈冪偣鐨勫煎ぇ浜庣瓑浜庤鍊兼椂锛岃鍒ゅ畾涓洪ケ鍜屾暟 - - - 楗卞拰鏁版渶灏忓 -褰撴瘮杈冪偣鐨勫煎皬浜庣瓑浜庤鍊兼椂锛岃鍒ゅ畾涓洪ケ鍜屾暟 - - - - 鎺ユ敹PRE鍔熻兘閰嶇疆瀵勫瓨鍣 - - 鎺ユ敹搴忓垪鐐逛箻鍙傛暟 - - - 鎺ユ敹绯荤粺甯﹀ -3鈥檋5: 20M (瀵瑰簲闄嶉噰鏍风巼1/16) -3鈥檋4: 15M (瀵瑰簲闄嶉噰鏍风巼1/16) -3鈥檋3: 10M (瀵瑰簲闄嶉噰鏍风巼1/8) -3鈥檋2: 5M (瀵瑰簲闄嶉噰鏍风巼1/4) -3鈥檋1: 3M (瀵瑰簲闄嶉噰鏍风巼1/2) -3鈥檋0: 1.4M -Other:涓嶅彲閰嶇疆 - - - 鎺ユ敹鐐逛箻璁＄畻浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - FIR婊ゆ尝浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 鎺ユ敹FIR涔樼疮鍔犲悗姣旂壒閫夋嫨锛 -5鈥檅00000锛34-23 -5鈥檅00001锛33-22 -5鈥檅00010锛32-21 -5鈥檅00011锛31-20 -5鈥檅00100锛30-19 -5鈥檅00101锛29-18 -5鈥檅00110锛28-17 -5鈥檅00111锛27-16 -5鈥檅01000锛26-15 -5鈥檅01001锛25-14 -5鈥檅01010锛24-13 -5鈥檅01011锛23-12 -5鈥檅01100锛22-11 -5鈥檅01101锛21-10 -5鈥檅01110锛20-9 -5鈥檅01111锛19-8 -5鈥檅10000锛18-7 -5鈥檅10001锛17-6 -5鈥檅10010锛16-5 -Other锛氫笉鑳介厤缃 - - - - 鎺ユ敹杈呭姪鎺у埗瀵勫瓨鍣 - - - 鎺ユ敹杞欢閰嶇疆鍥犲瓙瀵勫瓨鍣 - - - 鎺ユ敹鐩存祦鍊奸厤缃瘎瀛樺櫒 - - DCOC鍊兼洿鏂颁娇鑳 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹鐩存祦鍊糏 - - - 鎺ユ敹鐩存祦鍊糛 - - - - 鎺ユ敹澧炵泭1閰嶇疆瀵勫瓨鍣 - - GAIN1浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹GAIN1鍊 - - - - 鎺ユ敹澧炵泭2閰嶇疆瀵勫瓨鍣 - - GAIN2浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 鎺ユ敹GAIN2鍊 - - - - 鎺ユ敹鏁版嵁杈撳嚭閰嶇疆瀵勫瓨鍣 - - IDDET鏁版嵁鎴綅璧风偣 -2鈥檋0:bit7 -2'h1:bit8 -2鈥榟2:bit9 -2'h3:bit10 - - - IDDET鏁版嵁鎴綅缁堢偣 -3鈥檋0:bit0 -3'h1:bit1 -3鈥榟2:bit2 -3'h3:bit3 -3鈥檋4:bit4 -other:reserved - - - OTDOA鏁版嵁鎴綅璧风偣 -2鈥檋0:bit7 -2'h1:bit8 -2鈥榟2:bit9 -2'h3:bit10 - - - OTDOA鏁版嵁鎴綅缁堢偣 -3鈥檋0:bit0 -3'h1:bit1 -3鈥榟2:bit2 -3'h3:bit3 -3鈥檋4:bit4 -other:reserved - - - MEASPWR鏁版嵁鎴綅璧风偣 -2鈥檋0:bit7 -2'h1:bit8 -2鈥榟2:bit9 -2'h3:bit10 - - - MEASPWR鏁版嵁鎴綅缁堢偣 -3鈥檋0:bit0 -3'h1:bit1 -3鈥榟2:bit2 -3'h3:bit3 -3鈥檋4:bit4 -other:reserved - - - - - 鍙戦佸叏灞閰嶇疆瀵勫瓨鍣 - - 鍙戦佸洖鐜娇鑳斤紙璋冭瘯浣跨敤锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 涓婅DATA_DRIVE鏈哄埗 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 1锛氭墿灞旵P -0锛氭櫘閫欳P - - - 鍙戦侀氳矾浣胯兘 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 鍙戦侀涓狾FDM绗﹀彿闀垮害淇鍊 - - 鍙戦侀涓狾FDM绗﹀彿闀垮害淇鍊奸厤缃(-32~31涓偣) - - - - 鍙戦丳ING鏁版嵁鍜孋P闀垮害瀵勫瓨鍣 - - 鍙戦丳ING鏁版嵁鍜孋P闀垮害锛堥暱搴︿粠0寮濮嬶級 - - - - 鍙戦丳ANG鏁版嵁鍜孋P闀垮害瀵勫瓨鍣 - - 鍙戦丳ANG鏁版嵁鍜孋P闀垮害锛堥暱搴︿粠0寮濮嬶級 - - - - 鍙戦丳OST鍔熻兘閰嶇疆瀵勫瓨鍣 - - PRACH浣胯兘鎺у埗 -1锛氫娇鑳 -0锛氫笉浣胯兘 -锛堟潵鑷狣FT妯″潡锛屽瓙甯х骇鏇存柊锛岃蒋浠跺彧璇伙級 - - - PRACH 鏍煎紡鎺у埗 -3鈥榟x锛氭牸寮弜锛坸涓0~4锛 -锛堟潵鑷狣FT妯″潡锛屽瓙甯х骇鏇存柊锛岃蒋浠跺彧璇伙級 - - - 鍙戦佸簭鍒楃偣涔樺弬鏁帮細NB鍦ㄧ郴缁熷甫瀹戒腑鐨勮捣濮嬪 -锛堟潵鑷狣FT妯″潡锛屽瓙甯х骇鏇存柊锛岃蒋浠跺彧璇伙級 - - - 鍙戦佹护娉娇鑳斤紱 -1锛氫娇鑳 -0锛氫笉浣胯兘 -锛堟潵鑷狣FT妯″潡锛屽瓙甯х骇鏇存柊锛岃蒋浠跺彧璇伙級 - - - 鍙戦佸甫瀹 -3鈥檋5: 20M (瀵瑰簲鍗囬噰鏍风巼16) -3鈥檋4: 15M (瀵瑰簲鍗囬噰鏍风巼16) -3鈥檋3: 10M (瀵瑰簲鍗囬噰鏍风巼8) -3鈥檋2: 5M (瀵瑰簲鍗囬噰鏍风巼4) -3鈥檋1: 3M (瀵瑰簲鍗囬噰鏍风巼2) -3鈥檋0: 1.4M -Other:涓嶅彲閰嶇疆 - - - 鍙戦侀鍋忕偣涔樹娇鑳斤細 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 鍙戦丗IR涔樼疮鍔犲悗姣旂壒閫夋嫨锛 -5鈥檅00000锛34-23 -5鈥檅00001锛33-22 -5鈥檅00010锛32-21 -5鈥檅00011锛31-20 -5鈥檅00100锛30-19 -5鈥檅00101锛29-18 -5鈥檅00110锛28-17 -5鈥檅00111锛27-16 -5鈥檅01000锛26-15 -5鈥檅01001锛25-14 -5鈥檅01010锛24-13 -5鈥檅01011锛23-12 -5鈥檅01100锛22-11 -5鈥檅01101锛21-10 -5鈥檅01110锛20-9 -5鈥檅01111锛19-8 -5鈥檅10000锛18-7 -5鈥檅10001锛17-6 -5鈥檅10010锛16-5 -Other锛氫笉鑳介厤缃 - - - - 鍙戦佸啑浣欐暟鎹暟閲忓瘎瀛樺櫒 - - 鍙戦佸啑浣欐暟鎹0涓暟 -8鈥檋ff : 255涓 -8鈥檋fe: 254涓 -鈥︹︹︹ -8鈥檋01: 1涓 -8鈥檋00: 0涓紙涓嶅彂閫佸啑浣欐暟鎹級 - - - - - 鎺ユ敹杞欢閰嶇疆鍥犲瓙褰撳墠鍊煎瘎瀛樺櫒 - - - 鎺ユ敹楗卞拰鏁版嵁缁熻瀵勫瓨鍣 - - - 鎺ユ敹褰掍竴鍖栧洜瀛愬瘎瀛樺櫒 - - 鎺ユ敹褰掍竴鍖栧洜瀛愬瘎瀛樺櫒 - - - - RSSI 鏈澶у煎瘎瀛樺櫒1 - - - RSSI 鏈澶у煎瘎瀛樺櫒2 - - - RSSI 鏈澶у煎瘎瀛樺櫒3 - - - RSSI 鏈澶у煎瘎瀛樺櫒4 - - - RSSI 鏈澶у煎瘎瀛樺櫒5 - - - 鎺ユ敹鐩存祦璁＄畻杈撳嚭鍊煎瘎瀛樺櫒 - - 鎺ユ敹鐩存祦璁＄畻杈撳嚭鍊糏 - - - 鎺ユ敹鐩存祦璁＄畻杈撳嚭鍊糛 - - - - - 鎺ユ敹OFDM绗﹀彿鎸囩ず瀵勫瓨鍣 - - 褰撳墠RX_MEM鐨勫啓鍦板潃 - - - AD_ON椹卞姩鎺у埗淇″彿 - - - 鎺ユ敹杩愯鎸囩ず淇″彿 -0锛氳繍琛屼腑 -1锛氭湭杩愯 - - - DLFFT鍔熻兘浣胯兘淇″彿 - - - OTDOA鍔熻兘浣胯兘淇″彿 - - - IDDET鍔熻兘浣胯兘淇″彿 - - - MEAS鍔熻兘浣胯兘淇″彿 - - - 涓娆℃帴鏀惰繃绋嬩腑CP绫诲瀷淇敼 -0锛氭棤淇敼 -1锛氭湁淇敼 - - - 鏃犳帴鏀舵暟鎹紓甯告寚绀 -0锛氭棤寮傚父 -1锛氭湁寮傚父 - - - 鎺ユ敹鐨凱ING_PANG鐘舵佹寚绀 - - - 鎸囩ず褰撳墠鎺ユ敹鐨勬槸绗嚑涓狾FDM绗﹀彿 - - - - 鍙戦丗IFO浣嶇疆瀵勫瓨鍣 - - 褰撳墠TX_MEM鐨勮鍦板潃 - - - DA_ON椹卞姩鎺у埗淇″彿 - - - 鎺ユ敹杩愯鎸囩ず淇″彿 -0锛氭湭杩愯 -1锛氳繍琛屼腑 - - - 鍙戦丗IFO浣嶇疆瀵勫瓨鍣 -0锛氬湪ping瀛樺偍鍣 -1锛氬湪pang瀛樺偍鍣 - - - 鎸囩ず褰撳墠鍙戦佺殑鏄鍑犱釜OFDM绗﹀彿 - - - - 鎺ユ敹閿欒鏃跺埢鐘舵佸瘎瀛樺櫒 - - 甯у彿锛堝瓙甯э級 - - - 瀛愬抚鍐呯殑TS璁℃暟鍊 - - - 绗﹀彿璁℃暟 - - - AD_ON椹卞姩鎺у埗淇″彿 - - - 鎺ユ敹杩愯鎸囩ず淇″彿0锛氭湭杩愯1锛氳繍琛屼腑 - - - 杈撳叆鐨刴em閫夋嫨淇″彿 - - - 杈撳嚭鐨勪箳涔撲俊鍙 - - - CP 绫诲瀷 - - - - 鍙戦侀敊璇椂鍒荤姸鎬佸瘎瀛樺櫒 - - 甯у彿锛堝瓙甯э級 - - - 瀛愬抚鍐呯殑TS璁℃暟鍊 - - - 绗﹀彿璁℃暟 - - - DA_ON椹卞姩鎺у埗淇″彿 - - - 鎺ユ敹杩愯鎸囩ず淇″彿 -0锛氭湭杩愯 -1锛氳繍琛屼腑 - - - PING RAM閫夋嫨淇″彿 - - - DFT鍐橮ING閿欒淇″彿 - - - DFT鍐橮ANG閿欒淇″彿 - - - PING璇诲彇鏃剁┖閿欒淇″彿 - - - PANG璇诲彇鏃剁┖閿欒淇″彿 - - - - RF瀛愬抚FRAMC閿佸瓨鍊煎瘎瀛樺櫒 - - ADON涓婂崌娌挎椂鐨凢RAMC鍊 - - - 绗竴涓帴鏀跺瓙甯т腑鏂椂鐨凢RAMC鍊 - - - - RF瀛愬抚FRAMC鍋忓樊瀵勫瓨鍣 - - 鏈鎺ユ敹鐨勫瓙甯т腑鏂釜鏁 - - - 褰撳墠鐨勫瓙甯т腑鏂拰棣栨瀛愬抚涓柇鐨凢RAMC宸 - - - - AD_ON鍙樺寲鏃堕棿瀵勫瓨鍣 - - 濂囨暟娆D_ON涓嬮檷娌挎椂闂 - - - 濂囨暟娆D_ON涓婂崌娌挎椂闂 - - - 鍋舵暟娆D_ON涓嬮檷娌挎椂闂 - - - 鍋舵暟娆D_ON涓婂崌娌挎椂闂 - - - - DA_ON鍙樺寲鏃堕棿瀵勫瓨鍣 - - 濂囨暟娆A_ON涓嬮檷娌挎椂闂 - - - 濂囨暟娆A_ON涓婂崌娌挎椂闂 - - - 鍋舵暟娆A_ON涓嬮檷娌挎椂闂 - - - 鍋舵暟娆A_ON涓婂崌娌挎椂闂 - - - - FFTBUF1涓柇鏃堕棿瀵勫瓨鍣 - - 绗4娆FTBUF1涓柇鏃堕棿 - - - 绗3娆FTBUF1涓柇鏃堕棿 - - - 绗2娆FTBUF1涓柇鏃堕棿 - - - 绗1娆FTBUF1涓柇鏃堕棿 - - - - FFTBUF2涓柇鏃堕棿瀵勫瓨鍣 - - 绗4娆FTBUF2涓柇鏃堕棿 - - - 绗3娆FTBUF2涓柇鏃堕棿 - - - 绗2娆FTBUF2涓柇鏃堕棿 - - - 绗1娆FTBUF2涓柇鏃堕棿 - - - - FFT2LDTC涓柇鏃堕棿瀵勫瓨鍣 - - 绗4娆FT2LDTC涓柇鏃堕棿 - - - 绗3娆FT2LDTC涓柇鏃堕棿 - - - 绗2娆FT2LDTC涓柇鏃堕棿 - - - 绗1娆FT2LDTC涓柇鏃堕棿 - - - - TX FIR3 绯绘暟閰嶇疆瀵勫瓨鍣 - - 婊ゆ尝鍣ˋ2绯绘暟鍊间綆8bit - - - 婊ゆ尝鍣ˋ1绯绘暟鍊 - - - 婊ゆ尝鍣ˋ0绯绘暟鍊 - - - - TX FIR3 绯绘暟閰嶇疆瀵勫瓨鍣 - - 婊ゆ尝鍣ˋ5绯绘暟鍊间綆4bit - - - 婊ゆ尝鍣ˋ4绯绘暟鍊 - - - 婊ゆ尝鍣ˋ3绯绘暟鍊 - - - 婊ゆ尝鍣ˋ2楂4bit绯绘暟鍊 - - - - TX FIR3 绯绘暟閰嶇疆瀵勫瓨鍣 - - 婊ゆ尝鍣ˋ7绯绘暟鍊 - - - 婊ゆ尝鍣ˋ6绯绘暟鍊 - - - 婊ゆ尝鍣ˋ5楂8bit绯绘暟鍊 - - - - TX FIR3 閰嶇疆瀵勫瓨鍣 - - FIR3婊ゆ尝鍣ㄧ浉鍏崇郴鏁 - - - FIR3婊ゆ尝鍣ㄧ浉鍏崇郴鏁 - - - 婊ゆ尝鍣ㄦ椂閽熶娇鑳戒綅 - - - 婊ゆ尝鍣ㄤ娇鑳戒綅 - - - - TX FIR3 閰嶇疆瀵勫瓨鍣 - - 鏁版嵁鏈夋晥淇″彿璁℃暟 - - - - - - - - - - - - - - - - - - - - - - MEASPWR鐨勬帴鏀舵暟鎹帶鍒跺瘎瀛樺櫒1 - - FDD_TDD鎸囩ず锛 -0锛欶DD -1锛歍DD - - - TXRX妯″潡鐨凙D_ON鎷夐珮鎺ユ敹鏁版嵁鐨勮捣鐐逛綅缃紝 -0~30720*10-1锛10ms锛(AD ON璺濈鏈嶅姟灏忓尯甯уご鐨勮窛绂) - - - - MEASPWR鐨勬帴鏀舵暟鎹帶鍒跺瘎瀛樺櫒2 - - MEASPWR浣跨敤鐨勬湁鏁堟暟鎹殑闀垮害1~30720*6(6ms) - - - - MEASPWR鐨勬湁鏁堟暟鎹帶鍒跺瘎瀛樺櫒 - - Offset2鏃犳晥鎸囩ず -0锛歰ffset2閰嶇疆鏈夋晥 -1锛歰ffset2閰嶇疆鏃犳晥 - - - MEASPWR浣跨敤鐨勬湁鏁堟暟鎹殑璧风偣浣嶇疆 锛0~30720*6-1锛 - - - - MEASPWR鐨処D1鏃跺欢鎺у埗瀵勫瓨鍣 - - ID1鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D2鏃跺欢鎺у埗瀵勫瓨鍣 - - ID2鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D3鏃跺欢鎺у埗瀵勫瓨鍣 - - s - - - - MEASPWR鐨処D4鏃跺欢鎺у埗瀵勫瓨鍣 - - ID4鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D5鏃跺欢鎺у埗瀵勫瓨鍣 - - ID5鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D6鏃跺欢鎺у埗瀵勫瓨鍣 - - ID6鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D7鏃跺欢鎺у埗瀵勫瓨鍣 - - ID7鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR鐨処D8鏃跺欢鎺у埗瀵勫瓨鍣 - - ID8鍩轰簬鏈嶅姟灏忓尯鐨勫悓姝ュ亸宸 (0~30720*10-1) - - - - MEASPWR NB OFSET4瀵勫瓨鍣 - - Nb涓媜ffset4鍊 - - - - MEASPWR璁＄畻鎬诲瓙甯ф暟瀵勫瓨鍣 - - 鎵鏈塈D3~ID8璁＄畻鐨勬诲瓙甯т釜鏁 -0锛1 -1锛2 -2锛3 -鈥︹ -511:512 - - - 鎵鏈塈D1鍜孖D2璁＄畻鐨勬诲瓙甯т釜鏁 -0锛1 -1锛2 -2锛3 -鈥︹ -511:512 - - - - IFFT鎴綅鍥犲瓙閰嶇疆瀵勫瓨鍣 - - IFFT绗竷绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗叚绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗簲绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗洓绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗笁绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗簩绾ф埅浣嶅洜瀛愶細 -鍚屼笅 - - - IFFT绗竴绾ф埅浣嶅洜瀛愶細 -2鈥檅00:鎴彇bit[25:14] -2鈥檅01:鎴彇bit[26:15] -2鈥檅10:鎴彇bit[27:16] -2鈥檅11:鎴彇bit[28:17] - - - - MEASPWR IFFT鍊掓暟绗簩绾чケ鍜岄棬闄愪釜鏁板煎瘎瀛樺櫒 - - IFFT鍊掓暟绗簩绾чケ鍜岄棬闄愪釜鏁板 - - - - MEASPWR涓柇浣胯兘瀵勫瓨鍣 - - ID8 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[28]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[29]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[30]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[31]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID7 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[24]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[25]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[26]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[27]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID6 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[20]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[21]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[22]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[23]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID5 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[16]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[17]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[18]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[19]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID4 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[12]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[13]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[14]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[15]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID3 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[8]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[9]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[10]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[11]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID2 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[4]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[5]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[6]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[7]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - ID1 鐨勪腑鏂娇鑳斤紝1鏈夋晥锛0鏃犳晥 -bit[0]锛氭牱鏈粨鏉熶腑鏂娇鑳 -bit[1]锛氶棬闄愬煎埌杈句腑鏂娇鑳 -bit[2]锛欰FC缁撴灉杈撳嚭涓柇浣胯兘 -bit[3]:agc_compare闂ㄩ檺鍒拌揪涓柇浣胯兘 - - - - MEASPWR涓柇鐘舵佸瘎瀛樺櫒 - - ID8 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[28]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[29]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[30]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[31]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID7 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[24]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[25]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[26]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[27]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID6 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[20]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[21]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[22]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[23]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID5 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[16]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[17]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[18]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[19]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID4 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[12]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[13]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[14]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[15]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID3 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[8]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[9]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[10]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[11]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID2 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[4]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[5]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[6]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[7]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - ID1 鐨勪腑鏂姸鎬侊紝1鏈夋晥锛0鏃犳晥 -bit[0]锛氭牱鏈粨鏉熶腑鏂姸鎬 -bit[1]锛氶棬闄愬煎埌杈句腑鏂姸鎬 -bit[2]锛欰FC缁撴灉杈撳嚭涓柇鐘舵 -bit[3]:agc_compare闂ㄩ檺鍒拌揪鐘舵 - - - - ID1鍜孖D2鐨凪EASPWR鍔熻兘鎺у埗瀵勫瓨鍣 - - TRMS棰戝煙璁＄畻鍔熻兘浣胯兘 - - - SIGMA鍔熻兘浣胯兘 - - - DOPPLER鍔熻兘浣胯兘 - - - SINR鍔熻兘浣胯兘 - - - AFC鏅氭ā寮忓姛鑳戒娇鑳 - - - AFC楂橀熸ā寮忎娇鑳 - - - TRMS鍔熻兘浣胯兘 - - - RSRP鍔熻兘浣胯兘 - - - IRT鍔熻兘浣胯兘 - - - - ID3~ID8鐨凪EASPWR鍔熻兘鎺у埗瀵勫瓨鍣 - - TRMS棰戝煙璁＄畻鍔熻兘浣胯兘 - - - SIGMA鍔熻兘浣胯兘 - - - DOPPLER鍔熻兘浣胯兘 - - - SINR鍔熻兘浣胯兘 - - - AFC鏅氭ā寮忓姛鑳戒娇鑳 - - - AFC楂橀熸ā寮忎娇鑳 - - - TRMS鍔熻兘浣胯兘 - - - RSRP鍔熻兘浣胯兘 - - - IRT鍔熻兘浣胯兘 - - - - MEASPWR AGC宸奸棬闄愬煎瘎瀛樺櫒 - - 瀛愬抚闂碼gc宸奸棬闄愬硷紝褰撳墠瀛愬抚agc姣斿墠涓甯gc澶т簬姝ゅ兼椂锛屽皢娓呴浂鍓嶉潰鐨勮绠楀硷紝閲嶆柊寮濮嬭绠椼傦紙鏃犵鍙锋暟锛 - - - - MEASPWR 绐勫甫鍙傛暟瀵勫瓨鍣 - - ID3-8鐨勭獎甯﹀弬鏁帮細0-15锛堝彧鏈塁ATM闇瑕侊級 - - - ID2鐨勭獎甯﹀弬鏁帮細0-15锛堝彧鏈塁ATM闇瑕侊級 - - - ID1鐨勭獎甯﹀弬鏁帮細0-15锛堝彧鏈塁ATM闇瑕侊級 - - - - MEASPWR ID2鐨勫甫瀹藉弬鏁板瘎瀛樺櫒 - - ID3-8娴嬮噺甯﹀鍙傛暟 -0锛1.4m -1锛3m -2锛5m -3锛10m -4锛15m -5锛20m - - - ID3-8绯荤粺甯﹀鍙傛暟 -0锛1.4m -1锛3m -2锛5m -3锛10m -4锛15m -5锛20m - - - ID1-2娴嬮噺甯﹀鍙傛暟 -0锛1.4m -1锛3m -2锛5m -3锛10m -4锛15m -5锛20m - - - ID1-2绯荤粺甯﹀鍙傛暟 -0锛1.4m -1锛3m -2锛5m -3锛10m -4锛15m -5锛20m - - - - - AFC閰嶇疆瀵勫瓨鍣 - - Afc_factor - - - AFC璁＄畻瀛愬抚闂磋繛缁爣蹇 -0锛氫笉杩炵画 -1锛氳繛缁 -杩炵画琛ㄧず瀛愬抚闂存暟鎹叧鑱旇繘琛屽叡杞绠楋紱涓嶈繛缁〃绀哄瓙甯у唴4涓鍙疯繘琛屽叡杞绠楋紝瀛愬抚闂存棤鍏宠仈銆 - - - AFC璁＄畻棰戝煙鐩稿叧涓暟 -000锛1 -001锛2 -010锛3 -011锛4 -100锛6锛 -101锛12 -Other:1 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID1 AFC杞籂閰嶇疆鍥犲瓙 - - - - Sigpwr閰嶇疆瀵勫瓨鍣 - - SIGPWR alpha鍙傛暟 - - - SIGPWR璁＄畻鏃跺煙鐩稿叧涓暟 -00锛1 -01锛2 -11锛4 -Other锛1 - - - ID1-2 SIGPWR璁＄畻棰戝煙鐩稿叧涓暟(鎸夊疄闄呮暟鎹釜鏁伴厤缃級 - - - - SIGMA閰嶇疆瀵勫瓨鍣 - - SIGMA alpha鍙傛暟 - - - SIGMA璁＄畻婊戝姩绐楅暱涓暟锛屾湁鏁堝彇鍊间负1~80 - - - - DOPPLER閰嶇疆瀵勫瓨鍣 - - Id1-2 Doppler alpha鍙傛暟 - - - Doppler_scale锛圦12鐨勬湁绗﹀彿鏁帮級 - - - DOPPLER璁＄畻婊戝姩绐楅暱涓暟锛屾湁鏁堝彇鍊间负1~80 - - - - TRMS閰嶇疆瀵勫瓨鍣1 - - Trms閫夊緞闂ㄩ檺锛堟棤绗﹀彿鐨勶紝8q0锛屾鏁帮級 - - - 鍣０鍖哄煙閫夋嫨 -0锛氫娇鐢═RMS鐨凞is_Limit鍘昏绠楀櫔澹 -1锛氫娇鐢≧SRP鐨凞is_Limit鍘昏绠楀櫔澹 - - - ID3-8鎶藉兼爣蹇: -0:杩炵画鎶藉彇锛岀浉褰撲簬娉1鐨凩_U16ExtractStepTab_true闂撮殧涓1 -1锛氭寜鐓ф敞1鐨凩_U16ExtractStepTab_true闂撮殧杩涜鎶藉彇 - - - ID1-2鎶藉兼爣蹇: -0:杩炵画鎶藉彇锛岀浉褰撲簬娉1鐨凩_U16ExtractStepTab_true闂撮殧涓1 -1锛氭寜鐓ф敞1鐨凩_U16ExtractStepTab_true闂撮殧杩涜鎶藉彇 - - - 淇″彿鍖哄煙(鍗曡竟闀垮害锛屽嵆鍗婂緞N锛屼俊鍙峰尯鍩熶负2N+1) - - - - TRMS閰嶇疆瀵勫瓨鍣2 - - ID1-2淇″彿闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q15锛屾鏁帮級 - - - ID1-2鍣０闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q10锛屾鏁帮級 - - - - RSRP閰嶇疆瀵勫瓨鍣1 - - ID3-8鎶藉兼爣蹇 - - - ID1-2鎶藉兼爣蹇 - - - ID1-2鍣０闂ㄩ檺鍥犲瓙beta鍊硷紙鏈夌鍙风殑16Q10锛屽彧鑳介厤缃负姝ｆ暟锛 - - - 淇″彿鍖哄煙 - - - - RSRP閰嶇疆瀵勫瓨鍣2 - - ID3-8RSRP鐨勮ˉ鍋垮 - - - ID1-2RSRP鐨勮ˉ鍋垮 - - - L_S32RsrpdB_Temp = L_S32RsrpdB - AGC_Base*16 - RSRPAgcAdjust*16 + L_U16DownSamplingCompensate*16锛 - - - - RSRP閰嶇疆瀵勫瓨鍣3 - - ID1-2淇″彿闂ㄩ檺鍥犲瓙 - - - RSSI Q鍊硷紱(鏈夌鍙) - - - - RSRP閰嶇疆瀵勫瓨鍣4 - - FFT鍜孖FFT鐨凲鍊煎彉鍖栵紱 - - - 缁忚繃FFT鍜孖FFT鐨勬斁澶у嶆暟锛 - - - - IRT鍙傛暟閰嶇疆瀵勫瓨鍣1 - - IRT璐熸椂寤跺墠鍚戜繚鎶ゆ爣蹇 -0锛氫笉淇濇姢锛堝師8910鏂规锛 -1锛氫繚鎶 - - - pow鏈澶у间釜鏁 - - - Scale璁＄畻浣跨敤寰勬暟 - - - 淇″彿鍖哄煙 - - - IRT璁＄畻鏃跺煙鍗曟绱姞鏍锋湰涓暟 -00锛1 -01锛2 -11锛4 - - - - IRT 鍙傛暟閰嶇疆瀵勫瓨鍣2 - - ID1-2淇″彿闂ㄩ檺鍥犲瓙 - - - ID1-2鍣０闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q10锛屾鏁帮級 - - - - IRT ID1-2 Scale1闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale2闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale4闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale8闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale16闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale32闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale64闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale128闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale256闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID1-2 Scale512闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - RSSI鍙傛暟閰嶇疆瀵勫瓨鍣 - - ID3-8 Rssi琛ュ伩鍊 - - - ID1-2 Rssi琛ュ伩鍊 - - - 鎵鏈塈D鐨凴SSI鐨勮绠楁柟寮忛夋嫨锛 -0锛歁EASPWR浣跨敤鐨勬湁鏁堟暟鎹腑鏈夋晥鐨凮FDM绗﹀彿璁＄畻RSSI -1锛歁EASPWR浣跨敤鐨勬湁鏁堟暟鎹暱搴︾殑鏁版嵁璁＄畻 - - - - MEASPWR鐨勬帴鏀舵暟鎹殑AGC瀵勫瓨鍣 - - 鎺ユ敹澶╃嚎鐨凙GC锛屾湁绗﹀彿鏁 - - - - MEASPWR ID1鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - AFC杈撳嚭姝ヨ繘鍙傛暟锛屼互瀹為檯鍊煎噺涓閰嶇疆 - - - Crs_rssi褰掑睘閫夋嫨 -00锛氬綊灞炰竴 -01锛氬綊灞炰簩 -10锛氬綊灞炰笁 -11锛歳eserved - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - AFC缁撴灉杈撳嚭鏃堕棿閫夋嫨 -0锛氬悓IRT -1锛氫互bit[8:1]閰嶇疆鐨勫瓙甯ф暟涓洪棿闅 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - - MEASPWR ID1鍙傛暟瀵勫瓨鍣2 - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[25:16]涓娆″搴斿瓙甯9-0 - - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - SINR褰掑睘棰戞璁剧疆 -000锛歂A锛堜笉浣胯兘绐勫甫SINR锛 -001锛氶娈1 -010锛氶娈2 -011锛氶娈3 -100锛氶娈4 -Other锛歂A - - - AFC鍏宠仈浣胯兘 -0锛氫笌鍓嶄竴瀛愬抚鏁版嵁鍏宠仈 -1锛氫笌鍓嶄竴瀛愬抚鏁版嵁涓嶅叧鑱 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID2鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - AFC杈撳嚭姝ヨ繘鍙傛暟锛屼互瀹為檯鍊煎噺涓閰嶇疆 - - - Crs_rssi褰掑睘閫夋嫨 -00锛氬綊灞炰竴 -01锛氬綊灞炰簩 -10锛氬綊灞炰笁 -11锛歳eserved - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - AFC缁撴灉杈撳嚭鏃堕棿閫夋嫨 -0锛氬悓IRT -1锛氫互bit[8:1]閰嶇疆鐨勫瓙甯ф暟涓洪棿闅 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - - MEASPWR ID2鍙傛暟瀵勫瓨鍣2 - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[25:16]涓娆″搴斿瓙甯9-0 - - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - - AFC鍏宠仈浣胯兘 -0锛氫笌鍓嶄竴瀛愬抚鏁版嵁鍏宠仈 -1锛氫笌鍓嶄竴瀛愬抚鏁版嵁涓嶅叧鑱 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID3鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID4鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID5鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID6鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID7鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID8鍙傛暟瀵勫瓨鍣1 - - FFT鐨勯噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜 -鈥. - - - OFFLINE妯″紡0姝ヨ繘娆℃暟 - - - 涓嬭棣栧瓙甯ч绗﹀彿鏈夋晥鎸囩ず -0锛氭棤鏁 -1锛氭湁鏁 - - - NID鍊硷細鍙栧间负 0~503 - - - 鍙戝皠澶╃嚎涓2鏃朵娇鐢ㄧ殑port鎸囩ず -0锛歱ort 0 and port 1 -1锛歰nly port 1 - - - 鍙戝皠澶╃嚎鏁帮細 -0锛1鍙戝皠澶╃嚎 -1锛2鍙戝皠澶╃嚎 - - - CP绫诲瀷锛 -0锛氬父瑙凜P -1锛氭墿灞旵P - - - Crs_rssi娓呴浂鎺у埗 - - - 鏈鍚庝竴涓暟鎹獥鏍囪 - - - 婊戝姩绐楁竻闆舵帶鍒 -0锛氫笉娓呴浂 -1锛氭竻闆 - - - 閲嶆柊寮濮嬫帶鍒朵綅锛 -0锛氫笌鍓嶉潰瀛愬抚杩炵画 -1锛氬紑濮嬪叏鏂拌绠 -璇ヤ綅琚疆1鍚庯紝鍦ㄤ笅涓瀛愬抚灏嗗墠闈㈢殑璁＄畻缁撴灉鍏ㄩ儴娓呴浂锛岄噸鏂板紑濮嬭绠楀拰瀛愬抚璁℃暟 - - - - MEASPWR ID鎺у埗瀵勫瓨鍣 - - Offline妯″紡閫夋嫨 -0锛氭ā寮0澶氭鑷姩璁＄畻妯″紡 -1锛氭ā寮1鍗曟鐩存帴閰嶇疆妯″紡 - - - offline鏁版嵁閫夋嫨锛 -0锛氫娇鐢ㄥ綋鍓嶆暟鎹 -1锛氫娇鐢ㄥ師濮嬫暟鎹 - - - NID1-2鍙傛暟淇℃伅 - - - IRT杞籂姝ｄ娇鑳斤細 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - AFC杞籂姝ｄ娇鑳斤細 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - 妯″紡閫夋嫨锛 -0锛欳ATM -1锛欳AT1 -2锛歂B -鍏朵粬锛歂B_LTE涓嬪惎鍔‵FT鍔熻兘 - - - - MEASPWR ID鎺у埗瀵勫瓨鍣 - - NID_MAP鏃犳晥鎸囩ず -0锛氶厤缃湁鏁 -1锛氶厤缃棤鏁 - - - NID3-8鍙傛暟淇℃伅 - - - Offline涓巓nline妯″紡閫夋嫨锛 -0锛歰nline妯″紡 -1锛歰ffline妯″紡 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - 鎸囩ず褰撳墠绐楁湁鏁圛D锛1 -鏈夋晥锛0鏃犳晥 - - - - MEASPWR鎺у埗瀵勫瓨鍣 - - 鍚姩NID8 - - - 鍚姩NID7 - - - 鍚姩NID6 - - - 鍚姩NID5 - - - 鍚姩NID4 - - - 鍚姩NID3 - - - 鍚姩NID2 - - - 鍚姩NID1 - - - - ID1 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID2 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID3 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID4 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID5 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID1鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID2鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID3鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID4鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID5鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - 棰戞1 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞2 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞3 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞4 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞5 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞6 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID2 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID3 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID4 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID5 SIGPWR杈撳嚭瀵勫瓨鍣 - - - 棰戞1 SIGMA杈撳嚭瀵勫瓨鍣 - - - 棰戞1鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞1鐨凷INR LOG鍊 - - - 棰戞1鐨凷IGMA瀵瑰簲鐨凙GC - - - - 棰戞2 SIGMA杈撳嚭瀵勫瓨鍣 - - - 棰戞2鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞2鐨凷INR LOG鍊 - - - 棰戞2鐨凷IGMA瀵瑰簲鐨凙GC - - - - 棰戞3 SIGMA杈撳嚭瀵勫瓨鍣 - - - 棰戞3鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞3鐨凷INR LOG鍊 - - - 棰戞3鐨凷IGMA瀵瑰簲鐨凙GC - - - - 棰戞4 SIGMA杈撳嚭瀵勫瓨鍣 - - - 棰戞4鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞4鐨凷INR LOG鍊 - - - 棰戞4鐨凷IGMA瀵瑰簲鐨凙GC - - - - 绐勫甫鎬籗IGMA杈撳嚭瀵勫瓨鍣 - - - 绐勫甫鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞5鐨凷INR LOG鍊 - - - 绐勫甫鎬荤殑SIGMA瀵瑰簲鐨凙GC - - - - ID1 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID1鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - 棰戞6鐨凷INR LOG鍊 - - - ID1鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID2 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID2鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID2鐨凷INR LOG鍊 - - - ID2鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID3 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID3鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID3鐨凷INR LOG鍊 - - - ID3鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID4 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID4鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID4鐨凷INR LOG鍊 - - - ID4鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID5 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID5鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID5鐨凷INR LOG鍊 - - - ID5鐨凷IGMA瀵瑰簲鐨凙GC - - - - 棰戞1鐨凷INR杈撳嚭瀵勫瓨鍣 - - - 棰戞2鐨凷INR杈撳嚭瀵勫瓨鍣 - - - 棰3鐨凷INR杈撳嚭瀵勫瓨鍣 - - - 棰戞4鐨凷INR杈撳嚭瀵勫瓨鍣 - - - 绐勫甫鎬荤殑SINR杈撳嚭瀵勫瓨鍣 - - - ID1鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID2鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID3鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID4鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID5鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID1 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID1 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP绾挎у煎瘎瀛樺櫒 - - - RSRP鍔熺巼鍊煎瘎瀛樺櫒 - - RSRP鍔熺巼dB鍊 - - - - RSRP 鐨凷cale鍊煎瘎瀛樺櫒 - - - RSRP 鐨凷cale鐨刣B鍊煎瘎瀛樺櫒 - - Scale鐨刣B鍊 - - - - RSRP 鐨凴SRQ鐨刣B鍊煎瘎瀛樺櫒 - - RSRQ鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - RSRP 鐨凴SSI鐨勭嚎鎬у煎瘎瀛樺櫒 - - - RSRP 鐨凴SSI鐨刣B鍊煎瘎瀛樺櫒 - - RSSI鐨刣B鍊硷紙閫氶亾浠ュ強OFDM绗﹀彿鎷夐綈涔嬪悗鐨勭粨鏋滐級 - - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - IRT鐨刣elay鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - IRT scale鏍囧織瀵勫瓨鍣 - - Irt_scale鍊兼槸鍚﹁揪鍒伴棬闄愭爣蹇 -1锛氳揪鍒伴棬闄 -0锛氭湭杈鹃棬闄 - - - IRTscale瀵瑰簲鐨勬牱鏈暟 - - - - IRT鐨凷cale鍊煎瘎瀛樺櫒 - - - ID1 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID1 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣1 - - ID2淇℃伅杈撳嚭 - - - ID1淇℃伅杈撳嚭 - - - - RBIS鍙傛暟瀵勫瓨鍣 - - ID1-2 RBIS CORRECT浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID1-2 RBIS JUDGE浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID1-2 RBIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID1-2 RBIS浣跨敤鐩存帴浣嶇疆鎸囩ず锛 -0锛氫笉浣跨敤鐩存帴浣嶇疆 -1锛氫娇鐢ㄧ洿鎺ヤ綅缃 - - - ID1-2 RBIS妫娴嬩釜鏁帮細 -0锛1 -1锛2 -2锛3 -3锛4 -4锛5 - - - ID1-2 RBIS鐨勭洿鎺ヤ綅缃 - - - ID1-2 RBIS鍥犲瓙 - - - - RBIS ID1 杈撳嚭瀵勫瓨鍣1 - - ID1绗4寮篟BI鎵澶凱RB绱㈠紩杈撳嚭 - - - ID1绗3寮篟BI鎵澶凱RB绱㈠紩杈撳嚭 - - - ID1绗2寮篟BI鎵澶凱RB绱㈠紩杈撳嚭 - - - ID1绗1寮篟BI鎵澶凱RB绱㈠紩杈撳嚭 - - - - RBIS ID1杈撳嚭瀵勫瓨鍣2 - - ID1 RBIS JUDGE涓暟杈撳嚭 - - - ID1绗5寮篟BI鎵澶凱RB绱㈠紩杈撳嚭 - - - - RBIS ID1 AVE杈撳嚭瀵勫瓨鍣 - - - RBIS ID1 MAX杈撳嚭瀵勫瓨鍣 - - ID1 RBIS妫娴嬪嚭鐨勬渶澶у - - - - RX_IRT杈撳嚭瀵勫瓨鍣 - - ID2 offset4鍊 - - - ID2 RX IRT鍊 - - - ID1 offset4鍊 - - - ID1 RX IRT鍊 - - - - DEBUG杈撳嚭瀵勫瓨鍣 1 - - debug_rev_flag - - - debug_update_flag - - - id_update - - - offset2_update - - - din_id_sel - - - datagen_state - - - datain_state - - - - DEBUG杈撳嚭瀵勫瓨鍣 2 - - inmem_in_act - - - invalid_data_cont - - - inmem_cont - - - - DEBUG杈撳嚭瀵勫瓨鍣 3 - - datain_state_cur - - - func_id_sel - - - pow_state - - - func_state - - - - ID6 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID7 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID8 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID6 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID6鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID6鐨凷INR LOG鍊 - - - ID6鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID7 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID7鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID7鐨凷INR LOG鍊 - - - ID7鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID8 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID8鍩哄噯AGC杈撳嚭瀵勫瓨鍣 - - ID8鐨凷INR LOG鍊 - - - ID8鐨凷IGMA瀵瑰簲鐨凙GC - - - - ID6鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID7鐨凷INR杈撳嚭瀵勫瓨鍣 - - - ID8鐨凷INR杈撳嚭瀵勫瓨鍣 - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID2 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID3 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID4 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID5 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID6 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID7 AFC杞籂閰嶇疆鍥犲瓙 - - - - AFC杞籂閰嶇疆瀵勫瓨鍣 - - ID8 AFC杞籂閰嶇疆鍥犲瓙 - - - - DOPPLER閰嶇疆瀵勫瓨鍣 - - Id3-8 Doppler alpha鍙傛暟 - - - - 棰戝煙TRMS閰嶇疆瀵勫瓨鍣 - - trmsf_scale(Q12鐨勬湁鏁堢鍙凤級 - - - 棰戝煙TRMS鏁版嵁璁＄畻闂撮殧 - - - 棰戝煙TRMS alpha鍙傛暟 - - - - MEASPWR ID3鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - MEASPWR ID4鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - MEASPWR ID5鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - MEASPWR ID6鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - MEASPWR ID7鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - MEASPWR ID8鐨勫弬鏁板瘎瀛樺櫒2 - - OFFLINE妯″紡0姝ヨ繘闀垮害 - - - Hmmse QF mem閫夋嫨锛 -0锛氬浐瀹歈F mem -1锛氬姩鎬丵F mem - - - IRT scale闂ㄩ檺涓嶄娇鑳芥帶鍒 -0锛氫娇鑳介棬闄愬垽鏂 -1锛氫笉浣胯兘闂ㄩ檺鍒ゆ柇 - - - AFC\POW鏁版嵁杈撳叆閫夋嫨 -00锛歨ls -01锛歨mmse -10锛歠reqfirst -11锛歨ls - - - 鏈夋晥瀛愬抚鏄犲皠锛屼粠bit[9:0]渚濇瀵瑰簲瀛愬抚9-0 - - - - ID1 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID2 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID3 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID4 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID5 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID6 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID7 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID8 AFC HST杈撳嚭瀵勫瓨鍣 - - AFC HST杈撳嚭缁撴灉 - - - - ID1 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID2 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID3 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID4 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID5 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID6 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID7 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID8 SIGPWR杈撳嚭瀵勫瓨鍣 - - - ID1 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID2 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID3 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID4 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID5 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID6 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID7 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID8 SIGMA杈撳嚭瀵勫瓨鍣 - - - ID3 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID4 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID5 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID6 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID7 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID8 DOPPLER杈撳嚭瀵勫瓨鍣 - - hls_agc_base杈撳嚭 - - - DOPPLER杈撳嚭 - - - - ID1 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID1 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID2 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID2 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID1 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID2 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID3 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID4 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID5 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID6 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID7 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - ID8 TRMS棰戝煙杈撳嚭瀵勫瓨鍣 - - - - ID1 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID1 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID2 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID2 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID3 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID3 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID4 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID4 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID5 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID5 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID6 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID6 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID7 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID7 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID8 TRMS棰戝煙PART1杈撳嚭瀵勫瓨鍣 - - - ID8 TRMS棰戝煙PART2杈撳嚭瀵勫瓨鍣 - - - ID1 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID2 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID3 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID4 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID5 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID6 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID7 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID8 POW鏈澶у煎瘎瀛樺櫒 - - POW鏈澶у硷紙鏈澶у肩殑bit[23:0]锛 - - - 鏈澶у间綅缃 - - - - ID3 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID4 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID5 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID6 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID7 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - ID8 TRMS鐨凷cale鍊煎瘎瀛樺櫒 - - 鏃跺欢浼拌鍊 - - - - REIS閰嶇疆瀵勫瓨鍣 - - REIS_DC浣胯兘 - - - REIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - REIS鐨凬UM涓暟 - - - - REIS浣嶇疆瀵勫瓨鍣0 - - REIS1鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS0鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣1 - - REIS3鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS2鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣0 - - REIS5鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS4鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - REIS浣嶇疆瀵勫瓨鍣0 - - REIS7鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - REIS6鐨凴E浣嶇疆锛20M甯﹀1200涓猂E鐨勭粷瀵逛綅缃級 - - - - OFFLINE妯″紡0閫夋嫨瀵勫瓨鍣 - - Pos\delay鍒ゅ喅閫夋嫨鏍囧織 -0锛歱os -1:delay - - - 闂ㄩ檺鐩爣閫夋嫨锛 -00锛欼RT_Scale -01锛歊SRP_Scale -10锛歋INR -11锛歅OWMAX_Scale - - - 鎺掑簭鐩爣閫夋嫨锛 -00锛欼RT_Scale -01锛歋igpwr -10锛歋INR -11锛欼RT_Scale - - - - OFFLINE妯″紡0闂ㄩ檺鍊煎瘎瀛樺櫒 - - - OFFLINE妯″紡0鏈澶у间綅缃瘎瀛樺櫒 - - Id8鏈浣砊Bin浣嶇疆 - - - Id7鏈浣砊Bin浣嶇疆 - - - Id6鏈浣砊Bin浣嶇疆 - - - Id5鏈浣砊Bin浣嶇疆 - - - Id4鏈浣砊Bin浣嶇疆 - - - Id3鏈浣砊Bin浣嶇疆 - - - Id2鏈浣砊Bin浣嶇疆 - - - Id1鏈浣砊Bin浣嶇疆 - - - - OFFLINE妯″紡0闂ㄩ檺璺冲嚭浣嶇疆瀵勫瓨鍣 - - 鏈浣砊bin浣嶇疆鏈夋晥鏍囧織锛屽垎鍒搴擨D1~ID8 -0锛氭棤鏁 -1锛氭湁鏁 - - - Offline闂ㄩ檺鍊艰烦鍑轰綅缃瘎瀛樺櫒 -濡傛灉鏈揪鍒伴棬闄愬垯璇ュ瘎瀛樺櫒杈撳嚭涓0xF - - - - OFFLINE妯″紡1鍙傛暟瀵勫瓨鍣 - - 棣栫鍙峰畾涔 -0锛氱鍙0 -1锛氱鍙4鎴3 - - - Offline妯″紡1妯″紡閫夋嫨 -00锛氾經0锝濆瓙甯 -01锛氾經0銆5锝濆瓙甯 -10锛氾經5銆0锝濆瓙甯 -11锛氾經9锛0锝濆瓙甯 - - - Offline妯″紡1鍗曟璁＄畻瀛愬抚鏁 -0锛1涓 -1锛2涓 - - - Offline妯″紡1璁＄畻娆℃暟 - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣1 - - 瀛愬抚3 AGC - - - 瀛愬抚2 AGC - - - 瀛愬抚1 AGC - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣2 - - 瀛愬抚6 AGC - - - 瀛愬抚5 AGC - - - 瀛愬抚4 AGC - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣3 - - 瀛愬抚9 AGC - - - 瀛愬抚8 AGC - - - 瀛愬抚7 AGC - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣4 - - 瀛愬抚12 AGC - - - 瀛愬抚11 AGC - - - 瀛愬抚10 AGC - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣5 - - 瀛愬抚15 AGC - - - 瀛愬抚14 AGC - - - 瀛愬抚13 AGC - - - - OFFLINE妯″紡1AGC瀵勫瓨鍣6 - - 瀛愬抚18 AGC - - - 瀛愬抚17 AGC - - - 瀛愬抚16 AGC - - - - ID1 CRS_RSSI1鏈澶у煎瘎瀛樺櫒 - - - ID1 CRS_RSSI2鏈澶у煎瘎瀛樺櫒 - - - ID1 CRS_RSSI3鏈澶у煎瘎瀛樺櫒 - - - ID2 CRS_RSSI1鏈澶у煎瘎瀛樺櫒 - - - ID2 CRS_RSSI2鏈澶у煎瘎瀛樺櫒 - - - ID2 CRS_RSSI3鏈澶у煎瘎瀛樺櫒 - - - - ID3 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID4 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID5 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID6 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID7 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID8 CRS_RSSI鏈澶у煎瘎瀛樺櫒 - - - ID1 CRS_RSSI1AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID1 CRS_RSSI2AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID1 CRS_RSSI3AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID2 CRS_RSSI1AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID2 CRS_RSSI2AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID2 CRS_RSSI3AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID3 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID4 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID5 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID6 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID7 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - ID8 CRS_RSSI AGC瀵勫瓨鍣 - - Crs rssi鏈澶у煎搴旂殑agc - - - - HMMSE棰戝煙浼拌绐楅暱鎸囩ず瀵勫瓨鍣 - - 棰戝煙浼拌绐楅暱鎸囩ず -0锛氶鍩熶及璁＄獥闀夸负3PRB锛 -1锛氶鍩熶及璁＄獥闀夸负6PRB - - - - HMMSE鎴綅鍙傛暟瀵勫瓨鍣 - - 涔樼疮鍔犲悗鎴彇13bit鏁版嵁鐨勬瘮鐗归夋嫨锛 -0x0锛氭埅鍙栭夋嫨29~17 -0x1锛氭埅鍙栭夋嫨28~16 -0x2锛氭埅鍙栭夋嫨27~15 -0x3锛氭埅鍙栭夋嫨26~14 -0x4锛氭埅鍙栭夋嫨25~13 -0x5锛氭埅鍙栭夋嫨24~12 -0x6锛氭埅鍙栭夋嫨23~11 -0x7锛氭埅鍙栭夋嫨22~10 -0x8锛氭埅鍙栭夋嫨21~9 -0x9锛氭埅鍙栭夋嫨20~8 -0xa锛氭埅鍙栭夋嫨19~7 -0xb锛氭埅鍙栭夋嫨18~6 -0xc锛氭埅鍙栭夋嫨17~5 -0xd锛氭埅鍙栭夋嫨16~4 -0xe锛氭埅鍙栭夋嫨15~3 -0xf锛氭埅鍙栭夋嫨14~2 - - - - HMMSE QF MEM浣跨敤瀵勫瓨鍣 - - USED_WL_IND - - - QF MEM瀹為檯浣跨敤鎸囩ず -00锛氫箳mem锛 -01锛氫箵mem -Other锛氬浐瀹歮em - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣2 - - ID38淇℃伅杈撳嚭 - - - - INMEM浣跨敤妯″紡閫夋嫨瀵勫瓨鍣 - - INMEM浣跨敤妯″紡閫夋嫨锛 -00锛 measpwr鍔熻兘浣跨敤 -01锛歄TDOA鍔熻兘浣跨敤 -10锛氱瓑鍒嗗叡浜 -11锛氬ぇ灏忓叡浜 - - - - ID1鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID2鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID3鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID4鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID5鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID6鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID7鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID8鍩轰簬AFC HST鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC HST鐨凴SRP db杈撳嚭缁撴灉 - - - - ID1 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID2 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID3 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID4 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID5 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID6 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID7 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID8 POWMAX SCALE鍊煎瘎瀛樺櫒 - - - ID6 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID7 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID8 AFC杈撳嚭瀵勫瓨鍣 - - AFC杈撳嚭缁撴灉 - - - - ID6鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID7鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID8鍩轰簬AFC鐨凴SRP db鍊艰緭鍑哄瘎瀛樺櫒 - - 鍩轰簬AFC鐨凴SRP db杈撳嚭缁撴灉 - - - - ID3 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID3 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID4 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID4 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID5 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID5 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID6 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID6 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID7 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID7 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - ID8 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒1 - - - ID8 DOPPLER骞虫粦鍓嶈緭鍑哄瘎瀛樺櫒2 - - - OFFLINE妯″紡1AGC瀵勫瓨鍣7 - - 瀛愬抚20AGC - - - 瀛愬抚19AGC - - - - MEASPWR涓柇鍏宠仈瀵勫瓨鍣 - - 涓柇鍏宠仈鏍囧織锛宐it[7:0]鍒嗗埆瀵瑰簲id8-id1 -0:涓嶅叧鑱 -1锛氬叧鑱 - - - - MEASPWR涓柇璁板綍瀵勫瓨鍣 - - 鍚孖D1 - - - 鍚孖D1 - - - 鍚孖D1 - - - 鍚孖D1 - - - 鍚孖D1 - - - 鍚孖D1 - - - 鍚孖D1 - - - ID1鐨勪腑鏂爣蹇楋紝1鏈夋晥锛0鏃犳晥 -bit[0]锛氭牱鏈粨鏉焅offine缁撴潫涓柇鏍囧織 -bit[1]锛氶棬闄愬艰揪鍒颁腑鏂爣蹇 -bit[2]锛欰FC缁撴灉杈撳嚭涓柇鏍囧織 -bit[3]锛欰gc_compare闂ㄩ檺杈惧埌鏍囧織 - - - - MEASPWR涓柇鏍囧織瀵勫瓨鍣 - - 涓柇鏍囧織锛宐it[7:0]鍒嗗埆瀵瑰簲id8-id1 -0锛氭棤鏁 -1锛氭湁鏁 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣1 - - ID1鍒ゅ喅浣嶇疆3 - - - ID1鍒ゅ喅浣嶇疆2 - - - ID1鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣2 - - ID2鍒ゅ喅浣嶇疆3 - - - ID2鍒ゅ喅浣嶇疆2 - - - ID2鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣3 - - ID3鍒ゅ喅浣嶇疆3 - - - ID3鍒ゅ喅浣嶇疆2 - - - ID3鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣4 - - ID4鍒ゅ喅浣嶇疆3 - - - ID4鍒ゅ喅浣嶇疆2 - - - ID4鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣5 - - ID5鍒ゅ喅浣嶇疆3 - - - ID5鍒ゅ喅浣嶇疆2 - - - ID5鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣6 - - ID6鍒ゅ喅浣嶇疆3 - - - ID6鍒ゅ喅浣嶇疆2 - - - ID6鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣7 - - ID7鍒ゅ喅浣嶇疆3 - - - ID7鍒ゅ喅浣嶇疆2 - - - ID7鍒ゅ喅浣嶇疆1 - - - - OFFLINE妯″紡0鍒ゅ喅浣嶇疆瀵勫瓨鍣8 - - ID8鍒ゅ喅浣嶇疆3 - - - ID8鍒ゅ喅浣嶇疆2 - - - ID8鍒ゅ喅浣嶇疆1 - - - - RBIS鍙傛暟瀵勫瓨鍣2 - - ID3-8 RBIS CORRECT浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID3-8 RBIS JUDGE浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID3-8 RBIS浣胯兘锛 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - ID3-8 RBIS浣跨敤鐩存帴浣嶇疆鎸囩ず锛 -0锛氫笉浣跨敤鐩存帴浣嶇疆 -1锛氫娇鐢ㄧ洿鎺ヤ綅缃 - - - ID3-8 RBIS妫娴嬩釜鏁帮細 -0锛1 -1锛2 -2锛3 -3锛4 -4锛5 - - - ID3-8 RBIS鐨勭洿鎺ヤ綅缃 - - - ID3-8 RBIS鍥犲瓙 - - - - RBIS ID2 杈撳嚭瀵勫瓨鍣1 - - ID2绗4寮篟BI鎵澶凱RB绱㈠紩 - - - ID2绗3寮篟BI鎵澶凱RB绱㈠紩 - - - ID2绗2寮篟BI鎵澶凱RB绱㈠紩 - - - ID2绗1寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID2杈撳嚭瀵勫瓨鍣2 - - ID2 RBIS JUDGE涓暟 - - - ID2绗5寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID2 AVE杈撳嚭瀵勫瓨鍣 - - - RBIS ID2 MAX杈撳嚭瀵勫瓨鍣 - - ID2 RBIS妫娴嬪嚭鐨勬渶澶у - - - - RBIS ID3-8 杈撳嚭瀵勫瓨鍣1 - - ID3-8绗4寮篟BI鎵澶凱RB绱㈠紩 - - - ID3-8绗3寮篟BI鎵澶凱RB绱㈠紩 - - - ID3-8绗2寮篟BI鎵澶凱RB绱㈠紩 - - - ID3-8绗1寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID3-8杈撳嚭瀵勫瓨鍣2 - - ID3-8 RBIS JUDGE涓暟 - - - ID3-8绗5寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID3-8 AVE杈撳嚭瀵勫瓨鍣 - - - RBIS ID3-8 MAX杈撳嚭瀵勫瓨鍣 - - ID3-8 RBIS妫娴嬪嚭鐨勬渶澶у - - - - IRT ID3-8 Scale1闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale2闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale4闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale8闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale16闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale32闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale64闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale128闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale256闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - IRT ID3-8 Scale512闂ㄩ檺鍙傛暟鍊煎瘎瀛樺櫒 - - - Sigpwr閰嶇疆瀵勫瓨鍣2 - - ID3-8 SIGPWR璁＄畻棰戝煙鐩稿叧涓暟锛堟寜瀹為檯鏁版嵁涓暟閰嶇疆锛 - - - - IRT鍙傛暟閰嶇疆瀵勫瓨鍣2 - - ID3-8淇″彿闂ㄩ檺鍥犲瓙 - - - id3-8鍣０闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q10锛屾鏁帮級 - - - - TRMS閰嶇疆瀵勫瓨鍣3 - - ID3-8淇″彿闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q15锛屾鏁帮級 - - - ID3-8鍣０闂ㄩ檺鍥犲瓙锛堟湁绗﹀彿鐨勶紝16q10锛屾鏁帮級 - - - - RSRP閰嶇疆瀵勫瓨鍣5 - - id3-8鍣０闂ㄩ檺鍥犲瓙beta鍊硷紙鏈夌鍙风殑16Q10锛屽彧鑳介厤缃负姝ｆ暟锛 - - - ID3-8淇″彿闂ㄩ檺鍥犲瓙 - - - - RBIS ID1 杈撳叆瀵勫瓨鍣1 - - ID1绗4寮篟BI鎵澶凱RB绱㈠紩 - - - ID1绗3寮篟BI鎵澶凱RB绱㈠紩 - - - - ID1绗2寮篟BI鎵澶凱RB绱㈠紩 - - - ID1绗1寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID1 杈撳叆瀵勫瓨鍣2 - - ID1 RBIS JUDGE涓暟 - - - ID1绗5寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID2杈撳叆瀵勫瓨鍣1 - - ID2绗4寮篟BI鎵澶凱RB绱㈠紩 - - - ID2绗3寮篟BI鎵澶凱RB绱㈠紩 - - - - ID2绗2寮篟BI鎵澶凱RB绱㈠紩 - - - ID2绗1寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID2杈撳叆瀵勫瓨鍣2 - - ID2 RBIS JUDGE涓暟 - - - ID2绗5寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID3-8杈撳叆瀵勫瓨鍣1 - - ID3-8绗4寮篟BI鎵澶凱RB绱㈠紩 - - - ID3-8绗3寮篟BI鎵澶凱RB绱㈠紩 - - - - ID3-8绗2寮篟BI鎵澶凱RB绱㈠紩 - - - ID3-8绗1寮篟BI鎵澶凱RB绱㈠紩 - - - - RBIS ID3-8杈撳叆瀵勫瓨鍣2 - - ID3-8 RBIS JUDGE涓暟 - - - ID3-8绗5寮篟BI鎵澶凱RB绱㈠紩 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 鍚姩瀵勫瓨鍣 - - 浜х敓DMA璇锋眰鎶婁互鍓嶈绠楀嚭鐨勭疮鍔犲姛鐜囨惉鍏DDET锛岀敤浜庣画鎺ヨ绠椼 -0:涓嶄骇鐢熻姹 -1:浜х敓璇锋眰 - - - 浜х敓DMA璇锋眰鎶婃渶鍚庝竴涓牱鏈绠楀嚭鐨勭疮鍔犲姛鐜囧瓨鍏ュ閮∕EM锛屽湪缁帴璁＄畻鏃朵娇鐢ㄣ -0:涓嶄骇鐢熻姹 -1:浜х敓璇锋眰 - - - 闈炶繛缁ā寮忎笅鏍锋湰闀垮害涓嶈冻5ms+2OFDM鏃剁殑鏍锋湰闀垮害锛 -鍙栧艰寖鍥达細1~9856鐐 - - - 闈炶繛缁ā寮忎笅鎺ユ敹鏁版嵁鏍锋湰鏁 -4鈥檅000: 鏁版嵁涓嶈冻5ms+2OFDM -4鈥檅0001: 1涓牱鏈 -鈥︹ -4鈥檅1111: 15涓牱鏈 - - - 0: 鎺ユ敹鏁版嵁闈炶繛缁 -1:鎺ユ敹鏁版嵁杩炵画 - - - 3鈥檅001: PSS绮楀悓姝 -3鈥檅010: PSS绮惧悓姝 -3鈥檅011: SSS鍚屾 -3鈥檅100: 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂 -3鈥檅101:閲嶅悓姝 -3鈥檅110:棰戠偣鐩叉悳 - - - TXRX鎺ユ敹鏁版嵁OFFSET浣胯兘 -1:OFFSET浣胯兘 -0:OFFSET涓嶄娇鑳 - - - 1: TXRX鎺ユ敹鏁版嵁鎼嚭DMA璇锋眰浣胯兘; -0: TXRX鎺ユ敹鏁版嵁鎼嚭DMA璇锋眰涓嶄娇鑳 - - - 1: IDDET妯″潡鏆傚仠涓 -0: IDDET 妯″潡宸叉殏鍋滄垨鏆傚仠鏈娇鑳 - - - 1: IDDET妯″潡鍚姩 -0: IDDET 妯″潡涓嶅惎鍔 - - - - PSS1_CTRL绮楀悓姝ユ帶鍒跺瘎瀛樺櫒 - - RSSI璁＄畻浣胯兘 - - - PSS杈撳嚭涓昏妭鐐规暟.鍙栧艰寖鍥1~12锛岀籂鏈湴棰戝亸浣胯兘鏃惰緭鍑5涓妭鐐癸紝姣忎釜棰戝亸涓涓紱绾犳湰鍦伴鍋忎笉浣胯兘鏃舵渶澶氳緭鍑12涓妭鐐 - - - 鏈澶у间釜鏁颁繚瀛,鍙栧艰寖鍥1~5 - - - 0: ICS娴佺▼;1: IDDET娴佺▼ - - - 0: 瀹氭椂婕傜Щ涓嶄娇鑳 0: 瀹氭椂婕傜Щ涓嶄娇鑳 - - - 0: ID2鏈煡 1: ID2宸茬煡涓0 2: ID2宸茬煡涓1 3: ID2宸茬煡涓2 - - - 0: 绾犳湰鍦伴鍋忎笉浣胯兘 1: 鏈湴棰戝亸灏濊瘯涓1 -2: 鏈湴棰戝亸灏濊瘯涓3 3: 鏈湴棰戝亸灏濊瘯涓5 - - - 0: 鏁板瓧AGC涓嶄娇鑳 1: 鏁板瓧AGC浣胯兘 - - - 0: 杈撳叆娑堢洿浠ュ強鎼暟浣胯兘涓嶄娇鑳 1: 杈撳叆娑堢洿浠ュ強鎼暟浣胯兘浣胯兘 - - - - PSS2_CTRL绮惧悓姝ユ帶鍒跺瘎瀛樺櫒 - - RSSI璁＄畻浣胯兘 - - - 绮惧悓姝ヨ绠楃偣鏁 鍙栧艰寖鍥1~12 - - - 1:瀹氭椂婕傜Щ浣胯兘 -0:瀹氭椂婕傜Щ涓嶄娇鑳 - - - 1: 绾犳湰鍦伴鍋忎娇鑳 -0: 绾犳湰鍦伴鍋忎笉浣胯兘 - - - 1: 鏁板瓧AGC浣胯兘 -0: 鏁板瓧AGC涓嶄娇鑳 - - - 1: 鎺ユ敹鏁版嵁娑堢洿浣胯兘 -0: 鎺ユ敹鏁版嵁娑堢洿涓嶄娇鑳 - - - - SSS_CTRL鏃犵嚎甯у悓姝ユ帶鍒跺瘎瀛樺櫒 - - RSSI璁＄畻浣胯兘 - - - 杈撳叆浣嶇疆婊戝姩璁＄畻娆℃暟 -0:涓嶈繘琛屽乏鍙虫粦鍔 -1:宸﹀彸鍒嗗埆婊戝姩1涓偣 -2:宸﹀彸鍒嗗埆婊戝姩2涓偣 -3:宸﹀彸鍒嗗埆婊戝姩4涓偣 - - - 0:宄板潎姣旀帓搴 -1:宄板兼帓搴 - - - 姣忎釜鑺傜偣杈撳嚭鏈澶у间釜鏁 -1~10 - - - NID1鍊硷紝ID宸茬煡鏃惰捣鏁 鍙栧艰寖鍥翠负0~168 - - - 鏃犵嚎甯у悓姝ヨ绠楃偣鏁 ICS鍜孖DDET鏃跺彇鍊艰寖鍥翠负1~12 - - - 1:瀹氭椂婕傜Щ浣胯兘 -0:瀹氭椂婕傜Щ涓嶄娇鑳 - - - 0:ICS娴佺▼ -1: ID DETECT娴佺▼ - - - 1: ID宸茬煡 0: ID鏈煡 - - - 1: FDD妯″紡 0: TDD妯″紡 - - - 1: 骞叉壈娑堥櫎浣胯兘 -0: 骞叉壈娑堥櫎涓嶄娇鑳 - - - 1: 骞叉壈娑堥櫎浣胯兘 -0: 骞叉壈娑堥櫎涓嶄娇鑳 - - - 1: 鏁板瓧AGC浣胯兘 -0: 鏁板瓧AGC涓嶄娇鑳 - - - 1: 鎺ユ敹鏁版嵁娑堢洿浣胯兘 -0: 鎺ユ敹鏁版嵁娑堢洿涓嶄娇鑳 - - - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂帶鍒跺瘎瀛樺櫒 - - RSSI璁＄畻浣胯兘 - - - 杈撳叆浣嶇疆婊戝姩璁＄畻娆℃暟 -0:涓嶈繘琛屽乏鍙虫粦鍔 -1:宸﹀彸鍒嗗埆婊戝姩1涓偣 -2:宸﹀彸鍒嗗埆婊戝姩2涓偣 -3:宸﹀彸鍒嗗埆婊戝姩4涓偣 - - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂绠楃偣鏁 鍙栧艰寖鍥翠负1~12 - - - 棰戠巼绮惧悓姝ユ椂锛孭SS涓嶴SS婊戝姩鐩稿叧鐨勬粦鍔ㄦ闀縈锛氬彇鍊间负0~4 - - - 1: FDD妯″紡 -0: TDD妯″紡 - - - 1: 棰戝亸绾犳浣胯兘 -0: 棰戝亸绾犳涓嶄娇鑳 - - - 1: 棰戠巼绮惧悓姝ヤ娇鑳 -0: 棰戠巼绮惧悓姝ヤ笉浣胯兘 - - - 1:瀹氭椂婕傜Щ浣胯兘 -0:瀹氭椂婕傜Щ涓嶄娇鑳 - - - 1: 鏁板瓧AGC浣胯兘 -0: 鏁板瓧AGC涓嶄娇鑳 - - - 1: 鎺ユ敹鏁版嵁娑堢洿浣胯兘 -0: 鎺ユ敹鏁版嵁娑堢洿涓嶄娇鑳 - - - - RESYNC_CTRL閲嶅悓姝ユ帶鍒跺瘎瀛樺櫒 - - RSSI璁＄畻浣胯兘 - - - 涓涓牱鏈緭鍏ユ暟鎹暱搴 -0:1ms -1:2ms -2:3ms -3:4ms -4:5ms - - - 00:瀛愬抚鏈煡 01: 瀛愬抚0 10: 瀛愬抚5 - - - 鏈澶у间釜鏁颁繚瀛 鍙栧艰寖鍥1~5 - - - ID1鍊 鍙栧艰寖鍥0~167 - - - ID2鍊 鍙栧艰寖鍥0~2 - - - 0: 鏁板瓧AGC涓嶄娇鑳 -1: 鏁板瓧AGC浣胯兘 - - - 0: 杈撳叆娑堢洿浠ュ強鎼暟浣胯兘涓嶄娇鑳 -1: 杈撳叆娑堢洿浠ュ強鎼暟浣胯兘浣胯兘 - - - - 棰戠巼绉讳綅鎺у埗瀵勫瓨鍣0 - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - - 棰戠巼绉讳綅鎺у埗瀵勫瓨鍣1 - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - - 棰戠巼绉讳綅鎺у埗瀵勫瓨鍣2 - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - 鎺ユ敹鏁版嵁RSSI绉讳綅鍊 鍙栧艰寖鍥-8~7 - - - - INT_CTRL涓柇鎺у埗瀵勫瓨鍣 - - 1:闈炶繛缁帴鏀跺崟娆¤绠楀畬鎴愭柇浣胯兘 -0:瀹屾垚鐘舵佸凡娓呴櫎鎴栨湭浜х敓涓柇涓嶄娇鑳 - - - 1: 棰戠巼鐩叉悳1涓瓙娈垫悳绱㈠畬鎴愪腑鏂娇鑳 -0: 棰戠巼鐩叉悳1涓瓙娈垫悳绱㈠畬鎴愪腑鏂笉浣胯兘 - - - 1:RSSI鍊艰绠楀畬鎴愪腑鏂娇鑳 -0: RSSI鍊艰绠楀畬鎴愪腑鏂笉浣胯兘 - - - 1:鏆傚仠涓柇浣胯兘 -0: 鏆傚仠涓柇涓嶄娇鑳 - - - 1: AXIDMA鎼暟閿欒涓柇浣胯兘 -0: AXIDMA鎼暟閿欒涓柇涓嶄娇鑳 - - - 1:TXRX鎺ユ敹鏁版嵁鏆傚仠涓柇浣胯兘 -0: TXRX鎺ユ敹鏁版嵁鏆傚仠涓柇涓嶄娇鑳 - - - 1:閲嶅悓姝ュ畬鎴愪腑鏂娇鑳 -0:閲嶅悓姝ュ畬鎴愪腑鏂笉浣胯兘 - - - 1:棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂畬鎴愪腑鏂娇鑳 -0: 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂畬鎴愪腑鏂笉浣胯兘 - - - 1:SSS鍚屾瀹屾垚涓柇浣胯兘 -0: SSS鍚屾瀹屾垚涓柇涓嶄娇鑳 - - - 1:PSS绮惧悓姝ュ畬鎴愪腑鏂娇鑳 -0: PSS绮惧悓姝ュ畬鎴愪腑鏂笉浣胯兘 - - - 1:PSS绮楀悓姝ュ畬鎴愪腑鏂娇鑳 -0: PSS绮楀悓姝ュ畬鎴愪腑鏂笉浣胯兘 - - - - PSS绮惧悓姝/SSS鍚屾鎺ユ敹鏁版嵁璧峰浣嶇疆閰嶇疆瀵勫瓨鍣 - - 绮楀悓姝SSI闂ㄩ檺鍊 - - - PSS绮楀悓姝XRX杈撳叆绗竴涓暟鎹殑浣嶇疆涓0锛孭SS绮惧悓姝ュ拰SSS鍚屾TXRX -杈撳叆绗竴涓暟鎹浉瀵0浣嶇疆鐨勫硷細0~19200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - SAM_NUM_CTRL 鏍锋湰鑷傚簲鎺у埗瀵勫瓨鍣 - - 璁＄畻鏍锋湰 鍙栧艰寖鍥0~200 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺瀵勫瓨鍣 - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊1 - - - 鏍锋湰缁勫搴斿嘲鍧囨瘮鍒ゅ埆闂ㄩ檺鍊0 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - PSS绮惧悓姝D閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - PSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - SSS ID閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲棰戝亸锛氬彇鍊艰寖鍥-32768~32767 - - - PSS绮楀悓姝ヨ绠楀嚭鐨勬瘡涓狪D瀵瑰簲鐨勫畾鏃舵紓绉伙細鍙栧艰寖鍥翠负-32~31 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - 棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂 ID閰嶇疆瀵勫瓨鍣 - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂弬鏁癗ID1 鍙栧艰寖鍥0-167 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS绮惧悓姝/SSS鍚屾/棰戠巼绮惧悓姝ュ拰ID鏈夋晥鎬у垽鏂璉D浣嶇疆閰嶇疆瀵勫瓨鍣 - - 姣忎釜ID鐨勪綅缃 鍙栧艰寖鍥0~9599 - - - - PSS_SSS_FIND閰嶇疆瀵勫瓨鍣 - - SSSMAX鏌ユ壘鍗婂緞闀垮害锛 鍙厤缃负灏忎簬10 - - - 鍣０绐楅暱搴﹂夋嫨锛 0:31 1:61 2:127 - - - 鍦↖DDET PSS娴佺▼涓紝闇瑕佸湪杩囬棬闄愮殑鏈寮鸿妭鐐圭殑ASSIST_WIN鍗婂緞鍐咃紝灏嗘壘鍑猴紝MAX_NUM鐐逛腑鏄惁鏈夋湭鎺掑湪鍓峆OS_NUM鐨勮妭鐐癸紝濡傛灉鏈夛紝鎶婅繖浜涜妭鐐瑰綋鍋氳緟鑺傜偣鍦ㄦ渶鍚庤緭鍑猴紝骞朵繚璇佽繖浜涚偣鍜孭OS_NUM涓殑鑺傜偣涓嶉噸澶嶃 - - - 澶氬緞绐楀崐寰勯暱搴︼細2鈥檅00:2 2鈥檅01:4 2鈥檅10:8 others:2 - - - 涓诲嘲涓庝富宄扮殑闂撮殧鍗婂緞锛屽悓鏃惰〃绀鸿緟宄版煡鎵捐寖鍥村崐寰勶細鍙厤缃负0-127 - - - 鍣０闂ㄩ檺浣胯兘 - - - 鍧囧肩殑涔樹互姝ょ郴鏁颁綔涓哄櫔澹伴棬闄愶紙Q3锛夛紙鏈夌鍙风殑闈為浂鏁帮級 - - - - PSS绮楀悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒1 - - PSS绮楀悓姝ラ鍋忓皾璇2 绉讳綅浣嶆暟鍙栧艰寖鍥-1024~1023 - - - PSS绮楀悓姝ラ鍋忓皾璇1 绉讳綅浣嶆暟鍙栧艰寖鍥-1024~1023 - - - PSS绮楀悓姝ラ鍋忓皾璇0 绉讳綅浣嶆暟鍙栧艰寖鍥-1024~1023 - - - - PSS绮楀悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒2 - - PSS绮楀悓姝ラ鍋忓皾璇4 绉讳綅浣嶆暟鍙栧艰寖鍥-1024~1023 - - - PSS绮楀悓姝ラ鍋忓皾璇3 绉讳綅浣嶆暟鍙栧艰寖鍥-1024~1023 - - - - PSS绮惧悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒1 - - PSS绮惧悓姝ラ鍋忓皾璇 鍙栧艰寖鍥-4096~4095 - - - - PSS绮惧悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒2 - - PSS绮惧悓姝ラ鍋忓皾璇 鍙栧艰寖鍥-4096~4095 - - - - PSS绮惧悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒3 - - PSS绮惧悓姝ラ鍋忓皾璇 鍙栧艰寖鍥-4096~4095 - - - - PSS绮惧悓姝ラ鍋忓皾璇曢厤缃瘎瀛樺櫒4 - - PSS绮惧悓姝ラ鍋忓皾璇 鍙栧艰寖鍥-4096~4095 - - - - RSSI鐩爣鍊奸厤缃瘎瀛樺櫒 - - - 绮楀悓姝ュ畾鏃跺亸绉婚厤缃瘎瀛樺櫒1 - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - - 绮楀悓姝ュ畾鏃跺亸绉婚厤缃瘎瀛樺櫒2 - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - - 绮楀悓姝ュ畾鏃跺亸绉婚厤缃瘎瀛樺櫒3 - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - - 绮楀悓姝ュ畾鏃跺亸绉婚厤缃瘎瀛樺櫒4 - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - - 绮楀悓姝ュ畾鏃跺亸绉婚厤缃瘎瀛樺櫒5 - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - PSS绮楀悓姝ュ畾鏃舵紓绉荤Щ浣嶅 鍙栧艰寖鍥翠负-32~31 - - - - PSS绮惧悓姝SS鍚屾瀹氭椂鍋忕Щ澧為噺閰嶇疆瀵勫瓨鍣 - - 瀹氭椂鍋忕Щ澧為噺 鍙栧艰寖鍥翠负-8~7 - - - 瀹氭椂鍋忕Щ澧為噺 鍙栧艰寖鍥翠负-8~7 - - - 瀹氭椂鍋忕Щ澧為噺 鍙栧艰寖鍥翠负-8~7 - - - 瀹氭椂鍋忕Щ澧為噺 鍙栧艰寖鍥翠负-8~7 - - - - FFT鎴綅鍥犲瓙瀵勫瓨鍣 - - 鎸囩ず FFT/IFFT 涓噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟(骞叉壈娑堥櫎)锛 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -鈥 - - - 鎸囩ず FFT/IFFT 涓噰鐢ㄥ畾鐐规暟鎴綅鏂瑰紡涓鐨勫墠鍑犵骇绾ф暟锛圥SS/SSS鍚屾锛夛細 -4`b0000锛氬悇绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -4`b0001锛氱涓绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -4`b0010锛氱涓銆佷簩绾ч噰鐢ㄦ埅浣嶆柟寮忎竴锛屽悗闈㈠嚑绾ч兘閲囩敤鎴綅鏂瑰紡浜岋紱 -鈥 - - - - 骞叉壈娑堥櫎鐨処D閰嶇疆瀵勫瓨 - - 骞叉壈灏忓尯棰戝亸绾犳浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - 骞叉壈灏忓尯棰戝亸绾犳鍥犲瓙 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP 0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 0锛氬瓙甯0 - - - SSS搴忓垪鐨勫弬鏁 - - - SSS搴忓垪鐨勫弬鏁 - - - - IC_CFG閰嶇疆瀵勫瓨鍣 - - 骞叉壈灏忓尯瀹氭椂婕傜Щ鍥犲瓙 - - - SSS鍚屾鏃剁殑骞叉壈娑堥櫎棣栦綅缃細 鍦9600鐐逛腑鐨勪綅缃 - - - 鎴綅鍥犲瓙 -0锛氫笉绉讳綅 -1锛氬彸绉1浣 -2锛氬彸绉2浣 -鈥 --1锛氬乏绉1浣 --2锛氬乏绉2浣 -鈥 - - - - ID棰戠巼绮惧悓姝ヨ緭鍑哄瘎瀛樺櫒 0 - - 棰戠巼绮惧悓姝ヨ緭鍑虹粨鏋0 - - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杩囬棬闄愭湁鏁堜釜鏁板瘎瀛樺櫒 - - SSS鍚屾杩囬棬闄愰佺粰灏忓尯鏈夋晥鎬у垽鏂釜鏁 -0锛氬墠0涓緭鍑烘湁鏁 -1锛氬墠1涓緭鍑烘湁鏁 -鈥 -12锛氬墠12涓緭鍑烘湁鏁 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杩囬棬闄愭湁鏁堜釜鏁 -0锛氬墠0涓緭鍑烘湁鏁 -1锛氬墠1涓緭鍑烘湁鏁 -鈥 -12锛氬墠12涓緭鍑烘湁鏁 - - - - 璁＄畻鏍锋湰鎬绘暟瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾銆侀鐜囩簿鍚屾鍜屽皬鍖烘湁鏁堟у垽鏂绠楃粨鏉熸椂浣跨敤鐨勬牱鏈绘暟 -鍙栧艰寖鍥0~200 - - - - RSSI鍊艰緭鍑哄瘎瀛樺櫒 - - PSS绮楀悓姝ユ粦鍔≧SSI鍊硷紝PSS绮惧悓姝ャ丼SS鍚屾銆侀鐜囩簿鍚屾鍜屽皬鍖烘湁鏁堟у垽鏂涓涓 -浣嶇疆RSSI鍊 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - SSS IDDET妯″紡涓嬫帓搴忓悗瀛樻斁浣嶇疆绱㈠紩 -鍙栧艰寖鍥0~11 - - - 鏃犵嚎甯у悓姝ャ侀鐜囩簿鍚屾鍋忕Щ浣嶇疆 -鍙栧艰寖鍥0-8 - - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 鍔熺巼鍣０杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍣０ - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭鍔熺巼 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - 棰戝亸灏濊瘯鍊 - - - PSS绮楀悓姝ャ丳SS绮惧悓姝ャ丼SS鍚屾杈撳嚭ID浣嶇疆 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - ID淇℃伅杈撳嚭瀵勫瓨鍣 - - 瀹氭椂婕傜Щ灏濊瘯鍊 - - - NID1鍊 -鍙栧艰寖鍥0-167 - - - ID瀵瑰簲鐨凜P绫诲瀷锛 -1锛欵XTEND CP -0锛歂ORMAL CP - - - ID瀵瑰簲鐨勫瓙甯у彿(SSS鏈湴淇″彿浜х敓浣跨敤)锛 -1锛氬瓙甯5 -0锛氬瓙甯0 - - - NID2鍊 -鍙栧艰寖鍥0-2 - - - - INT_FLAG鏍囧織瀵勫瓨鍣 - - 1:闈炶繛缁帴鏀跺崟娆¤绠楀畬鎴 -0:瀹屾垚鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:棰戠巼鐩叉悳鎵鏈夊瓙甯︿互鍙婃墍鏈夐娈垫悳绱㈠畬鎴 -0:瀹屾垚鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:棰戠巼鐩叉悳1涓瓙娈垫悳绱㈠畬鎴 -0:瀹屾垚鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:RSSI鍊艰绠楀畬鎴 -0: RSSI鍊艰绠楀畬鎴愮姸鎬佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:鏆傚仠瀹屾垚 -0: 鏆傚仠鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:AXIDMA鏈兘鍙婃椂鎼暟浜х敓閿欒 -0:閿欒鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:TXRX鎺ユ敹鏁版嵁鏆傚仠 -0:鏆傚仠鐘舵佸凡娓呴櫎鎴栨湭浜х敓 - - - 1:閲嶅悓姝ュ畬鎴 -0: 瀹屾垚鐘舵佹竻闄ゆ垨鏈畬鎴 - - - 1:棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂畬鎴 -0:瀹屾垚鐘舵佹竻闄ゆ垨鏈畬鎴 - - - 1:SSS鍚屾瀹屾垚 -0:瀹屾垚鐘舵佹竻闄ゆ垨鏈畬鎴 - - - 1:PSS绮惧悓姝ュ畬鎴 -0:瀹屾垚鐘舵佹竻闄ゆ垨鏈畬鎴 - - - 1:PSS绮楀悓姝ュ畬鎴 -0:瀹屾垚鐘舵佹竻闄ゆ垨鏈畬鎴 - - - - IDDET鐘舵佸瘎瀛樺櫒 - - 棰戠偣鐘舵佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - 閲嶅悓姝ョ姸鎬佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂姸鎬佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - 鏃犵嚎甯у悓姝ョ姸鎬佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - PSS绮惧悓姝ョ姸鎬佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - PSS绮楀悓姝ョ姸鎬佹寚绀 -1锛氭鍦ㄨ繘琛 -0锛氭湭鍚姩鎴栧凡缁忕粨鏉 - - - - 杞欢浣跨敤瀵勫瓨鍣 - - - 鍓嶆璁＄畻鏍锋湰涓暟瀵勫瓨鍣 - - 鍓嶆璁＄畻鏍锋湰涓暟 0~1023 - - - - 棰戠巼鐩叉悳鎺у埗瀵勫瓨鍣 - - 0:浣跨敤鍔熺巼鎺掑簭 -1:浣跨敤鍔熺巼绐楁瘮鍊兼帓搴 - - - 鍗曠嫭FFT浣胯兘锛 -0: 鍗曠嫭FFT涓嶄娇鑳 -1: 鍗曠嫭FFT(鍥哄畾1024鐐)浣胯兘,涓斿彧鍋氫竴娆FT锛屽氨缁撴潫 - - - 鍗曠嫭鎺掑簭浣胯兘: -0: 鍗曠嫭鎺掑簭涓嶄娇鑳 -1: 鍗曠嫭鎺掑簭浣胯兘,涓斿彧鍋氭帓搴忥紝灏辩粨鏉 - - - 鎺掑簭鐨勭粨鏉熷湴鍧1~999 - - - 鎺掑簭鐨勮捣濮嬪湴鍧0~999 - - - 鎺ユ敹鏁版嵁棰戠巼閫夋嫨 -0: 5M -1: 10M -2: 20M -鍏朵粬: 5M - - - 0: 涓嶆槸鏈鍚5ms鏁版嵁 -1: 鏈鍚5ms鏁版嵁 - - - 0: 涓嶆槸棣栦釜5ms鏁版嵁 -1: 棣栦釜5ms鏁版嵁 - - - - 棰戠巼鐩叉悳閰嶇疆瀵勫瓨鍣1 - - 鍔熺巼绐楁瘮鍊兼椂鐨勬埅浣嶅洜瀛愰厤缃; -0:鎴彇[19:0],杩涜淇濇姢涓20bit鐨勫姛鐜 -1:鎴彇[20:1],杩涜淇濇姢涓20bit鐨勫姛鐜 -鈥︹ -12:鎴彇[31:12],杩涜淇濇姢涓20bit鐨勫姛鐜 -鍏朵粬:鍚12鐨勯厤缃; - - - 鎺ユ敹鐨勬暟鎹鍩熻绠椾箣鍚,鍔熺巼鐨勬埅浣嶅洜瀛愰厤缃;I^2+Q^2=PWR(32bit) -0:鎴彇[31:15],杩涜淇濇姢涓16bit鐨勫姛鐜 -1:鎴彇[31:14],杩涜淇濇姢涓16bit鐨勫姛鐜 -鈥︹ -15:鎴彇[31:0],杩涜淇濇姢涓16bit鐨勫姛鐜 - - - 褰撳墠棰戞鐨勫瓙甯︾紪鍙 -鍙栧艰寖鍥0~49 - - - 褰撳墠棰戞鐨勫瓙甯︽绘暟 鍙栧艰寖鍥0~50 - - - 20MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 15MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 10MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 5MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 3MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 1.4MHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 200KHz鍔熺巼绐楁瘮鍊艰绠椾娇鑳 -0: 涓嶄娇鑳 -1: 浣胯兘 - - - 鍔熺巼璋辨粦鍔ㄥ钩鍧囩獥闀,鍙栧间负1~11 - - - - 棰戠巼鐩叉悳閰嶇疆瀵勫瓨鍣2 - - Selectbinnum鍙宠竟閰嶇疆锛0~511 - - - selectbinnum宸﹁竟閰嶇疆锛0~511 - - - - 鍔熺巼绐楁瘮鍊煎甫瀹借〃START鍊奸厤缃瘎瀛樺櫒1 - - 鍙栧艰寖鍥0~99 - - - 鍙栧艰寖鍥0~99 - - - 鍙栧艰寖鍥0~99 - - - 鍙栧艰寖鍥0~99 - - - - 鍔熺巼绐楁瘮鍊煎甫瀹借〃START鍊奸厤缃瘎瀛樺櫒2 - - 鍙栧艰寖鍥0~99 - - - 鍙栧艰寖鍥0~99 - - - 鍙栧艰寖鍥0~99 - - - - 鍔熺巼绐楁瘮鍊煎甫瀹借〃END鍊奸厤缃瘎瀛樺櫒1 - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - 鍙栧艰寖鍥0~15 - - - - 鍔熺巼绐楁瘮鍊煎甫瀹借〃END鍊奸厤缃瘎瀛樺櫒2 - - - AGC閰嶇疆瀵勫瓨鍣 - - 鍙栧艰寖鍥0~127 - - - - 纭欢宸茬粡璁＄畻鐨勫瓙甯︾殑鎬婚暱搴﹀瘎瀛樺櫒 - - 褰撳墠棰戞鐨勫瓙甯︿腑锛岀‖浠跺凡缁忚绠楃殑瀛愬甫鐨勯暱搴︾殑鍜屽 - - - - 纭欢宸茬粡璁＄畻鐨勫瓙甯︾殑鐩爣AGC瀵勫瓨鍣 - - 褰撳墠棰戞鐨勫瓙甯︿腑锛岀‖浠跺凡缁忚绠楃殑瀛愬甫鐨勭洰鏍嘇GC - - - - ID棰戠巼绮惧悓姝ヨ緭鍑哄瘎瀛樺櫒 1 - - 棰戠巼绮惧悓姝ヨ緭鍑虹粨鏋2 - - - 棰戠巼绮惧悓姝ヨ緭鍑虹粨鏋1 - - - - PSS1_RESYN_CTRL绮楀悓姝ラ噸鍚屾RSSI璁＄畻鑼冨洿閰嶇疆瀵勫瓨鍣 - - PSS绮楀悓姝ャ侀噸鍚屾RSSI璁＄畻鑼冨洿缁撴潫鍊硷紝绮楀悓姝ュ彇鍊艰寖鍥达細0~4799锛岄噸鍚屾鍙栧艰寖鍥达細0~9599 - - - PSS绮楀悓姝ャ侀噸鍚屾RSSI璁＄畻鑼冨洿璧峰鍊硷紝绮楀悓姝ュ彇鍊艰寖鍥达細0~4799锛岄噸鍚屾鍙栧艰寖鍥达細0~9599 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - 浣嶇疆杈撳嚭瀵勫瓨鍣 - - PSS绮楀悓姝ユ渶澶у糝SSI鍊 - - - - - 1銆 PSS绮楀悓姝ャ侀噸鍚屾鍔熺巼锛 -2銆 PSS绮楀悓姝ャ侀噸鍚屾RSSI鍊 - - - - 1銆 PSS绮惧悓姝ュ姛鐜 -2銆 SSS鍚屾鍔熺巼 - - - - 棰戠巼绮惧悓姝ュ拰灏忓尯鏈夋晥鎬у垽鏂姛鐜 - - - - QF鍊间繚瀛 - - - - 闈炰箳涔撴ā寮廙EM1-8 -涔掍箵妯″紡MEM1-11 -RF杈撳叆鏁版嵁瀵煎嚭锛堝彧璇伙級 - - - - - - 鐢ㄤ簬瀛樻斁棰戠巼鐩叉悳涓紝姣忎釜瀛愬甫鐨凙GC鎷夐綈涔嬪墠鐨勫姛鐜 - - 绗1涓瓙甯︾殑PWR1 - - - 绗1涓瓙甯︾殑PWR0 - - - - - 鐢ㄤ簬瀛樻斁棰戠巼鐩叉悳涓紝姣忎釜瀛愬甫鐨勯暱搴︿互鍙夾GC鍊 - - 绗1涓瓙甯︾殑闀垮害 - - - 绗1涓瓙甯︾殑AGC - - - - - - - - - CSI鍚姩瀵勫瓨鍣 - - data_drive妯″紡浣胯兘銆 -0锛氶潪data_drive -1锛歞ata_drive - - - DMA鍚姩CSI妯″潡鐨勪娇鑳姐 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - CSI妯″潡浣胯兘淇″彿銆 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 涓嬩釜瀛愬抚鐨凜SI閰嶇疆瀵勫瓨鍣 - - cp鎸囩ず銆 -0锛氬父瑙 -1锛氭墿灞 - - - FH杈撳嚭鎴綅鏂规銆 -5鈥檇0锛氭埅鍙杅h[11:0] -5鈥檇1锛氭埅鍙杅h[12:1] -5鈥檇2锛氭埅鍙杅h[13:2] -鈥︹ -5鈥檇16锛氭埅鍙杅h[27:16] -others锛氭埅鍙杅h[28:17] - - - CSI-RS鍜孋RS鐨勬寚绀恒 -0锛欳SI-RS -1锛欳RS - - - LS/FH/鍔熺巼璁＄畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻LS/FH/鍔熺巼 -1锛氫娇鑳斤紝瑕佽绠 - - - 杞欢閰嶇疆鐨勫甯I锛屽湪ri_sel=1鏃剁敤鏉ヨ绠桺MI銆 -0锛歊I=1 -1锛歊I=2 - - - 璁＄畻PMI鎵鐢ㄧ殑RI鐨勬潵婧愰夋嫨銆 -0锛氫娇鐢ㄧ‖浠惰绠楃殑瀹藉甫RI -1锛氫娇鐢ㄨ蒋浠堕厤缃殑RI - - - PMI浼扮畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻PMI -1锛氫娇鑳斤紝瑕佽绠桺MI - - - RI浼扮畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻RI -1锛氫娇鑳斤紝瑕佽绠桼I - - - 浼扮畻RI鏃舵槸鍚︿娇鐢≧I鍘嗗彶鍊肩殑鎸囩ず銆 -0锛氫笉浣跨敤鍘嗗彶鍊硷紝榛樿涓篟I=1 -1锛氫娇鐢ㄤ笂涓懆鏈熺殑瀹藉甫RI鍊 - - - 绯荤粺甯﹀銆傚彇鍊6/15/25/50/75/100PRB - - - 瀛愬甫甯﹀銆備笌绯荤粺甯﹀涓涓瀵瑰簲銆倀otal_nrb=6/15/25/50/75/100鏃讹紝sub_nrb=6/2/2/3/4/4 PRB銆 - - - 鍙戝皠澶╃嚎鏁般侰SI-RS鍙厤缃1銆2銆4銆8澶╃嚎锛孋RS鍙厤缃2銆4澶╃嚎銆 -0锛1澶╃嚎锛堝彧璁＄畻鍔熺巼锛屼笉璁＄畻RI鍜孭MI锛 -1锛2澶╃嚎 -2锛4澶╃嚎 -3锛8澶╃嚎 - - - - 涓嬩釜瀛愬抚鐨凴I浼拌闂ㄩ檺瀵勫瓨鍣 - - 銆((1-th2)/(1+th2))銆梌2鐨勫笺備及璁I鏃朵娇鐢ㄧ殑鍒ゅ喅闂ㄩ檺锛屽彇鍊间负澶т簬0灏忎簬1鐨勫皬鏁般傜敤Q15琛ㄧず銆倀h2鐨勫吀鍨嬪间负40銆 - - - 銆((1-th1)/(1+th1))銆梌2鐨勫笺備及璁I鏃朵娇鐢ㄧ殑鍒ゅ喅闂ㄩ檺锛屽彇鍊间负澶т簬0灏忎簬1鐨勫皬鏁般傜敤Q15琛ㄧず銆倀h1鐨勫吀鍨嬪间负60銆 - - - - 涓嬩釜瀛愬抚鐨勭爜鏈储寮曞瘎瀛樺櫒1 - - RI=2鏃剁殑2銆4澶╃嚎鐨勭爜鏈储寮曞彿鍙8澶╃嚎鐨勭爜鏈储寮曞彿i1鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - RI=1鏃剁殑2銆4澶╃嚎鐨勭爜鏈储寮曞彿鍙8澶╃嚎鐨勭爜鏈储寮曞彿i1鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - - 涓嬩釜瀛愬抚鐨勭爜鏈储寮曞瘎瀛樺櫒2 - - RI=2鏃剁殑8澶╃嚎鐨勭爜鏈储寮曞彿i2鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - RI=1鏃剁殑8澶╃嚎鐨勭爜鏈储寮曞彿i2鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - - 涓嬩釜瀛愬抚鐨勪腑鏂娇鑳藉瘎瀛樺櫒 - - 鐗╃悊灞備富鍗℃爣蹇椾綅 - - - 澶勭悊瀹屾垚涓柇浣胯兘銆 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 涓嬩釜瀛愬抚鐨凮FDM0鐨凜搴忓垪鍒濆鍊煎瘎瀛樺櫒 - - OFDM绗﹀彿0鐨凜搴忓垪鐨勫垵濮嬪硷紝鐢ㄦ潵璁＄畻鏈湴CSI-RS銆 - - - - 涓嬩釜瀛愬抚鐨凮FDM1鐨凜搴忓垪鍒濆鍊煎瘎瀛樺櫒 - - OFDM绗﹀彿1鐨凜搴忓垪鐨勫垵濮嬪硷紝鐢ㄦ潵璁＄畻鏈湴CSI-RS銆 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 妯″潡涓诲崱鏍囧織杈撳嚭 - - - 澶勭悊瀹屾垚涓柇鏍囧織銆 -0锛氭湭澶勭悊瀹 -1锛氬鐞嗗畬鎴 - - - - 杞欢鏆傚仠鍜屽仠姝娇鑳藉瘎瀛樺櫒 - - 褰搒w_pause_en=1鏃讹紝杞欢鏆傚仠纭欢鐨勭瓥鐣ラ夋嫨銆 -0锛氬湪寮濮嬪鐞嗕箣鍓嶆殏鍋 -1锛氬湪瀛愬抚澶勭悊缁撴潫涔嬪悗鏆傚仠 - - - 杞欢鏆傚仠纭欢鐨勪娇鑳姐 -0锛氫笉鏆傚仠 -1锛氭殏鍋滐紝纭欢瀹屾垚褰撳墠瀛愬抚澶勭悊鍚庢垨寮濮嬪鐞嗕箣鍓嶏紝鏆傚仠澶勭悊锛岀瓑璇ヤ娇鑳界疆涓0鍚庡啀缁х画 - - - 杞欢鍋滄纭欢鐨勪娇鑳姐 -0锛氫笉鍋滄 -1锛氬仠姝紝纭欢鍦ㄥ鐞嗗瓙甯у墠鎴栧畬鎴愬綋鍓嶅瓙甯у鐞嗗悗锛屽仠姝㈠鐞 - - - - 杞欢鏆傚仠鍜屽仠姝㈡爣蹇楀瘎瀛樺櫒 - - 杞欢鏆傚仠纭欢鏍囧織銆 -0锛氳蒋浠舵湭鎴愬姛鏆傚仠纭欢 -1锛氳蒋浠舵垚鍔熸殏鍋滅‖浠 - - - 杞欢鍋滄纭欢鏍囧織銆 -0锛氳蒋浠舵湭鎴愬姛鍋滄纭欢 -1锛氳蒋浠舵垚鍔熷仠姝㈢‖浠 - - - - 瀹藉甫RI涓婃姤瀵勫瓨鍣 - - 绯荤粺甯﹀鍐呮荤殑RI锛屽嵆瀵规墍鏈塒RB鐨凴I鎸夊鏁板師鍒欑粺璁″緱鍒扮殑鍊笺 -0锛歊I=1 -1锛歊I=2 - - - - 瀹藉甫PMI涓婃姤瀵勫瓨鍣 - - 绯荤粺甯﹀鍐呮荤殑PMI锛屽嵆瀵规墍鏈塒RB鐨凱MI鎸夊鏁板師鍒欑粺璁″緱鍒扮殑鍊 - - - - 鎺ユ敹澶╃嚎1鐨勫甯︿俊鍙峰姛鐜囦笂鎶ュ瘎瀛樺櫒 - - 鎺ユ敹澶╃嚎1鐨勫甯︿俊鍙峰姛鐜囧拰锛屽嵆瀵规墍鏈夊瓙甯︿俊鍙峰姛鐜囩疮鍔犲緱鍒般 - - - - 鎺ユ敹澶╃嚎2鐨勫甯︿俊鍙峰姛鐜囦笂鎶ュ瘎瀛樺櫒 - - 鎺ユ敹澶╃嚎2鐨勫甯︿俊鍙峰姛鐜囧拰锛屽嵆瀵规墍鏈夊瓙甯︿俊鍙峰姛鐜囩疮鍔犲緱鍒般 - - - - 鎺ユ敹澶╃嚎1鐨勫甯﹀櫔澹板姛鐜囦笂鎶ュ瘎瀛樺櫒 - - 鎺ユ敹澶╃嚎1鐨勫甯﹀櫔澹板姛鐜囧拰锛屽嵆瀵规墍鏈夊瓙甯﹀櫔澹板姛鐜囩疮鍔犲緱鍒般 - - - - 鎺ユ敹澶╃嚎2鐨勫甯﹀櫔澹板姛鐜囦笂鎶ュ瘎瀛樺櫒 - - 鎺ユ敹澶╃嚎2鐨勫甯﹀櫔澹板姛鐜囧拰锛屽嵆瀵规墍鏈夊瓙甯﹀櫔澹板姛鐜囩疮鍔犲緱鍒般 - - - - 褰撳墠澶勭悊瀛愬抚鐨凜SI閰嶇疆瀵勫瓨鍣 - - cp鎸囩ず銆 -0锛氬父瑙 -1锛氭墿灞 - - - FH杈撳嚭鎴綅鏂规銆 -5鈥檇0锛氭埅鍙杅h[11:0] -5鈥檇1锛氭埅鍙杅h[12:1] -5鈥檇2锛氭埅鍙杅h[13:2] -鈥︹ -5鈥檇16锛氭埅鍙杅h[27:16] -others锛氭埅鍙杅h[28:17] - - - CSI-RS鍜孋RS鐨勬寚绀恒 -0锛欳SI-RS -1锛欳RS - - - LS/FH/鍔熺巼璁＄畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻LS/FH/鍔熺巼 -1锛氫娇鑳斤紝瑕佽绠 - - - 杞欢閰嶇疆鐨勫甯I锛屽湪ri_sel=1鏃剁敤鏉ヨ绠桺MI銆 -0锛歊I=1 -1锛歊I=2 - - - 璁＄畻PMI鎵鐢ㄧ殑RI鐨勬潵婧愰夋嫨銆 -0锛氫娇鐢ㄧ‖浠惰绠楃殑瀹藉甫RI -1锛氫娇鐢ㄨ蒋浠堕厤缃殑RI - - - PMI浼扮畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻PMI -1锛氫娇鑳斤紝瑕佽绠桺MI - - - RI浼扮畻浣胯兘淇″彿銆 -0锛氫笉浣胯兘锛屼笉璁＄畻RI -1锛氫娇鑳斤紝瑕佽绠桼I - - - 浼扮畻RI鏃舵槸鍚︿娇鐢≧I鍘嗗彶鍊肩殑鎸囩ず銆 -0锛氫笉浣跨敤鍘嗗彶鍊硷紝榛樿涓篟I=1 -1锛氫娇鐢ㄤ笂涓懆鏈熺殑瀹藉甫RI鍊 - - - 绯荤粺甯﹀銆傚彇鍊6/15/25/50/75/100PRB - - - 瀛愬甫甯﹀銆備笌绯荤粺甯﹀涓涓瀵瑰簲銆倀otal_nrb=6/15/25/50/75/100鏃讹紝sub_nrb=6/2/2/3/4/4 PRB銆 - - - 鍙戝皠澶╃嚎鏁般侰SI-RS鍙厤缃1銆2銆4銆8澶╃嚎锛孋RS鍙厤缃2銆4澶╃嚎銆 -0锛1澶╃嚎锛堝彧璁＄畻鍔熺巼锛屼笉璁＄畻RI鍜孭MI锛 -1锛2澶╃嚎 -2锛4澶╃嚎 -3锛8澶╃嚎 - - - - 褰撳墠澶勭悊瀛愬抚鐨凴I浼拌闂ㄩ檺瀵勫瓨鍣 - - 銆((1-th2)/(1+th2))銆梌2鐨勫笺備及璁I鏃朵娇鐢ㄧ殑鍒ゅ喅闂ㄩ檺锛屽彇鍊间负澶т簬0灏忎簬1鐨勫皬鏁般傜敤Q15琛ㄧず銆倀h2鐨勫吀鍨嬪间负40銆 - - - 銆((1-th1)/(1+th1))銆梌2鐨勫笺備及璁I鏃朵娇鐢ㄧ殑鍒ゅ喅闂ㄩ檺锛屽彇鍊间负澶т簬0灏忎簬1鐨勫皬鏁般傜敤Q15琛ㄧず銆倀h1鐨勫吀鍨嬪间负60銆 - - - - 褰撳墠澶勭悊瀛愬抚鐨勭爜鏈储寮曞瘎瀛樺櫒1 - - RI=2鏃剁殑2銆4澶╃嚎鐨勭爜鏈储寮曞彿鍙8澶╃嚎鐨勭爜鏈储寮曞彿i1鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - RI=1鏃剁殑2銆4澶╃嚎鐨勭爜鏈储寮曞彿鍙8澶╃嚎鐨勭爜鏈储寮曞彿i1鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - - 褰撳墠澶勭悊瀛愬抚鐨勭爜鏈储寮曞瘎瀛樺櫒2 - - RI=2鏃剁殑8澶╃嚎鐨勭爜鏈储寮曞彿i2鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - RI=1鏃剁殑8澶╃嚎鐨勭爜鏈储寮曞彿i2鐨刡itmap銆俠it0~bit15鍒嗗埆瀵瑰簲绱㈠紩鍙0~15锛屼负鈥1鈥濈殑姣旂壒浣嶅搴旂殑绱㈠紩鍙锋湁鏁堬紝闇瑕佽绠楄绱㈠紩瀵瑰簲鐨勯缂栫爜鐭╅樀銆 - - - - 褰撳墠澶勭悊瀛愬抚鐨勪腑鏂娇鑳藉瘎瀛樺櫒 - - 澶勭悊瀹屾垚涓柇浣胯兘銆 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 褰撳墠澶勭悊瀛愬抚鐨凮FDM0鐨凜搴忓垪鍒濆鍊煎瘎瀛樺櫒 - - OFDM绗﹀彿0鐨凜搴忓垪鐨勫垵濮嬪硷紝鐢ㄦ潵璁＄畻鏈湴CSI-RS銆 - - - - 褰撳墠澶勭悊瀛愬抚鐨凮FDM1鐨凜搴忓垪鍒濆鍊煎瘎瀛樺櫒 - - OFDM绗﹀彿1鐨凜搴忓垪鐨勫垵濮嬪硷紝鐢ㄦ潵璁＄畻鏈湴CSI-RS銆 - - - - - - - - - - - - - - - - - - - - - - - - - - - 鍙傛暟瀵勫瓨鍣 - - 鏈湴搴忓垪闀垮害锛歮ax384 - - - 鎺ユ敹鏁版嵁闀垮害锛歮ax2800 - - - ID涓暟锛歮ax10 - - - - 鍚姩瀵勫瓨鍣 - - 妯″潡鍚姩锛 -1锛氬惎鍔 -0锛氭湭鍚姩鎴栬呭凡缁忓畬鎴 - - - - 缁撴灉杈撳嚭瀵勫瓨鍣 - - 杈撳嚭鐨勭浉鍏冲煎湪涔掓垨鑰呬箵锛 -0锛氫箳 -1锛氫箵 - - - 鏈澶т綅缃細max锛2800 - - - 鏈澶D锛歮ax10 - - - - MAX杈撳嚭瀵勫瓨鍣 - - CORR_MAX - - - - SUM杈撳嚭瀵勫瓨鍣 - - - 涓柇浣胯兘瀵勫瓨鍣 - - 涓柇浣胯兘锛 -0锛氫腑鏂笉浣胯兘 -1锛氫腑鏂娇鑳 - - - - 涓柇鏍囧織瀵勫瓨鍣 - - 涓柇鏍囧織锛 -0锛氭病鏈変腑鏂 -1锛氫骇鐢熶腑鏂 - - - - - - - - - 閰嶇疆瀵勫瓨鍣 - - 浣胯兘浣 -0锛氫笉浣胯兘 -1锛氫娇鑳 - - - - 閰嶇疆瀵勫瓨鍣 - - 鍚姩鎶揇ump鏁版嵁 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍚姩鎶揟x Trace鏁版嵁 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍚姩鎶揑DDET offline杈撳叆鍙ｆ暟鎹 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍚姩鎶揙DTOA鏁版嵁 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍚姩鎶揜X杈撳叆鍙ｆ暟鎹 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - - 鐏屾暟閰嶇疆瀵勫瓨鍣 - - 鐏屾暟闀垮害 - - - 鍚姩DL offline鐏屾暟 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍒嗛鍙傛暟锛岀敤浜庣敓鎴愮亴鏁拌緭鍑烘暟鎹 -3鈥檋0:4鍒嗛锛堝搴20M/15M甯﹀锛 -3鈥檋1:8鍒嗛锛堝搴10M甯﹀锛 -3鈥檋2:16鍒嗛锛堝搴5M甯﹀锛 -3鈥檋3:32鍒嗛锛堝搴3M甯﹀锛 -3鈥檋4:64鍒嗛锛堝搴1.4M甯﹀锛 -Others: 4鍒嗛 - - - - 鐏屾暟閰嶇疆瀵勫瓨鍣2 - - 鐏屾暟闀垮害 - - - 鍚姩IDDET offline鐏屾暟 -1锛氬惎鍔 -0锛氫笉鍚姩 - - - 鍒嗛鍙傛暟锛岀敤浜庣敓鎴愮亴鏁拌緭鍑烘暟鎹 -3鈥檋0:4鍒嗛锛堝搴20M/15M甯﹀锛 -3鈥檋1:8鍒嗛锛堝搴10M甯﹀锛 -3鈥檋2:16鍒嗛锛堝搴5M甯﹀锛 -3鈥檋3:32鍒嗛锛堝搴3M甯﹀锛 -3鈥檋4:64鍒嗛锛堝搴1.4M甯﹀锛 -Others: 4鍒嗛 - - - - 璇锋眰DMA鎼暟浣胯兘瀵勫瓨鍣 - - DMA_req7浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req6浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req5浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req4浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req3浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req2浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req1浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - DMA_req0浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - - 涓柇浣胯兘瀵勫瓨鍣 - - Capt_err34涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Capt_err12涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - - 涓柇浣胯兘缃綅瀵勫瓨鍣 - - Capt_err34涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Capt_err12涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - - 涓柇浣胯兘娓呴浂瀵勫瓨鍣 - - Capt_err34涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Capt_err12涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem56 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem34 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 finish涓柇浣胯兘銆 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 pang涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - Mem12 ping涓柇浣胯兘 -1锛氫娇鑳 -0锛氫笉浣胯兘 - - - - 涓柇鐘舵佸瘎瀛樺櫒 - - Capt_err34涓柇 - - - Capt_err12涓柇 - - - Mem56 finish涓柇鐘舵 - - - Mem56 pang涓柇鐘舵 - - - Mem56 ping涓柇鐘舵 - - - Mem34 finish涓柇鐘舵 - - - Mem34 pang涓柇鐘舵 - - - Mem34 ping涓柇鐘舵 - - - Mem12 finish涓柇鐘舵併 - - - Mem12 pang涓柇鐘舵 - - - Mem12 ping涓柇鐘舵 - - - - MEM12涓柇閰嶇疆瀵勫瓨鍣 - - Mem12涓柇閰嶇疆瀵勫瓨鍣 - - - - MEM34涓柇閰嶇疆瀵勫瓨鍣 - - Mem34涓柇閰嶇疆瀵勫瓨鍣 - - - - MEM12涓柇閰嶇疆瀵勫瓨鍣 - - Mem12涓柇閰嶇疆瀵勫瓨鍣 - - - - MEM56涓柇閰嶇疆瀵勫瓨鍣 - - Mem56涓柇閰嶇疆瀵勫瓨鍣 - - - - 閫氱敤鎺у埗瀵勫瓨鍣 - - - MEM12褰撳墠鐘舵佸瘎瀛樺櫒 - - Mem12 pang璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem12 pang鍦板潃 - - - Mem12 ping璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem12 ping鍦板潃 - - - - MEM34褰撳墠鐘舵佸瘎瀛樺櫒 - - Mem34 pang璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem34 pang鍦板潃 - - - Mem34 ping璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem34 ping鍦板潃 - - - - MEM56褰撳墠鐘舵佸瘎瀛樺櫒 - - Mem56 pang璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem56 pang鍦板潃 - - - Mem56 ping璇诲啓鐘舵 -000锛欼DLE -001锛氬線MEM鐏屾暟鎹 -010锛歁EM琚亴婊★紝娌℃惉鍑 -011锛欴MA鎼暟鎹 -100锛歁EM琚惉绌 -Others: IDLE - - - Mem56 ping鍦板潃 - - - - 鎶撴暟EER12鐘舵佸瘎瀛樺櫒 - - 鎶撴暟Err鐨勫瓨鍌ㄥ櫒 -0锛歁EM12 Ping -1锛歁EM12 Pang - - - 鎶撴暟Error鏃剁殑甯у彿(鍙戠敓鎶撴暟ERR鏃堕攣瀛樼殑甯у彿 - - - - 鎶撴暟EER34鐘舵佸瘎瀛樺櫒 - - 鎶撴暟Err鐨勫瓨鍌ㄥ櫒 -0锛歁EM34 Ping -1锛歁EM34 Pang - - - 鎶撴暟Error鏃剁殑甯у彿(鍙戠敓鎶撴暟ERR鏃堕攣瀛樼殑甯у彿 - - - - 鎶撴暟鐘舵佸瘎瀛樺櫒 - - otdoa_sta -00锛氭湭杩愯鎶撴暟鍔熻兘 -01锛氭鎶撳彇OTDOA -10锛氱‖浠秄inish淇″彿缁撴潫鎶撴暟 -11锛氳蒋浠舵竻capt_cfg浣胯兘浣嶇粨鏉熸姄鏁 - - - iddet_sta -00锛氭湭杩愯鎶撴暟鍔熻兘 -01锛氭鎶撳彇IDDET -10锛氱‖浠秄inish淇″彿缁撴潫鎶撴暟 -11锛氳蒋浠舵竻capt_cfg浣胯兘浣嶇粨鏉熸姄鏁 - - - tx_sta -00锛氭湭杩愯鎶撴暟鍔熻兘 -01锛氭鎶撳彇TX -10锛氱‖浠秄inish淇″彿缁撴潫鎶撴暟 -11锛氳蒋浠舵竻capt_cfg缁撴潫浣胯兘浣嶇粨鏉熸姄鏁 - - - dump_sta -00锛氭湭杩愯鎶撴暟鍔熻兘 -01锛氭鎶撳彇DUMP -10锛氱‖浠秄inish淇″彿缁撴潫鎶撴暟 -11锛氳蒋浠舵竻capt_cfg浣胯兘浣嶇粨鏉熸姄鏁 - - - rx_sta -00锛氭湭杩愯鎶撴暟鍔熻兘 -01锛氭鎶撳彇RX -10锛氱‖浠秄inish淇″彿缁撴潫鎶撴暟 -11锛氳蒋浠舵竻capt_cfg浣胯兘浣嶇粨鏉熸姄鏁 - - - - DL offline鐏屾暟鐘舵佸瘎瀛樺櫒1 - - fill_running_sta -00锛氭湭杩愯鐏屾暟鍔熻兘 -01锛氭鐏屾暟 -10锛氱‖浠舵惉瀹宭en缁撴潫鐏屾暟 -11锛氳蒋浠舵竻fill_cfg浣胯兘浣嶇粨鏉熺亴鏁 - - - out_len -褰撳墠HW鍚愬嚭鏁版嵁闀垮害锛圛/Q瀵规暟锛 - - - - DL offline鐏屾暟鐘舵佸瘎瀛樺櫒2 - - in_len -褰撳墠DMA鎼叆鏁版嵁闀垮害锛圛/Q瀵规暟锛 - - - - IDDET offline鐏屾暟鐘舵佸瘎瀛樺櫒1 - - fill_running_sta -00锛氭湭杩愯鐏屾暟鍔熻兘 -01锛氭鐏屾暟 -10锛氱‖浠舵惉瀹宭en缁撴潫鐏屾暟 -11锛氳蒋浠舵竻fill_cfg浣胯兘浣嶇粨鏉熺亴鏁 - - - out_len -褰撳墠HW鍚愬嚭鏁版嵁闀垮害锛圛/Q瀵规暟锛 - - - - IDDET offline鐏屾暟鐘舵佸瘎瀛樺櫒2 - - in_len -褰撳墠DMA鎼叆鏁版嵁闀垮害锛圛/Q瀵规暟锛 - - - - DMA鐘舵佸瘎瀛樺櫒 - - DMA_ACK - - - DMA_REQ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AUXADC IP version AUXADC IP version - - IP version r7p0 - - - - ADC ctrl information configure ADC ctrl information configure - - Auxadc offset function enable -0: disable offset function -1: enable offset function - - - auxadc convert data out average control: -000: disable adc average, output 12bit data and valid after once conversion; -001: adc convert twice and output the average data; -010: adc convert 4 times and output the average data; -011: adc convert 8 times and output the average data; -100: adc convert 16 times and output the average data; -101: adc convert 32 times and output the average data; -110: adc convert 64 times and output the average data; -111: adc convert 128 times and output the average data; - - - the number of SW channel accessing, N+1. - - - AUXADC output code selection: -0: adc_dout = (data-Doff) -1: if adc_offset_cal_en is 0 -adc_dout = data - if adc_offset_cal_en is 1 -adc_dout = data-(Doff-2047) -more detail see Function Description - - - ADC 12bits mode -0: ADC in 10bits mode; -1: ADC in 12bits mode. - - - SW channel run, -Write '1' to run a SW channel accessing, it is cleared by HW. - - - ADC global enable, -0: ADC module disable; -1: ADC module enable. - - - - ADC SW channel configure ADC SW channel configure - - ADC scale setting for current ADC channel - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC software config channel ID. - - - - ADC fast HW channel0 configure ADC fast HW channel0 configure - - ADC scale setting for current ADC channel - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel1 configure ADC fast HW channel1 configure - - ADC scale setting for current ADC channel - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel2 configure ADC fast HW channel2 configure - - ADC scale setting for current ADC channel - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel3 configure ADC fast HW channel3 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel4 configure ADC fast HW channel4 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel5 configure ADC fast HW channel5 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel6 configure ADC fast HW channel6 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC fast HW channel7 configure ADC fast HW channel7 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel0 configure ADC slow HW channel0 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel1 configure ADC slow HW channel1 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel2 configure ADC slow HW channel2 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel3 configure ADC slow HW channel3 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel4 configure ADC slow HW channel4 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel5 configure ADC slow HW channel5 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel6 configure ADC slow HW channel6 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC slow HW channel7 configure ADC slow HW channel7 configure - - output the analog - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: -0: quick mode, conversion initial includes 50 ADC clocks; -1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - ADC HW channel accessing dealy ADC HW channel accessing dealy - - ADC HW channel accessing delay, its unit is ADC clock. -It can be use for signal without enough setup time. - - - - ADC conversion result ADC conversion result - - ADC conversion result. - - - - ADC interrupt enable ADC interrupt enable - - ADC interrupt enable, 0: disable; 1: enable. - - - - ADC interrupt clear ADC interrupt clear - - ADC interrupt clear. Write "1" to clear. - - - - ADC masked interrupt ADC masked interrupt - - ADC masked interrupt. - - - - ADC raw interrupt ADC raw interrupt - - ADC raw interrupt. - - - - ADC debug information ADC debug information - - 0~7: fast HW channels; -8: SW channels; -9~16: slow HW channel; -31: no request. - - - ADC accessing state: -0: idle; -1: fast HW request; -2: SW request; -3: slow HW request; -4: wait for fast HW request; -5: wait for slow HW request. - - - ADC internal counter status, 0: idle; 1~n: work or wait counter. - - - - ADC fast HW channel timer enable ADC fast HW channel timer enable - - ADC fast HW channel7 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel6 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel5 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel4 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel3 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel2 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel1 timer enable, 0:disable; 1: enable. - - - ADC fast HW channel0 timer enable, 0:disable; 1: enable. - - - - ADC fast HW channel timer working clock divider ADC fast HW channel timer working clock divider - - ADC fast HW channel timer working clock divider. - - - - ADC fast HW channel0 timer threshold ADC fast HW channel0 timer threshold - - ADC fast HW ch0 timer threshold. - - - - ADC fast HW channel1 timer threshold ADC fast HW channel1 timer threshold - - ADC fast HW ch1 timer threshold. - - - - ADC fast HW channel2 timer threshold ADC fast HW channel2 timer threshold - - ADC fast HW ch2 timer threshold. - - - - ADC fast HW channel3 timer threshold ADC fast HW channel3 timer threshold - - ADC fast HW ch3 timer threshold. - - - - ADC fast HW channel4 timer threshold ADC fast HW channel4 timer threshold - - ADC fast HW ch4 timer threshold. - - - - ADC fast HW channel5 timer threshold ADC fast HW channel5 timer threshold - - ADC fast HW ch5 timer threshold. - - - - ADC fast HW channel6 timer threshold ADC fast HW channel6 timer threshold - - ADC fast HW ch6 timer threshold. - - - - ADC fast HW channel7 timer threshold ADC fast HW channel7 timer threshold - - ADC fast HW ch7 timer threshold. - - - - ADC fast HW channel0 data ADC fast HW channel0 data - - ADC fast HW ch0 data, read twice, and capture the second value. - - - - ADC fast HW channel1 data ADC fast HW channel1 data - - ADC fast HW ch1 data, read twice, and capture the second value. - - - - ADC fast HW channel2 data ADC fast HW channel2 data - - ADC fast HW ch2 data, read twice, and capture the second value. - - - - ADC fast HW channel3 data ADC fast HW channel3 data - - ADC fast HW ch3 data, read twice, and capture the second value. - - - - ADC fast HW channel4 data ADC fast HW channel4 data - - ADC fast HW ch4 data, read twice, and capture the second value. - - - - ADC fast HW channel5 data ADC fast HW channel5 data - - ADC fast HW ch5 data, read twice, and capture the second value. - - - - ADC fast HW channel6 data ADC fast HW channel6 data - - ADC fast HW ch6 data, read twice, and capture the second value. - - - - ADC fast HW channel7 data ADC fast HW channel7 data - - ADC fast HW ch7 data, read twice, and capture the second value. - - - - ADC NTC ctrl information ADC NTC ctrl information - - output to analog - - - output to analog -THM calibration enable signal, -0: disable THM calibration(default) -1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration - - - output to analog -Aux ADC current sense enable signal, active high, default 0. - - - - ADC fast HW channel data valid ADC fast HW channel data valid - - ADC fast HW channel7 data valid. - - - ADC fast HW channel6 data valid. - - - ADC fast HW channel5 data valid. - - - ADC fast HW channel4 data valid. - - - ADC fast HW channel3 data valid. - - - ADC fast HW channel2 data valid. - - - ADC fast HW channel1 data valid. - - - ADC fast HW channel0 data valid. - - - - - - - - - BLTC control 1. BLTC output select -2. BLTC output select(1: output by SW, 0: output by HW); -3. BLTC output type select (1: normal PWM, 0: breath light); -4, BLTC run enable signal - - BLTC WLED output value when by SW. - - - BLTC WLED output selection - - - BLTC WLED output type - - - BLTC WLED run - - - BLTC B output value when by SW. - - - BLTC B output selection - - - BLTC B output type - - - BLTC B run - - - BLTC G output value when by SW. - - - BLTC G output selection - - - BLTC G output type - - - BLTC G run - - - BLTC R output value when by SW. - - - BLTC R output selection - - - BLTC R output type - - - BLTC R run - - - - BLTC R prescale coefficient PWM prescale coefficient for work clock. - - BLTC prescale coefficient. - - - - BLTC R duty config PWM duty config. - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - BLTC R rise/fall config BLTC R rise/fall config - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - BLTC R high/low config BLTC R high/low config - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - BLTC G prescale coefficient PWM prescale coefficient for work clock. - - BLTC prescale coefficient. - - - - BLTC G duty config PWM duty config. - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - BLTC G rise/fall config BLTC G rise/fall config - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - BLTC G high/low config BLTC G high/low config - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - BLTC B prescale coefficient PWM prescale coefficient for work clock. - - BLTC prescale coefficient. - - - - BLTC B duty config PWM duty config. - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - BLTC B rise/fall config BLTC B rise/fall config - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - BLTC B high/low config BLTC B high/low config - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - BLTC status BLTC status - - BLTC WLED busy, active high. - - - BLTC B busy, active high. - - - BLTC G busy, active high. - - - BLTC R busy, active high. - - - - BLTC R current strength config. BLTC current strength config. - - Current strength config. - - - - BLTC G current strength config. BLTC current strength config. - - Current strength config. - - - - BLTC B current strength config. BLTC current strength config. - - Current strength config. - - - - BLTC WLED current strength config. BLTC current strength config. - - Current strength config. - - - - BLTC WLED prescale coefficient PWM prescale coefficient for work clock. - - BLTC prescale coefficient. - - - - BLTC WLED duty config PWM duty config. - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - BLTC WLED rise/fall config BLTC WLED rise/fall config - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - BLTC WLED high/low config BLTC WLED high/low config - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - BLTC current strength config. BLTC current strength config. - - Power down signal - - - Power down signal - - - - BLTC version BLTC WLED high/low config - - bltc version information - - - - - - - - - efuse global control register - - Control efs_clk gate -1: gate efs_clk - - - Efuse type select, 00:TSMC default - - - Efuse SW programme enable - - - - Data read from efuse memory - - Efuse read data, -If SW use efuse controller to send a read command to efuse memory, the return value will store here. - - - - Data to be write to efuse memory - - Efuse data to be write. -If SW want to program the efuse memory, the data to be programmed will write to this register before SW issue a PGM command. - - - - block index for read, program - - The efuse memory block index to be read or write. - - - - Mode control of efuse memory - - Write 1 to this bit will clear normal read flag.This bit is self-clear, read this bit will always get 0 - - - Write 1 to this bit start READ mode(read mode).This bit is self-clear, read this bit will always get 0 - - - Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0 - - - - Efuse controller internal status - - 鈥1鈥 indicate EFUSE normal read has been done - - - If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1. - - - 鈥1鈥 indicate efuse memory in standby mode - - - 鈥1鈥 indicate efuse memory in read mode - - - 鈥1鈥 indicate efuse memory in programming mode - - - - magic number to protect efuse from un-intentionally programming - - Magic number, only when this field is 0x7520, the Efuse programming command can be handle. -So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : -a) PGM_EN =1; -b) EFUSE_MAGIC_NUMBER = 0x7520 - - - - magic number to protect efuse from un-intentionally programming - - Magic number, only when this field is 0x6688, the margin read is usable. - - - - Write command timing control - - Config this register to control the timing of writing operation related signals - - - - Read command timing control - - Config this register to control the timing of writing operation related signals - - - - EFUSE control version registers - - Efuse control version register - - - - - EFUSE POR READ BLK00 - - should be the efuse macro value - - - - EFUSE POR READ BLK01 - - should be the efuse macro value - - - - EFUSE POR READ BLK02 - - should be the efuse macro value - - - - EFUSE POR READ BLK03 - - should be the efuse macro value - - - - EFUSE POR READ BLK04 - - should be the efuse macro value - - - - EFUSE POR READ BLK05 - - should be the efuse macro value - - - - EFUSE POR READ BLK06 - - should be the efuse macro value - - - - EFUSE POR READ BLK07 - - should be the efuse macro value - - - - EFUSE POR READ BLK08 - - should be the efuse macro value - - - - EFUSE POR READ BLK09 - - should be the efuse macro value - - - - EFUSE POR READ BLK10 - - should be the efuse macro value - - - - EFUSE POR READ BLK11 - - should be the efuse macro value - - - - EFUSE POR READ BLK12 - - should be the efuse macro value - - - - EFUSE POR READ BLK13 - - should be the efuse macro value - - - - EFUSE POR READ BLK14 - - should be the efuse macro value - - - - EFUSE POR READ BLK15 - - should be the efuse macro value - - - - EFUSE POR READ BLK16 - - should be the efuse macro value - - - - EFUSE POR READ BLK17 - - should be the efuse macro value - - - - EFUSE POR READ BLK18 - - should be the efuse macro value - - - - EFUSE POR READ BLK19 - - should be the efuse macro value - - - - EFUSE POR READ BLK20 - - should be the efuse macro value - - - - EFUSE POR READ BLK21 - - should be the efuse macro value - - - - EFUSE POR READ BLK22 - - should be the efuse macro value - - - - EFUSE POR READ BLK23 - - should be the efuse macro value - - - - EFUSE POR READ BLK24 - - should be the efuse macro value - - - - EFUSE POR READ BLK25 - - should be the efuse macro value - - - - EFUSE POR READ BLK26 - - should be the efuse macro value - - - - EFUSE POR READ BLK27 - - should be the efuse macro value - - - - EFUSE POR READ BLK28 - - should be the efuse macro value - - - - EFUSE POR READ BLK29 - - should be the efuse macro value - - - - EFUSE POR READ BLK30 - - should be the efuse macro value - - - - EFUSE POR READ BLK31 - - should be the efuse macro value - - - - EFUSE POR READ BLK32 - - should be the efuse macro value - - - - EFUSE POR READ BLK33 - - should be the efuse macro value - - - - EFUSE POR READ BLK34 - - should be the efuse macro value - - - - EFUSE POR READ BLK35 - - should be the efuse macro value - - - - EFUSE POR READ BLK36 - - should be the efuse macro value - - - - EFUSE POR READ BLK37 - - should be the efuse macro value - - - - EFUSE POR READ BLK38 - - should be the efuse macro value - - - - EFUSE POR READ BLK39 - - should be the efuse macro value - - - - EFUSE POR READ BLK40 - - should be the efuse macro value - - - - EFUSE POR READ BLK41 - - should be the efuse macro value - - - - EFUSE POR READ BLK42 - - should be the efuse macro value - - - - EFUSE POR READ BLK43 - - should be the efuse macro value - - - - EFUSE POR READ BLK44 - - should be the efuse macro value - - - - EFUSE POR READ BLK45 - - should be the efuse macro value - - - - EFUSE POR READ BLK46 - - should be the efuse macro value - - - - EFUSE POR READ BLK47 - - should be the efuse macro value - - - - EFUSE POR READ BLK48 - - should be the efuse macro value - - - - EFUSE POR READ BLK49 - - should be the efuse macro value - - - - EFUSE POR READ BLK50 - - should be the efuse macro value - - - - EFUSE POR READ BLK51 - - should be the efuse macro value - - - - EFUSE POR READ BLK52 - - should be the efuse macro value - - - - EFUSE POR READ BLK53 - - should be the efuse macro value - - - - EFUSE POR READ BLK54 - - should be the efuse macro value - - - - EFUSE POR READ BLK55 - - should be the efuse macro value - - - - EFUSE POR READ BLK56 - - should be the efuse macro value - - - - EFUSE POR READ BLK57 - - should be the efuse macro value - - - - EFUSE POR READ BLK58 - - should be the efuse macro value - - - - EFUSE POR READ BLK59 - - should be the efuse macro value - - - - EFUSE POR READ BLK60 - - should be the efuse macro value - - - - EFUSE POR READ BLK61 - - should be the efuse macro value - - - - EFUSE POR READ BLK62 - - should be the efuse macro value - - - - EFUSE POR READ BLK63 - - should be the efuse macro value - - - - - - - - - EIC_DBNC bits data register, read only - - EIC_DBNC bits data input - - - - EIC_DBNC bits data mask register - - EIC_DBNC_DATA register can be read if EIC_DBNC_DMSK set 鈥1鈥 - - - - - EIC_DBNC bits interrupt status register - - EIC_DBNC bits interrupt status register: -鈥1鈥 high levels trigger interrupts, -鈥0鈥 low levels trigger interrupts. - - - - EIC_DBNC bits interrupt enable register - - EIC_DBNC bits interrupt enable register: -鈥1鈥 corresponding bit interrupt is enabled. -鈥0鈥 corresponding bit interrupt isn't enabled - - - - EIC_DBNC bits raw interrupt status register, and it reflects the status of interrupts trigger conditions detection on pins (prior to EIC_DBNC_MIS) - - EIC bits raw interrupt status register: -鈥1鈥 interrupt condition met -鈥0鈥 condition not met - - - - EIC_DBNC bits masked interrupt status register - - EIC_DBNC bits masked interrupt status register: -鈥1鈥 Interrupt active -鈥0鈥 interrupt not active - - - - EIC_DBNC_ bits interrupt clear register - - EIC_DBNC bits interrupt clear register: -鈥1鈥 clears detected interrupt. -鈥0鈥 has no effect. - - - - EIC_DBNC bits trig control register - - EIC_DBNC bits trig control register: -鈥1鈥: generate the trig_start pulse -鈥0鈥: no effect -It must set EIC_DBNC_TRIG for using de-bounce function and getting active interrupt. - - - - - EIC0_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC1_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC2_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC3_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC4_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC5_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC6_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC7_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC8_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC9_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC10_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC11_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC12_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC13_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC14_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - EIC15_DBNC control register - - 1: clock of dbnc forced open; -0: no effect - - - de-bounce mechanism enable or disable: -1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the one unit is 0.977 锛1000/1024锛 millisecond - - - - - - - - - RTC second counter value - - RTC second counter value - - - - RTC minute counter value - - RTC minute counter value - - - - RTC hour counter value - - RTC hour counter value - - - - RTC day counter value - - RTC day counter value - - - - RTC second counter update - - RTC second counter update -Write new counter value to this register to start a second counter updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC minute counter update - - RTC minute counter update -Write new counter value to this register to start a minute counter updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC hour counter update - - RTC hour counter update -Write new counter value to this register to start an hour counter updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC day counter update - - RTC day counter update -Write new counter value to this register to start a day counter updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC second alarm update - - RTC second alarm update -Write new counter value to this register to start a second alarm updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC minute alarm update - - RTC minute alarm update -Write new counter value to this register to start a minute alarm updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC hour alarm update - - RTC hour alarm update -Write new counter value to this register to start an hour alarm updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC day alarm update - - RTC day alarm update -Write new counter value to this register to start a day alarm updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - - RTC interrupt enable and -hour format control - - Day alarm updating complete interrupt enable -0: disable -1: enable - - - Hour alarm updating complete interrupt enable - - - Minute alarm updating complete interrupt enable - - - Second alarm updating complete interrupt enable - - - Day counter updating complete interrupt enable - - - Hour counter updating complete interrupt enable - - - Minute counter updating complete interrupt enable - - - Second counter updating complete interrupt enable - - - Spare register updating complete interrupt enable - - - auxiliary alarm interrupt enable - - - Hour format select -0: The read back hour count is formatted as 0 to 23. -1: The read back hour count is formatted as 0 to 11, and bit 4 represent AM or PM 鈥 AM is 0 and PM is 1. - - - alarm interrupt enable - - - day interrupt enable - - - hour interrupt enable - - - minute interrupt enable - - - Second interrupt enable - - - - RTC interrupt raw status - - Day alarm updating complete interrupt raw status - - - Hour alarm updating complete interrupt raw status - - - Minute alarm updating complete interrupt raw status - - - Second alarm updating complete interrupt raw status - - - Day counter updating complete interrupt raw status - - - Hour counter updating complete interrupt raw status - - - Minute counter updating complete interrupt raw status - - - Second counter updating complete interrupt raw status - - - Spare register updating complete interrupt raw status - - - auxiliary alarm interrupt raw status - - - Reserved for debug - - - alarm interrupt raw status - - - day interrupt raw status - - - hour interrupt raw status - - - minute interrupt raw status - - - Second interrupt raw status - - - - RTC interrupt clear - - Day alarm updating complete interrupt clear -Write 1 to this bit to clear corresponding interrupt - - - Hour alarm updating complete interrupt clear - - - Minute alarm updating complete interrupt clear - - - Second alarm updating complete interrupt clear - - - Day counter updating complete interrupt clear - - - Hour counter updating complete interrupt clear - - - Minute counter updating complete interrupt clear - - - Second counter updating complete interrupt clear - - - Spare register updating complete interrupt clear - - - Auxiliary alarm interrupt clear - - - alarm interrupt clear - - - day interrupt clear - - - hour interrupt clear - - - minute interrupt clear - - - Second interrupt clear - - - - RTC interrupt masked status - - Day alarm updating complete interrupt masked status - - - Hour alarm updating complete interrupt masked status - - - Minute alarm updating complete interrupt masked status - - - Second alarm updating complete interrupt masked status - - - Day counter updating complete interrupt masked status - - - Hour counter updating complete interrupt masked status - - - Minute counter updating complete interrupt masked status - - - Second counter updating complete interrupt masked status - - - Spare register updating complete interrupt masked status - - - auxiliary alarm interrupt masked status - - - alarm interrupt masked status - - - day interrupt masked status - - - hour interrupt masked status - - - minute interrupt masked status - - - Second interrupt masked status - - - - RTC second alarm value - - RTC second alarm value - - - - RTC minute alarm value - - RTC minute alarm value - - - - RTC hour alarm value - - RTC hour alarm value - - - - RTC day alarm value - - RTC day alarm value - - - - RTC spare register value - - RTC spare register value - - - RTC alarm lock register value - - - - RTC spare register update - - RTC spare register update -Write new counter value to this register to start a spare register updating operation in VDDRTC domain. -Reading this register can get recent updating value. - - - RTC alarm lock register update -Write new counter value to this register to start a register updating operation in VDDRTC domain. -Reading this register can get recent updating value. -Write 8鈥檋A5 to this register to unlock alarm function, and write other data to lock alarm function. That means, software must 8鈥檋A5 to this register to enable alarm function before using this function. - - - - RTC power flag control register - - RTC power flag register set - - - RTC power flag register clear - - - - RTC power flag status - - RTC power flag status register - - - - RTC second auxiliary alarm - update - - RTC second auxiliary alarm register - - - - RTC minute auxiliary alarm - update - - RTC minute auxiliary alarm register - - - - RTC hour auxiliary alarm - update - - RTC hour auxiliary alarm register - - - - RTC day auxiliary alarm - update - - RTC day auxiliary alarm register - - - - RTC second counter raw value - - RTC second counter raw value -Only for debug - - - - RTC minute counter raw value - - RTC minute counter raw value -Only for debug - - - - RTC hour counter raw value - - RTC hour counter raw value -Only for debug - - - - RTC second counter raw value - - RTC day counter raw value -Only for debug - - - - - - - - - the IP version of this timer the IP version of this timer - - the IP version of this timer - - - the IP patch version of this timer - - - - timer load value of lower 16 bit timer load value of lower 16 bit - - timer load value of lower 16 bit. -Write to this register will reload the timer with the new value. -In one-time mode, this value is the first counting start number. -In periodic mode, this value is each counting start number. - - - - timer load value of higher 16 bit timer load value of higher 16 bit - - timer load value of higher 16 bit -Write to this register will reload the timer with the new value. -In one-time mode, this value is the first counting start number. -In periodic mode, this value is each counting start number. - - - - timer control register timer control register - - timer open bit -0: timer stops -1: timer runs - - - timer mode select -0: one-time mode -1: period mode - - - - timer interrupt timer interrupt - - timer Interrupt clear -Write 1 to this bit to clear interrupt - - - timer interrupt masked status - - - timer interrupt raw status - - - timer interrupt enable - - - - timer counter shadow value of lower 16 bit for read timer counter shadow value of lower 16 bit for read - - timer counter of lower 16bit shadow value for read. -This read-only register indicates current counter value. -The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. - - - - timer counter shadow value of higher 16 bit for read timer counter shadow value of higher 16 bit for read - - timer counter of higher 16bit shadow value for read. -This read-only register indicates current counter value. -The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. - - - - - - - - - CHIP_ID_LOW - - CHIP ID low 16 bits,default:a000 - - - - CHIP_ID_HIGH - - CHIP ID high 16 bits,default:8850 - - - - MODULE_EN0 - - TMR module enable -0: Disable the PCLK of timer -1: Enable the PCLK of timer - - - BLTC module enable -0: Disable the PCLK of BLTC -1: Enable the PCLK of BLTC - - - Efuse module enable -0: Disable the PCLK of efuse ctrl -1: Enable the PCLK of efuse ctrl - - - AUXADC module enable -0: Disable the PCLK of AUXADC -1: Enable the PCLK of AUXADC - - - CAL module enable -0: Disable the PCLK of CAL -1: Enable the PCLK of CAL - - - - DIG_CLK_EN0 - - AUXAD clock enable, the clock is connected to AUXADC converter -0: disable AUXAD_CLK -1: enable AUXAD_CLK - - - AUXADC module work clock enable -0: disable clk_adc -1: enable clk_adc - - - Calibration module clock source select 2'b00:RC64K -2'b01:N/A -2'b10:N/A -2'b11:N/A - - - CLK_CAL eanble -0: disable clk_cal -1: enable clk_cal - - - - RTC_CLK_EN0 - - TIMER RTC clock soft enable -0: Disable the RTC clock of timer -1: Enable RTC clock of timer - - - BLTC RTC clock soft enable -0: Disable the RTC clock of BLTC -1: Enable RTC clock of BLTC - - - ARCH RTC clock soft enable -0: Disable the RTC clock of ARCH -1: Enable RTC clock of ARCH - - - - SOFT_RST0 - - BLTC soft reset - - - Efuse soft reset - - - Auxadc soft reset - - - TMR soft reset - - - CAL soft reset - - - - XTL_WAIT - - RGB driver power down enable in chip deep sleep mode - - - 26MHz crystal oscillator wait cycles - - - - RG_DVDD_RESERVED1 - - RG_DVDD_RESERVED0 - - - RG_DVDD_RESERVED1 - - - - VBAT_CTRL0 - - LDOs output selection control. (To AUXADC internal calibration) - - - - THM_OTP_CTRL - - OTP function enable control bit - - - OTP threshold -3'b011: 135C, default - - - - LED_CTRL - - Internal resistor for sink current calibration bit selection -0: From Software Register -1: From Ememory - - - current mode enable "0" disable (default) "1" enable (default) - - - set current level in current mode -bit3~bit1 effective, bit0 not used, -1.25/2.5/5/10/20/40/80/160uA 7step - - - sink current adjustment for test enable signale, high effective -Defautl 1'b0 - - - sink current calibration bit. 1.25uA/step -default 0000000(1.25uA) - - - - KPLED_CTRL1 - - KPLED LDO current limit threshold adjust: -default 1'b1 - - - Current control bit. 16 steps -(default 4鈥檅0) -(0000:0.9mA -0001:1.8mA - 0010:2.7mA - 0011:3.6mA - 0100:4.5mA - 0101:5.4mA - 0110:6.3mA - 0111:7.2mA - 1000:16.2mA - 1001:22.5mA - 1010:29.7mA - 1011:37.8mA - 1100:46.8mA - 1101:56.7mA - 1110:67.5mA - 1111:79.2mA) - - - KPLED LDO foldback current threshold adjust: -default 1'b1 - - - KPLED LDO stability compensation: -default 2'b10 - - - KPLED LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - KPLED LDO program bits: -100mV/step, 2.8V~3.5V; default 3.3V, 3'b101 - - - KPLED LDO short protection power down -default:0,on - - - - LDO_VBAT_CTRL1 - - LDO_USB current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_USB short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - LDO_USB short current threshold adjust default 1'b1 - - - LDO_USB compensation capacitor and resistor adjust - - - LDO_USB discharge en - - - - LDO_VBAT_CTRL2 - - LDO_VIO33 current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_VIO33 short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_VIO33 compensation capacitor and resistor adjust - - - LDO_VIO33 discharge en - - - LDO_CAMA current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_CAMA short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_CAMA compensation capacitor and resistor adjust - - - LDO_CAMA discharge en - - - - LDO_VBAT_CTRL3 - - LDO_LCD current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_LCD short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_LCD compensation capacitor and resistor adjust - - - LDO_LCD discharge en - - - LDO_MMC current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_MMC short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_MMC compensation capacitor and resistor adjust - - - LDO_MMC discharge en - - - - LDO_ANA_CTRL - - LDO_ANA current limit threshold adjust default 1'b0 - - - LDO_ANA short protect EN: -鈥1鈥 is disable -鈥0鈥 is enable(default) - - - LDO_ANA short current threshold adjust default 1'b0 - - - LDO_ANA compensation capacitor and resistor adjust - - - LDO_ANA bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - ANA LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - ANA LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step - - - - LDO_VIO18_CTRL - - LDO_VIO18 current limit threshold adjust default 1'b0 - - - LDO_VIO18 short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - LDO_VIO18 short current threshold adjust default 1'b1 - - - LDO_VIO18 compensation capacitor and resistor adjust - - - LDO_VIO18 bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - VIO18 LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - VIO18 LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step - - - - LDO_VGEN_CTRL1 - - LDO_MEM current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step - - - LDO_MEM short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - LDO_MEM short current threshold adjust default 1'b1 - - - LDO_MEM compensation capacitor and resistor adjust - - - LDO_MEM bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - MEM LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - MEM LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step - - - - LDO_SPIMEM_CTRL - - LDO_SPIMEM current limit threshold adjust default 1'b0 - - - LDO_SPIMEM short protect EN: -鈥1鈥 is disable -鈥0鈥 is enable(default) - - - LDO_SPIMEM short current threshold adjust default 1'b0 - - - LDO_SPIMEM compensation capacitor and resistor adjust - - - LDO_SPIMEM bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - SPIMEM LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - SPIMEM LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step - - - - LDO_CAMD_CTRL - - LDO_CAMD current limit threshold adjust default 1'b011 111~000 380mA~240mA 20mA/step - - - LDO_CAMD short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - LDO_CAMD short current threshold adjust default 1'b1 - - - LDO_CAMD compensation capacitor and resistor adjust - - - LDO_CAMD bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - CAMD LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - VIO18 LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step - - - - LDO_RF15_CTRL - - LDO_RF15 current limit threshold adjust default 1'b0 - - - LDO_RF15 short protect EN: -鈥1鈥 is disable -鈥0鈥 is enable(default) - - - LDO_RF15 short current threshold adjust default 1'b0 - - - LDO_RF15 compensation capacitor and resistor adjust - - - LDO_RF15 bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - LDO RF15 remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - RF15 LDO output voltage select 000000~111111 1.4V~1.8875V 12.5mV/step - - - - LDO_VGEN_CTRL3 - - - LDO_LP18_CTRL - - LDO_LP18 current limit threshold adjust default 1'b011 111~000 380mA~240mA 20mA/step - - - LDO_LP18 short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_LP18 compensation capacitor and resistor adjust - - - LDO_LP18 discharge en - - - - LDO_LP18_RF12_CTRL - - LDO_RF12 current limit threshold adjust default 1'b0 - - - LDO_RF12 short protect EN: -鈥1鈥 is disable -鈥0鈥 is enable(default) - - - LDO_RF12 short current threshold adjust default 1'b0 - - - RF12 LDO output voltage select 000000~111111 0.8125~1.6V 12.5mV/step - - - LDO_RF12 compensation capacitor and resistor adjust - - - LDO_RF12 bypass application: -default 1'b0, no bypass - 1'b1, bypass - - - RF12 LDO remote cap application: -default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - - DCDC_CTRL1 - - DCDC to AUXADC trim channel selection -3'b001: select VCORE -3'b010: select VRF (VRF*18/37) -3'b011: select VPA (VPA*18/68) -RG_DCDC_AUXTRIM_SEL[2], internal test mode select: -0: default, internal test mode disable -1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path -3'b100: enpwm_vrf -3'b101: zx_vrf -3'b110: enpwm_vcore -3'b111: zx_vcore - - - test mode control. -1'b0: default, clock output off -1'b1: clock output on - - - phase shift option -1'b0: default, w/i 1/5 phase shift at internal mode -1'b1: uni-phase mode, all ouputs = channel 0 - - - clock selection for each channel -RG_CLKOUT_SEL[0]: VCORE clk selection -RG_CLKOUT_SEL[1]: VGEN clk selection -RG_CLKOUT_SEL[2]: VRF clk selection -RG_CLKOUT_SEL[3]: VPA clk selection -0: internal mode, default -1: external mode - - - - VCORE_CTRL2 - - anti-ring enable -1'b0: default, anti-ring off -1'b1: anti-ring on - - - current limit threshold tuning -2'b00: default -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - current sense average ratio -current sense multiplier tuning -2'b00: default, x1 -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - current sense R ratio tuning -current sense multiplier tuning -2'b00: default, x1 -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - - VCORE_CTRL3 - - force PWM mode -1'b0: default, PFM/PWM auto mode -1'b1: force PWM mode - - - force zero-cross off -1'b0: default, zero_cross detect on -1'b1: zero-cross detect off - - - zero-cross offset tuning -2'b00: default -2'b01: +5mV offset -2'b10: -5mV offset -2'b11: -10mV offset - - - PFM mode threshold for upper limit -2'b00: default, 0.6V -2'b01: 0.55V -2'b10: 0.65V -2'b11: 0.7V - - - compensation R select -2'b00: default, 360k -2'b01: 320k -2'b10: 400k -2'b11: 440k - - - slope compensation tuning -2'b00: default -2'b01: 0.5x -2'b10: 1.5x -2'b11: 2x - - - high side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - low side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - - VRF_CTRL0 - - anti-ring enable -1'b0: default, anti-ring off -1'b1: anti-ring on - - - current limit threshold tuning -2'b00: default -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - current sense average ratio -current sense multiplier tuning -2'b00: default, x1 -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - current sense R ratio tuning -current sense multiplier tuning -2'b00: default, x1 -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - - VRF_CTRL1 - - force PWM mode -1'b0: default, PFM/PWM auto mode -1'b1: force PWM mode - - - force zero-cross off -1'b0: default, zero_cross detect on -1'b1: zero-cross detect off - - - zero-cross offset tuning -2'b00: default -2'b01: +5mV offset -2'b10: -5mV offset -2'b11: -10mV offset - - - PFM mode threshold for upper limit -2'b00: default, 0.6V -2'b01: 0.55V -2'b10: 0.65V -2'b11: 0.7V - - - compensation R select -2'b00: default, 360k -2'b01: 320k -2'b10: 400k -2'b11: 440k - - - slope compensation tuning -2'b00: default -2'b01: 0.5x -2'b10: 1.5x -2'b11: 2x - - - high side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - low side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - - VGEN_CTRL2 - - soft reset of all dcdc generated clk - - - anti-ring enable -1'b0: default, anti-ring off -1'b1: anti-ring on - - - force zero-cross off -1'b0: default, zero_cross detect on -1'b1: zero-cross detect off - - - zero-cross offset tuning -2'b00: default -2'b01: +5mV offset -2'b10: -5mV offset -2'b11: -10mV offset - - - current limit threshold tuning -2'b00: default -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - current sense R ratio tuning -current sense multiplier tuning -2'b00: default, x1 -2'b01: -20% -2'b10: +40% -2'b11: +20% - - - - VGEN_CTRL3 - - force PWM mode -1'b0: default, PFM/PWM auto mode -1'b1: force PWM mode - - - reserved - - - PFM mode threshold for upper limit -2'b00: default, 0.6V -2'b01: 0.55V -2'b10: 0.65V -2'b11: 0.7V - - - compensation R select -2'b00: default, 360k -2'b01: 320k -2'b10: 400k -2'b11: 440k - - - slope compensation tuning -2'b00: default -2'b01: 0.5x -2'b10: 1.5x -2'b11: 2x - - - high side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - low side slew rate control -2'b00: default -2'b01: 0.75x -2'b10: 0.5x -2'b11: 0.25x - - - - CHGR_CTRL1 - - Select charger CC mode enable, high effective, Default 鈥0鈥 - - - Battery charging end voltage - 00: Vend=4.2V - 01: Vend=4.3V - 10: Vend=4.4V - 11: Vend=4.5V -(default 2鈥檅00) - - - Termination charger current programmable bits -00:cc*0.9 -01:cc*0.4 -10:cc*0.2 -11:cc*0.1 - - - control bits of over voltage protection for VCHG. When VCHG is above some level set by these 2 bits, charger power down and CHGR_OVI becomes high. - 00: 6.0V 01: 6.5V 10: 7.0V 11: 9.7V -Default 2鈥檅01 - - - CC mode charging current -0000:300mA 0001 : 350 -0010: 400mA 0011 : 450 -0100: 500mA 0101 :550 -0110: 600mA 0111: 650 -1000: 700mA 1001: 750 -1010: 800mA 1011: 900 -1100: 1000mA 1101: 1100 -1110: 1200mA 1111: 1300 -Default4鈥檅0 - - - - AUXADC_CTRL - - THM calibration enable signal, -0: disable THM calibration(default) -1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration - - - Aux ADC current sense enable signal, active high, default 0. - - - AUX ADC channel ATE test scan mode control. 1 for ATE test channel scan, 0 for normal work. For ATE test channel scan, set this reg to 1, and using AUXAD_CS[4:0] to scan channel. - - - AUXADC signal VSS selection, -0: share signal VSS ball with all analog circuit -1: use specific ground ball as signal VSS - - - AUXADC reference source selection, -0: from bandgap current generate internal reference (default) -1: from bandgap voltage reference directly. - - - AUXADC output code selection -0: output ADC 12 bit code with 11bit resolution.(default) -1: output ADC 12 bit original raw measured code. - - - - CHGR_STATUS - - Charging port of NON-DCP status -鈥1鈥 Charging port is NON-DCP -鈥0鈥 Charging port is not NON-DCP - - - Charging detect done after charger insert once - - - The output of the comparator of DCD detection or SDP/NON-DCP detection -鈥1鈥 means DCD pass when doing DCD, - or SDP if CHG_DET=0 -鈥0鈥 means DCD fail when doing DCD, -or NON-DCP if CHG_DET=0 - - - The output of the comparator of DCP_DET loop -鈥1鈥 means DCP if CHG_DET is 鈥1鈥 -鈥0鈥 means CDP if CHG_DET is 鈥1鈥 - - - The output of the comparator of CHG_DET loop -鈥1鈥 DCP or CDP -鈥0鈥 SDP or NON-DCP - - - Charging port of SDP status -鈥1鈥 Charging port is SDP -鈥0鈥 Charging port is not SDP - - - Charging port of DCP status -鈥1鈥 Charging port is DCP -鈥0鈥 Charging port is not DCP - - - Charging port of CDP status -鈥1鈥 Charging port is CDP -鈥0鈥 Charging port is not CDP - - - Flag when charging current below some level(0.5*full current) in CV mode -High effective - - - Charger voltage ready indicator, high effective -When VCHG<4.1V: 鈥0鈥 -When VCHG>4.3V: 鈥1鈥 - - - Charger present indicator, high effective -When VCHG<3.1V: 鈥0鈥 -When VCHG>3.3V: 鈥1鈥 - - - VCHG over voltage(programmable) flag -When VCHG higher than some voltage set by VCHG_OVP_V<5:0> and lasts 2mS, CHGR_OVI=鈥1鈥 -The hysteresis voltage is 600mV. - - - - ARCH_EN - - PCLK_arch enable - - - - MCU_WR_PROT_VALUE - - Arch_en write protect bit status. -When mcu_wr_prot_value==16'h3c4d, - the bit is "1",else "0" - - - Arch_en write protect value - - - - - DCDC_CORE_REG1 - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCCORE, in default the clock is from RC in analog -6'h0: no divide -6'h1: divide by 2 -鈥︹ -6'h3F: divide by 64 - - - - DCDC_GEN_REG1 - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCGEN, in default the clock is from RC in analog -6'h0: no divide -6'h1: divide by 2 -鈥︹ -6'h3F: divide by 64 - - - - DCDC_VRF_REG1 - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCVRF, in default the clock is from RC in analog -6'h0: no divide -6'h1: divide by 2 -鈥︹ -6'h3F: divide by 64 - - - - BG_CTRL - - Band-gap chopping enable: -鈥0鈥:chopping disable (default) -鈥1鈥: chopping enable - - - Band-gap test enable: -鈥0鈥:test disable (default) -鈥1鈥: test enable - - - - LDO_VOSEL1 - - USB33 LDO output voltage select 000000~111111 1.625V~3.225V 25mv/step - - - CAMA LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - - LDO_VOSEL3 - - MMC LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - VIO33 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - - LDO_VOSEL4 - - LCD LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - LP18 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - - LDO_LP18_CTRL1 - - LDO_LP18 increase feedback current 300nA in ULP mode - - - LDO_LP18 bias current trim in ulp mode;20nA/step - - - LDO_VIO33 increase feedback current 300nA in ULP mode - - - LDO_VIO33 bias current trim in ulp mode;20nA/step - - - - RESERVED_REG_CORE - - reserved for CORE: -RG_RESERVED_CORE[0] for ldo ANA cap sel, default 0; -RG_RESERVED_CORE[1] for ldo CAMIO cap sel, default 0; -RG_RESERVED_CORE[2] for ldo RF18A cap sel, default 0; -RG_RESERVED_CORE[3] for ldo RF18B cap sel, default 0; - - - - RESERVED_REG1 - - - RESERVED_REG2 - - - LDO_SIM_CTRL0 - - LDO_SIM1 current limit threshold adjust default 1'b011 000 to 111 current limit increase - - - LDO_SIM1 short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_SIM1 compensation capacitor and resistor adjust - - - LDO_SIM1 discharge en - - - LDO_SIM0 current limit threshold adjust default 1'b011 000 to 111 current limit increase - - - LDO_SIM0 short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - compensation resistor adjust default 1'b1 - - - LDO_SIM0 compensation capacitor and resistor adjust - - - LDO_SIM0 discharge en - - - - LDO_SIM_VOSEL - - SIM0 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step 1.8V=000111 3V=110111 - - - SIM1 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step 1.8V=000111 3V=110111 - - - - SIM_VPA_CTRL0 - - LDO_SIM0 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_SIM1 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_SIM0 lower power mode EN: -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_SIM1 lower power mode EN: -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - VPA low power mode -1'b0: active mode -1'b1: low-power mode - - - DCDC VPA power down -1'b0: DCDC on -1'b1: DCDC power down - - - - LDO_SIM_CTRL1 - - LDOSIM2 power down enable in deep sleep mode - - - LDO SIM1 power down enable in deep sleep mode - - - LDO SIM1 low power mode enable in deep sleep mode -0: Disable -1: Enable - - - LDO SIM0 low power mode enable in deep sleep mode -0: Disable -1: Enable - - - - VPA_CTRL0 - - DCDC VPA reference Bits selection -0: From efuse -1: From Software Register - - - output voltage trim -5'10000: default 1.2V, 18.75mV/step -5'11111: +15 step -5'00000: -16 step - - - - VPA_CTRL1 - - output voltage selection, 25mV/step. -7'h00=0.4V, -7'h7C=3.5V -default 7'h78=3.4V - - - - VPA_CTRL2 - - force zero-cross off -1'b0: default, zero_cross detect on -1'b1: zero-cross detect off - - - zero-cross offset tuning -2'b00: default -2'b01: +4mV offset -2'b10: -2mV offset -2'b11: -4mV offset - - - anti-ring enable -1'b0: default, anti-ring off -1'b1: anti-ring on - - - APC mode enable -1'b0: default, RG control mode -1'b1: APC mode - - - APC ramp selection -1'b0: default, 2.0x ramp -1'b1: 2.5x ramp - - - bypass mode disable -1'b0: default, auto bypass -1'b1: bypass off - - - bypass force on -1'b0: default, auto bypass -1'b1: force bypass mode on - - - bypass mode threshold -2'b00: default, ~200mV - - - compensation C3 -2'b00: default 6.5pF -2'b01: -0.5pF -2'b10: +1pF -2'b11: +0.5pF - - - current limit threshold tuning -2'b00: default 36k -2'b01: 52k -2'b10: 12k -2'b11: 28k - - - current sense multiplier tuning -2'b00: default, x1 -2'b01: x0.5 -2'b10: x2 -2'b11: x1.5 - - - - VPA_CTRL3 - - sawtooth calibration -1'b0: default, auto calibration before power-on -1'b1: calibration manully - - - DVS control -1'b0: default, off -1'b0: on, for DCM down discharge - - - force PWM mode -1'b0: default, PFM/PWM auto mode -1'b1: force PWM mode - - - 100% duty selection -1'b0: default, max duty=100% -1'b1: max duty ~95% - - - PFM mode threshold for upper limit -2'b00: default,960mV -2'b01: -40mV -2'b10: +40mV -2'b11: +80mV - - - compensation R2 select -2'b00: default, 960k -2'b01: 880k -2'b10: 1040k -2'b11: 1120k - - - compensation R3 select -2'b00: default, 9k -2'b01: 4.5k -2'b10: 18k -2'b11: 13.5k - - - sawtooth tuning manully -2'b00: default 0.75x -2'b01: 0.875x -2'b10: 0.5x -2'b11: 0.625x - - - high side slew rate control -2'b00: default 2.5x -2'b01: 2x -2'b10: 1.5x -2'b11: 1x - - - low side slew rate control -2'b00: default 2x -2'b01: 1.5x -2'b10: 1.5x -2'b11: 1x - - - - DCDC_VPA_REG1 - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCWPA, in default the clock is from RC in analog -6'h0: no divide -6'h1: divide by 2 -鈥︹ -6'h3F: divide by 64 - - - - - - - - - - - - - - - - - MODULE_EN0 - - PINREG module enable -0: Disable the PCLK of pin registers -1: Enable the PCLK of pin registers - - - RTC_TOPA module enable -0: Disable the PCLK of RTC_TOPA -1: Enable the PCLK of RTC_TOPA - - - PSM module enable -0: Disable the PCLK of PSM -1: Enable the PCLK of PSM - - - EIC module enable -0: Disable the PCLK of EIC -1: Enable the PCLK of EIC - - - WDG module enable -0: Disable the PCLK of watchdog -1: Enable the PCLK of watchdog - - - RTC module enable -0: Disable the PCLK of RTC -1: Enable the PCLK of RTC - - - - DIG_CLK_EN0 - - WDG clk sel -0: clk_wdg_rtc -1: clk_32k_rtc - - - - RTC_CLK_EN0 - - EFS RTC clock soft enable -0: Disable the RTC clock of EFS -1: Enable RTC clock of EFS - - - EIC RTC clock soft enable -0: Disable the RTC clock of EIC -1: Enable RTC clock of EIC - - - Watchdog RTC clock soft enable -0: Disable the RTC clock of Watchdog -1: Enable RTC clock of Watchdo - - - RTC RTC clock soft enable -0: Disable the RTC clock of RTC -1: Enable RTC clock of RTC - - - ARCH RTC clock soft enable -0: Disable the RTC clock of ARCH -1: Enable RTC clock of ARCH - - - - SOFT_RST0 - - EIC soft reset - - - Watchdog soft reset - - - RTC soft reset - - - - VBAT_CTRL1 - - LDO_VBAT ULP reference voltage trim bit - - - LDO_VBAT reference voltage trim bit - - - - LDO_VGEN_CTRL3 - - LDO_VGEN reference voltage trim bit - - - - DCDC_CTRL1 - - internal oscillator enable -1'b0: oscillator off -1'b1: oscillator on - - - oscillator frequency tuning -5'b10000: default 3MHz -5'b01111: -1 step -5'b10001: +1 step -5'b00000: -16 step -5'b11111: +15 step - - - - PM2_PD_EN - - PM2 VCORE ULP mode en -1'b0: disable -1'b1: enable - - - PM2 VIO33 ULP mode en -1'b0: disable -1'b1: enable - - - PM2 LP18 ULP mode en -1'b0: disable -1'b1: enable - - - PM2 VCORE LP mode en -1'b0: disable -1'b1: enable - - - PM2 VGEN LP mode en -1'b0: disable -1'b1: enable - - - PM2 VLP18 LP mode en -1'b0: disable -1'b1: enable - - - PM2 VDCXO LP mode en -1'b0: disable -1'b1: enable - - - PM2 VIO33 LP mode en -1'b0: disable -1'b1: enable - - - PM2 VIO18 LP mode en -1'b0: disable -1'b1: enable - - - VCORE power down en -1'b0: disable -1'b1: enable - - - VGEN power down en -1'b0: disable -1'b1: enable - - - VLP18 power down en -1'b0: disable -1'b1: enable - - - VDCXO power down en -1'b0: disable -1'b1: enable - - - VIO33 power down en -1'b0: disable -1'b1: enable - - - VIO18 power down en -1'b0: disable -1'b1: enable - - - - VGEN_CTRL1 - - output voltage selection, 12.5mV/step. -8'h00= 1.3V -default 8'h2c=1.85V - - - - LDO_VBAT_CTRL1 - - - CHGR_STATUS - - Chgr_int enable after CHG_DET_DONE - - - 0: switch DPDM to USB phy when DCP -1: keep to connect charger detector when DCP - - - - POWER_PD_SW0 - - LDO_SPIMEM power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_USB power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_ANA power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_RF12 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_LP18 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_VIO33 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - EMM domain power down 1: power down 0: power on - - - LDO of charge pump power down -1: power down -0: power on - - - LDO_DCXO power down 1: power down 0: power on - - - LDO_MEM power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_VIO18 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - DCDC power down -1'b0: DCDC on -1'b1: DCDC power down - - - DCDC power down -1'b0: DCDC on -1'b1: DCDC power down - - - DCDC power down -1'b0: DCDC on -1'b1: DCDC power down - - - LDO_MMC power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - Band-gap power down: -鈥1鈥 is power down -鈥0鈥 is power up -At reset, should be "1" - - - - POWER_PD_HW - - Power off_sequence enable - - - - SOFT_RST_HW - - register soft reset锛寃rite 1 can锛 -1銆 reset total system -2 銆乸ower down and up - - - - XTAL_RC_CTRL - - RC Oscillator 32kHz power up -1鈥榖0: power off -1'b1: power on - - - Crystal 64kHz power up -1鈥榖0: power off -1'b1: power on - - - Crystal 32kHz capacitor coarse adjust - - - Crystal 32kHz capacitor fine adjust - - - - RTC_CTRL - - LDO RTC output program bits -3'b100: 1.8V (Default) - - - Backup battery output program bits -3'b100: 3.0V default - - - RTC bandgap calibretion bit -cover +/-10% -step 0.625% acc +/- 0.3125% - - - - RG_RTC_RESERVED1 - - RG_RTC_RESERVED0 - - - RG_RTC_RESERVED1 - - - - DVDD_CTRL - - ULP global bias power down -1'b0: default, power on -1'b1: power down - - - DVDD18 isolation signal used in force mode -1'b1: default isolation - - - DVDD18 power down control used in force mode -1'b0: DVDD18 power switch on -1'b1: DVDD18 power switch off - - - - POWON_CTRL - - Control bit of de-glitch time for battery remove -"00" 32us "01" 64us "10" 128us "11" no de-glitch default"00" - - - Over voltage locked-out enable (high effective) -Default 鈥1鈥 - - - Over voltage locked-out detecting time -00 : 1ms (default) -01 : 0.5ms -10 : 0.25ms -11 : 2ms - - - Over voltage locked-out threshold -00 : 5.0V (default) -01 : 5.2V -10 : 4.8V -11 : 4.2V - - - over voltage locked-out threshold -00 : 1.9V (default) -01 : 1.95V -10 : 1.85V -11 : 1.8V - - - Battery crash voltage setting: -00: 1.7/2.1V (default) -01: 1.8/2.2V -10: 1.65/2.3V -11: 1.6/2.5V - - - BUA function enable -1'b0: default, off -1'b1: enable - - - PBINT pull-high control -1'b0: with internal pull-high. Default -1'b1: without internal pull-high - - - Power detect enable -1'b0: default, off -1'b1: Power detect on (UVLO/OVLO/VBATLOW) - - - VBATLOW detect enable control at LP mode -1'b0: VBATLOW detect off -1'b1: VBATLOW detect on - - - UVLO detect enable control at LP mode -1'b0: UVLO detect off -1'b1: UVLO detect on - - - - KPLED_CTRL0 - - Key PAD LED driver power down -鈥1鈥 power down (default) -鈥0鈥 enable - - - Keypad LED pull down enable signale, high effective -Defautl 1'b0 - - - KPLED LDO power down signal, high effective -(Default 1, Off) iload=50mA - - - LDO_KPLED trim bits: -6.25mV/step, 0.7V~0.89375V; default 0.8V, 5'b10000 - - - - POWER_PD_SW1 - - LDO_CAMA power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_CAMD power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_LCD power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - LDO_RF15 power down: -鈥1鈥 is power down(default) -鈥0鈥 is power up - - - - POWER_LP_SW0 - - LDO_USB lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_DCXO lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_CAMA lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_CAMD lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_MMC lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_LCD lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_VIO18 lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_ANA lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_MEM lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_SPIMEM lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_RF15 lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_RF12 lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_LP18 lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_VIO33 lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - - LDO_VOSEL1 - - DCXO LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step - - - - SLP_LDO_ULP_CTRL - - LDO_VCORE ultra lower power mode EN: -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_VIO33 ultra lower power mode EN: -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_LP18 ultra lower power mode EN: -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - - LDO_VGEN_CTRL - - DCDC supplied LDO TRIM CONTROL BITS: -000: cal disable (default) -001: LDO VDDCAMIOcal enable; -010: LDO ANA cal enable; -011: LDO VDDRF18A cal enable; -100: LDO VDDCAMD cal enable; -101: LDO VDDMEM cal enable; -110: LDO VDDCON cal enable; -111: LDO VDDRF18B cal enable; - - - - LDO_LP18_VIO33_ULP_EN - - LDO_VIO33 ultra lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - LDO_LP18 ultra lower power mode EN(force mode): -鈥1鈥 is enable -鈥0鈥 is disable(default) - - - - VCORE_CTRL0 - - output voltage selection -9'b100100000, default 0.9V - - - - VCORE_CTRL1 - - low power mode(force mode) -1'b0: active mode -1'b1: low-power mode - - - Ultra- low power mode(force mode) -1'b0: active mode -1'b1: low-power mode - - - Retention active at ULP mode(force mode) -1'b0: retention off -1'b1: retention active - - - output voltage trimming - - - output voltage trimming at low power mode - - - - VRF_CTRL2 - - VRF low power mode(force mode) -1'b0: active mode -1'b1: low-power mode - - - output voltage selection, 12.5mV/step. -8'h00= 1.3V -default 8'h2c=1.85V - - - - VRF_CTRL3 - - output voltage selection, 6.25mV/step. -9'b011010000, default 1.3V - - - - VGEN_CTRL0 - - LP mode VMEM power switch enable: -1'b0:VMEM out -1'b1:VMEM short lp18,lp18 out - - - PM2 LDO VMEM power switch value: -1'b0:VMEM out -1'b1:VMEM short lp18,lp18 out - - - VGEN low power mode(force mode) -1'b0: active mode -1'b1: low-power mode - - - VGEN output voltage trim -5'10000: default 1.2V, 18.75mV/step -5'11111: +15 step -5'00000: -16 step - - - - CHGR_CTRL0 - - 鈥1鈥 Internal charger power down - 鈥0鈥 Internal charger power up - - - Charger production test signal,testmode flag -"1"ATE test mode, reduce delay time after VCHG insert -"0" normal mode - - - Choice of charger external power device -0:PNP+NMOS -1:PMOS+DIODE -Default value is 0 - - - VCHG tracking voltage level for automatic input control loop(AICL) -00: 3.8V -01: 3.95V -10: 4.3V -11: 4.5V -Default value is 11 - - - Battery sense DAC (CC-CV trans-point control) -(default 6鈥檅010000) - - - - CHGR_DET_CTRL0 - - The DP DM path switch control -鈥1鈥 switch to USB phy, BC1P2 detect disable (default) -鈥0鈥 switch to BC1P2, BC1P2 detect enable - - - DP, DM to auxADC select signal: -鈥0鈥: switch off, no DP/DM to auxADC -鈥1鈥: switch on, DP/DM to auxADC - - - charger int delay time: -000锛0ms -001锛64ms -010锛2脳64ms -鈥.. -111锛7脳64ms - - - - SLP_LDO_PD_CTRL0 - - LDO VIO18 power down enable in PM1 -0: disable -1: enable - - - LDO ANA power down enable in deep sleep mode -0: disable -1: enable - - - LDO RF12 power down enable in deep sleep mode -0: disable -1: enable - - - LDO LP18 power down enable in PM1 -0: disable -1: enable - - - LDO DCXO power down enable PM1 -0: disable -1: enable - - - LDO VIO33 power down enable in PM1 -0: disable -1: enable - - - LDO RF15 power down enable in deep sleep mode -0: disable -1: enable - - - LDO SPIMEM power down enable in deep sleep mode -0: disable -1: enable - - - LDO USB power down enable in PM1 -0: disable -1: enable - - - LDO KPLED power down enable in deep sleep mode -0: disable -1: enable - - - LDO MMC power down enable in deep sleep mode -0: disable -1: enable - - - LDO LCD power down enable in deep sleep mode -0: disable -1: enable - - - LDO CAMD power down enable in deep sleep mode -0: disable -1: enable - - - LDO CAMA power down enable in deep sleep mode -0: disable -1: enable - - - - SLP_LDO_PD_CTRL1 - - LDO CP power down enable in PM1 -0: disable -1: enable - - - ALL LDO and DCDC power down enable in deep sleep mode -0: disable -1: enable - - - IO PAD sleep enable in deep sleep mode -0: disable -1: enable - - - LDO and DCDC can be controlled by external device if this bit is set -0: disable -1: enable - - - LDO MEM power down enable in PM1 -0: disable -1: enable - - - - SLP_DCDC_PD_CTRL - - The number of 32K cycles set reset delay in DCDC CORE power down sleep mode - - - The number of 32K cycles release reset delay in DCDC CORE power down sleep mode - - - DCDC CORE power drop enable in deep sleep mode -0: disable -1: enable - - - DCDC RF power down enable in deep sleep mode -0: disable -1: enable - - - DCDC GEN power down enable in PM1 -0: disable -1: enable - - - - DCDC_CORE_SLP_CTRL0 - - delay between two steps in PM1 -00:1*32k clock -01:2*32k clock -10:3*32k clock -11:4*32k clock - - - step number in PM1 - - - voltage per step in PM1 -00000:0mv -00001:1*3.125mv -00010:2*3.125mv -鈥.. -11111:31*3.125mv - - - DCDC CORE power down enable in deep sleep mode -0: disable -1: enable - - - DCDCCORE step tune enable in deep sleep -0: disable -1: enable - - - - DCDC_CORE_SLP_CTRL1 - - DCDC CORE voltage control in PM1 - - - - SLP_DCDC_LP_CTRL - - DCDC CORE low power mode enable in PM1 -0: disable -1: enable - - - DCDC VRF low power mode enable in deep sleep mode -0: disable -1: enable - - - DCDC GEN low power mode enable in PM1 -0: disable -1: enable - - - - SLP_LDO_LP_CTRL0 - - LDO RF15 low power mode enable in deep sleep mode -0: disable -1: enable - - - LDO RF12 low power mode enable in deep sleep mode -0: disable -1: enable - - - LDO EMMCCORE low power mode enable in PM1 -0: disable -1: enable - - - LDO DCXO low power mode enable in PM1 -0: disable -1: enable - - - LDO VIO18 low power mode enable in PM1 -0: disable -1: enable - - - LDO ANA low power mode enable in deep sleep mode -0: disable -1: enable - - - LDO MEM low power mode enable in deep sleep mode -0: Disable -1: Enable - - - LDO MMC low power mode enable in deep sleep mode -0: Disable -1: Enable - - - LDO USB low power mode enable in PM1 -0: Disable -1: Enable - - - LDO LCD low power mode enable in deep sleep mode -0: Disable -1: Enable - - - LDO CAMD low power mode enable in deep sleep mode -0: Disable -1: Enable - - - LDO CAMA low power mode enable in deep sleep mode -0: Disable -1: Enable - - - - SLP_LDO_LP_CTRL1 - - DCDC CORE voltage control in PM2 - - - LDO LP18 low power mode enable in PM1 -0: Disable -1: Enable - - - LDO MEM low power mode enable in PM1 -0: Disable -1: Enable - - - - RESERVED_REG_RTC - - RG_RESERVED_RTC[4:0], DCXO trim bit for 32k-less poweroff mode. SW load from Efuse at first time power on. -RG_RESERVED_RTC[15:5], reserved - - - - DCDC_VLG_SEL - - DCDC Voltage Program Bits selection -0: From efuse -1: From Software Register - - - DCDC Voltage Trim Bits selection -0: From efuse -1: From Software Register - - - DCDC Voltage Program Bits selection -0: From efuse -1: From Software Register - - - DCDC Voltage Program Bits selection -0: From efuse -1: From Software Register - - - - LDO_VLG_SEL0 - - LDO_VGEN reference voltage trim bit selection -0: From efuse -1: From Software Register - - - LDO_VBAT reference ULP voltage trim bit selection -0: From efuse -1: From Software Register - - - LDO_VBAT reference voltage trim bit selection -0: From efuse -1: From Software Register - - - oscillator frequency tuning selection -0: From efuse -1: From Software Register - - - RTC bandgap calibretion bit selection -0: From efuse -1: From Software Register - - - VRF output voltage selection, -0: From efuse -1: From Software Register - - - output voltage trim selection -0: From efuse -1: From Software Register - - - LDO Voltage trim selection -0: From efuse -1: From Software Register - - - LDO Voltage trim selection -0: From efuse -1: From Software Register - - - - CLK32KLESS_CTRL0 - - RC_MODE write ack flag - - - RC_MODE write ack flag clear, high effective - - - Low power LDO_DCXO power down set in RTC - - - Low power LDO_DCXO power down clear in RTC - - - 0: 32k crystal -1: 32k-less - - - 32K clock select in 32K crystal removal option - 0: From XO 1: From RC - - - RC 32K oscillator enable - - - - CLK32KLESS_CTRL1 - - RC 32K mode in battery drop case: -16'h95A5: RC oscillator stop working. -Others: RC oscillator keep working. - - - - XTL_WAIT_CTRL0 - - - POR_RST_MONITOR - - When POR reset active, this register is reset to 0 - - - - WDG_RST_MONITOR - - When WDG reset active, this register is reset to 0 - - - - POR_PIN_RST_MONITOR - - When POR_EXT_RST active, this register is reset to 0 - - - - POR_SRC_FLAG - - Setting this bit could disable the 1S debouncing time of power key after boot. - - - register reset flag clear - - - Power on source flag: -[0]: Debounced PBINT signal, set when PBINT=0 >50ms, clear when PBINT=1>50ms. -[1]: PBINT initiating power-up hardware flag, set when PBINT=0>1s, clear after power down. -[2]: reserved. -[3]: reserved. -[4]: Debounced CHGR_INT signal, set when VCHG=1 >50ms, clear when VCHG=0>50ms. -[5]: Charger plug-in initiating power-up hardware flag, set when VCHG=1>1s, clear after power down. -[6]: RTC alarm initiating power-up hardware flag -[7]: Long pressing power key reboot hardware flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear after power down. -[8]: PBINT initiating power-up software flag, set when PBINT=0>1s, clear by pbint_flag_clr. -[9]: reserved. -[10]: Charger plug-in initiating power-up software flag, set when VCHG=1>1s, clear by chgr_int_flag_clr. -[11: External pin reset reboot software flag, set when EXTRSTN=0>30ms, clear by ext_rstn_flag_clr. -[12]: Long pressing power key reboot software flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear by pbint_7s_flag_clr. -[13]: flag when register reset happened - - - - POR_7S_CTRL - - Write 1鈥檅1 to this bit will clear pbint_7s_flag. - - - Write 1鈥檅1 to this bit will clear ext_rstn_flag. - - - Write 1鈥檅1 to this bit will clear chgr_int_flag. - - - Write 1鈥檅1 to this bit will clear pbint_flag. - - - 1: One-key Reset Mode; -0: Two-key Reset Mode; - - - 0: long reset; -1: short reset; - - - The power key long pressing time threshold: -0~1: 2S -2: 3S -3: 4S -4: 5S -5: 6S -6: 7S -7: 8S -8: 9S -9: 10S -10:11S -11:12S -12: 13S -13:14S -14:15S -15:16S - - - EXT_RSTN PIN function mode when 1key 7S reset -0: EXT_INT -1: RESET - - - RTC register PBINT_7S_AUTO_ON_EN - - - 0: enable 7s reset function; -1: disable 7s reset function; - - - 0: software reset; -1: hardware reset; - - - - HWRST_RTC - - RTC status register, set by HWRST_RTC_SET. - - - Software set this register to test VBAT and RTC power status. - - - - SMPL_CTRL0 - - SMPL mode: -[15:13]: SMPL timer threshold - 0: 0.25s - 1: 0.5s - 2: 0.75s - 鈥︹.. - 7: 2s -[12:0]: SMPL enable - 13'h1935: enable - Others: disable - - - - RTC_RST0 - - RTC register flag - - - - RTC_RST1 - - RTC register flag - - - - RTC_RST2 - - RTC register flag, reset by RTC_RST, default is 16'hA596 - - - - RTC_CLK_STOP - - rtc time over thresthold value - - - set reset rtc cnt time,default 16s - - - - VBAT_DROP_CNT - - VBAT Drop Time Count - - - - MIXED_CTRL - - Power detect enable -1'b0: default, off -1'b1: Power detect on (UVLO/OVLO/VBATLOW) - - - Battery presence flag to SW and POCV, so need RTC domain -"0" no battery -"1" battery presence - - - VBAT detect. Active 鈥0鈥 is reset, no need 32K osc (same as BATDET_OK). - - - ALL GPI source debug - - - GPI debug enable - - - ALL_INT debug, if 1, interrupt will be sent - - - Interupt debug enable - - - - POR_OFF_FLAG - - uvlo + ovlo chip power down flag - - - uvlo + ovlo chip power down flag clear - - - uvlo chip power down flag - - - uvlo chip power down flag clear - - - 7s hard chip power down flag - - - 7s hard chip power down flag clear - - - SW chip power down flag - - - SW chip power down flag clear - - - HW chip power down flag - - - HW chip power down flag clear - - - OTP chip power down flag - - - OTP chip power down flag clear - - - - SWRST_CTRL0 - - Software reset certain power enable when ext_rstn valid - - - Software reset certain power enable when pb_7s_rst valid - - - Software reset certain power enable when reg_rst valid - - - Software reset certain power enable when wdg_rst valid - - - register reset enable: -0: disable -1: enable - - - reset LDO to normal mode threshold time -8ms/step,default 8ms - - - - SWRST_CTRL1 - - Software reset LDO_SPIMEM_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_VIO18_PD enable when global reset valid -0: disable -1: enable - - - Software reset DCDC_GEN_PD enable when global reset valid -0: disable -1: enable - - - Software reset DCDC_CORE_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_MEM_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_DCXO_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_RF12_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_ANA_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_RF15_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_USB_PD enable when global reset valid -0: disable -1: enable - - - Software reset LDO_EMMCCORE_PD enable when global reset valid - - - - FREE_TIMER_LOW - - low 16 bit value of free timer - - - - FREE_TIMER_HIGH - - high 16 bit value of free timer - - - - RESERVED_REG1 - - voltage per step in PM2 -00000:0mv -00001:1*3.125mv -00010:2*3.125mv -鈥.. -11111:31*3.125mv - - - PM1 LDO VMEM power switch value: -1'b0:VMEM out -1'b1:VMEM short lp18,lp18 out - - - OVLO dbnc enable: -0: enable -1: disable - - - UVLO dbnc enable: -0: enable -1: disable - - - PM1 power detect off enable: -0:disable -1:enable - - - PM1 bg_pd off enable: -0:disable -1:enable - - - PM1 OSW3M off enable: -0:disable -1:enable - - - PM1 DVDD_PD off and DVDD_ISO hold enable: -0:disable -1:enable - - - - RESERVED_REG2 - - delay betwwen IO and VCORE when PM1 exits.(IO delay== {2'h0,pm1_sleep_dly2,2'h0}) - - - delay betwwen IO and VCORE when entering PM1.(VCORE delay== {2'h0,pm1_sleep_dly1,2'h0} + 1) - - - if chip_sleep is low,ULP mode can use this value - - - [3:0]:ULP cycle sel -4'h0:2; -4'h1:4; -4'h2:8; -鈥 -4'hb:4096. - - - - RESERVED_REG3 - - UVLO dbnc time: -0:1ms -1:61us -2:91.5:us -3:122us -鈥︹ -ff:7.8ms - - - UVLO dbnc time: -0:2ms -1:61us -2:91.5:us -3:122us -鈥︹ -ff:7.8ms - - - - RESERVED_REG4 - - delay betwwen IO and VCORE when PM1 exits.(IO delay== pm1_sleep_dly2) - - - delay betwwen IO and VCORE when entering PM1.(VCORE delay== pm1_sleep_dly1 + 1) - - - - RESERVED_REG5 - - LDO CP power down enable in PM2 -0: disable -1: enable - - - delay between two steps in PM2 -00:1*32k clock -01:2*32k clock -10:3*32k clock -11:4*32k clock - - - step number in PM2 - - - PM2 power detect off enable: -0:disable -1:enable - - - PM2 bg_pd off enable: -0:disable -1:enable - - - PM2 OSW3M off enable: -0:disable -1:enable - - - PM2 DVDD_PD off and DVDD_ISO hold enable: -0:disable -1:enable - - - LDO USB low power mode enable in PM2 -0: disable -1: enable - - - LDO MEM low power mode enable in PM2 -0: disable -1: enable - - - LDO USB power down enable in PM2 -0: disable -1: enable - - - LDO MEM power down enable in PM2 -0: disable -1: enable - - - - RESERVED_REG6 - - select the configuration used under PM2 -0: disable -1: enable - - - - PWR_WR_PROT_VALUE - - All power which default on write protect bit status. -When mcu_wr_prot_value==16'h6e7f, - the bit is "1",else "0" - - - Arch_en write protect value - - - - VOL_TUNE_CTRL_CORE - - clock source for CORE DVFS -0: clock 26M -1: clock 32K - - - delay between two steps -00:1*32k clock or 2us in 26M -01:2*32k clock or 4us in 26M -10:3*32k clock or 8us in 26M -11:4*32k clock or 16us in 26M - - - step number - - - DVFS voltage per step -00000:0mv -00001:1*3.125mv -00010:2*3.125mv -鈥.. -11111:31*3.125mv - - - voltage tune start bit - - - voltage tune flag -0:done -1:on going - - - voltage tune enable -0: disable -1: enable - - - - SMPL_CTRL1 - - Set once SMPL timer not expired. - - - Set once SMPL mode write finish - - - Clear SMPL_PWR_ON_FLAG - - - Clear SMPL_MODE_WR_ACK - - - Set once SMPL timer not expired, - - - SMPL enable indication - - - - - - - - - - - - - - - - - - - low 16 bits of watchdog value low 16 bits of watchdog value - - wdg_ld_value_low: low 16 bit of watchdog timer load value -wdg_ld_value_high: high 16 bit of watchdog timer load value -wdg_ld_value_higher: higher 16 bit of watchdog timer load value -wdg_ld_value_low, wdg_ld_value_high and wdg_ld_value_higher are used together.Software should write wdg_ld_value_higher firstly, and then write wdg_ld_value_high, last write wdg_ld_value_low, because writing wdg_ld_value_low can trig loading both wdg_ld_value_low and wdg_ld_value_high to watchdog counter, and writing wdg_ld_value_high cannot trig this event. So software must guarantee wdg_ld_value_high is ready when writing wdg_ld_value_low. -In reset mode, software should load new value before timer decrease to 0. In interrupt mode, this value is counting start number. The default value is about 8 seconds. - - - - high 16 bits of watchdog value high 16 bits of watchdog value - - See wdg_ld_value_low description. - - - - watchdog control watchdog control - - Watchdog reset enable bit -0: reset is disabled -1: reset is enabled -For reset mode: wdg_rst_en =1, wdg_irq_en=0. -For interrupt mode: wdg_rst_en =0, wdg_irq_en=1. -For combined mode: wdg_rst_en =1, wdg_irq_en=1. -Reset can't be triggered before wdg_rst_raw is cleared. - - - Watchdog version -0: watchdog use old behavior, this is for backward compatibility -1: watchdog uses new behavior, such as multiple loads without checking busy bit, only need to read once to get timer counter value. - - - Watchdog counter open: -0: counter stops. -1: counter runs. - - - Watchdog interrupt enable bit -0: interrupt is disabled -1: interrupt is enabled -For reset mode: wdg_rst_en =1, wdg_irq_en=0. -For interrupt mode: wdg_rst_en =0, wdg_irq_en=1. -For combined mode: wdg_rst_en =1, wdg_irq_en=1. - - - - watchdog interrupt clear watchdog interrupt clear - - Watchdog reset clear -Write 1 to this bit to clear reset -Read this bit always get 0. - - - Watchdog interrupt clear -Write 1 to this bit to clear interrupt -Read this bit always get 0. - - - - watchdog interrupt raw status watchdog interrupt raw status - - Watchdog load busy status -0: Watchdog is ready for new loading -1: Last loading is not completed -Software must not load new value when this bit is busy, that is, this bit should be checked before any new loading. -This bit is set after a new loading, and lasts two or three RTC clock cycles, about 60us - 92us. - - - Watchdog reset raw status. Watchdog reset cannot clear this raw status, Also it can be used to judge if or not system rebooting comes from watchdog reset. Write wdg_rst_clr can clear this raw status. - - - Watchdog interrupt raw status. Watchdog reset cannot clear this raw status. Write wdg_irq_clr can clear this raw status. - - - - watchdog interrupt mask status watchdog interrupt mask status - - Watchdog interrupt masked status - - - - low 16 bits of watchdog counter value low 16 bits of watchdog counter value - - wdg_cnt_low: Low 16 bit of watchdog timer counter value. -wdg_cnt_high: Mid 16 bit of watchdog timer counter value. -wdg_cnt_higher: High 16 bit of watchdog timer counter value. -wdg_cnt_low, wdg_cnt_mid and wdg_cnt_high are used together. -This read-only register indicates current counter value. -It鈥檚 not recommended to read this register in normal usage. -Because the counter is in different clock domain with APB, software needs use double-reading method to read this value, like system timer. - - - - high 16 bits of watchdog counter value high 16 bits of watchdog counter value - - See wdg_cnt_low description. - - - - watchdog lock control watchdog lock control - - Watchdog lock control -Write 16鈥檋E551 to this register to unlock watchdog. -Write other value to this register to lock watchdog -If reading this register, bit-0 is lock status, and other bits are reserved. -If watchdog is locked, all control registers cannot be written by software. - - - - low 16 bits of watchdog counter value for read low 16 bits of watchdog counter value for read - - wdg_cnt_read_low: Low 16 bit of watchdog timer counter value for read. -wdg_cnt_read_high: High 16 bit of watchdog timer counter value for read. -wdg_cnt_read_higher: Higher 16 bit of watchdog timer counter value for read. -wdg_cnt_read_low and wdg_cnt_read_high are used together. -This read-only register indicates current counter value. -Read once can get watchdog counter value. No need to double read this reg. -Refer to timer鈥檚 TIMER0_CNT_RD or TIMER1_CNT_RD - - - - high 16 bits of watchdog counter value for read high 16 bits of watchdog counter value for read - - Refer to wdg_cnt_read_low - - - - low 16 bits of watchdog irq value low 16 bits of watchdog irq value - - wdg_ irq_value_low: Low 16 bit of watchdog irqvalue. -wdg_ irq_value_high: High 16 bit of watchdog irqvalue. -wdg_ irq_value_higher: Higher 16 bit of watchdog irqvalue. -wdg_ irq_value_low and wdg_ irq_value_high are used together. -It鈥檚 useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. -Default value of watchdog irqvalue is 48鈥0000_h0003_0000, corresponds to 6 seconds, which means reset will occur after irq is 1 for 6 seconds. - - - - high 16 bits of watchdog irq value high 16 bits of watchdog irq value - - wdg_ irq_value_low: Low 16 bit of watchdog irq value. -wdg_ irq_value_high: High 16 bit of watchdog irq value. -wdg_ irq_value_higher: Higher 16 bit of watchdog irq value. -wdg_ irq_value_low, wdg_irq_value_mid and wdg_ irqvalue_high are used together, which means reset will occur after irq is 1 for 6 seconds. -It鈥檚 useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irq value, an interrupt is generated. -Default value of watchdog irqvalue is 48鈥檋0000_0003_0000, corresponds to 6 seconds. - - - - higher 16 bits of watchdog value higher 16 bits of watchdog value - - See wdg_ld_value_low description. - - - - higher 16 bits of watchdog counter value higher 16 bits of watchdog counter value - - See wdg_cnt_low description. - - - - higher 16 bits of watchdog counter value for read higher 16 bits of watchdog counter value for read - - Refer to wdg_cnt_read_low - - - - higher 16 bits of watchdog irq value higher 16 bits of watchdog irq value - - wdg_ irq_value_low: Low 16 bit of watchdog irq value. -wdg_ irq_value_high: High 16 bit of watchdog irq value. -wdg_ irq_value_higher: Higher 16 bit of watchdog irq value. -wdg_ irq_value_low, wdg_irq_value_high and wdg_ irq_value_higher are used together, which means reset will occur after irq is 1 for 6 seconds. -It鈥檚 useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irq value, an interrupt is generated. -Default value of watchdog irqvalue is 48鈥檋0000_0003_0000, corresponds to 6 seconds. - - - - - - - - - - if write 0x454e to enable write psm reg, readback only [15] is high - - - - - psm calibration pre time. The time is from pull DCXO high to OSC 26M stable. unit is (clk_cal_64k_div_th +1)ms - - - psm calibration time 1s/(2^(16-rc_32k_cal_cnt_n))/( rc_32k_cal_cnt_p+1) - - - - - psm 26m calibration value update down threshold. -Value = (1/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) - - - - - psm 26m calibration value update up threshold -Value = (3/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) - - - - - 1'b1: rtc use psm cal 32K clock in 32K less mode,1'b0:rtc use RC 32K clock in 32K less mode - - - enable psm cal - - - clear psm int status - - - enble psm timer cnt - - - posedge to update psm cnt value - - - software reset psm module, auto clear - - - enable psm timer to wake up sys - - - enable psm alarm function - - - enable charger to power on sys - - - enable pbint2 to power on sys - - - enable pbint1 to power on sys - - - enable ext int to power on sys - - - enable rtc power on time out detect - - - enable psm fsm - - - - - The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms - - - The time to disable rtc clk in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms - - - The time to reset rtc in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to power off rtc done in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to release reset in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to power on rtc , unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The time to clock enable in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to release hold ISO in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The time to mark power on timeout in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to power on rtc done , unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The low 16 bits threshold of psm time , unit is 10*(clk_cal_64k_div_th +1)ms - - - - - The high 16 bits threshold of psm time , unit is 10ms - - - - - The low 16 bits threshold of psm alarm time , unit is 10*(clk_cal_64k_div_th +1)ms - - - - - The high 16 bits threshold of psm alarm time - - - - - The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms - - - - - The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms - - - - - 0锛歴el clk_cal_1k锛1锛歴el clk_rc_64k or xtal32k - - - 0锛歞isable 锛1锛歟nable - - - LDO_DCXO discharge en - - - LDO_DCXO short protect EN: -鈥0鈥 is disable -鈥1鈥 is enable(default) - - - LDO_DCXO compensation capacitor and resistor adjust - - - compensation resistor adjust - - - LDO_DCXO current limit threshold adjust , 111~000 380mA~240mA 20mA/step - - - DCXO LDO output voltage select, 000000~111111 1.625V~3.225V 25mV/step - - - - - Psm calibration divider, -1锛墂hen rc_64k calib(clude xtal_32k calib use rc_64k por on first time)锛宨t is calculated with rc_32k_cal_cnt_n 鈥 log2(clk_cal_64k_div_th+1)锛沞.g: I. clk_cal_1k=128Hz, cnt_p=0x4,cnt_n=0x8锛宒iv_th=0xf锛汭I. clk_cal_1k=1KHz, cnt_p=0x4,cnt_n=0x5锛宒iv_th=0x1 -2锛墂hen 32k_xtal calib锛宨t is calculated with rc_32k_cal_cnt_n-log2(clk_cal_64k_div_th+1)-1锛沞.g: I. clk_cal_1k=128Hz, cnt_p=0x4,cnt_n=0x8锛宒iv_th=0x7锛汭I. clk_cal_1k=1KHz, cnt_p=0x4,cnt_n=0x5锛宒iv_th=0x0 -3锛墂hen 32k_xtal no calib, e.g: I. clk_cal_1k=128Hz,div_th=4'hf锛 II. clk_cal_1k=1KHz,div_th=4'h0 - - - psm rc 64K divider, the input RC clock is divider to CLK_64K/( clk_cal_64k_div_th+1) - - - Enable watchdog power on chip by internal RC clock - - - - - - - - - - - - - - - Psm cnt updated low 16 bits value, the step of read this value is : -(1)enable psm_cnt_update, -(2)wait till psm_cnt_update_vld ==1.(psm_fsm_status[6]) - - - - - Psm cnt updated high 16 bits value - - - - - - - - - - - psm cnt updated valid - - - when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when psm_cnt_en==1, then if psm cnt get psm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when pbint2_pwr_en==1, then if pbint2 is low, this bit is high, -When psm_status_clr is high, this bit is low - - - when pbint1_pwr_en==1, then if pbint1 is low, this bit is high, -When psm_status_clr is high, this bit is low - - - when ext_int_en==1, then if ext_int is high, this bit is high, -When psm_status_clr is high, this bit is low - - - - - Only debug use - - - - - We can use this value to calculate the RC 64K clock real frequency. Rc_64k=( clk_cal_64k_div_th+1)*(2^ rc_32k_cal_cnt_p)*26*10^6/ (psm_cal_cnt*2^9) - - - - - PBINT or CHGR_INT dbs time,0.244ms step - - - - - bg pd power on timer,0.244ms step - - - ext rst_n release timer,0.244ms step - - - - - ext xtl0_en~ext_xtl3_en dbs time锛32kHz - - - ext xtl0_en~ext_xtl3_en dbs time锛32kHz - - - - - 0~7:ext_xtl_en0~7 high or low enable to exit psm锛0锛歭ow vld锛1锛歨igh vld - - - - - 0锛歞isable xtal32k clk锛1锛歟nable xtal32k - - - 0:clk_32k_xtal not calibra;1:clk_32k_xtal or rc_64k calibra - - - - - xtl7_flag - - - xtl6_flag - - - xtl5_flag - - - xtl4_flag - - - xtl3_flag - - - xtl2_flag - - - xtl1_flag - - - xtl0_flag - - - 0:xtal_32k por on use xtal_32k,xtal not calibra must configure 0 ;1:xtal_32k por on use rc_64k - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT_MASK_STATUS - - - - - - - - - - INT_RAW_STATUS - - - - - - - - - - INT_EN - - - - - - - - - - - - - - - PIN_ADI_SCLK - - - - - - - - - - - PIN_ADI_D - - - - - - - - - - - PIN_EXT_RST_B - - - - - - - - - - - PIN_ANA_INT - - - - - - - - - - - PIN_CHIP_SELLP - - - - - - - - - - - PIN_CLK_32K - - - - - - - - - - - PIN_PTESTO - - - - - - - - - - - PIN_CLK26M - - - - - - - - - - - EXT_XTL_EN0 - - - - - - - - - - - EXT_XTL_EN1 - - - - - - - - - - - EXT_XTL_EN2 - - - - - - - - - - - EXT_XTL_EN3 - - - - - - - - - - - EXT_XTL_EN4 - - - - - - - - - - - EXT_XTL_EN5 - - - - - - - - - - - EXT_XTL_EN6 - - - - - - - - - - - EXT_XTL_EN7 - - - - - - - - - - - - - - - - CAL_START - - 鏈夊啓鎿嶄綔灏变細缃1 - - - - CAL_CYCLE_P0 - - - - CAL_CYCLE_P1 - - - - - DIV_FAC_UPD_REQ - - 鏈夊啓鎿嶄綔灏变細缃1 - - - - DIV_FAC_P0 - - DIV_FAC_DENOM[31:16] - - - - DIV_FAC_P1 - - DIV_FAC_NUM[31:16] - - - - INT_EN - - [0]:CAL_DONE_INT -[1]:FAC_UPD_DONE_INT - - - - INT_CLR - - [0]:CAL_DONE_INT_CLR -[1]:FAC_UPD_DONE_INT_CLR - - - - - DIV_FAC_P2 - - DIV_FAC_DENOM[15:0] - - - - DIV_FAC_P3 - - DIV_FAC_NUM[15:0] - - - - - - - - - - adi low bits version. - - - adi high bits version,read only. - - - - - addr mode for access. "00" word mode,means addr[x:2],"01" half word,means addr[x:1], "1x" byte mode, means addr[x:0]. - - - configure write bit flag. - - - addr bit number configure, "00" address is 12 bits, "01" address is 10 bits, "10" address is 15 bits. - - - "1" write uses command mode, in this mode, must first configure channel addr, then data. - - - - - write channel 0 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 1 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 2 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 3 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 4 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 5 priority. 0 has lowest priority, 4 has highest priority. - - - - - - "1" write command fifo enable. - - - fifo overfolow interrupt mask. - - - - - fifo overfolow interrupt without mask status. - - - - - fifo overfolow interrupt with mask status. - - - - - fifo overfolow interrupt clear. - - - - - total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len. - - - total adi cmd length = rf_gssi_addr_len + read/write flag. - - - total adi data length . - - - write bit position in frame stream . - - - "1" write means 1, "0" write means 0. - - - "1" hardware auto generate sync, "0" software generates sync. - - - "1" sync is pulse, "0" sync is level. - - - "1" software generates sync. - - - "1" invert output sck. - - - output oen : "1" oen add dummy cycle, "0" oen not add dummy cycle. - - - reserved. - - - "1" output dummy_clock, "0" gate dummy clock. - - - "1" rx sample delay 1 adi clk cycle, "0" delay 0 adi clk cycle. - - - "1" sck always on, "0" audo gate clock. - - - "1" write bit disable, "0" write bit enable. - - - - - "1" tx data at negedge of sck."0" tx data at posedge of sck. - - - "1" rx data at negedge of sck."0" rx data at posedge of sck. - - - F_sck = F_clk/(2*(rf_gssi_clk_div+1)) - - - sync before data transfer - - - sync end data transfer - - - extral dummy sck - - - extral dummy sck - - - start sequence condition, only used in RFFE - - - master turn around to salve length , only used in RFFE - - - slave turn around to master length , only used in RFFE - - - "1" 2 wires enable - - - - - configure read address and start a read operation. - - - - - read data from analog die. - - - read address map to arm_red_cmd[16:2]. - - - 1 means has not been read back. - - - - - "1" write channel is busy - - - "1" read channel is busy - - - "1" adi operation is busy - - - wfifo full status - - - wfifo empty status - - - wfifo fill data number - - - adi fsm status - - - event 0 wr status - - - event 1 wr status - - - event 2 wr status - - - event 3 wr status - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - the address map to the PMIC chip space, just for write operation - - - - - the dat to the PMIC chip space, just for write operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. -
- Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. -
- When non-secure cpu read this register, the return value will automatic exlude the secure channel. -
- 00000 = use Channel0 -
- 00001 = use Channel1 -
- 00010 = use Channel2 -
- ... -
- 01111 = use Channel15 -
- 11111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- all 1 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - This register indicates which channel register can only be accessed by secure master. One bit per - channel, for example: -
- 0000_0000 = All channels registers can be accessed by secure master or non-secure master. -
- 0000_0001 = Ch0 registers can only be accessed by secure master. -
- 0000_0010 = Ch1 registers can only be accessed by secure master. -
- 0000_0100 = Ch2 registers can only be accessed by secure master. -
- 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. -
- ...... -
- all 1 = all channels registers can only be accessed by secure master. - - - - This register indicates aif channel register can only be accessed by secure master. - - - - This register indicates which channel dma is secure master. One bit per - channel, for example: -
- 0000_0000 = All channels dma are non-secure master. -
- 0000_0001 = Ch0 dma is secure master. -
- 0000_0010 = Ch1 dma is secure master. -
- 0000_0100 = Ch2 dma is secure master. -
- 0000_0101 = Ch0 and Ch2 dma are secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. -
- ...... -
- all 1 = all channels dma are secure master. - - - - This register indicates aif channel dma is secure master. - - - This register indicates dbghost channel dma is secure master. - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Exchange the read data from fifo halfword MSB or LSB -
- - - - - Exchange the write data to fifo halfword MSB or LSB -
- - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - Set the MAX burst length for channel 0,1. - This bit field is only used in channel 0~1, for channel 2~6, it is reserved. -
- The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. -
- . - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. - - - - - - - - - - The Channel 0 conveys data from the AIF to the memory. -
- The Channel 1 conveys data from the memory to the AIF. -
- These Channels only exist with Voice Option. - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. - - - - - When 1 the channel is enabled - - - When 1 the fifo is empty - - - Cause interrupt End of FIFO. - - - Cause interrupt Half of FIFO. - - - Cause interrupt Quarter of FIFO. - - - Cause interrupt Three Quarter of FIFO. - - - Cause interrupt ahb error. - - - End of FIFO interrupt status bit. - - - Half of FIFO interrupt status bit. - - - Quarter of FIFO interrupt status bit. - - - Three Quarter of FIFO interrupt status bit. - - - ahb error interrupt status bit. - - - channel busy status bit. - - - - - AHB Start Address. This field represent the start address of the FIFO located in RAM. - - - - - - Fifo size in bytes, max 1MBytes. -
- The size of the fifo must be a multiple of 16 (The four LSB are always zero). - - - - - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - HALF FIFO Mask interrupt. When one this interrupt is enabled. - - - QUARTER FIFO Mask interrupt. When one this interrupt is - enabled. - - - THREE QUARTER FIFO Mask interrupt. When one this interrupt is - enabled. - - - ahb_error Mask interrupt. When one this interrupt is - enabled. - - - - - Write one to clear end of fifo interrupt. - - - Write one to clear half of fifo interrupt. - - - Write one to clear Quarter fifo interrupt. - - - Write one to clear Three Quarter fifo interrupt. - - - Write one to clear ahb_error interrupt. - - - - - Current AHB address value. The nine MSB bit is constant and - equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. -
- Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. -
- When non-secure cpu read this register, the return value will automatic exlude the secure channel. -
- 00000 = use Channel0 -
- 00001 = use Channel1 -
- 00010 = use Channel2 -
- ... -
- 01111 = use Channel15 -
- 11111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- all 1 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - This register indicates which channel register can only be accessed by secure master. One bit per - channel, for example: -
- 0000_0000 = All channels registers can be accessed by secure master or non-secure master. -
- 0000_0001 = Ch0 registers can only be accessed by secure master. -
- 0000_0010 = Ch1 registers can only be accessed by secure master. -
- 0000_0100 = Ch2 registers can only be accessed by secure master. -
- 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. -
- ...... -
- all 1 = all channels registers can only be accessed by secure master. - - - - - This register indicates which channel dma is secure master. One bit per - channel, for example: -
- 0000_0000 = All channels dma are non-secure master. -
- 0000_0001 = Ch0 dma is secure master. -
- 0000_0010 = Ch1 dma is secure master. -
- 0000_0100 = Ch2 dma is secure master. -
- 0000_0101 = Ch0 and Ch2 dma are secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. -
- ...... -
- all 1 = all channels dma are secure master. - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Exchange the read data from fifo halfword MSB or LSB -
- - - - - Exchange the write data to fifo halfword MSB or LSB -
- - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - Set the MAX burst length for channel 0,1. - This bit field is only used in channel 0~1, for channel 2~6, it is reserved. -
- The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. -
- . - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. - - - - - - - - - - - general used register security visit enable -0:security -1:unsecurity - - - response error stop function enable -0:enable -1:disable - - - the number of outstanding that can be send out -0: 2 -1: 3 -2: 4 - - - multe-channel transport priority mode control -0: there is no priority in the channels, using polling to DMA data -1: smaller channel number has high-priority.high-priority move data before low-priority channels - - - interrupt control bit -0: no interruption occurs when all logical channels finish -1: interruption occurs when all logical channels finish - - - the control bit of logical channel transport finish -0: don't stop all the channel,or automatically clear after setting -1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared - - - - - in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. - - - - - stop status -0: not finish -1: finish - - - the channel number of the final transmission -0000: channel 0 just finished the transmission -0001: channel 1 just finished the transmission -0010: channel 2 just finished the transmission -...... -1011: channel 11 just finished the transmission -others: nonentity - - - - - logic channel stop interrupt status - - - channel 11 interrupts state -0: the channel 11 has not been interrupted, or the interrupt bit has been cleared -1: channel 11 is interrupted - - - channel 10 interrupts state -0: the channel 10 has not been interrupted, or the interrupt bit has been cleared -1: channel 10 is interrupted - - - channel 9 interrupts state -0: the channel 9 has not been interrupted, or the interrupt bit has been cleared -1: channel 9 is interrupted - - - channel 8 interrupts state -0: the channel 8 has not been interrupted, or the interrupt bit has been cleared -1: channel 8 is interrupted - - - channel 7 interrupts state -0: the channel 7 has not been interrupted, or the interrupt bit has been cleared -1: channel 7 is interrupted - - - channel 6 interrupts state -0: the channel 6 has not been interrupted, or the interrupt bit has been cleared -1: channel 6 is interrupted - - - channel 5 interrupts state -0: the channel 5 has not been interrupted, or the interrupt bit has been cleared -1: channel 5 is interrupted - - - channel 4 interrupts state -0: the channel 4 has not been interrupted, or the interrupt bit has been cleared -1: channel 4 is interrupted - - - channel 3 interrupts state -0: the channel 3 has not been interrupted, or the interrupt bit has been cleared -1: channel 3 is interrupted - - - channel 2 interrupts state -0: the channel 2 has not been interrupted, or the interrupt bit has been cleared -1: channel 2 is interrupted - - - channel 1 interrupts state -0: the channel 1 has not been interrupted, or the interrupt bit has been cleared -1: channel 1 is interrupted - - - channel 0 interrupts state -0: the channel 0 has not been interrupted, or the interrupt bit has been cleared -1: channel 0 is interrupted - - - - - state of IRQ 23 generate requests of moving data -0: IRQ 23 does not generate requests of moving data -1: IRQ 23 generate requests of moving data - - - state of IRQ 22 generate requests of moving data -0: IRQ 22 does not generate requests of moving data -1: IRQ 22 generate requests of moving data - - - state of IRQ 21 generate requests of moving data -0: IRQ 21 does not generate requests of moving data -1: IRQ 21 generate requests of moving data - - - state of IRQ 20 generate requests of moving data -0: IRQ 20 does not generate requests of moving data -1: IRQ 20 generate requests of moving data - - - state of IRQ 19 generate requests of moving data -0: IRQ 19 does not generate requests of moving data -1: IRQ 19 generate requests of moving data - - - state of IRQ 18 generate requests of moving data -0: IRQ 18 does not generate requests of moving data -1: IRQ 18 generate requests of moving data - - - state of IRQ 17 generate requests of moving data -0: IRQ 17 does not generate requests of moving data -1: IRQ 17 generate requests of moving data - - - state of IRQ 16 generate requests of moving data -0: IRQ 16 does not generate requests of moving data -1: IRQ 16 generate requests of moving data - - - state of IRQ 15 generate requests of moving data -0: IRQ 15 does not generate requests of moving data -1: IRQ 15 generate requests of moving data - - - state of IRQ 14 generate requests of moving data -0: IRQ 14 does not generate requests of moving data -1: IRQ 14 generate requests of moving data - - - state of IRQ 13 generate requests of moving data -0: IRQ 13 does not generate requests of moving data -1: IRQ 13 generate requests of moving data - - - state of IRQ 12 generate requests of moving data -0: IRQ 12 does not generate requests of moving data -1: IRQ 12 generate requests of moving data - - - state of IRQ 11 generate requests of moving data -0: IRQ 11 does not generate requests of moving data -1: IRQ 11 generate requests of moving data - - - state of IRQ 10 generate requests of moving data -0: IRQ 10 does not generate requests of moving data -1: IRQ 10 generate requests of moving data - - - state of IRQ 9 generate requests of moving data -0: IRQ 9 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 8 generate requests of moving data -0: IRQ 8 does not generate requests of moving data -1: IRQ 8 generate requests of moving data - - - state of IRQ 7 generate requests of moving data -0: IRQ 7 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 6 generate requests of moving data -0: IRQ 6 does not generate requests of moving data -1: IRQ 6 generate requests of moving data - - - state of IRQ 5 generate requests of moving data -0: IRQ 5 does not generate requests of moving data -1: IRQ 5 generate requests of moving data - - - state of IRQ 4 generate requests of moving data -0: IRQ 4 does not generate requests of moving data -1: IRQ 4 generate requests of moving data - - - state of IRQ 3 generate requests of moving data -0: IRQ 3 does not generate requests of moving data -1: IRQ 3 generate requests of moving data - - - state of IRQ 2 generate requests of moving data -0: IRQ 2 does not generate requests of moving data -1: IRQ 2 generate requests of moving data - - - state of IRQ 1 generate requests of moving data -0: IRQ 1 does not generate requests of moving data -1: IRQ 1 generate requests of moving data - - - state of IRQ 0 generate requests of moving data -0: IRQ 0 does not generate requests of moving data -1: IRQ 0 generate requests of moving data - - - - - state of ACK 23 generate requests of moving data -0: ACK 23 does not generate requests of moving data -1: ACK 23 generate requests of moving data - - - state of ACK 22 generate requests of moving data -0: ACK 22 does not generate requests of moving data -1: ACK 22 generate requests of moving data - - - state of ACK 21 generate requests of moving data -0: ACK 21 does not generate requests of moving data -1: ACK 21 generate requests of moving data - - - state of ACK 20 generate requests of moving data -0: ACK 20 does not generate requests of moving data -1: ACK 20 generate requests of moving data - - - state of ACK 19 generate requests of moving data -0: ACK 19 does not generate requests of moving data -1: ACK 19 generate requests of moving data - - - state of ACK 18 generate requests of moving data -0: ACK 18 does not generate requests of moving data -1: ACK 18 generate requests of moving data - - - state of ACK 17 generate requests of moving data -0: ACK 17 does not generate requests of moving data -1: ACK 17 generate requests of moving data - - - state of ACK 16 generate requests of moving data -0: ACK 16 does not generate requests of moving data -1: ACK 16 generate requests of moving data - - - state of ACK 15 generate requests of moving data -0: ACK 15 does not generate requests of moving data -1: ACK 15 generate requests of moving data - - - state of ACK 14 generate requests of moving data -0: ACK 14 does not generate requests of moving data -1: ACK 14 generate requests of moving data - - - state of ACK 13 generate requests of moving data -0: ACK 13 does not generate requests of moving data -1: ACK 13 generate requests of moving data - - - state of ACK 12 generate requests of moving data -0: ACK 12 does not generate requests of moving data -1: ACK 12 generate requests of moving data - - - state of ACK 11 generate requests of moving data -0: ACK 11 does not generate requests of moving data -1: ACK 11 generate requests of moving data - - - state of ACK 10 generate requests of moving data -0: ACK 10 does not generate requests of moving data -1: ACK 10 generate requests of moving data - - - state of ACK 9 generate requests of moving data -0: ACK 9 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 8 generate requests of moving data -0: ACK 8 does not generate requests of moving data -1: ACK 8 generate requests of moving data - - - state of ACK 7 generate requests of moving data -0: ACK 7 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 6 generate requests of moving data -0: ACK 6 does not generate requests of moving data -1: ACK 6 generate requests of moving data - - - state of ACK 5 generate requests of moving data -0: ACK 5 does not generate requests of moving data -1: ACK 5 generate requests of moving data - - - state of ACK 4 generate requests of moving data -0: ACK 4 does not generate requests of moving data -1: ACK 4 generate requests of moving data - - - state of ACK 3 generate requests of moving data -0: ACK 3 does not generate requests of moving data -1: ACK 3 generate requests of moving data - - - state of ACK 2 generate requests of moving data -0: ACK 2 does not generate requests of moving data -1: ACK 2 generate requests of moving data - - - state of ACK 1 generate requests of moving data -0: ACK 1 does not generate requests of moving data -1: ACK 1 generate requests of moving data - - - state of ACK 0 generate requests of moving data -0: ACK 0 does not generate requests of moving data -1: ACK 0 generate requests of moving data - - - - - - channel 11 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 10 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 9 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 8 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 7 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 6 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 5 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 4 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 3 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 2 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 1 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 0 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - the source addr of this channel - - - the destination addr of this channel - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - first addr of the structural body - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - - - - - - - - - - - - - - [9:8]=='b00: select adc input data ; - [9:8]=='b01: select dac output loop data ; - [9:8]=='b1x: force to zero ; - - - [6]==0: fm input to aif1; [6]=1: audio codec input to aif1; - [7]==0: fm input to aif2; [7]=1: audio codec input to aif2; - - - [5:4]=='bx1: aif1 output to audio codec ; - [5:4]=='b10: aif2 output to audio codec ; - [5:4]=='b00: zero output to audio codec ; - - - ==1: enable adc left channel; - - - ==1: enable dac right channel; - - - ==1: enable adc left channel; - - - ==1: enable adc right channel; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ==1: enable mute; - - - ==1: enable soft mute; - - - dac mute counter1 threshold, step is countrolled by counter 0; - - - dac mute counter0 threshold - - - dac fs frequency - 0:96K - 1:48K - 2:44.1K - 3:32K - 4:24K - 5:22.05K - 6:16K - 7:12K - 8:11.025K - 9:9.6K - 10:8K - - - - - - - - - - - - - - - - - - - - - - - - - adc src upsample tap, sample rate=N*4K - - - - - - - - - - - - - ==1: enable audio adc parallel data loop to dac parallel data path; - - - - - - - - - - - - - - - - - - - - - - - - - - - ==0: force to 0 to select 26m audio clock; - - - - - - - ==1: invert output mclk ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - left adc channel dgain - 4'hf: 16dB - 4'he: 14dB - 4'hd: 12dB - 4'hc: 10dB - 4'hb: 8dB - 4'ha: 6dB - 4'h9: 4dB - 4'h8: 2dB - 4'h7: 0dB - 4'h6:-2dB - 4'h5:-4dB - 4'h4:-6dB - 4'h3:-8dB - 4'h2:-10dB - 4'h1:-12dB - 4'h0:mute - - - right adc channel dgain - 4'hf: 16dB - 4'he: 14dB - 4'hd: 12dB - 4'hc: 10dB - 4'hb: 8dB - 4'ha: 6dB - 4'h9: 4dB - 4'h8: 2dB - 4'h7: 0dB - 4'h6:-2dB - 4'h5:-4dB - 4'h4:-6dB - 4'h3:-8dB - 4'h2:-10dB - 4'h1:-12dB - 4'h0:mute - - - - - - - right adc channel dgain - 1:sel tone dac tone dgain - 0:sel normal dac dgain - - - - - - - left dac channel dgain - [5:1] = - 5'h1f: 05dB - 5'h1e: 04dB - 5'h1d: 03dB - 5'h1c: 02dB - 5'h1b: 01dB - 5'h1a: 00dB - 5'h19: -01dB - 5'h18: -02dB - 5'h17: -03dB - 5'h16: -04dB - 5'h15: -05dB - 5'h14: -06dB - 5'h13: -07dB - 5'h12: -08dB - 5'h11: -09dB - 5'h10: -10dB - 5'h0f: -11dB - 5'h0e: -12dB - 5'h0d: -13dB - 5'h0c: -14dB - 5'h0b: -15dB - 5'h0a: -16dB - 5'h09: -17dB - 5'h08: -18dB - 5'h07: -19dB - 5'h06: -20dB - 5'h05: -21dB - 5'h04: -22dB - 5'h03: -23dB - 5'h02: -24dB - 5'h01: -25dB - 5'h00: -26dB - [0]:1'b1,+0.5dB - [7]:1'b1,+12dB - [6]:1'b1,+6dB - - - right dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - - - left dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - right dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - - - - - - - - - - - - Enable camera controller,high active. - - - Enable camera controller,high active. - - - - - - - - - - - "0" = RGB565. -
- "1" = YUV422. -
- "2" = Compressed Data. -
- "3" = Reserved. - - - - - - - - - - '0' = keep output camera reset polarity. -
- '1' = invert output camera reset polarity. - - - - - - - - '0' = keep output camera power down polarity. -
- '1' = invert output camera power down polarity. - - - - - - - - '0' = keep input VSYNC polarity. -
- '1' = invert input VSYNC polarity. - - - - - - - - '0' = keep input HREF polarity so data is sampled when HREF high. -
- '1' = invert input HREF polarity so data is sampled when HREF low. - - - - - - - - '0' = keep pix clk polarity. -
- '1' = invert pix clk polarity. - - - - - - - - '0' = VSYNC irq always exists when Frame decimation is enabled. -
- '1' = VSYNC irq will drop when Frame data are dropped in decipation. - - - - - - - - "0"= All frame data will be sent. -
- "1"= only one frame out of two (1/2) will be sent. -
- "2"= only one frame out of three (1/3) will be sent. -
- "3"= only one frame out of four (1/4) will be sent. - - - - - - - - "0"= Pixel Decimation Disabled. -
- "1"= Pixel Decimation 1/2. -
- "2"= Pixel Decimation 1/3. -
- "3"= Pixel Decimation 1/4. - - - - - - - - "0"= line Decimation Disabled. -
- "1"= line Decimation 1/2. -
- "2"= line Decimation 1/3. -
- "3"= line Decimation 1/4. - - - - - Controls the Re-ordering of the FIFO data. -
- In following table, for input data, right comes before left. So YUYV means V comes first. -
- for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word. -
-
- If Bit 26 is '1', byte2 and byte0 is Y. -
- If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange. -
- If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26). -
-
- input YUYV, output YUYV: "000" -
- input YVYU, output YUYV: "001" -
- input UYVY, output YUYV: "110" -
- input VYUY, output YUYV: "111" -
-
- input YUYV, output UYVY: "010" -
- input YVYU, output UYVY: "011" -
- input UYVY, output UYVY: "100" -
- input VYUY, output UYVY: "101" -
-
- input YUYV, output YVYU: "001" -
- input YVYU, output YVYU: "000" -
- input UYVY, output YVYU: "111" -
- input VYUY, output YVYU: "110" -
-
- input YUYV, output VYUY: "011" -
- input YVYU, output VYUY: "010" -
- input UYVY, output VYUY: "101" -
- input VYUY, output VYUY: "100" -
-
- Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation. - This reorder is corrected using Bit 26 infomation. - - - - - - - - "0"= Cropping Disabled. -
- "1"= Cropping Enabled. -
- Note: this bit should set to '0' when bit field "DataFormat" is "10" (compressed data) - - - - - - - In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled. - - - - - - Debug only. A RGB565 test card is sent to system bus instead of real data from sensor. - - - - - - '1' = FIFO over-write IRQ status. -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = VSYNC rising edge IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = VSYNC falling edge IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = DMA Done IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - '1' = FIFO Empty status, not clear-able. - - - - - - Read in the receive FIFO - - - - '1' = FIFO over-write enable - - - '1' = VSYNC rising edge enable - - - '1' = VSYNC falling edge enable - - - '1' = DMA Done enable - - - - - Write '1' to clear FIFO over-write interrupt - - - Write '1' to clear VSYNC rising edge interrupt - - - Write '1' to clear VSYNC falling edge interrupt - - - Write '1' to clear DMA Done interrupt - - - - - '1' = FIFO over-write cause - - - '1' = VSYNC rising edge cause - - - '1' = VSYNC falling edge cause - - - '1' = DMA Done cause - - - - - Power down pin of CMOS sensor . - - - - Reset pin of CMOS sensor. -
- Active Low. - - - - For the software to clear FIFO. This bit is auto-reset to 0. - - - - - Power down pin of CMOS sensor . - - - Reset pin of CMOS sensor. - - - - - start pixel of cropped window. - - - end pixel of cropped window. - - - - - start line of cropped window. - - - end line of cropped window. - - - - - - - swap camera data output [15:0],[31:16]. - - - - - - - - - spi slave enable. - - - spi master enable. - - - yuv out format. - 3'b000: data_serial_mux = {Y0,U0,Y1,V0}; - 3'b001: data_serial_mux = {Y0,V0,Y1,U0}; - 3'b010: data_serial_mux = {U0,Y0,V0,Y1}; - 3'b011: data_serial_mux = {U0,Y1,V0,Y0}; - 3'b100: data_serial_mux = {V0,Y1,U0,Y0}; - 3'b101: data_serial_mux = {V0,Y0,U0,Y1}; - 3'b110: data_serial_mux = {Y1,V0,Y0,U0}; - 3'b111: data_serial_mux = {Y1,U0,Y0,V0}; - - - overflow rstn only vsync low. - - - overflow_observe_only_vsync_low. - - - overflow_rstn enable - - - big_end_dis - - - overflow inv control - - - href inv control - - - vsync inv control - - - block_num_per_line[9:0] pixels num of a line - - - line_num_per_frame[9:0] lines num of a frame - - - - - camera_clk_div_num - - - cts_spi_master_reg - - - ssn_cm inv control - - - sck_cm inv control - - - ssn_spi_oen select, 1:from reg 0: from logic - - - ssn_spi_oenb reg - - - sck_spi_oenb select, 1:from reg 0:from logic - - - sck_spi_oenb reg - - - sdo_spi_swap reg,swap camera_spi_0 and camera_spi_1 - - - clk inv control - - - sck double edge enable - - - - - ssn_wait_length[7:0] - - - init_wait_length[7:0] - - - word_num_per_block[7:0] - - - ssn_cs_delay[1:0] - - - data_receive_choose_bit[1:0] - - - ready_cs_inv - - - ssn_cs_inv - - - eco_bypass_isp - - -line_wait_length[15:0] - - - line_wait_length - - - block_wait_length[7:0] - - - ssn_high_length[7:0] - - - - - camera_spi_master no ssn mode enable - - - sdo_line_choose_bit[1:0] 0:1 line 1: 2lines 2:4lines - - - data_size_choose_bit 1: from reg 0:from logic - - - image_height_choose_bit 1: from reg 0:from logic - - - image_width_choose_bit 1: from reg 0:from logic - - - block_num_per_packet[9:0] - - - 0: spi data0 delay 0 - 1: spi data0 delay 2 cycles spi_cam_clk - 2: spi data0 delay 3 cycles spi_cam_clk - 3: spi data0 delay 4 cycles spi_cam_clk - - - 0: spi data1 delay 0 - 1: spi data1 delay 2 cycles spi_cam_clk - 2: spi data1 delay 3 cycles spi_cam_clk - 3: spi data1 delay 4 cycles spi_cam_clk - - - - - sync code - - - - - packet_id_data_start - - - packet_id_line_start - - - packet_id_frame_end - - - packet_id_frame_start - - - - - line_id[15:0] - - - data_id[7:0] - - - observe_data_size_wrong - - - observe_image_height_wrong - - - observe_image_width_wrong - - - observe_line_num_wrong - - - observe_data_id_wrong - - - - - image_height[15:0] - - - image_width[15:0] - - - - - num_d_term_en[7:0] term time reg - - - cur_frame_line_num[12:0] - - - data_lp_in_choose_bit[1:0] - - - clk_lp inv - - - trail_data_wrong_choose_bit 1:secelt trail1 0:select trail0 - - - sync_bypass - - - rdata_bit_inv en - - - hs_sync_find en - - - line_packet_enable - - - ecc_bypass - - - data_lane_choose_bit 1:select lane2 0:select lane1 - - - csi_module_enable - - - - - num_hs_settle[7:0] set hs settle time - - - lp_data_length_choose_bit[2:0] set data length - - - data_clk_lp_posedge_choose[2:0] select delay cycles - - - clk_lp_ck_inv - - - rclr_mask_en - - - rinc_mask_en - - - hs_enable_mask_en - - - den_csi_inv_bit - - - hsync_csi_inv_bit - - - vsync_csi_inv_bit - - - hs_data2_enable_reg - - - hs_data1_enable_reg - - - hs_data1_enable_choose_bit - - - hs_data1_enable_dr 1:select reg 0:select logic - - - data2_terminal_enable_reg - - - data1_terminal_enable_reg - - - data1_terminal_enable_dr 1:select reg 0:select logic - - - lp_data_interrupt_clr, clear flag - - - lp_cmd_interrupt_clr, clear flag - - - lp_data_clr, clear data out - - - lp_cmd_clr, clear cmd out - - - - - num_hs_settle_clk[15:0], set hs settle counter - - - num_c_term_en[15:0],set clk term counter - - - - - clk_lp_in_choose_bit - - - pu_lprx_reg - - - pu_hsrx_reg - - - pu_dr, 1:select reg 0:select logic - - - data_pnsw_reg - - - hs_clk_enable_reg - - - hs_clk_enable_choose_bit - - - hs_clk_enable_dr 1:select reg 0:select logic - - - clk_terminal_enable_reg - - - clk_terminal_enable_dr 1:select reg 0:select logic - - - observe_reg_5_low8_choose - - - ecc_error_flag_reg - - - ecc_error_dr - - - csi_channel_sel - - - two_lane_bit_reverse, reverse high and low 8bit - - - data2_lane_bit_reverse 1:select revert data - - - data1_lane_bit_reverse 1:select revert data - - - data2_hs_no_mask 1:data only valid when sync assert - - - data1_hs_no_mask 1:data only valid when sync assert - - - pu_lprx_d2_reg - - - pu_lprx_d1_reg - - - clk_edge_sel - - - clk_x2_sel - - - single_data_lane_en 1:1lane 0:2lanes - - - - - num_hs_clk_useful[30:0] hs clk useful counter - - - num_hs_clk_useful_en - - - - - vc_id_set[1:0] - - - data_lp_inv - - - fifo_rclr_8809p_reg - - - fifo_wclr_8809p_reg - - - hs_sync_16bit_8809p_mode - - - d_term_small_8809p_en - - - data_line_inv_8809p_en - - - hs_enable_8809p_mode - - - sp_to_trail_8809p_en - - - trail_wrong_8809p_bypass - - - rinc_trail_8809p_bypass - - - hs_data_enable_8809p_mode - - - hs_clk_enable_8809p_mode - - - data_type_re_check_en - - - sync_id_reg - - - sync_id_dr - - - csi_observe_choose_bit - - - crc_error_flag_reg - - - crc_error_flag_dr 1:select reg 0:select logic - - - csi_rinc_new_mode_dis - - - - - data_type_dp_reg[5:0], set data type - - - data_type_le_reg line end type - - - data_type_ls_reg line start type - - - data_type_fe_reg frame end type - - - data_type_fs_reg frame start type - - - 1: only support raw8 0:support more type - - - 1:select reg value - - - - - data_lane_16bits_mode - - - terminal_2_hs_exchage_8809p - - - terminal_1_hs_exchage_8809p - - - data2_terminal_enable_8809p_dr - - - hs_data2_enable_8809p_dr - - - csi_dout_test_8809p_en - - - csi_dout_test_8809p[7:0] - - - num_d_term_en[15:8] - - - num_hs_settle[15:8] - - - - - hs_data_state[13:0] - - - phy_data_state[14:0] - - - fifo_wfull_almost - - - fifo_wfull - - - fifo_wempty - - - - - if observe_reg_5_low8_choose=1, out is data_id[7:0], else out is lp_cmd_out[7:0] - - - lp_data_interrupt_flag - - - lp_data_interrupt_flag - - - phy_clk_state[8:0] - - - fifo_rcount[8:0] - - - crc_error - - - err_ecc_corrected_flag - - - err_data_corrected_flag - - - err_data_zero_flag - - - - if observe_reg_5_low8_choose=1, out is csi_observe_mon, else out is lp_data_out[63:32] - - - csi_observe_reg_7[31:0] - - - - csi_enable - - - - - dly_sel_clkn_reg,set clkn delay,to csi analog phy - - - dly_sel_clkp_reg,set clkp delay,to csi analog phy - - - dly_sel_data2_reg,set data2 delay,to csi analog phy - - - dly_sel_data1_reg,set data1 delay,to csi analog phy - - - vth_sel,to csi analog phy - - - - - - Direct FIFO Ram Access. They are enabled only in Bist Mode. - - - - - - rstn of dsp - - - - - - for A ctd block, u2.7 format - awb_x1_min[8:0]=[awb_ctd_msb[0],awb_x1_min[7:0]] - - - - - for A ctd block, u2.7 format - awb_x1_max[8:0]=[awb_ctd_msb[1],awb_x1_max[7:0]] - - - - - for A ctd block, u1.7 format - - - - - for A ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for D65 ctd block, u1.7 format - - - - - for D65 ctd block, u1.7 format - - - - - for D65 ctd block, u2.7 format - awb_y5_min[8:0]=[awb_ctd_msb[2],awb_y5_min[7:0]] - - - - - for D65 ctd block, u2.7 format - awb_y5_max[8:0]=[awb_ctd_msb[3],awb_y5_max[7:0]] - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - awb_x1_min[8:0]=[awb_x1_min_msb,awb_x1_min[7:0]] - - - awb_x1_max[8:0]=[awb_x1_max_msb,awb_x1_max[7:0]] - - - awb_y5_min[8:0]=[awb_y5_min_msb,awb_y5_min[7:0]] - - - awb_y5_max[8:0]=[awb_y5_max_msb,awb_y5_max[7:0]] - - - 2d0: awb_adj_sig=1 - 2d1: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 or cbsum_abs>vld_cnt_cb_thr x2 - 2d2: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x3 or cbsum_abs>vld_cnt_cb_thr x3 - 2d3: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 and cbsum_abs>vld_cnt_cb_thr x2 - - - 2d3: awb_ratio_lmax=4 - 2d2: awb_ratio_lmax=2 - 2d1: awb_ratio_lmax=0 - 2d0: awb_ratio_lmax= according to the proportion of cnt_max and cnt_lmax - - - - - - - - - - - - - - - vsync_end_reg=[vsync_end_high,vsync_end_low] - - - - - vsync_end_reg=[vsync_end_high,vsync_end_low] - - - - - line_num = [line_numH,line_numL] - - - - - pix_num = [pix_numH,pix_numL] - - - - - - - - not used here - - - - - - not used here - - - - - - - - - - - - - - - - - - - 00:YUV/RAW8(para) - 01:RAW8(mipi) - 10:RAW10(mipi) - - - - - - - - - - - - - - - - - - line_cnt=[line_cnt_H[1:0], [7:0]] - - - - - line_cnt=[line_cnt_H[1:0], line_cnt_L] - - - - - - - - - - - - - - - - - - - 1: kl 0: kldci () - - - 1: kl 0: kldci - - - 1: ku 0: kudci () - - - 1: ku 0: kudci - - - hist 2 - - - 00: 0x98regae_dark_hist_reg - 01: 0x98regyave_target_RO_reg - other: 0x98regyave_contr_reg - - - - - kl_ofstx1[4:0] = [kl_ofstx1, 1b0] (kl0x80) - - - ku_ofstx1[4:0] = [ku_ofstx1, 1b0] (kl0x80) - - - - - dk_histx1[4:0] = [dk_histx1, 1b0] (dhist) - - - br_histx1[4:0] = [br_histx1, 1b0] (bhist) - - - - - swaeswexp/gainnexphw// - - - sw/hwae,SWae, - - - - - THR_dark[4:0] = [THR_dark, 1'b0] (ytarget-yave THR_darkae) - - - THR_bright[4:0] = [THR_bright,1'b0](yave-ytargetTHR_brightae) - - - - - ytarget_dec - 2d3:4indexytargetregd[3:0]8index08 - 2d2:2indexytargetregd[3:0]8index016 - 2d1:1indexytargetregd[3:0]8index032 - 2d0:1indexytargetregd[3:0]8index064 - - - ytarget_dec - 2d3:4indexytargetregc[7:4]8index_max8 - 2d2:2indexytargetregc[7:4]8index_max16 - 2d1:1indexytargetregd[7:4]8index_max32 - 2d0:1indexytargetregd[7:4]8index_max64 - - - 1yave_diff_2frame - - - 1THR_big - - - 1bhist>0@is_dark - - - 1index_ofst - - - - - @nexp - - - @nexp - - - - - low_th = [[0], lsc_blc_gain_th[7:6]](nexp=low_th) - - - nexp>(8+high_th) - - - Fixed Ythr of contr = [[7:4], 4d0] - - - - - - - - 1: dynamic yave (Yave) - 0: fixed ythr contr_ythr_reg - - - YaveYthrofst (01) - - - - - upper@Low gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@Low gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - upper@Mid gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@Mid gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - upper@High gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@High gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - @Low gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - @Mid gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - @High gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - Cb@Low gain0x80 just x1.0 - - - - - Cr@Low gain0x80 just x1.0 - - - - - Cb@Mid gain0x80 just x1.0 - - - - - Cr@Mid gain0x80 just x1.0 - - - - - Cb@High gain0x80 just x1.0 - - - - - Cr@High gain0x80 just x1.0 - - - - - @luma/contr/satur(nexp=low_th) - - - not used here - - - @luma/contr/satur(nexp>(8+high_th)) - - - - - 4'd0: cc_type = 0; //D65 - 4'd1: cc_type = 1; //U30 - 4'd2:if(is_outdoor) cc_type = 0; - else cc_type = 1; - 4'd3:if(ana_gain>=cc_gain_th) cc_type = 0; - else cc_type = 1; - 4'd4:if(rgain_bigger) cc_type = 0; //D65 - else if(bgain_bigger) cc_type = 1; //U30 - 4'd5: if(is_outdoor) cc_type = 0; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd6: if(is_outdoor) cc_type = 0; - else if(ana_gain=cc_gain_th) cc_type = 0; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd7: if(is_outdoor) cc_type = 0; - else if(ana_gain=cc_gain_th) cc_type = 1; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd8: if(r_awb_gain_outr_low_non_A)cc_type = 1; - else if(r_awb_gain_out(r_low_non_A+8)) cc_type = 0; - 4d9: if(awb_idx_max2) cc_type = 1; - else if(awb_idx_max2) cc_type = 0; - other: SW driven ( reg1c2) - - - nexp>(8+high_th) - - - 1: 0: - - - - - r_big_th=[awb_cc_type_th_reg[3:0], 2d0] - - - b_big_th=[awb_cc_type_th_reg[7:4], 2d0] - - - - - 00: YUV422 01: RGB565 - 10: raw bayer 11: clip out - - - 00:YUYV 01:YVYU - 10:UYVY 11:VYUY - (Note:[2] uv_sel 0:UV 1:VU) - - - - - - - - - - - - - - - - - - - - - - - - Case(rgb_mode_reg) @clip out - 3'd0: to_n_clp_data 3'd1: y_data - 3'd2: cnr_1d_cb 3'd3: cnr_1d_cr - 3'd4: c_data 3'd5: yc2r_data - 3'd6: yc2g_data 3'd7: yc2b_data - Note:rgb_mode_reg[0] is also used to - 1, select the line of sub_YUV output - - - not used, sca_reg=1:sub mode - - - bypass vsync_in and hsync_in - - - - - - - - - - - Line_num=[lin_num_l_reg[5:0], 3d0] - - - - - Pix_num=[pix_num_l_reg[6:0], 3d0] - - - - - - - - HsyncNvsync - - - Mvsync - top_dummy>16, vtop_dummy=top_dummy-[7:4] - - - - - 1blc[ku, kl] - - - 1:nexp[3:0] 0:mono_color - - - 1: dpc_out 0: bayer_data - - - - - - 1: enable 0: disable - y_gamma_en = is_outdoor ? scg_reg[5] : scg_reg[4] - - - 1: SDI 0: BT.601 - - - 1: [ae_ok, nexp_sel[1:0], awb_ok, exp[11:8]] - 0: [ae_ok, 1b0, nexp_sel[1:0], awb_ok, exp[10:8]] - labview - - - - - (0x00)0 (0x00)0 (0x00)0 - - - - - (0x13)19 (0x10)16 (0x08)8 - - - - - (0x20)32 (0x1c)28 (0x10)16 - - - - - (0x36)54 (0x30)48 (0x20)32 - - - - - (0x49)73 (0x43)67 (0x30)48 - - - - - (0x5a)90 (0x54)84 (0x40)64 - - - - - (0x6b)107 (0x65)101 (0x50)80 - - - - - (0x7b)123 (0x75)117 (0x60)96 - - - - - RW(0x98)152 (0x93)147 (0x80)128 - - - - - (0xb4)180 (0xb0)176 (0xa0)160 - - - - - (0xce)206 (0xcb)203 (0xc0)192 - - - - - (0xe7)231 (0xe6)230 (0xe0)224 - - - - - 0.75 0.8 1.0 - - - - - r_gain_manual 2.6 format - - - - - g_gain_manual 2.6 format - - - - - b_gain_manual 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - - - - also update cc_type,gamma_type,is_outdoor - - - - - - - - 00: AWB - 01: AWB - 10: yaveAWB - 11: nexpAWB - - - - - - - - - - - - 1: mon ae index 0:mon awb_debug - - - - - 0yave 1yave - 2yave 3yave - - - 07/0f/17/1f Yave - - - 00: y2ave x1.0 01: y2ave x1.5 - 10: y3ave x1.0 11: y3ave x1.5 - - - 1:plus bh 0: only yave - - - 1:plus bh 0: only ywave - - - - - - - - - - - - - - - - - - - - - - pcnt_left =[ae_win_start_reg[3:0] ,1'd0] - - - lcnt_top =[ae_win_start_reg[7:4] ,1'd0] - - - - - ae(yave) win_width = [ae_win_width[7:0], 2'd0] - - - - - ae(yave) ae_win_height = [ae_win_height[7:0], 1'd0] - - - - - exp[7:0](ae_enMCUexp_init[6:0]indexae) - - - - - exp[11:8] - - - - - 10msexp - - - - - (ytarget) - THR_dark(reg41) - THR22index1 - THR24index2 - THR26index4+ofst0 - THR28index8+ofst1 - index16 - - - (ytarget) - THR_bright(reg41) - THR22index1 - THR24index2 - THR26index4+ofst0 - THR28index8+ofst1 - index16 - - - - - - - - Bh = Bh_mean * bh_factor /8 - bh_factor = is_outdoor? bh_factor_outdoor : bh_factor_indoor - - - 00: curr frame 01: 2 frame ave - 10: 3 frame ave 11: 4 frame ave - - - - - awb_mon_out[7:0][cbsum_abs_eq, crsum_abs_eq]SWAWB - - - 2.0xr/b - - - 4.0xr/b - - - 0: 1frame or 2frame - - - - - - - - - - - [ 2] 0:readback blc 1: readback awb - [1:0] 0: crsum_abs 1:cbsum_abs - 2: vld_cnt 3:awb_idx_lmax and max - - - AWB - - - 3'd0:awb_vld=vld_max||(vld_lmax and awb_ratio_lmax); - 3'd1: awb_vld = awb_vld1; - 3'd2: awb_vld = awb_vld2; - 3'd3: awb_vld = awb_vld3; - 3'd4: awb_vld = awb_vld4; - 3'd5: awb_vld = awb_vld5; - 3'd6: awb_vld =!skin_vld; - 3'd7: awb_vld = awb_vld1|awb_vld2|awb_vld3| awb_vld4 | awb_vld5; - - - - - - - - Y Y_maxAWB - - - - - Levelawb_stop - - - Levelawb_stop - - - Levelawb_stop - - - Levelawb_stop - - - - - [7:0]awb_algo_thr - Y > cr_abs+cb_abs+awb_algo_reg - // - - - - - - - - - - - - - - - - - 0: (vld_cntawb_vld_thr) - 1: (vld_cntawb_vld_thr)and(crsum_absawb_vld_thr)and(cbsum_absawb_vld_thr) - - - 0: awb_stopcb/cr - 1: - - - 0: use CTD block to detect skin - 1: use cb,cr to detect skin - - - 0: cb+cr - 1: cb/cr - - - - - awb_vld_thr = [awb_ctrl4[7:0], 4'hf] - - - - - - - - - - 1: 0 - - - - - - - - - y_low_thr = [1h0, y_thr_reg[7:3], 2'h0] - y_high_thr = ~y_low_thr - - - - - - - - - - Only for awb_adj, yaveAWB - y_low_limit = y_ave_target - [y_lmt_offset_reg[2:0],4'd0] - - - not used here - - - Only for awb_adj, yaveAWB - y_high_limit = y_ave_target+ [y_lmt_offset_reg[6:4],4'd0] - - - - - nexp=low_th - - - not used here - - - nexp>(8+high_th) - - - - - yave_target (yave_target0) - - - yave_target (yave_target0) - - - - - - - - - - - - - - - - - not used here - - - 1reg93vbright_hist - - - 1reg94vdark_hist - - - display edge pixel for sharpness - - - - - Ywave+bhist histYwave - - - - - bright hist - - - - - Yave+bhisthistYave - - - - - - - - - - exp_out[10:8] - - - - - - nexp_selbnr/dpc/int_dif - - - - - - - - - - - 00: cr_lt_1x 01: cr_gt_1x - 10: cr_gt_2x 11: cr_gt_4x - - - 00: cb_lt_1x 01: cb_gt_1x - 10: cb_gt_2x 11: cb_gt_4x - - - 0:crsum (5R B+4G) - 1:crsum (5R B+4G) - - - 0:cbsum (3B R+2G) - 1:cbsum (3B R+2G) - - - 0: crsum_abs cbsum_abs (crsum) - 1: crsum_abs cbsum_abs (cbsum) - - - ae_index - Note: regd[5]? ae_vbright_hist : - reg75[7]? ae_index[6:0] : awb_debug; - - - - - YUVnexp vdark_hist - Note: regd[6]? ae_vdark_hist : - reg5F[1]? nexp[3:0] : mono_color - - - - - - - - - - - - - - - - - - - - - - - - - - yavehist - Vbh_sel[1]? Yave_contr_reg : - Vbh_sel[0]? Yave_target_RO_reg : ae_dark_hist - NoteVbh_sel[1:0] = reg3d[7:6] - - - - - 3d0: gamma_type=0 - 3d1: gamma_type=1 - 3d2: gamma_type=is_outdoor - 3d3: gamma_type=ana_gain>=gamma_gain_th - default:gamma_type=gamma_type_sw - - - nexp>(8+high_th) - - - 00:QVGA 240x320 01:QVGA 320x240 - 10:CIF 352x288 11:VGA 640x480 - - - - - line_sel = [line_init_H, blc_line_reg[7:0]] - - - - - lsc gain@ - - - lsc gain@ - - - - - nexp=low_th - - - nexp>(8+high_th) - - - low_th = [csup_gain_low_th_H, [7:6]](nexp=low_th) - - - - - 2'd0: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_01] - 2'd1: [blc_out0_reg,blc_out1_reg] = [blc_10, blc_11] - 2'd2: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_10] - 2'd3: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_11] - - - - - - 0: plus 1: minus - - - 00: 1frame 01: 2frame ave - 10: 3frame ave 11: 4frame ave - - - - - - - - - - - blc00_ofst =[blc_init_reg[3:0] , 1'b0] - - - blc01_ofst =[blc_init_reg[7:4] , 1'b0] - - - - - blc10_ofst =[blc_offset_reg[3:0] , 1'b0] - - - blc11_ofst =[blc_offset_reg[7:4] , 1'b0] - - - - - High limit of black level pixel - blcofst - - - - - y_cent=[3:0]+240 - - - x_cent=[7:4]+320 - - - - - CNR - - - CNR - - - 1: 0: - - - edge monitor - - - 3d0: never skip 3d1: skip 2/8 skin point - 3d2: skip 3/8 skin point 3d3: skip 4/8 skin point - 3d4: skip 5/8 skin point 3d5: skip 6/8 skin point - 3d6: skip 7/8 skin point 3d7: skip 8/8 skin point - - - - - - - - cnr_thr_v = [cnr_thr[2:0], 2'd3] - - - enable - - - cnr_thr_h = [cnr_thr[6:4], 2'd3] - - - enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~awb_mon_sel? blc_out0_reg : kukl_sel ? kl : awb_mon_out[7:0] - - - - - ~awb_mon_sel? blc_out1_reg : kukl_sel ? ku : awb_mon_out[15:8] - Note: awb_mon_sel = reg1[2] Kukl_sel = reg5F[0] - - - - - dpc on - - - 1: median 0:adp_median - sel=(nexp[3:0]>dpc_ctrl0[3:2])? 1 : dpc_ctrl0[1] - This adp_med is used in int_dif_data and nrf_data_out - - - - - - not used here - - - 1:gausian filter 0:median filter - - - bayer nr on - - - cc on - - - - - 00: always not meet - 01: all round point must meet - 10: can be one except point - 11: can be two except point - - - 00: can be three sign diff with other - 01: can be two sign diff with other - 10: can be one sign diff with other - 11: 8 same sign - - - 1: gausian filter 0:median filter - - - - - Y_thr @ - - - - - Y_thr @mid - - - - - Y_thr @ - - - - - cfa_v_thr[2:0] - - - not used here - - - cfa_h_thr[2:0] - - - not used here - - - - - - - - - - - - - - - - - 0: inc 1:dec - - - - - - - - - - - - - - - - - - - - - - - - nexp=low_th @bnr/dpc/int_dif/sharp/cnr - - - not used here - - - nexp>(8+high_th) @bnr/dpc/int_dif/sharp/cnr - - - - - bnr low frequency str @Low gain @ - (ff) - - - - - bnr high frequency str @Low gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @Low gain - HF - - - - - bnr low frequency str @Mid gain - (ff) - - - - - bnr high frequency str @Mid gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @Mid gain - HF - - - - - bnr low frequency str @high gain @ - (ff) - - - - - bnr high frequency str @high gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @high gain - HF - - - - - - - - - - - - - - - - - - - - 0: 9 1:7 - 2: 5 3:3 - 4: median 5: adp_median - - - - - cfa_h_thr=[intp_cfa_h_thr[7:0], intp_cfa_hv[6:4]] - - - - - cfa_v_thr=[intp_cfa_v_thr[7:0], intp_cfa_hv[2:0]] - - - - - - - - - - gf_lmt_thr=[3d0, intp_gf_lmt_thr_reg] - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S1.6 format, x1=64, cc00+cc01+cc02=1 - - - - - - - - - - S1.6 format, x1=64, cc10+cc11+cc12=1 - - - - - - - - - - S1.6 format, x1=64, cc20+cc21+cc22=1 - - - - - - - - - - S7 format, after cc - - - - - S7 format, after cc - - - - - S7 format, after cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S1.6 format, x1=64, cc00+cc01+cc02=1 - - - - - - - - - - S1.6 format, x1=64, cc10+cc11+cc12=1 - - - - - - - - - - S1.6 format, x1=64, cc20+cc21+cc22=1 - - - - - - - - - - sharp data - - - db/da/d9 - - - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - 0: delay_df - 1: delay_de - 2: delay_dd - 3: delay_dc - - - 1:ppdif_sum - 0:pp_dif (8) - - - - - - - - plus @Low gain (2.6 format)@ - - - - - Sharp@Low gain - (edge) - - - - - plus @Mid gain (2.6 format) - - - - - Sharp@Mid gain - (edge) - - - - - plus @high gain (2.6 format)@ - - - - - Sharp@high gain - (edge) - - - - - - - - (Ey) - 2d0:Ey_H/V/D1/D2 - 2d1: - 2d2: - 2d3: - - - - - - (sharpness) - 00: - if(i_y_data8'ha0) sharp_data = sharp_out[6:2]; - else if(i_y_data8'h80) sharp_data = sharp_out[6:1]; - else sharp_data = sharp_out[6:0]; - 01: 0x80pixelsharpness - 10: 0x90pixelsharpness - 11: No change - - - AEYin - 00:y=yuv_y - 01:y=y_gamma // after ygamma - 10:y=luma_y_out // after y_luma - 11:y=contr_y_out // after y_contr - - - - - GMYc - - - - - @low gain - GMYc128Ey - - - - - @low gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @low gain - HF - - - - - @Mid gain - GMYc128Ey - - - - - @Mid gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @Mid gain - HF - - - - - @high gain - GMYc128Ey - - - - - @high gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @high gain - HF - - - - - sinx[7:0]=256*sin(x*pi/180) - - - - - cosx[7:0]=256*cos(x*pi/180) - cosx[7] fixed as 1, As abs(x) = pi/4 - - - 1: sinx is negative - 0: sinx is positive - - - - - CNR@Mid gain - - - - - - - - - - - - - - CNR@Low gain - - - CNR@High gain - - - - - Center point smaller than around, black point - - - - - Center point bigger than around, white point - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - E00 - - - - - E00 - - - E00 max is 3Line - - - - - E01 - - - - - E01 - - - E01 max is 7Line - - - - - E02max is 7F - - - - - E02 - - - E02 max is 15Line - - - - - E1 (64) - - - - - E1 (1E) - - - - - E2 (64) - - - - - E2 (2E) - - - - - E3 (64) - - - - - E3 (3E) - - - - - E4 (64) - - - - - E4 (4E) - - - - - E5 (64) - - - - - E5 (5E) - - - - - E6 (64) - - - - - E6 (6E) - - - - - E7 (64) - - - - - E7 (7E) - - - - - E8 (64) - - - - - E8 (8E) - - - - - E9 (64) - - - - - E9 (9E) - - - - - Ea (64) - - - - - Ea (aE) - - - - - Eb (64) - - - - - Eb (bE) - - - - - Ec (64) - - - - - Ec (cE) - - - - - Ed (64) - - - - - Ed (dE) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Y_thr7 (for 2 dead point) @ - - - - - Y_thr7 (for 2 dead point) @ mid - - - - - Y_thr7 (for 2 dead point) @ - - - - - 0: check one black dead point - 1: don't check one black dead point - - - 0: check 2 black dead point - 1: don't check 2 black dead point - - - 0: don't check 2 dead point - 1: check 2 dead point - - - - - (Note) - 0: check one black dead point - 1: don't check one black dead point - - - (Note) - 0: check 2 black dead point - 1: don't check 2 black dead point - - - (Note) - 0: don't check 2 dead point - 1: check 2 dead point - - - not used here - - - - - 2E 12 - - - 3E 12 - - - 4E 12 - - - 5E 12 - - - 6E 12 - - - 7E 12 - - - 8E 12 - - - 9E 12 - - - - - awb_win_height = [[7:0],1'd0] - //4:3 and keep height as even number - - - - - - - - - - - - - - - - - - - - - - - - - blue: 0x72 red: 0xD4 brown:0xAB - - - - - blue: 0xD4 red: 0x64 brown:0x60 - - - - - - - - - - 0x20~ff (x1~8) () - - - - - - - - - - 0x20~ff (x1~8) () - - - - - If bhist>bhist_too_big_thr, then bhist_too_big - - - - - If bhist>bhist_big_thr, then bhist_big - - - - - Y level of bhist and 4pbhist - - - - - outdoor_th=[outdoor_th_reg[3:0], 4'd0] - - - non_outdoor_th=[outdoor_th_reg[7:4], 4'd0] - - - - - Low limit of rgain = [[7:2], 2d0] - - - - - High limit of rgain = [[7:2], 2d0] - - - - - Low limit of bgain = [[7:2], 2d0] - - - - - High limit of bgain = [[7:2], 2d0] - - - - - awb_win_y_start = [[3:0], 2'd0]; - - - awb_win_x_start = [[7:4], 2'd0]; - - - - - awb_win_width =[[7:0],2'd0]; - //4:3 and keep height as even number - - - - - Y level of dark_hist - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - 0yave 1yave - 2yave 3yave - - - 0yave 1yave - 2yave 3yave - - - 0: win yave 1: ywave - - - - - - - - - - - - - - ae ywave - - - ae ywave - - - - - QVGA 240x320 :8d60 QVGA 320x240: 8d80 - CIF 352x288: 8d88 VGA 640x480: 8d160 - - - - - QVGA 240x320 :8d80 QVGA 320x240: 8d60 - CIF 352x288: 8d72 VGA 640x480: 8d120 - - - 0: x1(CIFx1) 1:x1.5 - - - - - yave pcnt_sta=[[3:0], 1b0] - - - yave lcnt_sta=[[7:4], 1b0] - - - - - yave Width=[[7:0], 2d0] - QVGA 240x320 :10d216 QVGA 320x240: 10d304 - CIF 352x288: 10d304 VGA 640x480: 10d596 - - - - - yave Height=[[7:0], 1d0] - QVGA 240x320 :10d304 QVGA 320x240: 10d216 - CIF 352x288: 10d216 VGA 640x480: 10d440 - - - - - - - - - - - - - - not used here - - - 3'd0: is_outdoor = 0; - 3'd1: is_outdoor = 1; - 3'd2: - if(ana_gain==0) begin - if(expoutdoor_th) is_outdoor = 1; - else if(expnon_outdoor_th) is_outdoor = 0; end - else is_outdoor = 0; - 3'd3: - if(ana_gain==0 and rgain_bigger) begin - if(expoutdoor_th) is_outdoor = 1; - else if(expnon_outdoor_th) is_outdoor = 0; end - else is_outdoor = 0; - default: - if(vsync_rp_d and sw_update_en) is_outdoor = is_outdoor_sw; - - - 1: when is_outdoor=1, only detect white point at D65 and Indoor CTD block - 0: dont care is_outdoor, detect white point at all ctd block - - - - - - - - - - awb_stop_cr_pos_level =[[3],awb_stop_reg[7:6]]; - awb_stop_cr_neg_level =[[2],awb_stop_reg[5:4]]; - awb_stop_cb_pos_level =[[1],awb_stop_reg[3:2]]; - awb_stop_cb_neg_level =[[0],awb_stop_reg[1:0]]; - - - awb_adj_again = [2'b11, [5:4]] - - - 1: add awb_algo_thr condition to detect white point@A - 0: detect white point according to A ctd block - - - - - - - - 0: normal(no scale) - 1: sub(yuv sub mode) - 2: sca_320x240(1/2) - 3: sca_176x144(1/3) - 4: sca_160x120(1/4) - 5: sca352x288(2/3) - 6: sca352x288(3/5) - 7: 3/4 - - - - - Ee (64) - - - - - Ee (eE) - - - - - Ef (64) - - - - - Ef (fE) - - - - - ae_thr_big = [reg1CA[3:0],2d0]@dark - - - ae_thr_big = [reg1CA[7:4],2d0]@bright - - - - - sharp gain @low gain(2.6 format) - - - - - sharp gain @medium gain(2.6 format) - - - - - sharp gain @high gain(2.6 format) - - - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - - - - - - - - Y = Y_min ( AWB) - - - - - - - - - - - - - - - - - - - - - - - - - Y level of vbright_hist - - - - - Y level of vdark_hist - - - - - - - - - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. -
- Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. -
- When non-secure cpu read this register, the return value will automatic exlude the secure channel. -
- 00000 = use Channel0 -
- 00001 = use Channel1 -
- 00010 = use Channel2 -
- ... -
- 01111 = use Channel15 -
- 11111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- all 1 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - This register indicates which channel register can only be accessed by secure master. One bit per - channel, for example: -
- 0000_0000 = All channels registers can be accessed by secure master or non-secure master. -
- 0000_0001 = Ch0 registers can only be accessed by secure master. -
- 0000_0010 = Ch1 registers can only be accessed by secure master. -
- 0000_0100 = Ch2 registers can only be accessed by secure master. -
- 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. -
- ...... -
- all 1 = all channels registers can only be accessed by secure master. - - - - - This register indicates which channel dma is secure master. One bit per - channel, for example: -
- 0000_0000 = All channels dma are non-secure master. -
- 0000_0001 = Ch0 dma is secure master. -
- 0000_0010 = Ch1 dma is secure master. -
- 0000_0100 = Ch2 dma is secure master. -
- 0000_0101 = Ch0 and Ch2 dma are secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. -
- ...... -
- all 1 = all channels dma are secure master. - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Exchange the read data from fifo halfword MSB or LSB -
- - - - - Exchange the write data to fifo halfword MSB or LSB -
- - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - Set the MAX burst length for channel 0,1. - This bit field is only used in channel 0~1, for channel 2~6, it is reserved. -
- The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. -
- . - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. - - - - - - - - - - - Address of data to be read or written. - - - - These two bits indicates element data size. -
- when "00" = "byte". -
- when "01" = "half word". -
- when "10" = "word". - - - - - This bit indicates command is read or write. -
- when "0" = "Read". -
- when "1" = "Write". - - - - - Those bits are data to be read or written by IFC. - - - - - When read, this bit is used for event semaphore. -
- '0' = no new event should be programed. -
- '1' = no pending event, new event is authorised. -
- If host is not enabled, this bit is always '1'. However in this case, - any event written will be ignored. -
- When Write, this bit is the least significant bit for a 32-bit event. - - - - These bits combined with bit0 consists a 32-bit event number. If a - new event is written before the previous event has been sent, it will - be ignored. - - - - - When '1', force the debug host on, use clock UART if clock host is not - detected. - - - - This bit indicates if clock host is detected to be on or not. -
- '0' = no clock host. -
- '1' = clock host detected. - - - - - - Status which can be written through debug uart interface into a debug host - internal register and read by APB. - - - - - - - write in this bit will reset h2p status register. - - - - - Status which can be written by APB and read through debug uart interface - as a debug host internal register. - - - - - - when write '1', clear the xcpu irq level which is programmed in a debug host - internal register, this bit is automatic cleared. -
- when read, get the xcpu - irq status. - - - - - when write '1', clear the bcpu irq level which is programmed in a debug host - internal register, this bit is automatic cleared. -
- when read, get the bcpu - irq status. - - - - - - - - - - - - - - - - - - - Allows to turn off the UART: -
- 0 = Disable -
- 1 = Enable - - - - - - - Number of data bits per character (least significant bit - first): -
- 0 = 7 bits -
- 1 = 8 bits -
- This bit will be masked to - '1' if debug host is enabled. - - - - - - - Stop bits controls the number of stop bits transmitted. Can - receive with one stop bit (more inaccuracy can be compensated with two - stop bits when divisor mode is set to 0). -
- 0 = one stop bit is - transmitted in the serial data. -
- 1 = two stop bits are generated and - transmitted in the serial data out. -
- This bit will be masked to - '0' if debug host is enabled. - - - - - - - Parity is enabled when this bit is set. -
- This bit will be masked to - '0' if debug host is enabled. - - - - - - - Controls the parity format when parity is enabled: -
- 00 = - an odd number of received 1 bits is checked, or transmitted (the parity - bit is included). -
- 01 = an even number of received 1 bits is checked - or transmitted (the parity bit is included). -
- 10 = a space is - generated and received as parity bit. -
- 11 = a mark is generated and - received as parity bit. -
- These bit will be ignored if debug host is - enabled. - - - - - Sends a break signal by holding the Uart_Tx line low until - this bit is cleared. -
- This bit will be masked to '0' if debug host - is enabled. - - - - - - reset rx fifo. - - - reset tx fifo. - - - - - Enables the DMA signaling for the Uart_Dma_Tx_Req_H and - Uart_Dma_Rx_Req_H to the IFC. - - - - When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre - flow ctrl is used. Otherwise, software flow control is used: -
- 00 = no transmit flow control. -
- 01 = transmit XON1/XOFF1 as flow control bytes -
- 10 = transmit XON2/XOFF2 as flow control bytes -
- 11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes -
- - - - - - - - - - When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre - flow ctrl is used. Otherwise, software flow control is used: -
- 00 = no receive flow control -
- 01 = receive XON1/XOFF1 as flow control bytes -
- 10 = receive XON2/XOFF2 as flow control bytes -
- 11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes -
-
- Note: If single XON/XOFF character is used for flow contol, the received - XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is - received when XOFF is expected. -
- If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently - by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. - Otherwise they will be considered as data. This is also the case if XOFF1 is followed - by character other than XOFF2. -
- - - - - - - - - When soft flow control characters or backslash are encountered in the data file, - they will be inverted and a backslash will be added before them. for example, if tx data - is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON). - - - When this bit is set the Tx engine terminates to send the - current byte and then it stops to send data. - - - - Selects the divisor value used to generate the baud rate - frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA - is enable, this bit is ignored and the divisor used will be 16. -
- 0 = - (BCLK = SCLK / 4) -
- 1 = (BCLK = SCLK / 16) -
- This bit will be - masked to '0' if debug host is enabled. - - - - - When set, the UART is in IrDA mode and the baud rate divisor - used is 16 (see UART Operation for details). -
- This bit will be - masked to '0' if debug host is enabled. - - - - - Controls the Uart_RTS output (not directly in auto flow control - mode). -
- 0 = the Uart_RTS will be inactive high -
- 1 = the Uart_RTS - will be active low -
- This bit will be masked to '1' if debug host is - enabled. - - - - - - - - - Enables the auto flow control. -
- In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0), - If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in - CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx - Fifo Level and AFC_Level in Triggers register). - Tx data flow is stopped If Uart_CTS become inactive high. -
- If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS - bit in CMD_Set register. Uart_CTS will not take effect. -
-
- In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0), - If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit - in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx - Fifo Level and AFC_Level in Triggers register). -
- If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit - in CMD_Set register. Tx data flow will be stoped when XOFF is received either - this bit is enable or disabled. -
-
- This bit will be masked to '1' if debug host is enabled. - - - - When set, data on the Uart_Tx line is held high, while the - serial output is looped back to the serial input line, internally. In - this mode all the interrupts are fully functional. This feature is used - for diagnostic purposes. Also, in loop back mode, the modem control - input Uart_CTS is disconnected and the modem control output Uart_RTS are - looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is - inverted (see IrDA SIR Mode Support). - - - - Allow to stop the data receiving when an error is detected - (framing, parity or break). The data in the fifo are kept. -
- This bit - will be masked to '0' if debug host is enabled. - - - - - - HST TXD output enable. '0' enable. - - - - - - Length of a break, in number of bits. -
- This bit will be masked - to "1011" if debug host is enabled. - - - - - - - - - - Those bits indicate the number of data available in the Rx - Fifo. Those data can be read. - - - - - - - Those bits indicate the number of data available in the Tx - Fifo. Those data will be sent. - - - This bit indicates that the UART is sending data. If no data is - in the fifo, the UART is currently sending the last one through the - serial interface. - - - This bit indicates that the UART is receiving a byte. - - - This bit indicates that the receiver received a new character - when the fifo was already full. The new character is discarded. This bit - is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the user tried to write a character when fifo was - already full. The written data will not be kept. This bit is cleared when - the UART_STATUS register is written with any value. - - - This bit is set if the parity is enabled and a parity error - occurred in the received data. This bit is cleared when the UART_STATUS - register is written with any value. - - - This bit is set whenever there is a framing error occured. A - framing error occurs when the receiver does not detect a valid STOP bit - in the received data. This bit is cleared when the UART_STATUS register - is written with any value. - - - This bit is set whenever the serial input is held in a logic 0 - state for longer than the length of x bits, where x is the value - programmed Rx Break Length. A null word will be written in the Rx Fifo. - This bit is cleared when the UART_STATUS register is written with any - value. - - - - In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), - This bit is set when the Uart_CTS line changed since the last - time this register has been written. -
- In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), - This bit is set when received XON/XOFF status changed since the last time - this register has been writtern. -
- This bit is cleared when the UART_STATUS register is written with any value. - - - - - In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), - current value of the Uart_CTS line. -
- '1' = Tx not allowed. -
- '0' = Tx allowed. -
- In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), - current state of software flow control. -
- '1' = when XOFF received. -
- '0' = when XON received. - - - - This bit is set when Tx Fifo Reset command is received by CTRL - register and is cleared when Tx fifo reset process has finished. - - - This bit is set when Rx Fifo Reset command is received by CTRL - register and is cleared when Rx fifo reset process has finished. - - - This bit is set when bit enable is changed from '0' to '1' or - from '1' to '0', it is cleared when the enable process has finished. - - - This bit is set when Uart Clk has been enabled and received by - UART after Need Uart Clock becomes active. It serves to avoid enabling - Rx RTS too early. - - - - - The UART_RECEIVE_BUFFER register is a read-only register that - contains the data byte received on the serial input port. This register - accesses the head of the receive FIFO. If the receive FIFO is full and - this register is not read before the next data character arrives, then - the data already in the FIFO will be preserved but any incoming data - will be lost. An overflow error will also occur. - - - The UART_TRANSMIT_HOLDING register is a write-only register - that contains data to be transmitted on the serial output port. 16 - characters of data may be written to the UART_TRANSMIT_HOLDING register - before the FIFO is full. Any attempt to write data when the FIFO is full - results in the write data being lost. - - - - - Clear to send signal change or XON/XOFF detected. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. - - - Pulse detected on Uart_Dma_Tx_Done_H signal. - - - Pulse detected on Uart_Dma_Rx_Done_H signal. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - - - - - - - Clear to send signal detected. Reset control: This bit is - cleared when the UART_STATUS register is written with any value. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER - until the Fifo drops below the trigger level. - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING - register above threshold level. - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. Reset control: Reading from the UART_RECEIVE_BUFFER register. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. Reset control: This bit is cleared when the UART_STATUS - register is written with any value. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - - - - Defines the threshold level at which the Data Available - Interrupt will be generated. -
- The Data Available interrupt is - generated when quantity of data in Rx Fifo > Rx Trigger. - - - - - Defines the threshold level at which the Data Needed - Interrupt will be generated. -
- The Data Needed Interrupt is generated - when quantity of data in Tx Fifo <= Tx Trigger. - - - - - Controls the Rx Fifo level at which the Uart_RTS Auto Flow - Control will be set inactive high (see UART Operation for more details - on AFC). -
- The Uart_RTS Auto Flow Control will be set inactive high - when quantity of data in Rx Fifo > AFC Level. - - - - - - XON1 character value. Reset Value is CTRL-Q 0x11. - - - XOFF1 character value. Reset Value is CTRL-S 0x13 - - - XON2 character value. - - - XOFF2 character value. - - These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces: - 0 Group 1 interrupts not forward. - 1 Group 1 interrupts forwarded, subject to the priority rules. - - - Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces: - 0 Group 0 interrupts not forwarded. - 1 Group 0 interrupts forwarded, subject to the priority rules. - - - - - If the GIC implements the Security Extensions, the value of this field is the maximum number of - implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111), see Configuration lockdown on - page 4-82. If this field is 0b00000 then the GIC does not implement configuration lockdown. - If the GIC does not implement the Security Extensions, this field is reserved. - - - Indicates whether the GIC implements the Security Extensions. - 0 Security Extensions not implemented. - 1 Security Extensions implemented. - - - Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is - one more than the value of this field, for example if this field is 0b011, there are four CPU interfaces. - If the GIC implements the Virtualization Extensions, this is also the number of virtual CPU interfaces. - - - Indicates the maximum number of interrupts that the GIC supports. If ITLinesNumber=N, the - maximum number of interrupts is 32(N+1). The interrupt ID range is from 0 to (number of IDs C 1). - For example: - 0b00011 Up to 128 interrupt lines, interrupt IDs 0-127. - The maximum number of interrupts is 1020 (0b11111). See the text in this section for more information. - Regardless of the range of interrupt IDs defined by this field, interrupt IDs 1020-1023 are reserved for - special purposes. - - - - - Product ID - - - An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish product variants, - or major revisions of a product. - - - An IMPLEMENTATION DEFINED revision number. Typically, this field is used to distinguish minor revisions - of a product. - - - Contains the JEP106 code of the company that implemented the GIC Distributor: - Bits [11:8] The JEP106 continuation code of the implementer. For an ARM implementation, this field - is 0x4. - Bits [7] Always 0. - Bits [6:0] The JEP106 identity code of the implementer. For an ARM implementation, bits[7:0] are - 0x3B. - - - - - The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC. - Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. - Accessible by Secure accesses Only. - For each bit: - 0 The corresponding interrupt is Group 0. - 1 The corresponding interrupt is Group 1.For interrupt ID m, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_IGROUPRn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_IGROUPR is (0x080 + (4*n)) - c. the bit number of the required group status bit in this register is m MOD 32. - - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - - The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC. - For each bit: - Reads 0 The corresponding interrupt is not pending on any processor. - 1 a. For PPIs and SGIs, the corresponding interrupt is pendinga on this - processor. - b. For SPIs, the corresponding interrupt is pendinga on at least one - processor. - Writes For SPIs and PPIs: - 0 Has no effect. - 1 The effect depends on whether the interrupt is edge-triggered or - level-sensitive: - Edge-triggered - Changes the status of the corresponding interrupt to: - a.pending if it was previously inactive - b.active and pending if it was previously active. - Has no effect if the interrupt is already pending. - Level sensitive - If the corresponding interrupt is not pendinga, changes the status - of the corresponding interrupt to: - a. pending if it was previously inactive - b. active and pending if it was previously active. - If the interrupt is already pending: - a. because of a write to the GICD_ISPENDR, the write has - no effect. - b. because the corresponding interrupt signal is asserted, the - write has no effect on the status of the interrupt, but the - interrupt remains pendinga if the interrupt signal is - deasserted. - For SGIs, the write is ignored. SGIs have their own Set-Pending registers. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ISPENDR number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ISPENDR is (0x200 + (4*n)) - c. the bit number of the required Set-pending bit in this register is m MOD 32. - - - - The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. - For each bit: - Reads 0 The corresponding interrupt is not pending on any processor. - 1 a. For SGIs and PPIs, the corresponding interrupt is pendinga on this - processor. - b. For SPIs, the corresponding interrupt is pendinga on at least one - processor. - Writes For SPIs and PPIs: - 0 Has no effect. - 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: - Edge-triggered - Changes the status of the corresponding interrupt to: - a. inactive if it was previously pending - b. active if it was previously active and pending. - Has no effect if the interrupt is not pending. - Level-sensitive - If the corresponding interrupt is pendinga only because of a write to - GICD_ISPENDRn, the write changes the status of the interrupt to: - a. inactive if it was previously pending - b. active if it was previously active and pending. - Otherwise the interrupt remains pending if the interrupt signal - remains asserted. - For SGIs, the write is ignored. SGIs have their own Clear-Pending registers. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ICPENDR is (0x280 + (4*n)) - c. the bit number of the required Set-pending bit in this register is m MOD 32. - - - - The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports. - For each bit: - Reads 0 The corresponding interrupt is not active. - 1 The corresponding interrupt is active. - Writes 0 Has no effect. - 1 Activates the corresponding interrupt, if it is not already active. If the interrupt - is already active, the write has no effect. - After a write of 1 to this bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ISACTIVERn is (0x300 + (4*n)) - c. the bit number of the required Set-active bit in this register is m MOD 32. - - - - The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC - supports. - For each bit: - Reads 0 The corresponding interrupt is not activea. - 1 The corresponding interrupt is activea. - Writes 0 Has no effect. - 1 Deactivates the corresponding interrupt, if the interrupt is active. If the - interrupt is already deactivated, the write has no effect. - After a write of 1 to this bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICACTIVERn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ICACTIVERn is (0x380 + (4*n)) - c. the bit number of the required Clear-active bit in this register is m MOD 32. - - - - The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the - GIC. - Each priority field holds a priority value, from an IMPLEMENTATION DEFINED range. The lower the - value, the greater the priority of the corresponding interrupt. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_IPRIORITYRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_IPRIORITYRn is (0x400 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - Asserted when the PPI inputs to the Distributor are active. - ID 31 nLEGACYIRQ signal - ID 30 Non-secure physical timer event - ID 29 Secure physical timer event - ID 28 nLEGACYFIQ signal - ID 27 Virtual timer event - ID 26 Hypervisor timer event - ID 25 Virtual maintenance interrupt. - - - - Returns the status of the IRQS inputs on the Distributor. For each bit: - 0 IRQS is LOW - 1 IRQS is HIGH. - - - - The GICD_NSACRs enable Secure software to permit Non-secure software on a particular - processor to create and manage Group 0 interrupts. They provide an access control for each - implemented interrupt. - If the corresponding interrupt does not support configurable Non-secure access, the field is - RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted - when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible - values of the field are: - 0b00 No Non-secure access is permitted to fields associated with the corresponding - interrupt. - 0b01 Non-secure write access is permitted to fields associated with the corresponding - interrupt in the GICD_ISPENDRn registers. A Non-secure write access to - GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding - interrupt. - 0b10 Adds Non-secure write access permission to fields associated with the - corresponding interrupt in the GICD_ICPENDRn registers. Also adds - Non-secure read access permission to fields associated with the corresponding - interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers. - 0b11 Adds Non-secure read and write access permission to fields associated with the - corresponding interrupt in the GICD_ITARGETSRn registers. - The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are - RAZ/WI. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_NSACR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_NSACRn is (0xE00 + (4*n)). - - - - - Determines how the distributor must process the requested SGI: - 0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda. - 0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the - interrupt. - 0b10 Forward the interrupt only to the CPU interface of the processor that requested the - interrupt. - 0b11 Reserved. - - - When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the - interrupt. - Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example - CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be - forwarded to the corresponding interface. - If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any - CPU interface. - - - Implemented only if the GIC includes the Security Extensions. - Specifies the required security value of the SGI: - 0 Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the - SGI is configured as Group 0 on that interface. - 1 Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if - the SGI is configured as Group 1 on that interface. - This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an - SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write. - - - The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the - Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. - - - - - The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source - processor combination. - For each bit: - Reads 0 SGI x from the corresponding processor is not pending. - 1 SGI x from the corresponding processor is pending. - Writes 0 Has no effect. - 1 Removes the pending state of SGI x for the corresponding processor. - For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_CPENDSGIR register number, n, is given by n = x DIV 4 - b. the offset of the required GICD_CPENDSGIR is (0xF10 + (4*n)); - c. the SGI Clear-pending field offset, y, is given by y = x MOD 4 - d. the required bit in the SGI x Clear-pending field is bit C. - - - The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and - source processor combination. - For each bit: - Reads 0 SGI x for the corresponding processor is not pendinga. - 1 SGI x for the corresponding processor is pendinga. - Writes 0 Has no effect. - 1 Adds the pending state of SGI x for the corresponding processor, - if it is not already pending. If SGI x is already pending for the - corresponding processor then the write has no effect. - For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4 - b. the offset of the required GICD_SPENDSGIR is (0xF20 + (4*n)) - c. the SGI Set-pending field offset, y, is given by y = x MOD 4 - d. the required bit in the SGI x Set-pending field is bit C. - - - - - Alias of EOImodeNS from the Non-secure copy of this register. - - - Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. In a GIC implementation - that includes the Security Extensions, this control applies only to Secure accesses, and the EOImodeNS - bit controls the behavior of Non-secure accesses to these registers: - 0 GICC_EOIR has both priority drop and deactivate interrupt functionality. Accesses to - the GICC_DIR are UNPREDICTABLE. - 1 GICC_EOIR has priority drop functionality only. GICC_DIR has deactivate interrupt - functionality. - - - Alias of IRQBypDisGrp1 from the Non-secure copy of this register. - - - Alias of FIQBypDisGrp1 from the Non-secure copy of this register. - - - When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass - IRQ signal is signaled to the processor: - 0 Bypass IRQ signal is signaled to the processor - 1 Bypass IRQ signal is not signaled to the processor. - - - When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass - FIQ signal is signaled to the processor: - 0 Bypass FIQ signal is signaled to the processor - 1 Bypass FIQ signal is not signaled to the processor. - - - Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts. - 0 To determine any preemption, use: - ? the GICC_BPR for Group 0 interrupts - ? the GICC_ABPR for Group 1 interrupts. - 1 To determine any preemption use the GICC_BPR for both Group 0 and Group 1 - interrupts. - - - Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or - the IRQ signal. - 0 Signal Group 0 interrupts using the IRQ signal. - 1 Signal Group 0 interrupts using the FIQ signal. - The GIC always signals Group 1 interrupts using the IRQ signal. - - - When the highest priority pending interrupt is a Group 1 interrupt, determines both: - ? whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID - ? whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or - returns a spurious interrupt ID. - 0 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR - or the GICC_HPPIR returns an Interrupt ID of 1022. A read of the GICC_IAR does - not acknowledge the interrupt, and has no effect on the pending status of the interrupt. - 1 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR - or the GICC_HPPIR returns the Interrupt ID of the Group 1 interrupt. A read of - GICC_IAR acknowledges and Activates the interrupt. - - - Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor: - 0 Disable signaling of Group 1 interrupts. - 1 Enable signaling of Group 1 interrupts. - - - Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor: - 0 Disable signaling of Group 0 interrupts. - 1 Enable signaling of Group 0 interrupts. - - - - - The priority mask level for the CPU interface. If the priority of an interrupt is higher than the - value indicated by this field, the interface signals the interrupt to the processor. - If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows: - 128 supported levels Bit [0] = 0. - 64 supported levels Bit [1:0] = 0b00. - 32 supported levels Bit [2:0] = 0b000. - 16 supported levels Bit [3:0] = 0b0000. - - - - - The value of this field controls how the 8-bit interrupt priority field is split into a group - priority field, used to determine interrupt preemption, and a subpriority field. - The minimum value of the Binary Point Register depends on which - security-banked copy is considered: - 0x2 Secure copy - 0x3 Non-secure copy - - - - - For SGIs in a multiprocessor implementation, this field identifies the processor that - requested the interrupt. It returns the number of the CPU interface that made the - request, for example a value of 3 means the request was generated by a write to the - GICD_SGIR on CPU interface 3. - For all other interrupts this field is RAZ. - - - The interrupt ID. - - - - - On a multiprocessor implementation, if the write refers to an SGI, this - the CPUID value from the corresponding GICC_IAR access. - In all other cases this field SBZ. - - - The Interrupt ID value from the corresponding GICC_IAR access. - - - - - The current running priority on the CPU interface. - - - - - On a multiprocessor implementation, if the PENDINTID field returns the ID of an - SGI, this field contains the CPUID value for that interrupt. This identifies the - processor that generated the interrupt. - In all other cases this field is RAZ. - - - The interrupt ID of the highest priority pending interrupt. See Table 4-42 on - page 4-144 for more information about the result of Non-secure reads of the - GICC_HPPIR when the GIC implements the Security Extensions. - - - - - A Binary Point Register for handling Group 1 interrupts. - - - - - CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that - requested the interrupt. It returns the number of the CPU interface that made the request, - for example a value of 3 means the request was generated by a write to the GICD_SGIR - on CPU interface 3. - For all other interrupts this field is RAZ. - - - Interrupt ID The interrupt ID. - - - - - On a multiprocessor implementation, when processing an SGI, this field must contain - the CPUID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, - access. - In all other cases this field SBZ. - - - The Interrupt ID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, - access. - - - - - On a multiprocessor implementation, if the PENDINTID field returns the ID of an - SGI, this field contains the CPUID value for that interrupt. This identifies the - processor that generated the interrupt. - In all other cases this field is RAZ. - - - The interrupt ID of the highest priority pending interrupt, if that interrupt is a Group 1 - interrupt. Otherwise, the spurious interrupt ID, 1023. - - - - - Active Priorities Registers - - - - NonSecure Active Priorities Registers - - - - - An IMPLEMENTATION DEFINED product identifier. - - - The value of this field depends on the GIC architecture version, as follows: - ? 0x1 for GICv1 - ? 0x2 for GICv2. - - - An IMPLEMENTATION DEFINED revision number for the CPU interface. - - - Contains the JEP106 code of the company that implemented the GIC CPU - interface: - Bits [11:8] The JEP106 continuation code of the implementer. - Bit [7] Always 0. - Bits [6:0] The JEP106 identity code of the implementer. - - - - - - For an SGI in a multiprocessor implementation, this field - identifies the processor that requested the interrupt. - For all other interrupts this field is RAZ. - - - The interrupt ID - - - - - - - - - - Maximum output width in pixels - - Number of bits coding position in virtual screen - - Number of bits of fractional part of internal fixed point values - - Number of bits of internal fixed point values - - Number of bits for stride storage - - - - - Starts the image transfer. Autoreset - - - - - High while image accelerator is busy - - - High while LCD controller is busy - - - - - - High when End Of Frame IRQ has been generated. -
- To clear it, write 1 in this bit or in eof_status. - - - - - Unmasked version of eof_cause. -
- To clear it, write 1 in this bit or in eof_status. - - - - - - - EOF interrupt generation mask: -
- 0: EOF IRQ disabled -
- 1: EOF IRQ enabled - - - - - - LCD Region Of Interest Top-Left pixel x-axis - - - LCD Region Of Interest Top-Left pixel y-axis - - - - - LCD Region Of Interest Bottom-Right pixel x-axis - - - LCD Region Of Interest Bottom-Right pixel y-axis - - - - - Blue component of the ROI background color - - - Green component of the ROI background color - - - Red component of the ROI background color - - - - - - Input image format -
- 00b: RGB565 pixel packed -
- 01b: YUV4:2:2 pixel packed (UYVY) -
- 10b: YUV4:2:2 pixel packed (YUYV) -
- 11b: YUV4:2:0 planar (IYUV) - - - - - Image stride in bytes (of Y component for planar formats). -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Defines Layer's activity: -
- 0: Layer disabled -
- 1: Layer active - - - - - - Video Layer (layer 0) Top-Left pixel x-axis position - - - Video Layer (layer 0) Top-Left pixel y-axis position - - - - - Video Layer (layer 0) Bottom-Right pixel x-axis position - - - Video Layer (layer 0) Bottom-Right pixel y-axis position - - - - - Number of lines of source image (idem gd_vl_br_ppos.y1 when - vertical scaling factor is one). - - - Number of columns of source image (idem gd_vl_br_ppos.x1 when - vertical scaling factor is one). - - - - - Blue component of the Chroma Key - - - - - - Green component of the Chroma Key - - - - - - Red component of the Chroma Key - - - - - - - - - - - Enables the Chroma Keying - - - - - - - Allows a range of color for the Chroma Keying: -
- 000b: exact color match -
- 001b: disregard 1 LSBit of each color component for matching -
- 011b: disregard 2 LSBit of each color component for matching -
- 111b: disregard 3 LSBit of each color component for matching - - - - - - - Layer Alpha blending coefficient - - - - - - - Layer rotation selection -
- 00b: No rotation -
- 01b: 90 degrees rotation (clockwise) -
- 10b: reserved -
- 11b: reserved - - - - - - - - Layer depth -
- 00b: Video layer behind all Overlay layers -
- 01b: Video layer between Overlay layers 1 and 0 -
- 10b: Video layer between Overlay layers 2 and 1 -
- 11b: Video layer on top of all Overlay layers - - - - - - - - - Dword-aligned address of the Y component (or RGB) of the source image - - - - - Dword-aligned address of the U component of the source image - - - - - Dword-aligned address of the V component of the source image - - - - - Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - - The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn. - - - - Input image format -
- 0: RGB565 pixel packed -
- 1: ARGB8888 pixel packed -
- others: reserved - - - - - Image stride in 16-bits word. -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Image stride in 16-bits word. -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Defines Layer's activity: -
- 0: Layer disabled -
- 1: Layer active - - - - - - Overlay Layer (layer X+1) Top-Left pixel x-axis position - - - Overlay Layer (layer X+1) Top-Left pixel y-axis position - - - - - Overlay Layer (layer X+1) Bottom-Right pixel x-axis position - - - Overlay Layer (layer X+1) Bottom-Right pixel y-axis position - - - - - Blue component of the Chroma Key - - - Green component of the Chroma Key - - - Red component of the Chroma Key - - - - - - - - Enables the Chroma Keying - - - - Allows a range of color for the Chroma Keying: -
- 000b: exact color match -
- 001b: disregard 1 LSBit of each color component for matching -
- 011b: disregard 2 LSBit of each color component for matching -
- 111b: disregard 3 LSBit of each color component for matching - - - - Layer Alpha blending coefficient - - - - - Dword-aligned address of the source image - - - - - - Destination Selection - - - - - - Output format -
- 000b: 8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB -
- 001b: 8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB -
- 010b: 8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB -
- 011b: reserved -
- 100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB -
- 101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB -
- 110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB -
- 111b: 32-bit - RGB5:6:5 - 1cycle/2pixel - RRRRRGGGGGGBBBBB/RRRRRGGGGGGBBBBB -
-
- The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected. -
- Must set to RGB565 when RAM type destination selected - - - - - - - - - Change Polarity of CS0 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of CS1 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RS signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of WR signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RD signal -
- 0: no change -
- 1: Inverted - - - - Number of command to be send to the LCD command (up to 31) - - - Start command transfer only. Autoreset - - - LCD reset signal. Low active - - - - All value are in cycle number of system clock - - Address setup time (RS to WR, RS to RD) - - - Adress hold time - - - Pulse Width Low level, between 2 and 63. - - - Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). - - - - - - Address destination pointer when memory destination is selected. -
- The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. - - - - - - - Address offset (in Bytes) skipped at the end of each line when memory destination is selected. -
- This 2D feature allows for in-memory image compositing. - - - - - - data to write or data readen (the readen data is ready when the lcd is not busy) - - - - Acesss type selection -
- 0: Command -
- 1: Data - - - - Start a single write access. Autoreset - - - Start a single read access (only when LCD output selected). Autoreset. - - - - - - - - - - - - - - - - - - - - - - - - 0:4 line mode - 1:3 line mode - 2:command mode - 3:3 line 2 lane mode tx - - - - - - - - - - - - - - - - - - - - - - - - Mirror enable. - - - . - - - . - - - . - - - . - - - - - - Count value to detect vsync pulse - - - 0:vsync te only 1:vsync and hsync te - - - Pol select - - - Te enable. - - - - - Te counter value - - - - - - - - - - - Gouda internal Sram space - - - - - - - - - I2C master enable, high active. - - - I2C master interrupt enable, high active. - - - - This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared. -
-
- Example: -
- PCLK_MOD is 52 MHz, desired SCL is 100 KHz. -
- Prescale = 52MHz / (5 * 100KHz) -1 = 103. - - - - - - - - - IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK. - - - IRQ status bit. - - - TIP, Transfer in progress. - '1' when transferring data. '0' when transfer complete. - - - AL,Arbitration lost. - This bit is set when the I2C master lost arbitration. - - - Busy,I2C bus busy. - '1' after START signal detected. - '0' after STOP signal detected. - - - RxACK, Received acknowledge from slave. - '1'= "No ACK" received. - '0'= ACK received. - - - - - - Byte to transmit via I2C. -
- for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit. -
- '1' = reading from slave. -
- '0' = writing to slave. - - - - Last byte received via I2C. - - - - - ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1'). - - - RD,read from slave, this bit is auto cleared. - - - STO,generate stop condition, this bit is auto cleared. - - - WR,write to slave, this bit is auto cleared. - - - STA,generate (repeated) start condition, this bit is auto cleared. - - - - - When write '1', clears a pending I2C interrupt. - - - - - - - - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. -
- Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. -
- When non-secure cpu read this register, the return value will automatic exlude the secure channel. -
- 00000 = use Channel0 -
- 00001 = use Channel1 -
- 00010 = use Channel2 -
- ... -
- 01111 = use Channel15 -
- 11111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- all 1 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - This register indicates which channel register can only be accessed by secure master. One bit per - channel, for example: -
- 0000_0000 = All channels registers can be accessed by secure master or non-secure master. -
- 0000_0001 = Ch0 registers can only be accessed by secure master. -
- 0000_0010 = Ch1 registers can only be accessed by secure master. -
- 0000_0100 = Ch2 registers can only be accessed by secure master. -
- 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. -
- ...... -
- all 1 = all channels registers can only be accessed by secure master. - - - - - This register indicates which channel dma is secure master. One bit per - channel, for example: -
- 0000_0000 = All channels dma are non-secure master. -
- 0000_0001 = Ch0 dma is secure master. -
- 0000_0010 = Ch1 dma is secure master. -
- 0000_0100 = Ch2 dma is secure master. -
- 0000_0101 = Ch0 and Ch2 dma are secure master. -
- 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. -
- ...... -
- all 1 = all channels dma are secure master. - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Exchange the read data from fifo halfword MSB or LSB -
- - - - - Exchange the write data to fifo halfword MSB or LSB -
- - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - Set the MAX burst length for channel 0,1. - This bit field is only used in channel 0~1, for channel 2~6, it is reserved. -
- The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. -
- . - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. - - - - - - - - - - - Writing 1 starts block decode - - - - - AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset. - - - Decode error flag. Reading 1 indicates block decode error and Lzma should be reset. - - - Decode done flag. Reading 1 indicates block decode done, writing 1 clears. - - - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1 - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1 - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1 - - - - not used - - - - Lzma dictionary size in byte - - - lzma block size in byte - - - - - lzma zip stream lenght in byte - - - - - 1: refbyte enable; 0: refbyte disable - - - 1: cabac_movebits=5; 0: cabac_movebits=4 - - - 1: cabac_totalbits=11; 0: cabac_totalbits=10 - - - - - current decoding byte position in zip stream - - - - - current recovering byte position in dictionary - - - - - Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2) - - - Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size - - - Equals to 1 when a symbol is decoded as match type with length more than 273 - - - Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size - - - Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion - - - Equals to 1 when first symbol in a block is decoded as match type - - - Equals to 1 when zip stream reading byte position exceeds the stream length - - - - not used - - - not used - - - Crc of lzma rdma read bytes - - - Crc of lzma wdma write bytes - - - not used - - - not used - - - Base address of lzma rdma - - - Base address of lzma wdma - - - - Set the margin between input_buf wrptr and rdptr for pending the decode process - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - Enables the SIM Card IF module - - - Selects the parity generation/detection - - - - - - Parity Error Receive Feed-through -
- 0 = Don't store bytes with detected parity errors -
- 1 = Feed-through bytes with detected parity errors - - - - - Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer. -
- 0 = Enable NULL character filtering, NULL characters are not reported if not data. -
- 1 = Disable NULL character filtering. NULL characters (0x60) are transferred to the SCI data buffer. - - - - - Manual SCI Clock Stop control. Manually starts and stops the SCI clock. This bit must be set to '1' when Autostop mode is enabled. -
- 0 = Enable the SCI clock -
- 1 = Disable SCI clock - - - - - Enables automatic clock shutdown when command is complete. Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol. -
- 0 = Auto clock control not enabled. SCI clock controlled by SCI_Clockstop bit -
- 1 = Auto clock control enabled. - - - - - Sets the transmission and reception bit order: -
- 0 = LSB is sent/recieved first (Direct convention) -
- 1 = MSB is sent/received first (Inverse convention) - - - - - Logic Level Invert: -
- 0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit. (Direct convention) -
- 1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit. (Inverse convention) - - - - - Parity Error signal length. This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU -
- 0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU -
- 1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU - - - - - Enable or disable parity error checking on the receive data -
- 0 = Disable parity error checking -
- 1 = Enable parity error checking - - - - - Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown) -
- 0 = Stop clock at low level -
- 1 = Stop clock at high level - - - - Automatic Reset Generator. Write a '1' to this bit to initiate an automatic reset procedure on the SIM. Write '0' to switch back to SCI_Reset control (bit 20). An ARG interrupt will be generated if the ARG process succeeded or failed. The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected. This bit needs to be cleared between ARG attempts. - - - - Automatic format detection. This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention. -
- 1 = Enable TS detection and automatic convention settings programming -
- 0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention - - - - - 1 = Enable automatic resend of characters when Tx parity error is detected -
- 0 = Disable automatic resend - - - - - Direct connection to the SIM card reset pin. This is overridden when ARG_H is enabled -
- 0 = SCI_Reset low voltage -
- 1 = SCI Reset high voltage - - - - - This selects between two delay times for the automatic clock stop startup and shutdown: -
- 0 = short delay -
- Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks -
- 1 = long delay -
- Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks - - - - - Input data average enable. -
- 0 = Disable -
- 1 = Enable - - - - Allows fine control of the parity check position during the parity error time period. - - - - - - Returns the status of the Rx FIFO: -
- 0 = Rx FIFO empty -
- 1 = There is at least 1 character in the Rx FIFO - - - - - Returns the status of the Tx FIFO: -
- 0 = Tx FIFO is full -
- 1 = There is at least 1 free spot in the Tx FIFO - - - - - Returns the status of the automatic format detection after reset: -
- 0 = TS character has not been detected in the ATR -
- 1 = TS character has been detected and SCI module is using the automatic convention settings -
-
- This bit is cleared when the AFD_En bit is cleared - - - - - Returns the status of the automatic reset procedure: -
- 0 = ARG detection has failed -
- 1 = ARG detection has detected that the SIM has responded to the reset -
-
- This bit is used in conjunction with the ARG interrupt. The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process. This bit can be used to determine the success or failure. - - - - This is the status of the Reset pin when automatic reset generation is enabled. This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection') - - - - Status of the control signal to the clock control module. This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready' -
- 0 = SCI clock may be on or off but is not ready for use -
- 1 = SCI clock is on and ready for use - - - - - Status bit of the Sci clock. -
- 0 = Sci clock is ON -
- 1 = Sci clock is OFF - - - - A receive parity error was detected. Reading this register clears the bit. - - - A transmit parity error was detected. Reading this register clears the bit. - - - The internal receive FIFO has reached an overflow condition. Reading this register clears the bit. - - - The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit. - - - Returns the state of the clock management state machine when AutoStop mode is enabled. This value is '00' when manual mode is selected. - - - - - - - - - - - - - Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. - - - Reading this register will read from the receive data FIFO. - - - - - Clock divider for generating the baud clock from the SCI clock. This value must match the value used by the SIM card whose default value is 0x174. - - - - Speed mode enable. -
- 0 = Low speed mode -
- 1 = High speed mode(372/32, 372/64, 512/64) - - - - Rx_clk_cnt wrap value. - - - - - Secondary clock divider for generating 16x baud clock. - - - - Main clock divider to generate the SCI clock. This value should be calculated as follows: -
- MainDiv = Clk_Sys/(2xSCI_Clk) - 1 -
- where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification. - - - - - - - - - Inverts the polarity of the SCI clock to the SIM card only. -
- 0 = No inversion -
- 1 = Invert external SCI clock - - - - - Inverts the polarity of the SCI clock to the SIM card and internal. -
- 0 = No inversion -
- 1 = Invert external SCI clock - - - - - - - This value should be programmed with the number of expected characters to receive. It will be decremented each time a character is - actually - received and should be 0 when the transfer is complete. If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero. - - - - - When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete. This should be used for multi-transfer commands where the clock must not be shut down until the command is complete. This bit must be programmed for each transfer. -
- 1 = Keep clock on -
- 0 = Allow clock shutdown when transfer is complete - - - - - - This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters. This should be programmed depending on the SIM's ATR. The total ETU guard time will be ChGuard + 1. - - - - - - - - Turnaround guard time configuration. This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character. The minimum time specified in the SIM recommendation is 16 ETU. The number of ETUs can be calculated using the following formula: -
- Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard - - - - - - - - - Work Waiting Time factor. A timeout will be generated when the WWT is exceeded. The WWT is calculated by: -
- WWT = 960 x WI x (F/Fi) -
- where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS. -
- The SCI_WI value must be calculated as follows: -
- SCI_WI = WI * D -
- Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure. - - - - - - - - Number of times to try resending character when the SIM indicates a parity error. - - - - - - Value of the character to be filtered. 0x60 is the NULL character in the SIM protocol. If character filtering is enabled, the - first - 0x60 character that is received by the SIM during a transfer will - not - be recorded. The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data. This filter has no effect on characters within the datastream. - - - - - - Clear RX FIFO. - - - Clear TX FIFO. - - clear RX/TX FIFO - - - - Number of expected Rx characters, as programmed in the RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - - This register is a - READ ONLY - register that returns the logical - and - of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt. Bits 21:16 return the - status - of the interrupt which is the interrupt state before the mask is applied. These bits should only be used for debugging. - - - - - Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in SCI_RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect. - - - - Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in SCI_RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt. - - - - - - - - - - - - - - - Controls the big endian or little endian of the FIFO data. -
- Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0. -
- "000": the order is not changed. -
- Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D". -
- "001": reversed on byte. -
- Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A". -
- "010": reversed on half word. -
- Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B". -
- "010": reversed on bit. -
- Byte3="B0",Byte2="30,Byte1="D0",Byte0="50". -
- "100": reversed on bit. -
- Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". - - - - - For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind. -
- Active Low. - - - - - - - Read in the receive FIFO - - Write to the transmit FIFO - - - - - - SD/MMC operation begin register, active high. -
- When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. - - - - SD/MMC operation suspend register, active high. - - - '1'indicates having a response,'0'indicates no response. - - - - - - Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. - - - '1' indicates data operation, which includes read and write. - - - - - - '1' means write operation,'0' means read operation. - - - - - - '1'means multiple block data operation. - - - - - - - '1' means the SD/MMC operation is not over. - - - '1' means SD/MMC is busy. - - - '1' means the data line is busy. - - - '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. - - - Response CRC checks error register '1' means response CRC check error. - - - '1' means the card has no response to command. - - - - CRC check for SD/MMC write operation -
- "101" transmission error -
- "010" transmission right -
- "111" flash programming error - - - - 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. - - - SDMMC DATA 3 value. - - - - - SD/MMC command register. - - - - SD/MMC command argument register, write data to the SD/MMC card. - - - - SD/MMC response index register. - - - - Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. - - - 95 to 64 bit response argument of R2. - - - 63 to 32 bit response argument of R2. - - - 31 to 0 bit response argument of R2. - - - - - SD/MMC data width: -
- 0x1: 1 data line -
- 0x2: 2 reserved -
- 0x4: 4 data lines -
- 0x8: 8 data lines - - - - - - - SD/MMC size of one block: -
- 0-1:reserved -
- 2: 1 word -
- 3: 2 words -
- 4: 4 words -
- 5: 8 words -
- 6: 16 words -
-
- 11: 512 words -
- 12-15 reserved - - - - - - Block number that wants to transfer. - - - - - '1' means no response. - - - '1' means CRC error of response. - - - '1' means CRC error of reading data. - - - '1' means CRC error of writing data. - - - '1' means data transmission is over. - - - '1' means tx dma done. - - - '1' means rx dma done. - - - '1' means no response is the source of interrupt. - - - '1' means CRC error of response is the source of interrupt. - - - '1' means CRC error of reading data is the source of interrupt. - - - '1' means CRC error of writing data is the source of interrupt. - - - '1' means the end of data transmission is the source of interrupt. - - - '1' means tx dma done is the source of interrupt. - - - '1' means rx dma done is the source of interrupt. - - - - - When no response, '1' means INT is disable. - - - When CRC error of response, '1' means INT is disable. - - - When CRC error of reading data, '1' means INT is disable. - - - When CRC error of writing data, '1' means INT is disable. - - - When data transmission is over, '1' means INT is disable. - - - when tx dma done, '1' means INT is disabled. - - - '1' means rx dma done, '1' means INT is disabled. - - - - - Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. - - - Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. - - - Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. - - - Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. - - - - - Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). - - - - - This register may delay the mclk output. - When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. - - - Invert Mclk. - - - - - - - - - - spi flash command to send. - - - spi flash address to send. - - - - - spi flash modebit,set 0xA0 to enable continuous read. - - - spi flash spi read/write block size. - - - - - - - spi flash data to send. - - - spi send byte, 1: quad send 0: spi send. - - - - - spi flash busy. - - - tx fifo empty. - - - tx fifo full. - - - rx fifo empty. - - - rx fifo data count. - - - read busy. - - - nand int . - - - spiflash_int = nand_int and nand_int_mask . - - - - flash rx status. - - - - spi flash read mode from AHB. - - - - - spi flash wprotect pin. - - - spi flash hold pin. - - - spi flash read sample delay cycles. - - - spi flash clock divider. - - - spi flash send command using quad lines. - - - - - - - rx fifo_clr,self clear. - - - tx fifo_clr,self clear. - - - - - spi flash cs num. - - - - - single chip spi flash size. - - - - - spi flash is 128m flash. - - - - - disable read from ahb. - - - - - sel flash 1, addr[24]. - - - - - addr[25]. - - - diff 128m diff cmd en. - - - spi_256m. - - - spi_512m. - - - spi_cs1_sel2. - - - spi_1g . - - - spi_2g. - - - spi_4g. - - - spi_cs1_sel3. - - - spi_cs1_sel4. - - - spi_cs1_sel5. - - - - - quad read command. - - - fast read command. - - - fast read command. - - - protect_byte, must be 0x55 when program this register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Value low 32bits loaded to OS timer. - - - - Value high 24bits loaded to OS timer. - - - - Write '1' to this bit will enable OS timer. -
- When read, the value is what we have written to this bit, it changes immediately after been written. - - - - - Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock. -
-
- '1' indicates OS timer enabled. -
- '0' indicates OS timer not enabled. - - - - - Read this bit will get the information if OS timer interruption clear operation is finished or not. -
-
- '1' indicates OS timer interruption clear operation is on going. -
- '0' indicates no OS timer interruption clear operation is on going. - - - - - Write '1' to this bit will set OS timer to repeat mode. -
- When read, get the information if OS timer is in repeat mode. -
-
- '1' indicates OS timer in repeat mode. -
- '0' indicates OS timer not in repeat mode. - - - - - Write '1' to this bit will set OS timer to wrap mode. -
- When read, get the information if OS timer is in wrap mode. -
-
- '1' indicates OS timer in wrap mode. -
- '0' indicates OS timer not in wrap mode. - - - - Write '1' to this bit will load the initial value to OS timer. - - - - Current value low 32bits of OS timer. - - - Current value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - Current locked value low 32bits of OS timer. - - - Current locked value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - - - This bit enables interval IRQ mode. -
-
- '0': hw delay timer does not generate interval IRQ. -
- '1': hw delay timer generate an IRQ each interval. - - - - - interval of generating an HwTimer IRQ. -
-
- "00": interval of 1/8 second. -
- "01": interval of 1/4 second. -
- "10": interval of 1/2 second. -
- "11": interval of 1 second. - - - - - Current low 32bits value of the hardware delay timer. - - - Current high 32bits value of the hardware delay timer. - - - Current locked low 32bits value of the hardware delay timer. - - - Current locked high 32bits value of the hardware delay timer. - - - - Set mask for OS timer IRQ. - - - Set mask for hardwre delay timer wrap IRQ. - - - Set mask for hardwre delay timer interval IRQ. - - - - - Clear mask for OS timer IRQ. - - - Clear mask for hardwre delay timer wrap IRQ. - - - Clear mask for hardwre delay timer interval IRQ. - - - - - Clear OS timer IRQ. - - - Clear hardware delay timer wrap IRQ. - - - Clear hardware delay timer interval IRQ. - - - - - OS timer IRQ cause. - - - hardware delay timer wrap IRQ cause. - - - hardware delay timer interval IRQ cause. - - - OS timer IRQ status. - - - hardware delay timer wrap IRQ status. - - - hardware delay timer interval IRQ status. - - - - - - - - - - - - - - - - - - - - - Value loaded to OS timer. - - - - Write '1' to this bit will enable OS timer. -
- When read, the value is what we have written to this bit, it changes immediately after been written. - - - - - Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock. -
-
- '1' indicates OS timer enabled. -
- '0' indicates OS timer not enabled. - - - - - Read this bit will get the information if OS timer interruption clear operation is finished or not. -
-
- '1' indicates OS timer interruption clear operation is on going. -
- '0' indicates no OS timer interruption clear operation is on going. - - - - - Write '1' to this bit will set OS timer to repeat mode. -
- When read, get the information if OS timer is in repeat mode. -
-
- '1' indicates OS timer in repeat mode. -
- '0' indicates OS timer not in repeat mode. - - - - - Write '1' to this bit will set OS timer to wrap mode. -
- When read, get the information if OS timer is in wrap mode. -
-
- '1' indicates OS timer in wrap mode. -
- '0' indicates OS timer not in wrap mode. - - - - Write '1' to this bit will load the initial value to OS timer. - - - - Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - - Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal. - - - Write '1' to this bit will stop watchdog timer. - - - - Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer. -
- Use this bit to implement the watchog keep alive. - - - - - Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock. -
-
- '1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted. -
- '0' indicates watchdog timer is not enabled. - - - - - - - Load value of watchdog timer. Number of 32kHz Clock before Reset. -
- - - - - - - This bit enables interval IRQ mode. -
-
- '0': hw delay timer does not generate interval IRQ. -
- '1': hw delay timer generate an IRQ each interval. - - - - - interval of generating an HwTimer IRQ. -
-
- "00": interval of 1/8 second. -
- "01": interval of 1/4 second. -
- "10": interval of 1/2 second. -
- "11": interval of 1 second. - - - - - Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF. - - - - Set mask for OS timer IRQ. - - - Set mask for hardwre delay timer wrap IRQ. - - - Set mask for hardwre delay timer interval IRQ. - - - - - Clear mask for OS timer IRQ. - - - Clear mask for hardwre delay timer wrap IRQ. - - - Clear mask for hardwre delay timer interval IRQ. - - - - - Clear OS timer IRQ. - - - Clear hardware delay timer wrap IRQ. - - - Clear hardware delay timer interval IRQ. - - - - - OS timer IRQ cause. - - - hardware delay timer wrap IRQ cause. - - - hardware delay timer interval IRQ cause. - - - OS timer IRQ status. - - - hardware delay timer wrap IRQ status. - - - hardware delay timer interval IRQ status. - - - - - - - - - - - - - - - - - - - - - - Allows to turn off the UART: -
- 0 = Disable -
- 1 = Enable - - - - Number of data bits per character (least significant bit first), - if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; - if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; - if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; - if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; - - - - - - Stop bits controls the number of stop bits transmitted. Can - receive with one stop bit (more inaccuracy can be compensated with two - stop bits when divisor mode is set to 0). -
- 0 = one stop bit is - transmitted in the serial data. -
- 1 = two stop bits are generated and - transmitted in the serial data out. - - - - - - Parity is enabled when this bit is set. - - - - - - Controls the parity format when parity is enabled: -
- 00 = - an odd number of received 1 bits is checked, or transmitted (the parity - bit is included). -
- 01 = an even number of received 1 bits is checked - or transmitted (the parity bit is included). -
- 10 = a space is - generated and received as parity bit. -
- 11 = a mark is generated and - received as parity bit. - - - - - Controls whether enable or disable soft flow ctrl function. -
- 0 = disable flow ctrl function -
- 1 = enable flow ctrl function - - - - - Controls whether enable or disable auto baud rate function. -
- 0 = disable auto baud rate function -
- 1 = enable auto baud rate function - - - - Number of data bits per character (least significant bit first), - if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; - if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; - if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; - if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; - - - - Selects the divisor value used to generate the baud rate - frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA - is enable, this bit is ignored and the divisor used will be 16. -
- 0 = - (BCLK = SCLK / 16) -
- 1 = (BCLK = SCLK / 4) -
- 2 = (BCLK = SCLK / 3) - - - - When set, the UART is in IrDA mode and the baud rate divisor - used is 16 (see UART Operation for details). - - - - - Enables the DMA signaling for the Uart_Dma_Tx_Req_H and - Uart_Dma_Rx_Req_H to the IFC. - - - - - Enables the auto flow control. Uart_RTS is controlled by the Rx - RTS bit and the UART Auto Control Flow System. If Uart_CTS - become inactive high, the Tx data flow is stopped. - - - When set, data on the Uart_Tx line is held high, while the - serial output is looped back to the serial input line, internally. In - this mode all the interrupts are fully functional. This feature is used - for diagnostic purposes. Also, in loop back mode, the modem control - input Uart_CTS is disconnected and the modem control output Uart_RTS are - looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is - inverted (see IrDA SIR Mode Support). - - - Allow to stop the data receiving when an error is detected - (framing, parity or break). The data in the fifo are kept. - - - Length of a break, in number of bits. - - - - - - - - - Those bits indicate the number of data available in the Rx - Fifo. Those data can be read. - - - - - - - Those bits indicate the number of space available in the Tx - Fifo. - - - - at_match flag -
- '0' = AT is detected successfully. -
- '1' = at is detected successfully. - When auto_enable is 0,this bit is cleared to 0. - - - - This bit indicates that the UART is sending data. If no data is - in the fifo, the UART is currently sending the last one through the - serial interface. - - - This bit indicates that the UART is receiving a byte. - - - This bit indicates that the receiver received a new character - when the fifo was already full. The new character is discarded. This bit - is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the user tried to write a character when fifo was - already full. The written data will not be kept. This bit is cleared when - the UART_STATUS register is written with any value. - - - This bit is set if the parity is enabled and a parity error - occurred in the received data. This bit is cleared when the UART_STATUS - register is written with any value. - - - This bit is set whenever there is a framing error occured. A - framing error occurs when the receiver does not detect a valid STOP bit - in the received data. This bit is cleared when the UART_STATUS register - is written with any value. - - - This bit is set whenever the serial input is held in a logic 0 - state for longer than the length of x bits, where x is the value - programmed Rx Break Length. A null word will be written in the Rx Fifo. - This bit is cleared when the UART_STATUS register is written with any - value. - - - - character miscompare flag -
- '0' = AT or at compare failed. -
- '1' = AT or at compare successfully. - When auto_enable is 0,this bit is cleared to 0. - - - - - auto baud locked flag -
- '0' = baud rate is detected failed. -
- '1' = baud rate is detected successfully. - When auto_enable is 0,this bit is cleared to 0. - - - - This bit is set when the Uart_CTS line changed since the last - time this register has been written. This bit is cleared when the - UART_STATUS register is written with any value. - - - - current value of the Uart_CTS line. -
- '1' = Tx not allowed. -
- '0' = Tx allowed. - - - - Auto mode ratio flag. - - - Mask tx enable flag. - - - Current value of the DTR line. - - - This bit is set when Uart Clk has been enabled and received by - UART after Need Uart Clock becomes active. It serves to avoid enabling - RTS too early. - - - - - The UART_RECEIVE_BUFFER register is a read-only register that - contains the data byte received on the serial input port. This register - accesses the head of the receive FIFO. If the receive FIFO is full and - this register is not read before the next data character arrives, then - the data already in the FIFO will be preserved but any incoming data - will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register - that contains data to be transmitted on the serial output port. 16 - characters of data may be written to the UART_TRANSMIT_HOLDING register - before the FIFO is full. Any attempt to write data when the FIFO is full - results in the write data being lost. - - - - - Clear to send signal change detected. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. - - - Pulse detected on Uart_Dma_Tx_Done_H signal. - - - Pulse detected on Uart_Dma_Rx_Done_H signal. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - - - Rising edge detected on the UART_DTR signal. - - - Falling edge detected on the UART_DTR signal. - - - Auto function fail. - - - When rx transfer num equals to transfer threshold, there is a interrupt flag. - - - When tx transfer num equals to transfer threshold, there is a interrupt flag. - - - This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. - - - This interrupt is generated when sw flow ctrl is enabled and rx char is xon. - - - This interrupt is generated when start bit is detected. - - - - - Clear to send signal detected. Reset control: This bit is - cleared when the UART_STATUS register is written with any value. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER - until the Fifo drops below the trigger level. - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING - register above threshold level. - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. Reset control: Reading from the UART_RECEIVE_BUFFER register. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. Reset control: This bit is cleared when the UART_STATUS - register is written with any value. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - Reset control: Write one in this register. - - - This interrupt is generated when a rising edge is detected on the - UART_DTR signal. Reset control: Write one in this register. - - - This interrupt is generated when a falling edge is detected on the - UART_DTR signal. Reset control: Write one in this register. - - - This interrupt is generated when auto function fail. - Reset control: Write 0 in auto_enable. - - - This interrupt is generated when rx transfer num is not less than transfer threshold. - Reset control: Write 1 in this register. - - - This interrupt is generated when tx transfer num is not less than transfer threshold. - Reset control: Write 1 in this register. - - - This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. - Reset control: Write 1 in this register. - - - This interrupt is generated when sw flow ctrl is enabled and rx char is xon. - Reset control: Write 1 in this register. - - - This interrupt is generated when start is detected. - Reset control: Write 1 in this register. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - - - - Defines the empty threshold level at which the Data Available - Interrupt will be generated. -
- The Data Available interrupt is - generated when quantity of data in Rx Fifo > Rx Trigger. - - - - - Defines the empty threshold level at which the Data Needed - Interrupt will be generated. -
- The Data Needed Interrupt is generated - when quantity of data in Tx Fifo <= Tx Trigger. - - - - - Controls the Rx Fifo level at which the Uart_RTS Auto Flow - Control will be set inactive high (see UART Operation for more details - on AFC). -
- The Uart_RTS Auto Flow Control will be set inactive high - when quantity of data in Rx Fifo > AFC Level. - - - - - - Ring indicator. When write '1', set RI bit. When read, get RI bit - value. - - - Data carrier detect. When write '1', set DCD bit. When read, get DCD - bit value. - - - Data set ready. When write '1', set RI bit. When read, get RI bit - value. - - - Sends a break signal by holding the Uart_Tx line low until - this bit is cleared. - - - When this bit is set the Tx engine terminates to send the - current byte and then it stops to send data. - - - - Controls the Uart_RTS output. -
- 0 = the Uart_RTS will be inactive high (Rx not allowed). -
- 1 = the Uart_RTS will be active low (Rx allowed). - - - - Writing a 1 to this bit resets and flushes the Receive Fifo. - This bit does not need to be cleared. - - - Writing a 1 to this bit resets and flushes the Transmit Fifo. - This bit does not need to be cleared. - - - - - Ring indicator. When write '1', clear RI bit. When read, get RI bit - value. - - - Data carrier detect. When write '1', clear DCD bit. When read, get DCD - bit value. - - - Data set ready. When write '1', clear RI bit. When read, get RI bit - value. - - - Sends a break signal by holding the Uart_Tx line low until - this bit is cleared. - - - When this bit is set the Tx engine terminates to send the - current byte and then it stops to send data. - - - - Controls the Uart_RTS output. -
- 0 = the Uart_RTS will be inactive high. -
- 1 = the Uart_RTS will be active low. - - - - - - Auto mode ratio. - - - - - XON character value. - - - - - XOFF character value. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Number of key in the keypad - - - Number of key in the low data register - - - Number of key in the high data register - - - For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) : - - - For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn): - - - - - For keys in lines status -
- 0 = Released -
- 1 = Pressed - - - - - - - - - Indicate Key ON pressing status : -
- 0 = Release -
- 1 = Pressed - - - - - - - - - - - - This bit enables key detection. If this bit is '0', the key detection function - is disabled. Key ON is an exception, it can be still detected and generate key interrupt - even if KP_En = '0', however in this case, the debouncing time configuration in key - control register is ignored and the key ON state is considerred to be stable if it keeps - same in consecutive 2 cycles of 16KHz clock. -
-
- 0 = keypad disable -
- 1 = keypad enable - - - - De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms. - - - Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. - - - - each bit masks one input lines. -
- '1' = enabled -
- '0' = disabled -
- The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset. -
- Key_In 0: BOOT_MODE_NO_AUTO_PU. -
- Key_In 1: BOOT_MODE_FORCE_MONITOR. -
- Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE. -
- Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE. -
- Key_In 4: reserved - - - - - each bit masks one output lines. -
- '1' = enabled -
- '0' = disabled - - - - - - - This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1). -
- 0 = keypad event irq disable -
- 1 = keypad event irq enable - - - - - This bit mask keypad irq generated by event1 (all keys release event). -
- 0 = keypad event irq disable -
- 1 = keypad event irq enable - - - - - This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time. -
- 0 = keypad interval irq disable -
- 1 = keypad interval irq enable - - - - - - keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. - - - keypad event1(all keys release event) IRQ cause. - - - keypad interval irq cause. - - - keypad event0(key press or key release event, not including all keys release which is event1) irq status. - - - keypad event1(all keys release event) irq status. - - - keypad interval irq status. - - - - - Write '1' to this bit clears key IRQ. - - - - - - - - - - - Set the direction of the GPIO n. - - - 'Write '1' sets the corresponding GPIO pin as output. - - - 'Write '1' sets the corresponding GPIO pin as input. - - - When write, update the output value. When read, get the input - value. - - - Write '1' will set GPIO output value. When read, get the GPIO - output value. - - - 'Write '1' clears corresponding GPIO output value. When read, get the GPIO - output value. - - - 'Write '1' will set GPIO interrupt mask for rising edge and - level high. When read, get the GPIO interrupt mask for rising edge and - level high. - - - 'Write '1' will clear GPIO interrupt mask for rising edge and - level high. - - - 'Write '1' will clear GPIO interrupt. - - - Each bit represents if there is a GPIO interrupt - pending. - - - - - time for which GPIO0 is set to output mode, after a start read - DCON command is issued. -
- The output time = (OUT_TIME+1)*30.5us. - - - - - time for which GPIO0 should wait before reading DC_ON, after - a start read DCON command is issued. -
- The wait time = (WAIT_TIME+1)*30.5us. -
- NOTE: wait_time must be strictly greater than out_time; - - - - - interruption mode of GPIO0 in mode DC_ON detection. -
- - - - - - - - - - - Write '1' to set GPIO0 to charger DCON detect mode. - - - Write '1' to set GPO0 to charger watchdog mode. - - - Write '1' to clear charger DCON detect mode of GPIO0. - - - Write '1' to clear the charger watchdog mode of GPO0. - - - Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles. - - - - - 'Write '1' will set GPO output value. When read, get the GPO - output value. - - - - - 'Write '1' will clear GPO output value. When read, get the GPO - output value. - - - - 'Write '1' will set GPIO interrupt mask for rising edge and - level high. When read, get the GPIO interrupt mask for rising edge and - level high. - - - 'Write '1' will clear GPIO interrupt mask for rising edge and - level high. - - - 'Write '1' will enable debounce mechanism. - - - 'Write '1' will disable debounce mechanism. - - - Write '1' will set interruption mode to level. - - - Write '1' will set interruption mode to edge - triggered. - - - - - - \ No newline at end of file diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/config.ini b/4G/tools/_temp/uis_tools/setting/chips/8850/config.ini deleted file mode 100644 index 974bf60..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/config.ini +++ /dev/null @@ -1,61 +0,0 @@ -[DiagPort] -Enable=0 -Com= -BaudRate=2000000 -MaxReadBlockSize=1920 -MaxWriteBlockSize=1920 -Timeout=5000 - -[ChannelServer] -Enable=1 -IP=127.0.0.1 -Port=36666 -MaxReadBlockSize=1920 -MaxWriteBlockSize=1920 -Timeout=5000 - -[DebugHost] -Enable=0 -Com= -BaudRate=921600 - -[DebugUart] -Enable=0 -Com= -BaudRate=921600 - -[Uart] -Enable=0 -Com= -BaudRate=921600 - -[CoolHost] -Enable=0 -IP=127.0.0.1 -Port=7726 - -[T32Cmm] -Enable=0 -File= -Mips=0 - -[Daplink] -Enable=0 -ID= -Type=openocd -MaxReadBlockSize=8192 -Timeout=5000 -Core=CP - -[UIEnable] -frmDebugHost=1 -frmCoolHost=1 -frmDebugUart=0 -frmUart=0 -frmDiagPort=1 -frmChannelServer=1 -frmDapLink=1 -frmT32=1 - -[Ping] -Address=0x80008000 diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850.xml deleted file mode 100644 index ab6b179..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850.xml +++ /dev/null @@ -1,226 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX.xml deleted file mode 100644 index e5458fa..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX.xml +++ /dev/null @@ -1,217 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_AP.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_AP.xml deleted file mode 100644 index 3c7ce8b..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_AP.xml +++ /dev/null @@ -1,66 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_CP.xml b/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_CP.xml deleted file mode 100644 index 43a8e94..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/fota8850BM_CX_CP.xml +++ /dev/null @@ -1,183 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_prv.pem b/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_prv.pem deleted file mode 100644 index fdb805e..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_prv.pem +++ /dev/null @@ -1,5 +0,0 @@ ------BEGIN PRIVATE KEY----- -MIGHAgEAMBMGByqGSM49AgEGCCqGSM49AwEHBG0wawIBAQQgh7+mKZqFnFWhQzqF -h1I89Ix32bdppKenfweoqmk0qLShRANCAASAJPdnp3zrVhg56bVHVg+pUOhSOkqI -tXysTx3xfYShl4PKyE1spSb1TW+R18w+wrFQ8OmI/uEQok6LmtoEqnjC ------END PRIVATE KEY----- diff --git a/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_pub.pem b/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_pub.pem deleted file mode 100644 index 93f7981..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8850/secp256r1_pub.pem +++ /dev/null @@ -1,4 +0,0 @@ ------BEGIN PUBLIC KEY----- -MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEgCT3Z6d861YYOem1R1YPqVDoUjpK -iLV8rE8d8X2EoZeDyshNbKUm9U1vkdfMPsKxUPDpiP7hEKJOi5raBKp4wg== ------END PUBLIC KEY----- diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/8910.xcp b/4G/tools/_temp/uis_tools/setting/chips/8910/8910.xcp deleted file mode 100644 index 19e9a9d..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/8910.xcp +++ /dev/null @@ -1,2490 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/8910_bsdump.xml b/4G/tools/_temp/uis_tools/setting/chips/8910/8910_bsdump.xml deleted file mode 100644 index 0b28b50..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/8910_bsdump.xml +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/8910_hard.xml b/4G/tools/_temp/uis_tools/setting/chips/8910/8910_hard.xml deleted file mode 100644 index 78cf888..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/8910_hard.xml +++ /dev/null @@ -1,122653 +0,0 @@ - - - - - - - AHB Address bus size - - - AXI Address bus size of DMA_AP - - - System AON Apb Bus Configuration - - - - - - 8910m sys aon apb module id - - - - - - - - - - - - - - - - - Last of AON Normal slave - - - - - - Num of System Aon Apb Slaves except Debug Host - - - The debug host is placed at last PSEL127 in the IFC - - - - Debug host slave id used for ifc channel. - - - System Apb Bus Configuration - - - - - - 8910m sys apb module id - - - - - - - - - - - - - - - - - - Last of Sys APB Normal slave - - - - - - - - - - - - - - - Num of System Apb Slaves - - - - System Ahb Bus Configuration - - - - 8910m sys ahb module id - - - - - - - - Num of System Ahb Slaves - - - - - Aif Apb Bus Configuration - - - - - 8910m aif apb module id - - - Num of Aif Apb Slaves - - - - Aif slave id used for ifc channel. - - - - - - - - - - - - - - - - - - - - - - Num of sys ifc dma req - - - - - - - - - - - - - - - - - - - Num of aon ifc dma req - - - - - System IRQ IDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Num of System IRQS - - - - - IRQ IDs For CP CPU - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Num of IRQS For CP CPU - - - - - Other IRQ IDs For CP CPU - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Num of Other IRQS For CP CPU - - - - Below is for compatibility to inherited design and for rtl compiling pass - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GGE System Apb Bus Configuration - - - - - 8910m gge sys apb module id - - - - - - - - - - - - - - - - - - Num of GGE System Apb Slaves - - - - - - Num of gge ifc dma req - - - - GGE System Apb Bus Configuration - - - - - 8910m gge bb apb module id - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Num of GGE Baseband Apb Slaves - - - - - GGE IRQ IDs - - - - - - - - - - Number of GGE Pulse IRQ - - - - - - - - - - - - - - - - - - - - - - - - - Num of Gge IRQS - - - - Number of GGE BB Level IRQ - - - - - - System RF Apb Bus Configuration - - - - 8910m rf apb module id - - - - - - - - - - - - - - - Num of RF Apb Slaves - - - - WCN System Apb Bus Configuration - - - - - 8910m wcn sys apb module id - - - - - - - - - - - - - - - Num of WCN System Apb Slaves - - - - - -#if defined(REG_ADDRESS_FOR_GGE) -#define KSEG0(addr) ( (addr) | 0x80000000 ) -#define KSEG1(addr) ( (addr) | 0xA0000000 ) -#else -#define KSEG0(addr) (addr) -#define KSEG1(addr) (addr) -#endif -#define REG_ACCESS_ADDRESS(addr) KSEG1(addr) -/* Define access cached or uncached */ -#define MEM_ACCESS_CACHED(addr) (assert(0, "NOT SUPPORTED")) -#define MEM_ACCESS_UNCACHED(addr) (assert(0, "NOT SUPPORTED")) -/* Register access for assembly */ -#define BASE_HI(val) (((0xa0000000 | val) & 0xffff8000) + (val & 0x8000)) -#define BASE_LO(val) (((val) & 0x7fff) - (val & 0x8000)) -/* to extract bitfield from register value */ -#define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) -#define EXP2(n) (1<<(n)) -#define REG32 volatile unsigned int -#define REG16 volatile unsigned short -#define REG8 volatile unsigned char -#define UINT32 unsigned int -#define UINT16 unsigned short -#define UINT8 unsigned char -#define REG_READ_UINT32( _reg_ ) (*(volatile unsigned int*)(_reg_)) -#define REG_WRITE_UINT32( _reg_, _val_) ((*(volatile unsigned int*)(_reg_)) = (unsigned int)(_val_)) -#define REG_READ_U64( _reg_ ) (*(volatile unsigned long*)(_reg_)) -#define REG_WRITE_U64( _reg_, _val_) ((*(volatile unsigned long*)(_reg_)) = (unsigned long)(_val_)) - - - - - 0= chip option; 1= FPGA option - - - 0= no baseband; 1= baseband included - - - 0= Nothing; 1= BIST; 2= TEST MASTER - - - 0= no monitor; 1=monitor included - - - 0= no debug host sel register as on test chip; 1=debug host sel register included - - - 0= No VOC ; 1= VOC included - - - 0= No aif channels (0,1) ; 1= All 3 channels - - - 0= No MMI ; 1= MMI included : keypad, PWL/PWT, calendar - - - GPIO/GPO OPTIONS: numbers - - - - - 0= No DMA ; 1= DMA included - - - 0 = no SPI, no GPADC, no UART1; 1 = SPI, GPADC, UART1 included - - - 0 = no USB; 1 = USB included - - - Ap Ifc Number of generic channel (range 2 to 7) - - - Aon Ifc Number of generic channel (range 2 to 7) - - - Gge Ifc Number of generic channel (range 2 to 7) - - - audio Ifc Number of generic channel (range 0 to 4) - - - 0 = no UART2; 1 = UART2 included - - - number of SPI1 CS - - - number of SPI1 DI - - - size of SPI1 DATA - - - 0 = no SPI2; 1 = SPI2 included - - - number of SPI2 CS - - - number of SPI DI - - - size of SPI2 DATA - - - 0 = no SPI3; 1 = SPI3 included - - - number of SPI3 CS - - - number of SPI DI - - - size of SPI3 DATA - - - 0 = no SDMMC; 1 = SDMMC controller included - - - 0 = no Camera; 1 = Camera controller included - - - 0 = no Gouda; 1 = Gouda included - - - 0 = EBC, 1 = AHBM - - - for membridge internal ram: number of 32k blocks - - - for EBC option only - - - for AHBM option only: address bus size - - - - - - - - - - - - Address of data to be read or written. - - - - These two bits indicates element data size. -
- when "00" = "byte". -
- when "01" = "half word". -
- when "10" = "word". - - - - - This bit indicates command is read or write. -
- when "0" = "Read". -
- when "1" = "Write". - - - - - - Those bits are data to be read or written by IFC. - - - - - - When read, this bit is used for event semaphore. -
- '0' = no new event should be programed. -
- '1' = no pending event, new event is authorised. -
- If host is not enabled, this bit is always '1'. However in this case, - any event written will be ignored. -
- When Write, this bit is the least significant bit for a 32-bit event. - - - - These bits combined with bit0 consists a 32-bit event number. If a - new event is written before the previous event has been sent, it will - be ignored. - - - - - When '1', force the debug host on, use clock UART if clock host is not - detected. - - - - This bit indicates if clock host is detected to be on or not. -
- '0' = no clock host. -
- '1' = clock host detected. - - - - - - Status which can be written through debug uart interface into a debug host - internal register and read by APB. - - - - - - - write in this bit will reset h2p status register. - - - - - Status which can be written by APB and read through debug uart interface - as a debug host internal register. - - - - - - when write '1', clear the xcpu irq level which is programmed in a debug host - internal register, this bit is automatic cleared. -
- when read, get the xcpu - irq status. - - - - - when write '1', clear the bcpu irq level which is programmed in a debug host - internal register, this bit is automatic cleared. -
- when read, get the bcpu - irq status. - - - - - - - - - - General control signals set. - - - Debug host generated reset. Signal to system control. Active high. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal sys_rst_others (host). - - - - - Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal rst_host_reg. - - - - - Force wakeup. Active high. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal rst_host_reg. - - - - - Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal sys_rst_others (host). - - - - - Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal sys_rst_others (host). - - - - - When write '1, generate a level IRQ to XCPU. Write '0 is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal sys_rst_others (host). - - - - - When write '1', generate a level IRQ to BCPU. Write '0' is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal sys_rst_others (host). - - - - - Lock Debug port set. -
- Write '1' to this bit will set it to '1'. -
- Reseted by signal rst_host_reg. - - - - - General control signals clear. - - - Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared. -
- Write '1' to this bit will clear it to '0'. -
- Reseted by signal rst_host_reg. - - - - - Force wakeup. Active high. -
- Write '1' to this bit will clear it to '0'. -
- Reseted by signal rst_host_reg. - - - - - Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU. -
- Write '1' to this bit will clear it to '0'. -
- Reseted by signal sys_rst_others (host). - - - - - Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU. -
- Write '1' to this bit will clear it to '0'. -
- Reseted by signal sys_rst_others (host). - - - - - Lock Debug port clear. -
- Write '1' to this bit will clear it to '0'. -
- Reseted by signal sys_rst_others (host). - - - - - Configure Debug UART Clock divider. - - - Debug host clock divider. The serial clock is generated by dividing 14,7456MHz Host Clock by (CFG_CLK+2). So By default, the serial clock is 14,7456MHz / (2+2) = 3,6864 MHz which corresponds to the 921,6K Baud-rate. -
- Reseted by signal rst_host_reg. - - - - - Configure Debug UART. - - - When '1', Disable Normal Uart functional group. -
- This bit is set to '1' when break. -
- Reseted by signal rst_host_reg. - - - - - When '1', Ignore IFC write and read access so only debug host internal is accessible. -
- This bit is set to '1' when break. -
- Reseted by signal rst_host_reg. - - - - - The usage of this bit is deternimed by the specific chip. -
- Can be used as Debug_Port_Lock register to protect some register change by the regular software while debug hosr is used to set thoses registers to specific values. -
- Reseted by signal rst_host_reg. - - - - - When '1', force the Debug Uart to have priority on TX. -
- Reseted by signal rst_host_reg. - - - - - Status of CRC. - - - This bit represents that an CRC error has occured in commands received by Debug Host. Once set to '1', it will keep the value until this register is clearred by write '1'. -
- '0' = no CRC error. -
- '1' = CRC error. -
- Reseted by signal sys_rst_others (host). - - - - - This bit represents if the 16-byte Flow Control FIFO has an overflow error. This status will be kept until a RX break is received. -
- '0' = no Flow Control Overflow Error. -
- '1' = Flow Control Overflow Error. -
- Reseted by signal sys_rst_others (host). - - - - - Host write, APB readable register. - - - These bits can be read by APB and write by host. Corresponds to APB register STATUS. They can also be reseted to zeros by APB command. (see details in debug host APB register mapping) -
- Reseted by signal sys_rst_others (host). - - - - - APB write, Host readable register. - - - These bits can be written by APB and read by host. Corresponds to APB register STATUS. -
- Write to Bit 0 can reset the P2H status. -
- Reseted by signal sys_rst_others (host). - - - - - Debug information of system side AHB bus status. - - The bit represent Sys Ifc HMBURSREQ. - - - The bit represent Dma HMBURSREQ. - - - The bit represent Sys Ahb2ahb HMBURSREQ. - - - The bit represent Xcpu HMBURSREQ. - - - The bit represent USBC HMBURSREQ. - - - The bit represent GOUDA HMBURSREQ. - - - - - The bit represent Sys Ifc HMGRANT. - - - The bit represent Dma HMGRANT. - - - The bit represent Sys Ahb2ahb HMGRANT. - - - The bit represent Xcpu HMGRANT. - - - The bit represent USBC HMGRANT. - - - The bit represent GOUDA HMGRANT. - - - - Debug information of AHB bus status HSEL. - - The bit represent Sys MEM_EXT HSEL. - - - The bit represent Sys MEM_INT HSEL. - - - The bit represent Sys Ifc HSEL. - - - The bit represent Sys Ahb2ahb HSEL. - - - The bit represent USBC HSEL. - - - The bit represent GOUDA HSEL. - - - The bit represent XCPU RAM HSEL. - - - - - The bit represent Sys Ifc HSREADY. - - - The bit represent Sys EBC HSREADY. - - - The bit represent Sys Ahb2ahb HSREADY. - - - The bit represent USBC HSREADY. - - - The bit represent GOUDA HSREADY. - - - The bit represent XCPU RAM HSREADY. - - - The bit represent Sys HSREADY which is sent to all sys AHB slaves. - - - - Debug information of baseband side AHB bus status. - - The bit represent BB Ifc HMBURSREQ. - - - The bit represent Voc HMBURSREQ. - - - The bit represent BB Ahb2ahb HMBURSREQ. - - - The bit represent Bcpu HMBURSREQ. - - - The bit represent BB Ifc HMGRANT. - - - The bit represent Voc HMGRANT. - - - The bit represent BB Ahb2ahb HMGRANT. - - - The bit represent Bcpu HMGRANT. - - - - Debug information of AHB bus status HSEL. - - The bit represent BB MEM HSREADY. - - - The bit represent BB VoC HSREADY. - - - The bit represent BB Sram HSREADY. - - - The bit represent BB Ifc HSREADY. - - - The bit represent BB Ahb2ahb HSREADY. - - - The bit represent BB HREADY which is sent to all BB AHB slaves. - - - - Debug information of AHB bus status HSEL. - - The bit represent BB MEM_EXT HSEL. - - - The bit represent BB MEM_INT HSEL. - - - The bit represent BB VOC HSEL. - - - The bit represent BB Sram HSEL. - - - The bit represent BB Ifc HSEL. - - - The bit represent BB Ahb2ahb HSEL. - - - - Represents the split status register of the SYS_AHBC. - - - - - Represents the split status register of the BB_AHBC. - - - - - - - - - - - - - - - - - - Allows to turn off the UART: -
- 0 = Disable -
- 1 = Enable - - - - - - - Number of data bits per character (least significant bit - first): -
- 0 = 7 bits -
- 1 = 8 bits -
- This bit will be masked to - '1' if debug host is enabled. - - - - - - - Stop bits controls the number of stop bits transmitted. Can - receive with one stop bit (more inaccuracy can be compensated with two - stop bits when divisor mode is set to 0). -
- 0 = one stop bit is - transmitted in the serial data. -
- 1 = two stop bits are generated and - transmitted in the serial data out. -
- This bit will be masked to - '0' if debug host is enabled. - - - - - - - Parity is enabled when this bit is set. -
- This bit will be masked to - '0' if debug host is enabled. - - - - - - - Controls the parity format when parity is enabled: -
- 00 = - an odd number of received 1 bits is checked, or transmitted (the parity - bit is included). -
- 01 = an even number of received 1 bits is checked - or transmitted (the parity bit is included). -
- 10 = a space is - generated and received as parity bit. -
- 11 = a mark is generated and - received as parity bit. -
- These bit will be ignored if debug host is - enabled. - - - - - Sends a break signal by holding the Uart_Tx line low until - this bit is cleared. -
- This bit will be masked to '0' if debug host - is enabled. - - - - - - - - - - - - Enables the DMA signaling for the Uart_Dma_Tx_Req_H and - Uart_Dma_Rx_Req_H to the IFC. - - - - When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre - flow ctrl is used. Otherwise, software flow control is used: -
- 00 = no transmit flow control. -
- 01 = transmit XON1/XOFF1 as flow control bytes -
- 10 = transmit XON2/XOFF2 as flow control bytes -
- 11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes -
- - - - - - - - - - When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre - flow ctrl is used. Otherwise, software flow control is used: -
- 00 = no receive flow control -
- 01 = receive XON1/XOFF1 as flow control bytes -
- 10 = receive XON2/XOFF2 as flow control bytes -
- 11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes -
-
- Note: If single XON/XOFF character is used for flow contol, the received - XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is - received when XOFF is expected. -
- If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently - by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. - Otherwise they will be considered as data. This is also the case if XOFF1 is followed - by character other than XOFF2. -
- - - - - - - - - When soft flow control characters or backslash are encountered in the data file, - they will be inverted and a backslash will be added before them. for example, if tx data - is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON). - - - - - When this bit is set the Tx engine terminates to send the - current byte and then it stops to send data. - - - - Selects the divisor value used to generate the baud rate - frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA - is enable, this bit is ignored and the divisor used will be 16. -
- 0 = - (BCLK = SCLK / 4) -
- 1 = (BCLK = SCLK / 16) -
- This bit will be - masked to '0' if debug host is enabled. - - - - - When set, the UART is in IrDA mode and the baud rate divisor - used is 16 (see UART Operation for details). -
- This bit will be - masked to '0' if debug host is enabled. - - - - - Controls the Uart_RTS output (not directly in auto flow control - mode). -
- 0 = the Uart_RTS will be inactive high -
- 1 = the Uart_RTS - will be active low -
- This bit will be masked to '1' if debug host is - enabled. - - - - - - - - - Enables the auto flow control. -
- In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0), - If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in - CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx - Fifo Level and AFC_Level in Triggers register). - Tx data flow is stopped If Uart_CTS become inactive high. -
- If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS - bit in CMD_Set register. Uart_CTS will not take effect. -
-
- In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0), - If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit - in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx - Fifo Level and AFC_Level in Triggers register). -
- If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit - in CMD_Set register. Tx data flow will be stoped when XOFF is received either - this bit is enable or disabled. -
-
- This bit will be masked to '1' if debug host is enabled. - - - - When set, data on the Uart_Tx line is held high, while the - serial output is looped back to the serial input line, internally. In - this mode all the interrupts are fully functional. This feature is used - for diagnostic purposes. Also, in loop back mode, the modem control - input Uart_CTS is disconnected and the modem control output Uart_RTS are - looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is - inverted (see IrDA SIR Mode Support). - - - - Allow to stop the data receiving when an error is detected - (framing, parity or break). The data in the fifo are kept. -
- This bit - will be masked to '0' if debug host is enabled. - - - - - - HST TXD output enable. '0' enable. - - - - - - Length of a break, in number of bits. -
- This bit will be masked - to "1011" if debug host is enabled. - - - - - - - - - - Those bits indicate the number of data available in the Rx - Fifo. Those data can be read. - - - - - - - Those bits indicate the number of data available in the Tx - Fifo. Those data will be sent. - - - This bit indicates that the UART is sending data. If no data is - in the fifo, the UART is currently sending the last one through the - serial interface. - - - This bit indicates that the UART is receiving a byte. - - - This bit indicates that the receiver received a new character - when the fifo was already full. The new character is discarded. This bit - is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the user tried to write a character when fifo was - already full. The written data will not be kept. This bit is cleared when - the UART_STATUS register is written with any value. - - - This bit is set if the parity is enabled and a parity error - occurred in the received data. This bit is cleared when the UART_STATUS - register is written with any value. - - - This bit is set whenever there is a framing error occured. A - framing error occurs when the receiver does not detect a valid STOP bit - in the received data. This bit is cleared when the UART_STATUS register - is written with any value. - - - This bit is set whenever the serial input is held in a logic 0 - state for longer than the length of x bits, where x is the value - programmed Rx Break Length. A null word will be written in the Rx Fifo. - This bit is cleared when the UART_STATUS register is written with any - value. - - - - In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), - This bit is set when the Uart_CTS line changed since the last - time this register has been written. -
- In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), - This bit is set when received XON/XOFF status changed since the last time - this register has been writtern. -
- This bit is cleared when the UART_STATUS register is written with any value. - - - - - In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), - current value of the Uart_CTS line. -
- '1' = Tx not allowed. -
- '0' = Tx allowed. -
- In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), - current state of software flow control. -
- '1' = when XOFF received. -
- '0' = when XON received. - - - - This bit is set when Tx Fifo Reset command is received by CTRL - register and is cleared when Tx fifo reset process has finished. - - - This bit is set when Rx Fifo Reset command is received by CTRL - register and is cleared when Rx fifo reset process has finished. - - - This bit is set when bit enable is changed from '0' to '1' or - from '1' to '0', it is cleared when the enable process has finished. - - - This bit is set when Uart Clk has been enabled and received by - UART after Need Uart Clock becomes active. It serves to avoid enabling - Rx RTS too early. - - - - - The UART_RECEIVE_BUFFER register is a read-only register that - contains the data byte received on the serial input port. This register - accesses the head of the receive FIFO. If the receive FIFO is full and - this register is not read before the next data character arrives, then - the data already in the FIFO will be preserved but any incoming data - will be lost. An overflow error will also occur. - - - The UART_TRANSMIT_HOLDING register is a write-only register - that contains data to be transmitted on the serial output port. 16 - characters of data may be written to the UART_TRANSMIT_HOLDING register - before the FIFO is full. Any attempt to write data when the FIFO is full - results in the write data being lost. - - - - - Clear to send signal change or XON/XOFF detected. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. - - - Pulse detected on Uart_Dma_Tx_Done_H signal. - - - Pulse detected on Uart_Dma_Rx_Done_H signal. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - - - - - - - Clear to send signal detected. Reset control: This bit is - cleared when the UART_STATUS register is written with any value. - - - Rx Fifo at or upper threshold level (current level >= Rx - Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER - until the Fifo drops below the trigger level. - - - Tx Fifo at or below threshold level (current level <= Tx - Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING - register above threshold level. - - - No characters in or out of the Rx Fifo during the last 4 - character times and there is at least 1 character in it during this - time. Reset control: Reading from the UART_RECEIVE_BUFFER register. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break - Interrupt. Reset control: This bit is cleared when the UART_STATUS - register is written with any value. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. - - - This interrupt is generated when a pulse is detected on the - Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. - - - In DMA mode, there is at least 1 character that has been read - in or out the Rx Fifo. Then before received Rx DMA Done, No characters - in or out of the Rx Fifo during the last 4 character times. - - - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - - - - - - Defines the threshold level at which the Data Available - Interrupt will be generated. -
- The Data Available interrupt is - generated when quantity of data in Rx Fifo > Rx Trigger. - - - - - Defines the threshold level at which the Data Needed - Interrupt will be generated. -
- The Data Needed Interrupt is generated - when quantity of data in Tx Fifo <= Tx Trigger. - - - - - Controls the Rx Fifo level at which the Uart_RTS Auto Flow - Control will be set inactive high (see UART Operation for more details - on AFC). -
- The Uart_RTS Auto Flow Control will be set inactive high - when quantity of data in Rx Fifo > AFC Level. - - - - - - XON1 character value. Reset Value is CTRL-Q 0x11. - - - XOFF1 character value. Reset Value is CTRL-S 0x13 - - - XON2 character value. - - - XOFF2 character value. - - These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. - - - - - - - - general used register security visit enable -0:security -1:unsecurity - - - response error stop function enable -0:enable -1:disable - - - the number of outstanding that can be send out -0: 2 -1: 3 -2: 4 - - - multe-channel transport priority mode control -0: there is no priority in the channels, using polling to DMA data -1: smaller channel number has high-priority.high-priority move data before low-priority channels - - - interrupt control bit -0: no interruption occurs when all logical channels finish -1: interruption occurs when all logical channels finish - - - the control bit of logical channel transport finish -0: don't stop all the channel,or automatically clear after setting -1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared - - - - - in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. - - - - - stop status -0: not finish -1: finish - - - the channel number of the final transmission -0000: channel 0 just finished the transmission -0001: channel 1 just finished the transmission -0010: channel 2 just finished the transmission -...... -1011: channel 11 just finished the transmission -others: nonentity - - - - - logic channel stop interrupt status - - - channel 11 interrupts state -0: the channel 11 has not been interrupted, or the interrupt bit has been cleared -1: channel 11 is interrupted - - - channel 10 interrupts state -0: the channel 10 has not been interrupted, or the interrupt bit has been cleared -1: channel 10 is interrupted - - - channel 9 interrupts state -0: the channel 9 has not been interrupted, or the interrupt bit has been cleared -1: channel 9 is interrupted - - - channel 8 interrupts state -0: the channel 8 has not been interrupted, or the interrupt bit has been cleared -1: channel 8 is interrupted - - - channel 7 interrupts state -0: the channel 7 has not been interrupted, or the interrupt bit has been cleared -1: channel 7 is interrupted - - - channel 6 interrupts state -0: the channel 6 has not been interrupted, or the interrupt bit has been cleared -1: channel 6 is interrupted - - - channel 5 interrupts state -0: the channel 5 has not been interrupted, or the interrupt bit has been cleared -1: channel 5 is interrupted - - - channel 4 interrupts state -0: the channel 4 has not been interrupted, or the interrupt bit has been cleared -1: channel 4 is interrupted - - - channel 3 interrupts state -0: the channel 3 has not been interrupted, or the interrupt bit has been cleared -1: channel 3 is interrupted - - - channel 2 interrupts state -0: the channel 2 has not been interrupted, or the interrupt bit has been cleared -1: channel 2 is interrupted - - - channel 1 interrupts state -0: the channel 1 has not been interrupted, or the interrupt bit has been cleared -1: channel 1 is interrupted - - - channel 0 interrupts state -0: the channel 0 has not been interrupted, or the interrupt bit has been cleared -1: channel 0 is interrupted - - - - - state of IRQ 23 generate requests of moving data -0: IRQ 23 does not generate requests of moving data -1: IRQ 23 generate requests of moving data - - - state of IRQ 22 generate requests of moving data -0: IRQ 22 does not generate requests of moving data -1: IRQ 22 generate requests of moving data - - - state of IRQ 21 generate requests of moving data -0: IRQ 21 does not generate requests of moving data -1: IRQ 21 generate requests of moving data - - - state of IRQ 20 generate requests of moving data -0: IRQ 20 does not generate requests of moving data -1: IRQ 20 generate requests of moving data - - - state of IRQ 19 generate requests of moving data -0: IRQ 19 does not generate requests of moving data -1: IRQ 19 generate requests of moving data - - - state of IRQ 18 generate requests of moving data -0: IRQ 18 does not generate requests of moving data -1: IRQ 18 generate requests of moving data - - - state of IRQ 17 generate requests of moving data -0: IRQ 17 does not generate requests of moving data -1: IRQ 17 generate requests of moving data - - - state of IRQ 16 generate requests of moving data -0: IRQ 16 does not generate requests of moving data -1: IRQ 16 generate requests of moving data - - - state of IRQ 15 generate requests of moving data -0: IRQ 15 does not generate requests of moving data -1: IRQ 15 generate requests of moving data - - - state of IRQ 14 generate requests of moving data -0: IRQ 14 does not generate requests of moving data -1: IRQ 14 generate requests of moving data - - - state of IRQ 13 generate requests of moving data -0: IRQ 13 does not generate requests of moving data -1: IRQ 13 generate requests of moving data - - - state of IRQ 12 generate requests of moving data -0: IRQ 12 does not generate requests of moving data -1: IRQ 12 generate requests of moving data - - - state of IRQ 11 generate requests of moving data -0: IRQ 11 does not generate requests of moving data -1: IRQ 11 generate requests of moving data - - - state of IRQ 10 generate requests of moving data -0: IRQ 10 does not generate requests of moving data -1: IRQ 10 generate requests of moving data - - - state of IRQ 9 generate requests of moving data -0: IRQ 9 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 8 generate requests of moving data -0: IRQ 8 does not generate requests of moving data -1: IRQ 8 generate requests of moving data - - - state of IRQ 7 generate requests of moving data -0: IRQ 7 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 6 generate requests of moving data -0: IRQ 6 does not generate requests of moving data -1: IRQ 6 generate requests of moving data - - - state of IRQ 5 generate requests of moving data -0: IRQ 5 does not generate requests of moving data -1: IRQ 5 generate requests of moving data - - - state of IRQ 4 generate requests of moving data -0: IRQ 4 does not generate requests of moving data -1: IRQ 4 generate requests of moving data - - - state of IRQ 3 generate requests of moving data -0: IRQ 3 does not generate requests of moving data -1: IRQ 3 generate requests of moving data - - - state of IRQ 2 generate requests of moving data -0: IRQ 2 does not generate requests of moving data -1: IRQ 2 generate requests of moving data - - - state of IRQ 1 generate requests of moving data -0: IRQ 1 does not generate requests of moving data -1: IRQ 1 generate requests of moving data - - - state of IRQ 0 generate requests of moving data -0: IRQ 0 does not generate requests of moving data -1: IRQ 0 generate requests of moving data - - - - - state of ACK 23 generate requests of moving data -0: ACK 23 does not generate requests of moving data -1: ACK 23 generate requests of moving data - - - state of ACK 22 generate requests of moving data -0: ACK 22 does not generate requests of moving data -1: ACK 22 generate requests of moving data - - - state of ACK 21 generate requests of moving data -0: ACK 21 does not generate requests of moving data -1: ACK 21 generate requests of moving data - - - state of ACK 20 generate requests of moving data -0: ACK 20 does not generate requests of moving data -1: ACK 20 generate requests of moving data - - - state of ACK 19 generate requests of moving data -0: ACK 19 does not generate requests of moving data -1: ACK 19 generate requests of moving data - - - state of ACK 18 generate requests of moving data -0: ACK 18 does not generate requests of moving data -1: ACK 18 generate requests of moving data - - - state of ACK 17 generate requests of moving data -0: ACK 17 does not generate requests of moving data -1: ACK 17 generate requests of moving data - - - state of ACK 16 generate requests of moving data -0: ACK 16 does not generate requests of moving data -1: ACK 16 generate requests of moving data - - - state of ACK 15 generate requests of moving data -0: ACK 15 does not generate requests of moving data -1: ACK 15 generate requests of moving data - - - state of ACK 14 generate requests of moving data -0: ACK 14 does not generate requests of moving data -1: ACK 14 generate requests of moving data - - - state of ACK 13 generate requests of moving data -0: ACK 13 does not generate requests of moving data -1: ACK 13 generate requests of moving data - - - state of ACK 12 generate requests of moving data -0: ACK 12 does not generate requests of moving data -1: ACK 12 generate requests of moving data - - - state of ACK 11 generate requests of moving data -0: ACK 11 does not generate requests of moving data -1: ACK 11 generate requests of moving data - - - state of ACK 10 generate requests of moving data -0: ACK 10 does not generate requests of moving data -1: ACK 10 generate requests of moving data - - - state of ACK 9 generate requests of moving data -0: ACK 9 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 8 generate requests of moving data -0: ACK 8 does not generate requests of moving data -1: ACK 8 generate requests of moving data - - - state of ACK 7 generate requests of moving data -0: ACK 7 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 6 generate requests of moving data -0: ACK 6 does not generate requests of moving data -1: ACK 6 generate requests of moving data - - - state of ACK 5 generate requests of moving data -0: ACK 5 does not generate requests of moving data -1: ACK 5 generate requests of moving data - - - state of ACK 4 generate requests of moving data -0: ACK 4 does not generate requests of moving data -1: ACK 4 generate requests of moving data - - - state of ACK 3 generate requests of moving data -0: ACK 3 does not generate requests of moving data -1: ACK 3 generate requests of moving data - - - state of ACK 2 generate requests of moving data -0: ACK 2 does not generate requests of moving data -1: ACK 2 generate requests of moving data - - - state of ACK 1 generate requests of moving data -0: ACK 1 does not generate requests of moving data -1: ACK 1 generate requests of moving data - - - state of ACK 0 generate requests of moving data -0: ACK 0 does not generate requests of moving data -1: ACK 0 generate requests of moving data - - - - - - channel 11 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 10 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 9 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 8 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 7 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 6 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 5 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 4 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 3 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 2 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 1 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 0 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0:disable -1:enable - - - security visit -0:security -1:unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -...... -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -...... -01111: IRQ15 trigger transmission -...... -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0:unset -1:set - - - bit type is changed from w1c to rc. - response error status -0:unset -1:set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -...... -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -...... -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - - - - - 1 - fix src address - 0 - increament src address - - - 1 - fix dst address - 0 - increament dst address - - - 0 - 1 byte - 1 - 2 byte - 2 - 4 byte - - - write cycles - - - 0 - normal dma mode - 1 - dma aes encode mode - 5 - dma aes decode mode - 2 - dma crc mode - - - - - source dma address - - - - - destination dma address - - - - - number of hsizem - - - - - crc generator, MSB aligned - - - - - --no-use 0 - crc8 1 - crc16 3 - crc32 - - - bit0 - input byte reverse - bit1 - input bit reverse - bit2 - output byte reverse - bit3 - output bit reverse - - - aes engine clk on - - - aes key generator clk on - - - crc engine clk on - - - trng engine clk on - - - - - aes key bit 31:0 - - - - - aes key bit 63:32 - - - - - aes key bit 95:64 - - - - - aes key bit 127:96 - - - - - aes iv bit 31:0 - - - - - aes iv bit 63:32 - - - - - aes iv bit 95:64 - - - - - aes iv bit 127:96 - - - - - 1 - CBC mode - 0 - ECB mode - - - 1 - start aes key calc - 0 - after start calc, need written to 0 - - - 1 - aes key calc started by every 32bit key change - 0 - aes key calc started by mode[1] :default - - - - - Not used. The mac rd/wr fifo mem used by cios - - - 0: 3'b000 - 1k 28bit mode - 4: 3'b100 - 2k 28bit mode - 1: 3'b001 - 1k 31bit mode - 5: 3'b101 - 2k 31bit mode - 2: 3'b010 - 1k 32bit mode - 6: 3'b110 - 2k 32bit mode - - - 1 - cios ram can be accessed only by ahb bus - 0 - when cios ram input data completely writed by bus, then accessed by cios engine - when engine accessed completely, then accessed by bus - - - cios clk on - - - 0 - cios start by cios_ctrl[7] - 1 - cios auto start when mod_N load done. - - - 1 - write 1'b1 to start cios compute. - 0 - after start compute, need written to 0 - - - - - cios reg - - - - - crc initial value, MSB aligned - - - - - crc output value xored value, LSB aligned - - - - - crc output value, LSB aligned - - - - - crc size: - 3'd0 - 8bit crc - 3'd1 - 16bit crc - 3'd2 - 32bit crc - - - - - low threshold to trigger ififo read from ahb - - - high threshold to switch ififo read to ofifo write - - - - - low threshold to switch ofifo write to ififo read - - - high threshold to trigger ofifo write to ahb - - - - - - interrupt output, write 1 for clear - bit0 - ahb dma done - bit1 - prng alert - bit2 - trng on fly test failed - bit3 - trng start test failed - bit4 - trng data ready - bit5 - cios done - - - - - interrupt mask, 1 for disable interrapt - bit0 - ahb dma done - bit1 - prng alert - bit2 - trng on fly test failed - bit3 - trng start test failed - bit4 - trng data ready - bit5 - cios done - - - - - - bit0 - trng enable - bit1 - trng mode, 1 for continualy mode, 0 for once - bit2 - trng start test enable - bit3 - trng on fly test enable - bit4 - trng source open - bit5 - trng test enable - bit6 - trng data mask enable - - - trng source mask - - - - - bit0 - prng enable - bit1 - prng seed load - bit2 - prng seed mode - bit3 - prng timer enable - - - - - prng seed - - - - - prng timer initial value * 2 - - - 0 - use 40m/32=1.25MHz clk to sample input data - 1 - use dma clk to sample input data - - - - - prng timer value - - - - - trng data0 - - - - - trng data0 mask - - - - - trng data1 - - - - - trng data1 mask - - - - - prng data - - - - - trng c value - - - trng h value - - - - - - When written to a one, the calculation starts. The complete and complete error bits - are cleared when this bit is written with a one. - - - Set to a one when the operation has completed. - - - When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the end byte of the message. - - - When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the starting byte of the message - - - 0x0 - SHA256 processing - 0x1 - SHA1 processing - 0x2 ~ 0xF - SHA1 processing - - - If set, and interrupt will be generated upon completion of message processing. - - - Swaps intra-word byte order of message words. If set byte addressing is Big Endian. - - - Swaps intra-word byte order of hash values. If set byte addressing is Big Endian. - - - Reserved. - - - The Command register was written with start=1 when the Message Length register held an illegal value. - No calculation was executed. - - - Reserved. - - - - - Starting Byte address of the message block in memory. - - - - - Byte Length of Message. Maximum of 256K - Message Address[1:0]. - - - - - HW state. Used for debug only. Umac Interface rd_counter. - - - - - HW state. Used for debug only. Umac Interface wr_counter. - - - - - HW state. Used for debug only. Umac Interface umac_state_c. - - - - - HW state. Used for debug only. Umac Interface sha_state_c. - - - - - - Write 1 to the bit to clear the Interrupt - - - - - Write 1 to the bit to enable SHA Interrupt - - - - - SAM Interrupt status - - - - - Write 1 to restart SHA module - - - - - - SHA Hash Values. The resulting message digest is the concatenation of H0. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H1. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H2. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H3. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H4. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H5. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H6. - - - - - SHA Hash Values. The resulting message digest is the concatenation of H7. - - - - - - Number of Message bytes processed. Maximum of 0x1FFF_FFFF. - Read for status or to save context. - Written to restore context. - - - - - - CIOS RAM Space -
- Used for CIOS Only. - - - - - - - - - Writing 1 starts block decode - - - - - AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset. - - - Decode error flag. Reading 1 indicates block decode error and Lzma should be reset. - - - Decode done flag. Reading 1 indicates block decode done, writing 1 clears. - - - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1 - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1 - - - Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1 - - - - - - - Lzma dictionary size in byte - - - lzma block size in byte - - - - - lzma zip stream lenght in byte - - - - - 1: refbyte enable; 0: refbyte disable - - - 1: cabac_movebits=5; 0: cabac_movebits=4 - - - 1: cabac_totalbits=11; 0: cabac_totalbits=10 - - - - - current decoding byte position in zip stream - - - - - current recovering byte position in dictionary - - - - - Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2) - - - Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size - - - Equals to 1 when a symbol is decoded as match type with length more than 273 - - - Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size - - - Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion - - - Equals to 1 when first symbol in a block is decoded as match type - - - Equals to 1 when zip stream reading byte position exceeds the stream length - - - - - - - - - Crc of lzma rdma read bytes - - - - - Crc of lzma wdma write bytes - - - - - - - - - Base address of lzma rdma - - - - - Base address of lzma wdma - - - - - Set the margin between input_buf wrptr and rdptr for pending the decode process - - - - - - - - - F8 -00 -01AES -10snow3G -11zuc - - - F8 -0F8 /group -1F8 /group - - - F8 -0F8 -1F8 - - - - - group - - - - - group - - - - - bit type is changed from w1c to rc. - 0F9 -1F9 - - - bit type is changed from w1c to rc. - 0F8/ -1F8/ - - - - - F9 -00AES -01AES -10snow3G -11zuc - - - F9 -0F9 /group -1F9 /group - - - F9 -0F9 -1F9 - - - - - F9 group - - - - - F9 - - - - - - - - - FSOE - - - SBWE - - - EDIS - - - SPEN - - - DISS - - - DISR - - - - - - MOD_NUMBER = F003H - - - REV_NUMBER = 20H - - - - - - Data Register (Bus address of buffer-32 GPRS_DATA registers are building the on-chip FIFO-buffer) - - - - - Overflow Status -Set to 1 by the GPRS unit when an overflow of the buffer occurs. -Can be reset by writing '0' to bit UFL. - - - Underflow Status -Set to 1 by the GPRS unit when an underflow of the buffer occurs. -Can be reset by writing '0' to bit UFL. - - - Overflow -By writing '0' to this bit, bit OFL_STAT will be reset. The current -overflow status can be read via bit OFL_STAT. - - - Write -Describes the number of on-chip buffer blocks which are free to be written by the microcontroller. -Note: If the XOR-combination is disabled by setting bit XOR_DIS in CTRL and ciphering is switched on by setting bit CIPH_CTRL in CTRL this bitfield is set to 0x00. - - - Underflow -By writing '0' to this bit, bit UFL_STAT will be reset. The current underflow status can be read via bit UFL_STAT. - - - Read -Describes the number of on-chip buffer blocks which have already been processed by the GPRS unit. These blocks can be read by the microcontroller. - - - - - MAC-I Bits [31:0] - - - - - - CIPH_CTRL Value for the Actual Block in Byte Count Mode -0 Ciphering switched off -1 Ciphering switched on -This bit is only valid for BC_EN = "1" (Byte count enabled)! - - - CRC_CTRL Value for Actual Block in Byte Count Mode -0 CRC calculation switched off, necessery for unprotected data stream -1 CRC calculation switched on -This bit is only valid for BC_EN = "1" (Byte count enabled)! - - - Byte Counter Value -Number of Bytes for the actual block. -Only valid if BC_EN = "1"! - - - - - Polynomial Bits [31:0] - - - - - FCS Bits [31:0] - - - - - FRESH Bits [31:0] - - - - - KC0 Bits [31:0] -GEA1/2: Cipher key. -GEA3/f8: Input CK to the core function KGCORE (see -Section 4.3.9). -f9: Integrity key IK. - - - - - KC1 Bits [31:0] -GEA1/2: Cipher key. -GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). -f9: Integrity key IK. - - - - - KC2 Bits [31:0] -GEA1/2: Cipher key. -GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). -f9: Integrity key IK. - - - - - KC3 Bits [31:0] -GEA1/2: Cipher key. -GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). -f9: Integrity key IK. - - - - - Input Key Bits [31:0] -GEA1/2: Input key for initialization. -GEA3/f8: Input CC[31:0] to the core function KGCORE (see Section 4.3.9). -f9: Frame dependent input Count-I[31:0]. - - - - - CB -Input CB[4:0] to the core function KGCORE (see Section 4.3.9). - - - CD -Input CD[0] to the core function KGCORE (see Section 4.3.9). -Note: For f8 and f9 calculation, this bit refers to the input -DIRECTION. - - - Input CA[7:0] -To the core function KGCORE (see Section 4.3.9). - - - Input CE[15:0] -To the core function KGCORE (see Section 4.3.9). - - - - - Length Bits [31:0] -Total number of bits of the input/output bit stream. - - - - - F9CAL Status -This bit is set by writing to bit F9CAL and reset by the GPRS block when the f9 calculation has finished. -After this bit is reset by the GPRS block, the MAC can be read by the CPU. -0 F9 calculation finished. -1 F9 calculation ongoing. - - - Offset -Indicates the size of the header part to be discarded for UMTS f8 - - - Initilisation Status -This bit is only valid for MIN_INT="1"! -This bit is set by writing to bit INT_EN and reset by the GPRS block. -0 GPRS_INT0 generation not enabled. -1 GPRS_INT0 generation enabled. - - - XOR Disable -By setting this bit, the XOR combination of input data and keystream will be omitted. This bit is valid only for f8 ciphering. -0 XOR combination enabled. -If CIPH_CTRL = '0' the GPRS unit can be used DMA copy with bit-shifting. Data register DATA is used for writing the input bit stream. -1 XOR combination disabled. -If CIPH_CTRL = '1' no input bit stream has to be written to the data register DATA. The produced keystream can be read from register DATA. -Note: This bit in combination with CIPH_CTRL has effect on the DMA BUFIN request generation (see Table 18 and Table 19) - - - GEA3 UMTS Mode -0 GEA3 or UMTS mode not enabled (default). GEA1 or GEA2 mode will be used according to the settings in bit MODE. -1 GEA3 or UMTS mode enabled. GEA3/UMTS f8 or UMTS f9 will be used according to the settings in bit MODE. -Note: For GEA3 or UTMS f8 mode additionally bit MODE has to be set to '0' . For UMTS f9 mode bit MODE has to be set to '1' (see Table 21). - - - Initilisation Status -This bit is set by writing to bit INIT and reset by the GPRS block. After this bit is reset by the GPRS block, processing of GPRS_DATA is automatically started. During initialisation GPRS_DATA processing is blocked. -0 Initialisation finished. -1 Initialisation ongoing. - - - F9 Calculation Bit -The f9 calculation bit can be set to "1" by the MCU before data for a new f9 calculation is written to the GPRS unit. The status of the f9 calculation can be read via bit F9CAL_STAT. -0 No effect. -1 Start the indicator for f9 operation. - - - FIFO Flush -0 No operation (default) -1 Data FIFO DATA is flushed. (This bit need not be reset by software.) - - - Burse Size -000 Burst Size 1 (default) -001 Burst Size 4 -010 Burst Size 8 -011 Burst Size 16 -100 Burst Size 32 - - - Byte Count Enable -0 Byte count feature disabled (default) -1 Byte count feature enabled - - - Buffer In Enable -0 GPRS_BUFIN/GPRS_INT1 not generated (default) -1 GPRS_BUFIN/GPRS_INT1 generation if: -WR in STAT >= BURSTSIZE if XOR_DIS = '0' or -The bit counter in UMTS f8 mode has reached the value programmed in register LENGTH if XOR_DIS = '1' and CIPH_CTRL = '1'.For details on programming this bit please check Table 18 and Table 19. - - - Buffer Out Enable -This bit is only valid for MIN_INT="1"! -0 GPRS_BUFOUT not generated (default) -1 GPRS_BUFOUT generation if: -RD in STAT >= BURSTSIZE or BCCC is worked out (only for BC_EN="1") For details on programming this bit please check Table 18. - - - Interrupt Enable -This bit is only valid for MIN_INT="1"! -The status of this bit can be read via bit INT_STAT. -0 GPRS_INT0 not generated (default) -1 GPRS_INT0 generation if: WR+RD in STAT = 32 (all data in DATA are processed) For details on programming this bit please check Table 18. -Note: This bit must not be set for DMA transfers! - - - Minimized Interrupt -0 Minimized interrupt generation frequency disabled (default) -1 Minimized interrupt generation frequency enabled -For details on programming this bit please check Table 18. - - - Mode -0 GEA1 ciphering mode if bit GEA3_UMTS is '0' (default) -1 GEA2 ciphering mode if bit GEA3_UMTS is '0' -Note: This bit performs different if bit GEA3_UMTS is set! In GEA3/UMTS f8 mode this bit must be '0', in UMTS f9 mode '1' (see Table 21). - - - Cipher Control -This bit is only valid for BC_EN = "0" (Byte count disabled)! -0 Ciphering switched off -1 Ciphering switched on -Notes: -1. This bit has to be set in all cipher modes (GPRS, UMTS) if the corresponding algorithm (GEA1/2/3, f8) shall be performed! -2. This bit in combination with XOR_DIS has effect on the DMA BUFIN request generation (see Table 18 and Table 19) - - - CRC Control -This bit is only valid for BC_EN = "0" (Byte count disabled)! -0 CRC calculation switched off, necessary for unprotected data stream -1 CRC calculation switched on -Note: As the CRC was originally implemented for GPRS mode, it is not recommended to use CRC in UMTS mode! - - - Initialisation Bit -The initialisation bit is set to "1" by the MCU. -The status of this bit can be read via bit INIT_STAT -0 No operation -1 Start of initialization Direction -Selects the encoding resp. decoding procedure for GEA1 and GEA2 -0 Uplink channel -1 Downlink channel -Note: In the UMTS f8 case this bit also indicates how the bitfield OFFSET operates on the ciphering process. - - - - - - Request Flag Set Bit -0 No action -1 Set request flag SRR (no action if CLRR = 1) -Written value is not stored. Read returns 0. - - - Request Flag Clear Bit -0 No action -1 Clear request flag SRR (no action if SETR = 1) -Written value is not stored. Read returns 0. - - - Service Request Flag -0 No service request pending -1 A service request is pending - - - Service Request Enable Control -0 Service request is disabled -1 Service request is enabled - - - Type-of-Service Control -0 Request CPU service (Service Provider 0) -1 Request DMA service (Service Provider 1) -Not all SRN can request DMA service. See column DMA Support in Table Interrupt -Source List - - - - - Request Flag Set Bit -0 No action -1 Set request flag SRR (no action if CLRR = 1) -Written value is not stored. Read returns 0. - - - Request Flag Clear Bit -0 No action -1 Clear request flag SRR (no action if SETR = 1) -Written value is not stored. Read returns 0. - - - Service Request Flag -0 No service request pending -1 A service request is pending - - - Service Request Enable Control -0 Service request is disabled -1 Service request is enabled - - - Type-of-Service Control -0 Request CPU service (Service Provider 0) -1 Request DMA service (Service Provider 1) -Not all SRN can request DMA service. See column DMA Support in Table Interrupt -Source List - - - - - - - - - Maximum output width in pixels - - Number of bits coding position in virtual screen - - Number of bits of fractional part of internal fixed point values - - Number of bits of internal fixed point values - - Number of bits for stride storage - - - - - Starts the image transfer. Autoreset - - - - - High while image accelerator is busy - - - High while LCD controller is busy - - - - - - High when End Of Frame IRQ has been generated. -
- To clear it, write 1 in this bit or in eof_status. - - - - - Unmasked version of eof_cause. -
- To clear it, write 1 in this bit or in eof_status. - - - - - - - EOF interrupt generation mask: -
- 0: EOF IRQ disabled -
- 1: EOF IRQ enabled - - - - - - LCD Region Of Interest Top-Left pixel x-axis - - - LCD Region Of Interest Top-Left pixel y-axis - - - - - LCD Region Of Interest Bottom-Right pixel x-axis - - - LCD Region Of Interest Bottom-Right pixel y-axis - - - - - Blue component of the ROI background color - - - Green component of the ROI background color - - - Red component of the ROI background color - - - - - - Input image format -
- 00b: RGB565 pixel packed -
- 01b: YUV4:2:2 pixel packed (UYVY) -
- 10b: YUV4:2:2 pixel packed (YUYV) -
- 11b: YUV4:2:0 planar (IYUV) - - - - - Image stride in bytes (of Y component for planar formats). -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Defines Layer's activity: -
- 0: Layer disabled -
- 1: Layer active - - - - - - Video Layer (layer 0) Top-Left pixel x-axis position - - - Video Layer (layer 0) Top-Left pixel y-axis position - - - - - Video Layer (layer 0) Bottom-Right pixel x-axis position - - - Video Layer (layer 0) Bottom-Right pixel y-axis position - - - - - Number of lines of source image (idem gd_vl_br_ppos.y1 when - vertical scaling factor is one). - - - Number of columns of source image (idem gd_vl_br_ppos.x1 when - vertical scaling factor is one). - - - - - Blue component of the Chroma Key - - - - - - Green component of the Chroma Key - - - - - - Red component of the Chroma Key - - - - - - - - - - - Enables the Chroma Keying - - - - - - - Allows a range of color for the Chroma Keying: -
- 000b: exact color match -
- 001b: disregard 1 LSBit of each color component for matching -
- 011b: disregard 2 LSBit of each color component for matching -
- 111b: disregard 3 LSBit of each color component for matching - - - - - - - Layer Alpha blending coefficient - - - - - - - Layer rotation selection -
- 00b: No rotation -
- 01b: 90 degrees rotation (clockwise) -
- 10b: reserved -
- 11b: reserved - - - - - - - - Layer depth -
- 00b: Video layer behind all Overlay layers -
- 01b: Video layer between Overlay layers 1 and 0 -
- 10b: Video layer between Overlay layers 2 and 1 -
- 11b: Video layer on top of all Overlay layers - - - - - - - - - Dword-aligned address of the Y component (or RGB) of the source image - - - - - Dword-aligned address of the U component of the source image - - - - - Dword-aligned address of the V component of the source image - - - - - Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. - - - - The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn. - - - - Input image format -
- 0: RGB565 pixel packed -
- 1: ARGB8888 pixel packed -
- others: reserved - - - - - Image stride in 16-bits word. -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Image stride in 16-bits word. -
- This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). - - - - - Defines Layer's activity: -
- 0: Layer disabled -
- 1: Layer active - - - - - - Overlay Layer (layer X+1) Top-Left pixel x-axis position - - - Overlay Layer (layer X+1) Top-Left pixel y-axis position - - - - - Overlay Layer (layer X+1) Bottom-Right pixel x-axis position - - - Overlay Layer (layer X+1) Bottom-Right pixel y-axis position - - - - - Blue component of the Chroma Key - - - Green component of the Chroma Key - - - Red component of the Chroma Key - - - - - - - - Enables the Chroma Keying - - - - Allows a range of color for the Chroma Keying: -
- 000b: exact color match -
- 001b: disregard 1 LSBit of each color component for matching -
- 011b: disregard 2 LSBit of each color component for matching -
- 111b: disregard 3 LSBit of each color component for matching - - - - Layer Alpha blending coefficient - - - - - Dword-aligned address of the source image - - - - - - Destination Selection - - - - - - Output format -
- 000b: 8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB -
- 001b: 8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB -
- 010b: 8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB -
- 011b: reserved -
- 100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB -
- 101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB -
- 110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB -
- 111b: 32-bit - RGB5:6:5 - 1cycle/2pixel - RRRRRGGGGGGBBBBB/RRRRRGGGGGGBBBBB -
-
- The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected. -
- Must set to RGB565 when RAM type destination selected - - - - - - - - - Change Polarity of CS0 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of CS1 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RS signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of WR signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RD signal -
- 0: no change -
- 1: Inverted - - - - Number of command to be send to the LCD command (up to 31) - - - Start command transfer only. Autoreset - - - LCD reset signal. Low active - - - - All value are in cycle number of system clock - - Address setup time (RS to WR, RS to RD) - - - Adress hold time - - - Pulse Width Low level, between 2 and 63. - - - Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). - - - - - - Address destination pointer when memory destination is selected. -
- The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. - - - - - - - Address offset (in Bytes) skipped at the end of each line when memory destination is selected. -
- This 2D feature allows for in-memory image compositing. - - - - - - data to write or data readen (the readen data is ready when the lcd is not busy) - - - - Acesss type selection -
- 0: Command -
- 1: Data - - - - Start a single write access. Autoreset - - - Start a single read access (only when LCD output selected). Autoreset. - - - - - - - - - - - - - - - - - - - - - - - - 0:4 line mode - 1:3 line mode - 2:command mode - 3:3 line 2 lane mode tx - - - - - - - - - - - - - - - - - - - - - - - - - - Mirror enable. - - - . - - - . - - - . - - - . - - - - - - Count value to detect vsync pulse - - - 0:vsync te only 1:vsync and hsync te - - - Pol select - - - Te enable. - - - - - Te counter value - - - - - - - - - - - Gouda internal Sram space - - - - - - - - - Starts the image transfer. Autoreset - - - - - High while image accelerator is busy - - - High while LCD controller is busy - - - - - - High when End Of Frame IRQ has been generated. -
- To clear it, write 1 in this bit or in eof_status. - - - - Vsync rise interrupt. - - - Vsync fall interrupt - - - Dpi overflow interrupt - - - Frame over interrupt. - - - interrupt. - - - - Unmasked version of eof_cause. -
- To clear it, write 1 in this bit or in eof_status. - - - - - - - EOF interrupt generation mask: -
- 0: EOF IRQ disabled -
- 1: EOF IRQ enabled - - - - Vsync rise interrupt. - - - Vsync fall interrupt. - - - Dpi overflow interrupt. - - - Frame over interrupt. - - - Mipi interrupt - - - - - Destination Selection - - - - - - Output format, when Destination is Memory -
- 110b: 16-bit - RGB5:6:5 -
- 111b: 32-bit - ARGB8:8:8:8 - - - - - - exchange high byte and low byte, when output data bus width is 16 bit - - - - Change Polarity of CS0 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of CS1 signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RS signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of WR signal -
- 0: no change -
- 1: Inverted - - - - - Change Polarity of RD signal -
- 0: no change -
- 1: Inverted - - - - gamma enable - - - - output data bus width select,when use mcu port -
- 0: 16bit rgb565 -
- 1: 18bit rgb666 -
- 2: 24bit rgb888 - - - - - All value are in cycle number of system clock - - Address setup time (RS to WR, RS to RD) - - - Adress hold time - - - Pulse Width Low level, between 2 and 63. - - - Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). - - - - - - Address destination pointer when memory destination is selected. -
- The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. - - - - - - - Address offset (in Bytes) skipped at the end of each line when memory destination is selected. -
- This 2D feature allows for in-memory image compositing. - - - - - - data to write or data readen (the readen data is ready when the lcd is not busy) - - - - Acesss type selection -
- 0: Command -
- 1: Data - - - - Start a single write access. Autoreset - - - Start a single read access (only when LCD output selected). Autoreset. - - - - - - - - - - - - - - - - - - - - - - - - 0:4 line mode - 1:3 line mode - 2:command mode - 3:3 line 2 lane mode tx - - - - - - - - - - - - - - - - - - - For vsync to hsync setup. - - - whether wait for data, when data is not ready for transfer - - - - - control outstanding number - - - - if this bit is enable and dsi is enable. lcdc will stop at the end of a frame. -
- this is used to send mipi cmd - - - - - control actions to take, when fifo underflow arise -
- bit0:control when fifo is underflow, output zero or data in the fifo. -
- 0:output data in the fifo -
- 1:output zero -
- bit1:whether clear fifo at the end of a frame, when fifo is underflow. -
- 0:not clear -
- 1:clear - - - - 0:24bit 1:16bit. 2:18bit - - - Mipi enable. - - - Rgb panel disable output data. - - - Rgb panel disable output clock. - - - Rgb panel disable output all. - - - 00:rgb565 01:rgb888 10:xrgb8888 11:rgbx8888. - - - 0:RGB 1:BGR. - - - Frame2 use. - - - Frame1 use. - - - Rgb panel enable. - - - - - - - Frame0 line step,in byte. - - - Frame 0 valid. - - - - - - - Frame1 line step,in byte. - - - Frame 1 valid. - - - - - - - Frame2 line step,in byte. - - - Frame 2 valid. - - - - - Vertical pix num. - - - Horizontal pix num. - - - - - Data fifo threshold when req axi. - - - Dpi fifo auto reset enable when occur overflow . - - - Dpi fifo reset. - - - - - Throttle period. delay time between read requests - - - Dpi dma throttle enable. - - - - - adjust dot clock phase. unit is fast dpi clock - - - Data enable pol. - - - Vsync pol. - - - Hsync pol. - - - Dot clock pol. - - - dot clock div. - - - - - vsync back porch + vsync display period. - - - vsync back porch num. - - - - - vsync low pulse width. - - - vsync period - 1. - - - - - hsync low pulse width. - - - hsync period -1. - - - - - data enable end. - - - data enable start. - - - - - - - - - - - - - - - - - - - - - - - - - 0:8bits to 6bits 1:8bits to 5bits - - - 0:8bits to 6bits 1:8bits to 5bits - - - 0:8bits to 6bits 1:8bits to 5bits - - - - 0: bypass mode -
- 1: 2x2 mode -
- 2: 4x4 mode -
- 3: lfsr mode - - - - - 0: bypass mode -
- 1: 2x2 mode -
- 2: 4x4 mode -
- 3: lfsr mode - - - - - 0: bypass mode -
- 1: 2x2 mode -
- 2: 4x4 mode -
- 3: lfsr mode - - - - - - - - - - - - - - - - - linear feedback shift register initial data - - - - - Count value to detect vsync pulse - - - 0:vsync te only 1:vsync and hsync te - - - Pol select - - - Te enable. - - - - - count hsync after vsync have been detected. - - - - - - Use to delay between rgb data over and fetch the next frame data. - - - .count by hclk - - - - - address - - - data will be write to address - - - - - address - - - data will be write to address - - - - - address - - - data will be write to address - - - - - - Dsi pll power up - - - Power up dsi - - - - - Enable digital dsi - - - - - - - - 1'b1: use the config register value 1'b0: use the compute value of controller - - - 2'b00: x1 2'b01: x2 2'b10: x4 2'b11: hz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - write '1' to clear sleep out done interrupt - - - write '1' to clear frame done interrupt - - - write '1' to clear rx te(tearing effect) interrupt - - - write '1' to clear rx fifo half full interrupt - - - write '1' to clear rx fifo overflow interrupt - - - write '1' to clear command queue tx end interrupt - - - write '1' to clear rx data end interrupt - - - write '1' to clear rx crc error interrupt - - - write '1' to clear rx ecc error interrupt - - - write '1' to clear rx bta timeout interrupt - - - write '1' to clear contention detect interrupt - - - - - sleep out done en - - - frame done en - - - rx te(tearing effect) en - - - rx fifo half full en - - - rx fifo overflow en - - - command queue tx end en - - - rx data end en - - - rx crc error en - - - rx ecc error en - - - rx bta timeout en - - - contention detect error en - - - - - clear the packet header stored in registers from lcd. auto-clear - - - Reset the read pointer of queue which store the long packet payload - - - Reset the write index of fifo which store the data read from lcd - - - Reset the read index of fifo which store the data read from lcd - - - - - rx fifo empty flag - - - sleep out done flag - - - frame done flag - - - rx te(tearing effect) flag - - - rx fifo half full flag - - - rx fifo overflow flag - - - command queue tx end flag - - - rx data end flag - - - rx crc error flag - - - rx ecc error flag - - - rx bta timeout flag - - - contention detect error flag - - - - - sleep out done cause - - - frame done cause - - - rx te(tearing effect) cause - - - rx fifo half full cause - - - rx fifo overflow cause - - - command queue tx end cause - - - rx data end cause - - - rx crc error cause - - - rx ecc error cause - - - rx bta timeout cause - - - contention detect error cause - - - - - - receive payload byte0~3 of long packet from lcd -
- [31:24]: byte3 -
- [23:16]: byte2 -
- [15:8]: byte1 -
- [7:0]: byte0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - receive payload of long packet from lcd stored in the FIFO. -
- The value indicates the word count of FIFO. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The value is to count the time that lprx0 and lpcd0 are not equal. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - config the transmission at cmd mode -
- [31:24]: data byte 1 of command -
- [23:16]: data byte 0 of command -
- [15:8]: data ID of command -
- [6:5]: cmd_type -
- 2'b00,01: short packet -
- 2'b10,11: long packet -
- [3:2]: 2'b00,2'b01: cmd_ddr_enable -
- enable to get long packet payload from ddr -
- 2'b10: cmd_buf_enable -
- enable to write frame buffer at cmd mode, only for high speed. -
- 2'b11: cmd_reg_enable -
- enable to get long packet payload from register -
- bit1: cmd_hs_enable -
- enable high-speed transmission -
- bit0: cmd_bta_enable -
- enable bta - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - config the transmission at cmd mode -
- [31:24]: data byte 1 of command -
- [23:16]: data byte 0 of command -
- [15:8]: data ID of command -
- [6:5]: cmd_type -
- 2'b00,01: short packet -
- 2'b10,11: long packet -
- [3:2]: 2'b00,2'b01: cmd_ddr_enable -
- enable to get long packet payload from ddr -
- 2'b10: cmd_buf_enable -
- enable to write frame buffer at cmd mode, only for high speed. -
- 2'b11: cmd_reg_enable -
- enable to get long packet payload from register -
- bit1: cmd_hs_enable -
- enable high-speed transmission -
- bit0: cmd_bta_enable -
- enable bta - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - config the transmission at cmd mode -
- [31:24]: data byte 1 of command -
- [23:16]: data byte 0 of command -
- [15:8]: data ID of command -
- [6:5]: cmd_type -
- 2'b00,01: short packet -
- 2'b10,11: long packet -
- [3:2]: 2'b00,2'b01: cmd_ddr_enable -
- enable to get long packet payload from ddr -
- 2'b10: cmd_buf_enable -
- enable to write frame buffer at cmd mode, only for high speed. -
- 2'b11: cmd_reg_enable -
- enable to get long packet payload from register -
- bit1: cmd_hs_enable -
- enable high-speed transmission -
- bit0: cmd_bta_enable -
- enable bta - - - - - - - read from lcd corresponding cmd queue index -
- [7:0]:DI -
- [15:8]: SP data0 or LP WC LS BYTE -
- [23:16]: SP data1 or LP WC MS BYTE -
- [24]: ack response -
- [25]: te response -
- [26]: lpdt response -
- [27]: ECC error flag -
- [28]: LP CRC error flag -
- [29]: Acknowledge and Error Report flag - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - read from lcd corresponding cmd queue index -
- [7:0]:DI -
- [15:8]: SP data0 or LP WC LS BYTE -
- [23:16]: SP data1 or LP WC MS BYTE -
- [24]: ack response -
- [25]: te response -
- [26]: lpdt response -
- [27]: ECC error flag -
- [28]: LP CRC error flag -
- [29]: Acknowledge and Error Report flag - - - - - - - - - - spi flash command to send. - - - spi flash address to send. - - - - - spi flash modebit,set 0xA0 to enable continuous read. - - - spi flash spi read/write block size. - - - - - - - spi flash data to send. - - - spi send byte, 1: quad send 0: spi send. - - - - - spi flash busy. - - - tx fifo empty. - - - tx fifo full. - - - rx fifo empty. - - - rx fifo data count. - - - read busy. - - - nand int . - - - spiflash_int = nand_int and nand_int_mask . - - - - - flash rx status. - - - - - spi flash read mode from AHB. - - - - - spi flash wprotect pin. - - - spi flash hold pin. - - - spi flash read sample delay cycles. - - - spi flash clock divider. - - - spi flash send command using quad lines. - - - - - - - rx fifo_clr,self clear. - - - tx fifo_clr,self clear. - - - - - spi flash cs num. - - - - - single chip spi flash size. - - - - - spi flash is 128m flash. - - - - - disable read from ahb. - - - - - sel flash 1, addr[24]. - - - - - addr[25]. - - - diff 128m diff cmd en. - - - spi_256m. - - - spi_512m. - - - spi_cs1_sel2. - - - spi_1g . - - - spi_2g. - - - spi_4g. - - - spi_cs1_sel3. - - - spi_cs1_sel4. - - - spi_cs1_sel5. - - - - - quad read command. - - - fast read command. - - - fast read command. - - - protect_byte, must be 0x55 when program this register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces: - 0 Group 1 interrupts not forward. - 1 Group 1 interrupts forwarded, subject to the priority rules. - - - Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces: - 0 Group 0 interrupts not forwarded. - 1 Group 0 interrupts forwarded, subject to the priority rules. - - - - - If the GIC implements the Security Extensions, the value of this field is the maximum number of - implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111), see Configuration lockdown on - page 4-82. If this field is 0b00000 then the GIC does not implement configuration lockdown. - If the GIC does not implement the Security Extensions, this field is reserved. - - - Indicates whether the GIC implements the Security Extensions. - 0 Security Extensions not implemented. - 1 Security Extensions implemented. - - - Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is - one more than the value of this field, for example if this field is 0b011, there are four CPU interfaces. - If the GIC implements the Virtualization Extensions, this is also the number of virtual CPU interfaces. - - - Indicates the maximum number of interrupts that the GIC supports. If ITLinesNumber=N, the - maximum number of interrupts is 32(N+1). The interrupt ID range is from 0 to (number of IDs C 1). - For example: - 0b00011 Up to 128 interrupt lines, interrupt IDs 0-127. - The maximum number of interrupts is 1020 (0b11111). See the text in this section for more information. - Regardless of the range of interrupt IDs defined by this field, interrupt IDs 1020-1023 are reserved for - special purposes. - - - - - Product ID - - - An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish product variants, - or major revisions of a product. - - - An IMPLEMENTATION DEFINED revision number. Typically, this field is used to distinguish minor revisions - of a product. - - - Contains the JEP106 code of the company that implemented the GIC Distributor: - Bits [11:8] The JEP106 continuation code of the implementer. For an ARM implementation, this field - is 0x4. - Bits [7] Always 0. - Bits [6:0] The JEP106 identity code of the implementer. For an ARM implementation, bits[7:0] are - 0x3B. - - - - - - The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC. - Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. - Accessible by Secure accesses Only. - For each bit: - 0 The corresponding interrupt is Group 0. - 1 The corresponding interrupt is Group 1.For interrupt ID m, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_IGROUPRn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_IGROUPR is (0x080 + (4*n)) - c. the bit number of the required group status bit in this register is m MOD 32. - - - - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - - - The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Enables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 - b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) - c.the bit number of the required Set-enable bit in this register is m MOD 32. - - - - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - - - The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the - GIC. - For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to - the CPU interfaces: - Reads 0 Forwarding of the corresponding interrupt is disabled. - 1 Forwarding of the corresponding interrupt is enabled. - Writes 0 Has no effect. - 1 Disables the forwarding of the corresponding interrupt. - After a write of 1 to a bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 - b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) - c.the bit number of the required Clear-enable bit in this register is m MOD 32. - - - - - - The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC. - For each bit: - Reads 0 The corresponding interrupt is not pending on any processor. - 1 a. For PPIs and SGIs, the corresponding interrupt is pendinga on this - processor. - b. For SPIs, the corresponding interrupt is pendinga on at least one - processor. - Writes For SPIs and PPIs: - 0 Has no effect. - 1 The effect depends on whether the interrupt is edge-triggered or - level-sensitive: - Edge-triggered - Changes the status of the corresponding interrupt to: - a.pending if it was previously inactive - b.active and pending if it was previously active. - Has no effect if the interrupt is already pending. - Level sensitive - If the corresponding interrupt is not pendinga, changes the status - of the corresponding interrupt to: - a. pending if it was previously inactive - b. active and pending if it was previously active. - If the interrupt is already pending: - a. because of a write to the GICD_ISPENDR, the write has - no effect. - b. because the corresponding interrupt signal is asserted, the - write has no effect on the status of the interrupt, but the - interrupt remains pendinga if the interrupt signal is - deasserted. - For SGIs, the write is ignored. SGIs have their own Set-Pending registers. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ISPENDR number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ISPENDR is (0x200 + (4*n)) - c. the bit number of the required Set-pending bit in this register is m MOD 32. - - - - - - The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. - For each bit: - Reads 0 The corresponding interrupt is not pending on any processor. - 1 a. For SGIs and PPIs, the corresponding interrupt is pendinga on this - processor. - b. For SPIs, the corresponding interrupt is pendinga on at least one - processor. - Writes For SPIs and PPIs: - 0 Has no effect. - 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: - Edge-triggered - Changes the status of the corresponding interrupt to: - a. inactive if it was previously pending - b. active if it was previously active and pending. - Has no effect if the interrupt is not pending. - Level-sensitive - If the corresponding interrupt is pendinga only because of a write to - GICD_ISPENDRn, the write changes the status of the interrupt to: - a. inactive if it was previously pending - b. active if it was previously active and pending. - Otherwise the interrupt remains pending if the interrupt signal - remains asserted. - For SGIs, the write is ignored. SGIs have their own Clear-Pending registers. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ICPENDR is (0x280 + (4*n)) - c. the bit number of the required Set-pending bit in this register is m MOD 32. - - - - - - The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports. - For each bit: - Reads 0 The corresponding interrupt is not active. - 1 The corresponding interrupt is active. - Writes 0 Has no effect. - 1 Activates the corresponding interrupt, if it is not already active. If the interrupt - is already active, the write has no effect. - After a write of 1 to this bit, a subsequent read of the bit returns the value 1. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ISACTIVERn is (0x300 + (4*n)) - c. the bit number of the required Set-active bit in this register is m MOD 32. - - - - - - The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC - supports. - For each bit: - Reads 0 The corresponding interrupt is not activea. - 1 The corresponding interrupt is activea. - Writes 0 Has no effect. - 1 Deactivates the corresponding interrupt, if the interrupt is active. If the - interrupt is already deactivated, the write has no effect. - After a write of 1 to this bit, a subsequent read of the bit returns the value 0. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICACTIVERn number, n, is given by n = m DIV 32 - b. the offset of the required GICD_ICACTIVERn is (0x380 + (4*n)) - c. the bit number of the required Clear-active bit in this register is m MOD 32. - - - - - - The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the - GIC. - Each priority field holds a priority value, from an IMPLEMENTATION DEFINED range. The lower the - value, the greater the priority of the corresponding interrupt. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_IPRIORITYRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_IPRIORITYRn is (0x400 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported - by the GIC.This field stores the list of target processors for the interrupt. That is, it holds - the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and - has sufficient priority. - GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns - a value that corresponds only to the processor reading the register. - Processors in the system number from 0, and each bit in a CPU targets field refers to the - corresponding processor. For example, a value of 0x3 means that the Pending - interrupt is sent to processors 0 and 1. - For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns - the number of the processor performing the read. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 - b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) - c. the byte offset of the required Priority field in this register is m MOD 4, where: - (1) byte offset 0 refers to register bits [7:0] - (2) byte offset 1 refers to register bits [15:8] - (3) byte offset 2 refers to register bits [23:16] - (4) byte offset 3 refers to register bits [31:24]. - - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. - For Int_config[1], the most significant bit, bit [2F+1], the encoding is: - 0 Corresponding interrupt is level-sensitive. - 1 Corresponding interrupt is edge-triggered. - Int_config[0], the least significant bit, bit [2F], reserved - For SGIs: - Int_config[1] Not programmable, RAO/WI. - For PPIs: - Int_config[1] Not programmable, RAZ/WI. - For SPIs: - Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value - to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) - c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits - [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. - - - - - - Asserted when the PPI inputs to the Distributor are active. - ID 31 nLEGACYIRQ signal - ID 30 Non-secure physical timer event - ID 29 Secure physical timer event - ID 28 nLEGACYFIQ signal - ID 27 Virtual timer event - ID 26 Hypervisor timer event - ID 25 Virtual maintenance interrupt. - - - - - Returns the status of the IRQS inputs on the Distributor. For each bit: - 0 IRQS is LOW - 1 IRQS is HIGH. - - - - - - The GICD_NSACRs enable Secure software to permit Non-secure software on a particular - processor to create and manage Group 0 interrupts. They provide an access control for each - implemented interrupt. - If the corresponding interrupt does not support configurable Non-secure access, the field is - RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted - when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible - values of the field are: - 0b00 No Non-secure access is permitted to fields associated with the corresponding - interrupt. - 0b01 Non-secure write access is permitted to fields associated with the corresponding - interrupt in the GICD_ISPENDRn registers. A Non-secure write access to - GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding - interrupt. - 0b10 Adds Non-secure write access permission to fields associated with the - corresponding interrupt in the GICD_ICPENDRn registers. Also adds - Non-secure read access permission to fields associated with the corresponding - interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers. - 0b11 Adds Non-secure read and write access permission to fields associated with the - corresponding interrupt in the GICD_ITARGETSRn registers. - The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are - RAZ/WI. - For interrupt ID m, when DIV and MOD are the integer division and modulo operations: - a. the corresponding GICD_NSACR number, n, is given by n = m DIV 16 - b. the offset of the required GICD_NSACRn is (0xE00 + (4*n)). - - - - - - Determines how the distributor must process the requested SGI: - 0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda. - 0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the - interrupt. - 0b10 Forward the interrupt only to the CPU interface of the processor that requested the - interrupt. - 0b11 Reserved. - - - When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the - interrupt. - Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example - CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be - forwarded to the corresponding interface. - If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any - CPU interface. - - - Implemented only if the GIC includes the Security Extensions. - Specifies the required security value of the SGI: - 0 Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the - SGI is configured as Group 0 on that interface. - 1 Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if - the SGI is configured as Group 1 on that interface. - This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an - SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write. - - - The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the - Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. - - - - - - The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source - processor combination. - For each bit: - Reads 0 SGI x from the corresponding processor is not pending. - 1 SGI x from the corresponding processor is pending. - Writes 0 Has no effect. - 1 Removes the pending state of SGI x for the corresponding processor. - For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_CPENDSGIR register number, n, is given by n = x DIV 4 - b. the offset of the required GICD_CPENDSGIR is (0xF10 + (4*n)); - c. the SGI Clear-pending field offset, y, is given by y = x MOD 4 - d. the required bit in the SGI x Clear-pending field is bit C. - - - - - The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and - source processor combination. - For each bit: - Reads 0 SGI x for the corresponding processor is not pendinga. - 1 SGI x for the corresponding processor is pendinga. - Writes 0 Has no effect. - 1 Adds the pending state of SGI x for the corresponding processor, - if it is not already pending. If SGI x is already pending for the - corresponding processor then the write has no effect. - For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and - modulo operations: - a. the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4 - b. the offset of the required GICD_SPENDSGIR is (0xF20 + (4*n)) - c. the SGI Set-pending field offset, y, is given by y = x MOD 4 - d. the required bit in the SGI x Set-pending field is bit C. - - - - - - Alias of EOImodeNS from the Non-secure copy of this register. - - - Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. In a GIC implementation - that includes the Security Extensions, this control applies only to Secure accesses, and the EOImodeNS - bit controls the behavior of Non-secure accesses to these registers: - 0 GICC_EOIR has both priority drop and deactivate interrupt functionality. Accesses to - the GICC_DIR are UNPREDICTABLE. - 1 GICC_EOIR has priority drop functionality only. GICC_DIR has deactivate interrupt - functionality. - - - Alias of IRQBypDisGrp1 from the Non-secure copy of this register. - - - Alias of FIQBypDisGrp1 from the Non-secure copy of this register. - - - When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass - IRQ signal is signaled to the processor: - 0 Bypass IRQ signal is signaled to the processor - 1 Bypass IRQ signal is not signaled to the processor. - - - When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass - FIQ signal is signaled to the processor: - 0 Bypass FIQ signal is signaled to the processor - 1 Bypass FIQ signal is not signaled to the processor. - - - Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts. - 0 To determine any preemption, use: - ? the GICC_BPR for Group 0 interrupts - ? the GICC_ABPR for Group 1 interrupts. - 1 To determine any preemption use the GICC_BPR for both Group 0 and Group 1 - interrupts. - - - Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or - the IRQ signal. - 0 Signal Group 0 interrupts using the IRQ signal. - 1 Signal Group 0 interrupts using the FIQ signal. - The GIC always signals Group 1 interrupts using the IRQ signal. - - - When the highest priority pending interrupt is a Group 1 interrupt, determines both: - ? whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID - ? whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or - returns a spurious interrupt ID. - 0 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR - or the GICC_HPPIR returns an Interrupt ID of 1022. A read of the GICC_IAR does - not acknowledge the interrupt, and has no effect on the pending status of the interrupt. - 1 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR - or the GICC_HPPIR returns the Interrupt ID of the Group 1 interrupt. A read of - GICC_IAR acknowledges and Activates the interrupt. - - - Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor: - 0 Disable signaling of Group 1 interrupts. - 1 Enable signaling of Group 1 interrupts. - - - Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor: - 0 Disable signaling of Group 0 interrupts. - 1 Enable signaling of Group 0 interrupts. - - - - - The priority mask level for the CPU interface. If the priority of an interrupt is higher than the - value indicated by this field, the interface signals the interrupt to the processor. - If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows: - 128 supported levels Bit [0] = 0. - 64 supported levels Bit [1:0] = 0b00. - 32 supported levels Bit [2:0] = 0b000. - 16 supported levels Bit [3:0] = 0b0000. - - - - - The value of this field controls how the 8-bit interrupt priority field is split into a group - priority field, used to determine interrupt preemption, and a subpriority field. - The minimum value of the Binary Point Register depends on which - security-banked copy is considered: - 0x2 Secure copy - 0x3 Non-secure copy - - - - - For SGIs in a multiprocessor implementation, this field identifies the processor that - requested the interrupt. It returns the number of the CPU interface that made the - request, for example a value of 3 means the request was generated by a write to the - GICD_SGIR on CPU interface 3. - For all other interrupts this field is RAZ. - - - The interrupt ID. - - - - - On a multiprocessor implementation, if the write refers to an SGI, this - the CPUID value from the corresponding GICC_IAR access. - In all other cases this field SBZ. - - - The Interrupt ID value from the corresponding GICC_IAR access. - - - - - The current running priority on the CPU interface. - - - - - On a multiprocessor implementation, if the PENDINTID field returns the ID of an - SGI, this field contains the CPUID value for that interrupt. This identifies the - processor that generated the interrupt. - In all other cases this field is RAZ. - - - The interrupt ID of the highest priority pending interrupt. See Table 4-42 on - page 4-144 for more information about the result of Non-secure reads of the - GICC_HPPIR when the GIC implements the Security Extensions. - - - - - A Binary Point Register for handling Group 1 interrupts. - - - - - CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that - requested the interrupt. It returns the number of the CPU interface that made the request, - for example a value of 3 means the request was generated by a write to the GICD_SGIR - on CPU interface 3. - For all other interrupts this field is RAZ. - - - Interrupt ID The interrupt ID. - - - - - On a multiprocessor implementation, when processing an SGI, this field must contain - the CPUID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, - access. - In all other cases this field SBZ. - - - The Interrupt ID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, - access. - - - - - On a multiprocessor implementation, if the PENDINTID field returns the ID of an - SGI, this field contains the CPUID value for that interrupt. This identifies the - processor that generated the interrupt. - In all other cases this field is RAZ. - - - The interrupt ID of the highest priority pending interrupt, if that interrupt is a Group 1 - interrupt. Otherwise, the spurious interrupt ID, 1023. - - - - - - Active Priorities Registers - - - - - - NonSecure Active Priorities Registers - - - - - - An IMPLEMENTATION DEFINED product identifier. - - - The value of this field depends on the GIC architecture version, as follows: - ? 0x1 for GICv1 - ? 0x2 for GICv2. - - - An IMPLEMENTATION DEFINED revision number for the CPU interface. - - - Contains the JEP106 code of the company that implemented the GIC CPU - interface: - Bits [11:8] The JEP106 continuation code of the implementer. - Bit [7] Always 0. - Bits [6:0] The JEP106 identity code of the implementer. - - - - - - For an SGI in a multiprocessor implementation, this field - identifies the processor that requested the interrupt. - For all other interrupts this field is RAZ. - - - The interrupt ID - - - - - - - - - - - - - - - Set the direction of the GPIO n. -
- 0 = output -
- 1 = - input - - - - - - 'Write '1' sets the corresponding GPIO pin as output. - - - - - 'Write '1' sets the corresponding GPIO pin as input. - - - - - When write, update the output value. When read, get the input - value. - - - - - Write '1' will set GPIO output value. When read, get the GPIO - output value. - - - - - 'Write '1' clears corresponding GPIO output value. When read, get the GPIO - output value. - - - - - 'Write '1' will set GPIO interrupt mask for rising edge and - level high. When read, get the GPIO interrupt mask for rising edge and - level high. - - - - - 'Write '1' will clear GPIO interrupt mask for rising edge and - level high. - - - - - 'Write '1' will clear GPIO interrupt. - - - - - Each bit represents if there is a GPIO interrupt - pending. - - - - - - - - - - - time for which GPIO0 is set to output mode, after a start read - DCON command is issued. -
- The output time = (OUT_TIME+1)*30.5us. - - - - - time for which GPIO0 should wait before reading DC_ON, after - a start read DCON command is issued. -
- The wait time = (WAIT_TIME+1)*30.5us. -
- NOTE: wait_time must be strictly greater than out_time; - - - - - interruption mode of GPIO0 in mode DC_ON detection. -
- - - - - - - - - - - Write '1' to set GPIO0 to charger DCON detect mode. - - - Write '1' to set GPO0 to charger watchdog mode. - - - Write '1' to clear charger DCON detect mode of GPIO0. - - - Write '1' to clear the charger watchdog mode of GPO0. - - - Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles. - - - - - 'Write '1' will set GPO output value. When read, get the GPO - output value. - - - - - 'Write '1' will clear GPO output value. When read, get the GPO - output value. - - - - - 'Write '1' will set GPIO interrupt mask for rising edge and - level high. When read, get the GPIO interrupt mask for rising edge and - level high. - - - - - 'Write '1' will clear GPIO interrupt mask for rising edge and - level high. - - - - - 'Write '1' will enable debounce mechanism. - - - - - 'Write '1' will disable debounce mechanism. - - - - - Write '1' will set interruption mode to level. - - - - - Write '1' will set interruption mode to edge - triggered. - - - - - - - - - I2C master enable, high active. - - - I2C master interrupt enable, high active. - - - - This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared. -
-
- Example: -
- PCLK_MOD is 52 MHz, desired SCL is 100 KHz. -
- Prescale = 52MHz / (5 * 100KHz) -1 = 103. - - - - - - - - - IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK. - - - IRQ status bit. - - - TIP, Transfer in progress. - '1' when transferring data. '0' when transfer complete. - - - AL,Arbitration lost. - This bit is set when the I2C master lost arbitration. - - - Busy,I2C bus busy. - '1' after START signal detected. - '0' after STOP signal detected. - - - RxACK, Received acknowledge from slave. - '1'= "No ACK" received. - '0'= ACK received. - - - - - - Byte to transmit via I2C. -
- for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit. -
- '1' = reading from slave. -
- '0' = writing to slave. - - - - Last byte received via I2C. - - - - - ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1'). - - - RD,read from slave, this bit is auto cleared. - - - STO,generate stop condition, this bit is auto cleared. - - - WR,write to slave, this bit is auto cleared. - - - STA,generate (repeated) start condition, this bit is auto cleared. - - - - - When write '1', clears a pending I2C interrupt. - - - - - - - - - - - - Write 0: disable pagespy; 1: enable pagespy - Read 0: pagespy idle; 1: pagespy active - - - - - Spy interface select, - 'b00: interface 0, 'b01: interface 1, - 'b10: interface 2, 'b11: interface 3. - - - Enable of One configured time monitor mode. - When timer reaches the time threshold, - this bit clear to 0 automatically. - - - Enable of long time continuously monitor mode. - - - Enable of a configured access threshold mode. - When accesses reaches the threshold, - this bit clear to 0 automatically. - - - Enable of address hit mode. - Once one access hit the configured address range, - this bit clear to 0 automatically. - - - enable monitoring write address hit. - - - enable monitoring read address hit. - - - - - - - - - high 28bit of start address of monitor. - - - - - high 28bit of end address of monitor. - - - - - enable timer reach threshold interrupt. - - - enable access reach threshold interrupt - - - enable access hit interrupt - - - - - In one configured time monitor mode, - when timer reach the time threshold, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - In long time continuously monitor mode, - when timer reach the time threshold, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - In the configured access threshold monitor mode, - when write access num reaches the threshold, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - In the configured access threshold monitor mode, - when read access num reaches the threshold, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - In the address hit monitor mode, - when one write access hit the address range, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - In the address hit monitor mode, - when one read access hit the address range, this interrupt source trigger. - Write 1: clear interrupt; 0: ignored - Read 1: the one has source triggerd; 0: not source triggerd - - - - - - - - - - - - - - - - - - - - - - - Write bytes when a monitor finishes in one configured time monitor mode - or long time continuously monitor mode. - - - - - Read bytes when a monitor finishes in one configured time monitor mode or - long time continuously monitor mode. - - - - - Current timer count value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - interrupt vector for all 16 pagespy channels - - - - - - - - - - Enable signal from1 Stage to 2 Stage: -1: 2 Stage work; -0: 2 Stage not work, HOLD state; - - - Inner Enable signal from 2 Stage -Control followed module : vad_2stg_probvad_2stg_para_update_feature_minvad_2stg_para_updatemean_adjust. -Not Control module vadflag_smooth. -1: Controlled modules work -0: Controlled modules not work - - - 1:vad_dma_req_h is valid -0:vad_dma_req_h is invalid - - - [18]:masked vadflag interrupt -[17]:masked wr_full interrupt -[16]:masked rd_empty interrupt - - - [14]:raw vadflag interrupt -[13]:raw wr_full interrupt -[12]:raw rd_empty interrupt - - - Force 2 Stage continue work -1: Force 2 Stage continue work -0: 2Stage normal work (depend vadflag..) - - - Interrupt clear -[10]:clear vadflag interrupt -[9]:clear wr_full interrupt -[8]:clear rd_empty interrupt - - - Enable frame vad_int_pulse(width is 500ns) - - - [18]:mask vadflag interrupt -[17]:mask wr_full interrupt -[16]:mask rd_empty interrupt - - - 1:write into mem data rate is 16K (hpf_out) -0:write into mem data rate is 8K(hbf_out) - - - 1:Probability four channel coeff(speech_means,noise_means,speech_std,noise_std) -0:Probability four channel coeff from para_update 4 channel output - - - 1:speech_means_adj[i] and noise_means_adj[i] of para_update input is fixed at 100 -0:speech_means_adj[i] and noise_means_adj[i] of para_update input is from means_adjust - - - 1:feature_min of noise_mean is fixed at 512 -0:feature_min of noise_mean is normal output - - - - - 1:bypass HPF, note: the output is input reduces hpf_dc_cal -0:normal HPF output - - - The DC of hpf - - - - - - The coeff of hpf - - - The coeff of hpf - - - - - 1:bypass LPF -0:normal LPF output. - - - The coeff of lpf - - - The coeff of lpf - - - - - The gain of lpf - - - relative threshold - - - The initial of mean_noise. -ABS thd = mean_noise * rela_thd. The cmp_trigger signal depending the comparation between ABS thd and lpf_out's absolute value - - - - - mean_noise changed in every refresh timer -The refresh_timer is more than average_timer - - - 00:begin average_timer = 16'd127 ;cut_bit = 4'd7; end -01:begin average_timer = 16'd255 ;cut_bit = 4'd8; end -10:begin average_timer = 16'd511 ;cut_bit = 4'd9; end -11:begin average_timer = 16'd1023;cut_bit = 4'd10;end - - - unsigned threshold value -When LLR[k]*4 > individualtest, vadflag is 1,otherwise 0 - - - - - unsigned threshold value -When sum of all LLR[k] > totaltest, vadflag is 1,otherwise 0 -There is a OR relationship with individualtest - - - valdflag smooth module -Count the number of successive detected speech frames,no longer count more than 6.After that , when detect no speech frames, smooth the overhead2 frames into speech frames. If less 6, smooth the overhead1 frames into speech frames - - - ditto - - - - - - - SFIFO's write address is reset to all 0, high active - - - SFIFO's read address is reset to all 0, high active - - - 0:test_port_s <= {1'b0,speech_stds_0 ,1'b0,speech_means_adj_0 } ; - - - 0: test_port_n <= {1'b0,noise_stds_0 ,1'b0,noise_means_adj_0 } ; - - - - - {1'b0,speech_stds ,1'b0,speech_means_adj } ; - - - - - {1'b0,noise_stds ,1'b0,noise_means_adj } - - - - - - - - - Enables the SIM Card IF module - - - Selects the parity generation/detection - - - - - - Parity Error Receive Feed-through -
- 0 = Don't store bytes with detected parity errors -
- 1 = Feed-through bytes with detected parity errors - - - - - Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer. -
- 0 = Enable NULL character filtering, NULL characters are not reported if not data. -
- 1 = Disable NULL character filtering. NULL characters (0x60) are transferred to the SCI data buffer. - - - - - Manual SCI Clock Stop control. Manually starts and stops the SCI clock. This bit must be set to '1' when Autostop mode is enabled. -
- 0 = Enable the SCI clock -
- 1 = Disable SCI clock - - - - - Enables automatic clock shutdown when command is complete. Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol. -
- 0 = Auto clock control not enabled. SCI clock controlled by SCI_Clockstop bit -
- 1 = Auto clock control enabled. - - - - - Sets the transmission and reception bit order: -
- 0 = LSB is sent/recieved first (Direct convention) -
- 1 = MSB is sent/received first (Inverse convention) - - - - - Logic Level Invert: -
- 0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit. (Direct convention) -
- 1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit. (Inverse convention) - - - - - Parity Error signal length. This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU -
- 0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU -
- 1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU - - - - - Enable or disable parity error checking on the receive data -
- 0 = Disable parity error checking -
- 1 = Enable parity error checking - - - - - Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown) -
- 0 = Stop clock at low level -
- 1 = Stop clock at high level - - - - Automatic Reset Generator. Write a '1' to this bit to initiate an automatic reset procedure on the SIM. Write '0' to switch back to SCI_Reset control (bit 20). An ARG interrupt will be generated if the ARG process succeeded or failed. The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected. This bit needs to be cleared between ARG attempts. - - - - Automatic format detection. This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention. -
- 1 = Enable TS detection and automatic convention settings programming -
- 0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention - - - - - 1 = Enable automatic resend of characters when Tx parity error is detected -
- 0 = Disable automatic resend - - - - - Direct connection to the SIM card reset pin. This is overridden when ARG_H is enabled -
- 0 = SCI_Reset low voltage -
- 1 = SCI Reset high voltage - - - - - This selects between two delay times for the automatic clock stop startup and shutdown: -
- 0 = short delay -
- Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks -
- 1 = long delay -
- Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks - - - - - Input data average enable. -
- 0 = Disable -
- 1 = Enable - - - - Allows fine control of the parity check position during the parity error time period. - - - - - - Returns the status of the Rx FIFO: -
- 0 = Rx FIFO empty -
- 1 = There is at least 1 character in the Rx FIFO - - - - - Returns the status of the Tx FIFO: -
- 0 = Tx FIFO is full -
- 1 = There is at least 1 free spot in the Tx FIFO - - - - - Returns the status of the automatic format detection after reset: -
- 0 = TS character has not been detected in the ATR -
- 1 = TS character has been detected and SCI module is using the automatic convention settings -
-
- This bit is cleared when the AFD_En bit is cleared - - - - - Returns the status of the automatic reset procedure: -
- 0 = ARG detection has failed -
- 1 = ARG detection has detected that the SIM has responded to the reset -
-
- This bit is used in conjunction with the ARG interrupt. The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process. This bit can be used to determine the success or failure. - - - - This is the status of the Reset pin when automatic reset generation is enabled. This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection') - - - - Status of the control signal to the clock control module. This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready' -
- 0 = SCI clock may be on or off but is not ready for use -
- 1 = SCI clock is on and ready for use - - - - - Status bit of the Sci clock. -
- 0 = Sci clock is ON -
- 1 = Sci clock is OFF - - - - A receive parity error was detected. Reading this register clears the bit. - - - A transmit parity error was detected. Reading this register clears the bit. - - - The internal receive FIFO has reached an overflow condition. Reading this register clears the bit. - - - The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit. - - - Returns the state of the clock management state machine when AutoStop mode is enabled. This value is '00' when manual mode is selected. - - - - - - - - - - - - - Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. - - - Reading this register will read from the receive data FIFO. - - - - - Clock divider for generating the baud clock from the SCI clock. This value must match the value used by the SIM card whose default value is 0x174. - - - - Speed mode enable. -
- 0 = Low speed mode -
- 1 = High speed mode(372/32, 372/64, 512/64) - - - - Rx_clk_cnt wrap value. - - - - - Secondary clock divider for generating 16x baud clock. - - - - Main clock divider to generate the SCI clock. This value should be calculated as follows: -
- MainDiv = Clk_Sys/(2xSCI_Clk) - 1 -
- where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification. - - - - - - - - - Inverts the polarity of the SCI clock to the SIM card only. -
- 0 = No inversion -
- 1 = Invert external SCI clock - - - - - Inverts the polarity of the SCI clock to the SIM card and internal. -
- 0 = No inversion -
- 1 = Invert external SCI clock - - - - - - - This value should be programmed with the number of expected characters to receive. It will be decremented each time a character is - actually - received and should be 0 when the transfer is complete. If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero. - - - - - When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete. This should be used for multi-transfer commands where the clock must not be shut down until the command is complete. This bit must be programmed for each transfer. -
- 1 = Keep clock on -
- 0 = Allow clock shutdown when transfer is complete - - - - - - This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters. This should be programmed depending on the SIM's ATR. The total ETU guard time will be ChGuard + 1. - - - - - - - - Turnaround guard time configuration. This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character. The minimum time specified in the SIM recommendation is 16 ETU. The number of ETUs can be calculated using the following formula: -
- Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard - - - - - - - - - Work Waiting Time factor. A timeout will be generated when the WWT is exceeded. The WWT is calculated by: -
- WWT = 960 x WI x (F/Fi) -
- where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS. -
- The SCI_WI value must be calculated as follows: -
- SCI_WI = WI * D -
- Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure. - - - - - - - - Number of times to try resending character when the SIM indicates a parity error. - - - - - - Value of the character to be filtered. 0x60 is the NULL character in the SIM protocol. If character filtering is enabled, the - first - 0x60 character that is received by the SIM during a transfer will - not - be recorded. The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data. This filter has no effect on characters within the datastream. - - - - - - Clear RX FIFO. - - - Clear TX FIFO. - - clear RX/TX FIFO - - - - Number of expected Rx characters, as programmed in the RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - - This register is a - READ ONLY - register that returns the logical - and - of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt. Bits 21:16 return the - status - of the interrupt which is the interrupt state before the mask is applied. These bits should only be used for debugging. - - - - - Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in SCI_RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect. - - - - Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. - - - Receiver FIFO is half full. - - - No Tx character has been sent NOR any Rx character detected within the WWT timeout. - - - An extra character has been received after the number of characters in SCI_RxCnt has been received. - - - The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. - - - End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. - - - DMA tx done. - - - DMA rx done. - - This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt. - - - - - - - - - - - - - - - - - - - - - Lps Skip Frame Enable. -
- When enabled the frame interrupt are masked until the programmed number of frames are elapsed. -
- This is done by masking the frame interrupt line from the regular TCU counter, and counting the frames. Also when activating the LowPower SkipFrame the frame counter is tranfered to the low power counter that will update it based on the 32kHz Clock. - - - - Controls the Lps Low Power Counters (counters at 32kHz) usage. - - - - - - - - - - - Enable fake Fint used with wakeupNumber=0. - - - - - - Enable fake Fint when sys_sf_frame_count>=cfg_sf_frame. -
- Default sys_sf_frame_count>cfg_sf_frame. - - - - - - - - - Lps Skip Frame Ready, status of the state machines to keep valid state between system clock and 32Khz clock. -
- Must read as '1' before entering Low Power Skip Frame or Calibration mode. - - - - - '1' when Lps Skip Frame Low Power Counters are Running. -
- When entering Low Power Skip Frame, the counters are not immediately started, they wait for the nextFrame interrupt. Reading this status allow to know if the counters are running, and the System Clock can be safely disabled. - - - - '1' when the Lps Skip Frame Calibration is Done. - - - '1' when the Lps Skip Frame Power-up sequence frame is reached. - - - '1' when tcu counter is restarted. - - - - - - Number of frames to Skip. -
- If the power up sequence is enabled, frames are skipped until both this number is reached and the powerup sequence has finished. -
- Note: The power up sequence must be - Done - before the the frame LPS_SF_Frame ends. - - - - - - Number of frames before activating the Power-up sequence. - - - - - - For LowPower SkipFrame mode: Value to restart TCU (and frame interrupt generation) on the system clock counter after a low power phase. -
- For Calibration mode: number of 32k cycles for the calibration. - - - - - - Value of the frame period in system clock count. - - - - The rate is the number of System Clocks per 32kHz Clocks. - - Integer part of the rate. - - - Fractional part of the rate. - - - - - - Current number of elapsed frames. -
- Valid when Skip Frame is Enabled. - - - - - - - Value of the system clock counter at the end of calibration (when CalibrationDone is '1' in LPS_SF_Status register). -
- The hardware behind it is reused during other operation, reading that register at any other time will return an undefined value. - - - - - - - 1 when the IRQ was triggered because the calibration is done. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the IRQ was triggered because the Slow Counter started. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the IRQ was triggered because the Power-Up frame was reached. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the IRQ was triggered because the tcu counter was restarted. -
- Write 1 in cause or status bit to clear. - - - - - - - - - - - 1 when the calibration is done. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the Slow Counter started. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the Power-Up frame was reached. -
- Write 1 in cause or status bit to clear. - - - - - 1 when the tcu counter was restarted. -
- Write 1 in cause or status bit to clear. - - - - - - - - - - - - when 1 the LPS_IRQ_Calibration_Done is enabled. - - - when 1 the LPS_IRQ_Slow_Running is enabled. - - - when 1 the LPS_IRQ_PU_Reached is enabled. - - - when 1 the LPS_IRQ_TCU_Restart is enabled. - - - - - - - - - - - - - - - - - Enable the module and activate the chip select selected by CS_sel field. - - - Selects the active CS. - - - - - - When set to 1 the inputs are activated, else only the output is driven and no data are stored in the receive FIFO. -
- Notes: The Input_mode bit status is also readable onto the bit rxtx_buffer[31]. - - - - - The spi clock polarity -
- when '0' the clock disabled level is low, and the first edge is a rising edge. -
- When '1' the clock disabled level is high, and the first edge is a falling edge. - - - - Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first clock edge. - - - Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first data out - - - - Transfer start to first data in sample delay value from 0 to 3 is the number of spi clock half period between the CS activation and the first data in sampled. -
- NOTE: DI_Delay must be less or equal to DO_Delay + CS_Delay + 2. -
- In other words DI_Delay can be 3 only if DO_Delay and CS_Delay are not both equal to 0. - - - - Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer and CS deactivation - - - Chip select deactivation to reactivation minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new CS activation (CS will activate only if more data are available in the transmit FIFO) - - - - Frame Size -
- The frame size is the binary value of this register + 1 valid value are 3 to 31 (frame size 4 to 32bits) - - - - - OE delay -
- When 0: regular mode, SPI_DO pin as output only. -
- Value from 1 to 31 is the number of data out to transfert before the SPI_DO pin switch to input. - - - - - Selects the active CS and Input_reg either from the ctrl or rxtx_buffer register. -
- If SPI FIFO 8b or 32b, when set to "0": CS from CS_sel and INPUT from Input_mode in the register ctrl. -
- Only if SPI FIFO 32b, when set to "1": CS and INPUT from SPI DATA.(Do not work for FIFO8b) - - - - - - - Selects the input line to be used as SPI data in.(Not used for SPI3) -
- when "00" the SPI_DI_0 is used. -
- When "01" the SPI_DI_1 is used. -
- When "10" the SPI_DI_2 is used. -
- When "11" reserved. - - - - - - '1' when a transfer is in progress. - - - - The receive FIFO overflow irq cause. -
- Writing a '1' clear the receive overflow status and cause. - - - - The transmit FIFO threshold irq cause. - - - - The transmit Dma Done irq cause. -
- Writing a '1' clear the transmit Dma Done status and cause. - - - - The receive FIFO threshold irq cause. - - - - The receive Dma Done irq cause. -
- Writing a '1' clear the receive Dma Done status and cause. - - - - - - - - - - - - The transmit FIFO overflow status. -
- Writing a '1' clear the transmit overflow status and cause. - - - - - The receive FIFO underflow status. -
- Writing a '1' clear the receive underflow status and cause. - - - - - The receive FIFO overflow status. -
- Writing a '1' clear the receive overflow status and cause. - - - - The transmit FIFO threshold status. - - - - The transmit Dma Done status. -
- Writing a '1' clear the transmit Dma Done status and cause. - - - - The receive FIFO threshold status. - - - - The receive Dma Done status. -
- Writing a '1' clear the receive Dma Done status and cause. - - - - - Transmit FIFO Space -
- Number of empty spot in the FIFO - - - - - - - - - Receive FIFO level -
- Number of DATA in the FIFO - - - - - - - - Writing '1' flush both FIFO, don't do it when SPI is active (transfer in progress) - - - - - Spi1 fifo size (rxtx_buffer): 8bits. -
- Spi2 fifo size (rxtx_buffer): 8bits. -
- Spi3 fifo size (rxtx_buffer): 32bits. -
- - - Write to the transmit FIFO - Read in the receive FIFO. - - - Chip Select on which write the data written in the - Fifo. - Data in bit [30:29] - Data out bit [30:29] - - - - - - - - Set this bit to one when the data received while sending - this peculiar data are expected to be kept in the FIFO, - otherwise no data is recorded in the FIFO. - Data in bit [31] - Data out bit [31] - - - - - - - - - - Chip select polarity - - - - - - - - - - - Clock Divider -
- The state machine clock is generated by dividing the system clock by the value of this register + 1. -
- So the output clock is divided by (register + 1)*2 - - - - - - - - - - When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz. -
- for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. - - - - - - - - - - - MMC Pattern value for RX pattern match mode. - - - Enable the pattern mode. - - - - - - - - - - Select the RX pattern matching mode when the pattern_mode is enabled( set 1). Used for SD/MMC SPI mode. - - - - - - - - - - - - When TX stream mode is enabled, once the TX fifo is empty, all new bits send have the value of this bit. - - - - - - Enable the TX stream mode. Used for SD/MMC SPI mode. -
- When enabled, this mode provide infinite bit stream for sending, after fifo is empty the extra bits generated all have the same value. The value is in tx_stream_bit. - - - - - - Allow to automatically clear the tx_stream_mode when Rx_Dma_Done is set. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mask the receive FIFO overflow irq - - - Mask the transmit FIFO threshold irq - - - Mask the transmit Dma Done irq - - - Mask the receive FIFO threshold irq - - - Mask the receive DMA Done irq - - - - - - - - - - Transmit FIFO threshold this threshold is used to generate the irq. - - - - - Receive FIFO threshold this threshold is used to generate the irq. - - - - - - - - - - - - CPU IDs - - - - - Sys Axi Clks IDs - - - - reserved base number - - - - - - - auto clock enable number - - - - - - - - Sys Ahb Clks IDs - - - - - reserved base number - - - - - - auto clock enable number - - - - - - - - - - - - Sys Apb Clks IDs - - - - - - - - - - - - - - - - - - - - - - - - - auto clock enable number - - - - - - - - - - - - - - - Aif Apb Clks IDs - - - - - - - - - - reserved base number - - - - - - - auto clock enable number - - - - - - - - Aon Ahb Clks IDs - - - reserved base number - - - - - - - auto clock enable number - - - - - - - - Aon Apb Clks IDs - - - - - - - - - - - - - - - - - - - - - - auto clock enable number - - - - - - - - - - - - - - - - - auto clock enable number - - - - - - - - - auto clock enable number - - - - - - - - Other Clks IDs - - - - - - - - - - - - - - - - System Spiflash Domain Clock ID Base - - - - - - - - - - - Psram Ctrl Domain Clock ID Base - - - - - - - - - - - Other Clks 1 IDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Psram Clks IDs - - - - - - - - - Sys Spiflash Clks IDs - - - - Sys Spiflash1 Clks IDs - - - - - - Sys Axi Rst IDs - - - - - - - - - - - - Sys Ahb Rst IDs - - - - - - - - - - - - - - - - - - Sys Apb Rst IDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Aif Apb Rst IDs - - - - - - - - - - - Aon Ahb Rst IDs - - - - - - - - - - Aon Apb Rst IDs - - - - - - - - - - - - - - - - - - - - - - - - - Rf Ahb Rst IDs - - - - - - - Rf Apb Rst IDs - - - - - - - APCPU Rst IDs - - - - - - - - - - CPCPU Rst IDs - - - - - - - - BBlte Rst IDs - - - - - - - Other Rsts IDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - For REG_DBG protect lock/unlock value - - - - - This register is used to Lock and Unlock the protected registers. - - - -
- [7:0] Write 0x89 to the register to release automatically for related clock gate enable in sysctrl datapath -
- [15:8] Write 0x89 to the register to release automatically for related soft reset in sysctrl datapath - - - - - Is set to 1 when a write attempt has been done on a protected register -
- Can be reset by writing 0xa50000 or 0xa50001 to the debug register (With the LSB at 1 to unlock the protected registers, with the LSB at 0 to lock them) - - - - - When this bit is set to 1, the protected registers are accessible -
- When this bit is set to 0, the protected registers can not be written -
- Write 0xa50000 to the debug register to set this bit to 0 -
- Write 0xa50001 to the debug register to set this bit to 1 - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - This register is protected. - - - Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - Writing a 1 to any of the reset bit will take the corresponding module out of reset state -
- Reading this register returns the reset state of all the corresponding modules -
- 0 : in reset -
- 1 : out of reset - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - - - - - - - - - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will enable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - This register is protected. - - - Each bit controls the manual enable for one clock -
- Writing a 1 to bit x of this register will disable the corresponding clocks -
- Writing a 0 to bit x has no effect on clock x -
- Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) - - - - - Register protected by Write_Unlocked_H. - - Mode of the Pll. This register is set to enable by the LPS_start_ExtPll_pulse_H. - - - - - Used to reset the PLL Lock Detector. - - - - - - - - - - - - - - Enables the Fast Clock from the ExtPll (Clock Gate Reg Resync). - - - - - - This register is protected. - - PreSelects between RF clock(26mhz) and Oscillator clock(32k) for Clock Slow - - - - - Selects between the Slow clock and the Fast Clock (APll clock) and Selects between the Slow clock and the APcpu Clock - - - - - - When 0, select 26m div32k. -
- When 1, select osc 32k. - - - - Disable PLL when LPS power up. - - - - - - - - - - - - If RF_Detect_Bypass = 0, RF clock is selected when she is detected. -
- If RF_Detect_Bypass = 1, RF clock is selected even she is not detected. - - - - - When 1, The RF clock detection counter is force reseted. -
- When 0, The RF clock detection counter is enabled. - - - - 0 when RF clock is effectively selected for Slow Clock. RF clock selection is not done until the clock has been detected. - - - - - - - - - - - - 0 when Fast clock is effectively selected. Fast clock selection is not done until the PLL has locked. - - - - - - - - - When 1, clk_spiflash is clk_slow. -
- When 0, switch from clk_slow to clk_spiflash - - - - - When 1, clk_mem_bridge is clk_slow. -
- When 0, switch from clk_slow to clk_pll_mem_bridge - - - - - When 1, clk_bblte is inverted. -
- When 0, clk_bblte is itself, pole select - - - - - When 1, clk_pix is clk_slow. -
- When 0, switch from clk_slow to clk_pll_pix_div_out - - - - - When 1, usb clock pll locked. -
- When 0, usb clock pll not locked. - - - - - When 1, select i_osc_26m. -
- When 0, select i_bb_26m(default). - - - - - When 1, clk_spiflash is clk_slow. -
- When 0, switch from clk_slow to clk_spiflash - - - - -
- When 1, apll locked -
- When 0, apll not locked - - - - -
- When 1, mempll locked -
- When 0, mempll not locked - - - - -
- When 1, audiopll locked -
- When 0, audiopll not locked - - - - -
- When 1, bbpll2 locked -
- When 0, bbpll2 not locked - - - - -
- When 1, bbpll1 locked -
- When 0, bbpll1 not locked - - - - -
- When 1, usbpll locked -
- When 0, usbpll not locked - - - - - - This register is protected. - - The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL. - - - - - - - - - - - - The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL. - - - - - - - The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL. - - - - - - - - The generated clock frequency is equal to the selected source frequency divided by this value. -
- The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details). -
- [9:0] numerator 'b0000000001 -
- [23:10] denominator 'b000000000000110 - - - - - - - - - - - - - - The Pwm reference clock frequency is the system clock divided by this register value + 1. - - - - - The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL. - - - - - Clk camera out enable. - - - - - Selects from which clock the Clk camera is generated. - - - - - - - - - Clk spi camera out enable. - - - - - - - - - - - - - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - - - - - - - - - - - - - Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. - - - - - - - - - - This contains the state of boot mode pins latched during Reset. -
- bit 16: Force download. -
- bit 17: Mass production. -
- bit 18: Secure boot 1-> secure boot, 0-> nonsecure boot. -
- bit 19: Unused. -
- bit 20: Unused. -
- bit 21: Unused. -
- see BootSequence for details. -
- This register is not reseted by a software or host reset. - - - - - - - - - Software boot mode (Reseted at zero by external reset pin) -
- This register is not reseted by a software or host reset. - - - - - - - - When 1 the chip has booted in fonctional test mode (for chip production tests). - - - - This register is protected. - - When 1, the wake up is set. When 0, the wake up is clear . - - - - This register is protected. - - When 1, the CHG_MASK line to PMU is set. When 0, it is cleared. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The generated clock frequency is equal to the selected source frequency divided by this value . -
- The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details). -
- [17:8] numerator 'b0000000001 -
- [30:18] denominator 'b0000000000101 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This register is ahb master protect cfg. - - - - - - - - - - - - - - - - - This register is cq memory cfg. - - - - - This register is a5_top_wrap/axidma/cp_a5_top/f8/gea3_wrap/lzma/sys_imem mem cfg. - - - - - This register is audio mem cfg. - - - - - This register is lcd/gouda mem cfg. - - - - - This register is camera mem cfg. - - - - - This register is peri(sdmmc/uart/usbc etc.) mem cfg. - - - - - This register is aon sys mem cfg. - - - - - This register is rf sys mem cfg. - - - - - This register is coresight mem cfg. - - - - - This register is vad mem cfg. - - - - - This register is for audio i2s mux ,aif load_position etc. config. - - - - - - -
- 000 = aif1 out mux to aif1 -
- 001 = aif2 out mux to aif1 -
- 010 = i2s1 out mux to aif1 -
- 011 = i2s2 out mux to aif1 -
- 100 = i2s3 out mux to aif1 -
- 101 = zero out mux to aif1 - - - - -
- 000 = aif1 out mux to aif2 -
- 001 = aif2 out mux to aif2 -
- 010 = i2s1 out mux to aif2 -
- 011 = i2s2 out mux to aif2 -
- 100 = i2s3 out mux to aif2 -
- 101 = zero out mux to aif2 - - - - -
- 000 = aif1 out mux to i2s1 -
- 001 = aif2 out mux to i2s1 -
- 010 = i2s1 out mux to i2s1 -
- 011 = i2s2 out mux to i2s1 -
- 100 = i2s3 out mux to i2s1 -
- 101 = zero out mux to i2s1 - - - - -
- 000 = aif1 out mux to i2s2 -
- 001 = aif2 out mux to i2s2 -
- 010 = i2s1 out mux to i2s2 -
- 011 = i2s2 out mux to i2s2 -
- 100 = i2s3 out mux to i2s2 -
- 101 = zero out mux to i2s2 - - - - -
- 000 = aif1 out mux to i2s3 -
- 001 = aif2 out mux to i2s3 -
- 010 = i2s1 out mux to i2s3 -
- 011 = i2s2 out mux to i2s3 -
- 100 = i2s3 out mux to i2s3 -
- 101 = zero out mux to i2s3 - - - - -
- 0 = i2s1 bck,lrck output enable -
- 1 = i2s1 bck,lrck output disable - - - - -
- 0 = i2s2 bck,lrck output enable -
- 1 = i2s2 bck,lrck output disable - - - - -
- 0 = i2s3 bck,lrck output enable -
- 1 = i2s3 bck,lrck output disable - - - - - This register is limit_en_spi,,clk_freq cfg. - - - - - - - - - - - - - - -
- 0 = wcn uart and ap uart(with wcn communication) connect -
- 1 = wcn uart output by iomux - - - - -
- 0 = ap uart(with wcn communication) and wcn uart connect -
- 1 = ap uart(with wcn communication) output by iomux - - - - - - - - - - - - - This register is misc cfg. - - - - - - -
- 0 = disable pwr_ctrl for ap reset -
- 1 = enable pwr_ctrl for ap reset - - - - -
- 0 = disable pwr_ctrl for gge reset -
- 1 = enable pwr_ctrl for gge reset - - - - -
- 0 = disable pwr_ctrl for btfm reset -
- 1 = enable pwr_ctrl for btfm reset - - - - -
- 0 = disable pwr_ctrl for ap clock -
- 1 = enable pwr_ctrl for ap clock - - - - -
- 0 = disable pwr_ctrl for gge clock -
- 1 = enable pwr_ctrl for gge clock - - - - -
- 0 = disable pwr_ctrl for btfm clock -
- 1 = enable pwr_ctrl for btfm clock - - - - -
- 0 = disable bbpll1 output -
- 1 = enable bbpll1 output - - - - -
- 0 = disable bbpll2 output -
- 1 = enable bbpll2 output - - - - -
- 0 = disable mempll output -
- 1 = enable mempll output - - - - -
- 0 = disable usbpll output -
- 1 = enable usbpll output - - - - -
- 0 = disable audiopll output -
- 1 = enable audiopll output - - - - -
- 0 = select clk_494m clock -
- 1 = select from apll clock - - - - -
- 0 = select i_apll_in clock -
- 1 = select clk_494m clock - - - - gic400 axi aruser sel - - - gic400 axi aruser dbg - - - gic400 axi awuser sel - - - gic400 axi awuser dbg - - - -
- 0 = select rfdig lvds -
- 1 = select wcn lvds - - - - -
- 0 = select rfdig from rf lvds -
- 1 = select rfdig from bb lvds - - - - -
- 0 = disable wcn_hclk and wcn_clk_26m wcn_osc_en control -
- 1 = enable wcn_hclk and wcn_clk_26m wcn_osc_en control - - - - -
- 0 = force clock on disable -
- 1 = force clock on enable - - - - -
- 0 = select vad clock(default) -
- 1 = select vad inv clock - - - - -
- 0 = select aud_sclk(default) -
- 1 = select aud_sclk inv clock - - - - -
- 0 = disable pwr_ctrl for aon_lp reset -
- 1 = enable pwr_ctrl for aon_lp reset - - - - -
- 0 = disable pwr_ctrl for aon_lp clock -
- 1 = enable pwr_ctrl for aon_lp clock - - - - -
- 0 = disable aon rf async bridge dump data to fifo -
- 1 = enable aon rf async bridge dump data to fifo for bus access efficiency - - - - - This register set lp related config. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This register is reserved. - - - - - - - - - - - - - - - - - - - - - - - - - - - - For WCN Ahb Bus peri prot. - - - For WCN Ahb Bus mem prot. - - - aes ahb bus prot. - - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is reserved. - - This register is reserved. - - - - This register is for CHIP_ID(METAL_ID[11:0],BOND_ID[15:12]),PROD[31:16] - - -
- [11:0] metal ID - - - - -
- [15:12] bond ID, bit15: spi_flash_sel 0->1.8v pad sequence 1->3.3v pad sequence; bit14: boot - - - - -
- [31:16] production ID - - - - - This register is for BUS QOS config. - - -
- [3:0] for wcn_mem_arqos -
- [4] for wcn_mem_arqos sync - - - - -
- [8:5] for wcn_mem_awqos -
- [9] for wcn_mem_awqos sync - - - - -
- [13:10] for gge_arqos -
- [14] for gge_arqos sync - - - - -
- [18:15] for gge_awqos -
- [19] for gge_awqos sync - - - - -
- [23:20] for a5_arqos -
- [24] for a5_arqos sync - - - - -
- [28:25] for a5_awqos -
- [29] for a5_awqos sync - - - - - This register is for BUS QOS config. - - -
- [3:0] for axidma_arqos -
- [4] for axidma_arqos sync - - - - -
- [8:5] for axidma_awqos -
- [9] for axidma_awqos sync - - - - -
- [13:10] for cp_a5_arqos -
- [14] for cp_a5_arqos sync - - - - -
- [18:15] for cp_a5_awqos -
- [19] for cp_a5_awqos sync - - - - -
- [23:20] for f8_arqos -
- [24] for f8_arqos sync - - - - -
- [28:25] for f8_awqos -
- [29] for f8_awqos sync - - - - - This register is for BUS QOS config. - - -
- [3:0] for lcdc_arqos -
- [4] for lcdc_arqos sync - - - - -
- [8:5] for lcdc_awqos -
- [9] for lcdc_awqos sync - - - - -
- [13:10] for lzma_arqos -
- [14] for lzma_arqos sync - - - - -
- [18:15] for lzma_awqos -
- [19] for lzma_awqos sync - - - - -
- [23:20] for gouda_arqos -
- [24] for gouda_arqos sync - - - - -
- [28:25] for gouda_awqos -
- [29] for gouda_awqos sync - - - - - This register is for BUS QOS config. - - -
- [3:0] for lte_arqos -
- [4] for lte_arqos sync - - - - -
- [8:5] for lte_awqos -
- [9] for lte_awqos sync - - - - -
- [13:10] for usb_arqos -
- [14] for usb_arqos sync - - - - -
- [18:15] for usb_awqos -
- [19] for usb_awqos sync - - - - - This register is for merge mem awqos/arqos QOS config. - - -
- [3:0] for merge_mem_awqos -
- [4] for merge_mem_awqos sync - - - - -
- [8:5] for merge_mem_arqos -
- [9] for merge_mem_arqos sync - - - - - This register is for bcpu break point debug. - - -
- [27:0] for bcpu break point address. - - - - -
- [29:28] for bcpu break point mode. - - - - -
- [30] for bcpu break point enable. - - - - -
- [31] for bcpu stalled write 1 clear. - - - - - - - - - - spi_flash_clk force enable for outoen. - - - spi_flash_clk force output value for output. - - - spi_flash_clk pin output value. - - - spi_flash_clk force outoen value. - - - spi_flash_clk force enable for pu/pd - - - spi_flash_clk PUll up - - - spi_flash_clk PUll down - - - spi_flash_clk select - - - - - - - spi_flash_cs force enable for outoen. - - - spi_flash_cs force output value for output. - - - spi_flash_cs pin output value. - - - spi_flash_cs force outoen value. - - - spi_flash_cs force enable for pu/pd - - - spi_flash_cs PUll up - - - spi_flash_cs PUll down - - - spi_flash_cs select - - - - - - - spi_flash_sel force enable for outoen. - - - spi_flash_sel force output value for output. - - - spi_flash_sel pin output value. - - - spi_flash_sel force outoen value. - - - spi_flash_sel force enable for pu/pd - - - spi_flash_sel PUll up - - - spi_flash_sel PUll down - - - spi_flash_sel select - - - - - - - spi_flash_sio_0 force enable for outoen. - - - spi_flash_sio_0 force output value for output. - - - spi_flash_sio_0 pin output value. - - - spi_flash_sio_0 force outoen value. - - - spi_flash_sio_0 force enable for pu/pd - - - spi_flash_sio_0 PUll up - - - spi_flash_sio_0 PUll down - - - spi_flash_sio_0 select - - - - - - - spi_flash_sio_1 force enable for outoen. - - - spi_flash_sio_1 force output value for output. - - - spi_flash_sio_1 pin output value. - - - spi_flash_sio_1 force outoen value. - - - spi_flash_sio_1 force enable for pu/pd - - - spi_flash_sio_1 PUll up - - - spi_flash_sio_1 PUll down - - - spi_flash_sio_1 select - - - - - - - spi_flash_sio_2 force enable for outoen. - - - spi_flash_sio_2 force output value for output. - - - spi_flash_sio_2 pin output value. - - - spi_flash_sio_2 force outoen value. - - - spi_flash_sio_2 force enable for pu/pd - - - spi_flash_sio_2 PUll up - - - spi_flash_sio_2 PUll down - - - spi_flash_sio_2 select - - - - - - - spi_flash_sio_3 force enable for outoen. - - - spi_flash_sio_3 force output value for output. - - - spi_flash_sio_3 pin output value. - - - spi_flash_sio_3 force outoen value. - - - spi_flash_sio_3 force enable for pu/pd - - - spi_flash_sio_3 PUll up - - - spi_flash_sio_3 PUll down - - - spi_flash_sio_3 select - - - - - - - sdmmc1_clk force enable for outoen. - - - sdmmc1_clk force output value for output. - - - sdmmc1_clk pin output value. - - - sdmmc1_clk force outoen value. - - - sdmmc1_clk force enable for pu/pd - - - sdmmc1_clk PUll up - - - sdmmc1_clk PUll down - - - sdmmc1_clk select - - - - - - - sdmmc1_cmd force enable for outoen. - - - sdmmc1_cmd force output value for output. - - - sdmmc1_cmd pin output value. - - - sdmmc1_cmd force outoen value. - - - sdmmc1_cmd force enable for pu/pd - - - sdmmc1_cmd PUll up - - - sdmmc1_cmd PUll down - - - sdmmc1_cmd select - - - - - - - sdmmc1_data_0 force enable for outoen. - - - sdmmc1_data_0 force output value for output. - - - sdmmc1_data_0 pin output value. - - - sdmmc1_data_0 force outoen value. - - - sdmmc1_data_0 force enable for pu/pd - - - sdmmc1_data_0 PUll up - - - sdmmc1_data_0 PUll down - - - sdmmc1_data_0 select - - - - - - - sdmmc1_data_1 force enable for outoen. - - - sdmmc1_data_1 force output value for output. - - - sdmmc1_data_1 pin output value. - - - sdmmc1_data_1 force outoen value. - - - sdmmc1_data_1 force enable for pu/pd - - - sdmmc1_data_1 PUll up - - - sdmmc1_data_1 PUll down - - - sdmmc1_data_1 select - - - - - - - sdmmc1_data_2 force enable for outoen. - - - sdmmc1_data_2 force output value for output. - - - sdmmc1_data_2 pin output value. - - - sdmmc1_data_2 force outoen value. - - - sdmmc1_data_2 force enable for pu/pd - - - sdmmc1_data_2 PUll up - - - sdmmc1_data_2 PUll down - - - sdmmc1_data_2 select - - - - - - - sdmmc1_data_3 force enable for outoen. - - - sdmmc1_data_3 force output value for output. - - - sdmmc1_data_3 pin output value. - - - sdmmc1_data_3 force outoen value. - - - sdmmc1_data_3 force enable for pu/pd - - - sdmmc1_data_3 PUll up - - - sdmmc1_data_3 PUll down - - - sdmmc1_data_3 select - - - - - - - aud_da_sync force enable for outoen. - - - aud_da_sync force output value for output. - - - aud_da_sync pin output value. - - - aud_da_sync force outoen value. - - - aud_da_sync force enable for pu/pd - - - aud_da_sync PUll up - - - aud_da_sync PUll down - - - aud_da_sync select - - - - - - - aud_da_d1 force enable for outoen. - - - aud_da_d1 force output value for output. - - - aud_da_d1 pin output value. - - - aud_da_d1 force outoen value. - - - aud_da_d1 force enable for pu/pd - - - aud_da_d1 PUll up - - - aud_da_d1 PUll down - - - aud_da_d1 select - - - - - - - aud_da_d0 force enable for outoen. - - - aud_da_d0 force output value for output. - - - aud_da_d0 pin output value. - - - aud_da_d0 force outoen value. - - - aud_da_d0 force enable for pu/pd - - - aud_da_d0 PUll up - - - aud_da_d0 PUll down - - - aud_da_d0 select - - - - - - - aud_ad_sync force enable for outoen. - - - aud_ad_sync force output value for output. - - - aud_ad_sync pin output value. - - - aud_ad_sync force outoen value. - - - aud_ad_sync force enable for pu/pd - - - aud_ad_sync PUll up - - - aud_ad_sync PUll down - - - aud_ad_sync select - - - - - - - aud_ad_d0 force enable for outoen. - - - aud_ad_d0 force output value for output. - - - aud_ad_d0 pin output value. - - - aud_ad_d0 force outoen value. - - - aud_ad_d0 force enable for pu/pd - - - aud_ad_d0 PUll up - - - aud_ad_d0 PUll down - - - aud_ad_d0 select - - - - - - - aud_sclk force enable for outoen. - - - aud_sclk force output value for output. - - - aud_sclk pin output value. - - - aud_sclk force outoen value. - - - aud_sclk force enable for pu/pd - - - aud_sclk PUll up - - - aud_sclk PUll down - - - aud_sclk select - - - - - - - adi_sda force enable for outoen. - - - adi_sda force output value for output. - - - adi_sda pin output value. - - - adi_sda force outoen value. - - - adi_sda force enable for pu/pd - - - adi_sda PUll up - - - adi_sda PUll down - - - adi_sda select - - - - - - - adi_sync force enable for outoen. - - - adi_sync force output value for output. - - - adi_sync pin output value. - - - adi_sync force outoen value. - - - adi_sync force enable for pu/pd - - - adi_sync PUll up - - - adi_sync PUll down - - - adi_sync select - - - - - - - adi_scl force enable for outoen. - - - adi_scl force output value for output. - - - adi_scl pin output value. - - - adi_scl force outoen value. - - - adi_scl force enable for pu/pd - - - adi_scl PUll up - - - adi_scl PUll down - - - adi_scl select - - - - - - - spi_lcd_sio force enable for outoen. - - - spi_lcd_sio force output value for output. - - - spi_lcd_sio pin output value. - - - spi_lcd_sio force outoen value. - - - spi_lcd_sio force enable for pu/pd - - - spi_lcd_sio PUll up - - - spi_lcd_sio PUll down - - - spi_lcd_sio select - - - - - - - spi_lcd_sdc force enable for outoen. - - - spi_lcd_sdc force output value for output. - - - spi_lcd_sdc pin output value. - - - spi_lcd_sdc force outoen value. - - - spi_lcd_sdc force enable for pu/pd - - - spi_lcd_sdc PUll up - - - spi_lcd_sdc PUll down - - - spi_lcd_sdc select - - - - - - - spi_lcd_clk force enable for outoen. - - - spi_lcd_clk force output value for output. - - - spi_lcd_clk pin output value. - - - spi_lcd_clk force outoen value. - - - spi_lcd_clk force enable for pu/pd - - - spi_lcd_clk PUll up - - - spi_lcd_clk PUll down - - - spi_lcd_clk select - - - - - - - spi_lcd_cs force enable for outoen. - - - spi_lcd_cs force output value for output. - - - spi_lcd_cs pin output value. - - - spi_lcd_cs force outoen value. - - - spi_lcd_cs force enable for pu/pd - - - spi_lcd_cs PUll up - - - spi_lcd_cs PUll down - - - spi_lcd_cs select - - - - - - - spi_lcd_select force enable for outoen. - - - spi_lcd_select force output value for output. - - - spi_lcd_select pin output value. - - - spi_lcd_select force outoen value. - - - spi_lcd_select force enable for pu/pd - - - spi_lcd_select PUll up - - - spi_lcd_select PUll down - - - spi_lcd_select select - - - - - - - lcd_fmark force enable for outoen. - - - lcd_fmark force output value for output. - - - lcd_fmark pin output value. - - - lcd_fmark force outoen value. - - - lcd_fmark force enable for pu/pd - - - lcd_fmark PUll up - - - lcd_fmark PUll down - - - lcd_fmark select - - - - - - - lcd_rstb force enable for outoen. - - - lcd_rstb force output value for output. - - - lcd_rstb pin output value. - - - lcd_rstb force outoen value. - - - lcd_rstb force enable for pu/pd - - - lcd_rstb PUll up - - - lcd_rstb PUll down - - - lcd_rstb select - - - - - - - i2c_m1_scl force enable for outoen. - - - i2c_m1_scl force output value for output. - - - i2c_m1_scl pin output value. - - - i2c_m1_scl force outoen value. - - - i2c_m1_scl force enable for pu/pd - - - i2c_m1_scl PUll up - - - i2c_m1_scl PUll down - - - i2c_m1_scl select - - - - - - - i2c_m1_sda force enable for outoen. - - - i2c_m1_sda force output value for output. - - - i2c_m1_sda pin output value. - - - i2c_m1_sda force outoen value. - - - i2c_m1_sda force enable for pu/pd - - - i2c_m1_sda PUll up - - - i2c_m1_sda PUll down - - - i2c_m1_sda select - - - - - - - camera_rst_l force enable for outoen. - - - camera_rst_l force output value for output. - - - camera_rst_l pin output value. - - - camera_rst_l force outoen value. - - - camera_rst_l force enable for pu/pd - - - camera_rst_l PUll up - - - camera_rst_l PUll down - - - camera_rst_l select - - - - - - - camera_pwdn force enable for outoen. - - - camera_pwdn force output value for output. - - - camera_pwdn pin output value. - - - camera_pwdn force outoen value. - - - camera_pwdn force enable for pu/pd - - - camera_pwdn PUll up - - - camera_pwdn PUll down - - - camera_pwdn select - - - - - - - camera_ref_clk force enable for outoen. - - - camera_ref_clk force output value for output. - - - camera_ref_clk pin output value. - - - camera_ref_clk force outoen value. - - - camera_ref_clk force enable for pu/pd - - - camera_ref_clk PUll up - - - camera_ref_clk PUll down - - - camera_ref_clk select - - - - - - - spi_camera_si_0 force enable for outoen. - - - spi_camera_si_0 force output value for output. - - - spi_camera_si_0 pin output value. - - - spi_camera_si_0 force outoen value. - - - spi_camera_si_0 force enable for pu/pd - - - spi_camera_si_0 PUll up - - - spi_camera_si_0 PUll down - - - spi_camera_si_0 select - - - - - - - spi_camera_si_1 force enable for outoen. - - - spi_camera_si_1 force output value for output. - - - spi_camera_si_1 pin output value. - - - spi_camera_si_1 force outoen value. - - - spi_camera_si_1 force enable for pu/pd - - - spi_camera_si_1 PUll up - - - spi_camera_si_1 PUll down - - - spi_camera_si_1 select - - - - - - - spi_camera_sck force enable for outoen. - - - spi_camera_sck force output value for output. - - - spi_camera_sck pin output value. - - - spi_camera_sck force outoen value. - - - spi_camera_sck force enable for pu/pd - - - spi_camera_sck PUll up - - - spi_camera_sck PUll down - - - spi_camera_sck select - - - - - - - gpio_13 force enable for outoen. - - - gpio_13 force output value for output. - - - gpio_13 pin output value. - - - gpio_13 force outoen value. - - - gpio_13 force enable for pu/pd - - - gpio_13 PUll up - - - gpio_13 PUll down - - - gpio_13 select - - - - - - - gpio_0 force enable for outoen. - - - gpio_0 force output value for output. - - - gpio_0 pin output value. - - - gpio_0 force outoen value. - - - gpio_0 force enable for pu/pd - - - gpio_0 PUll up - - - gpio_0 PUll down - - - gpio_0 select - - - - - - - gpio_1 force enable for outoen. - - - gpio_1 force output value for output. - - - gpio_1 pin output value. - - - gpio_1 force outoen value. - - - gpio_1 force enable for pu/pd - - - gpio_1 PUll up - - - gpio_1 PUll down - - - gpio_1 select - - - - - - - gpio_2 force enable for outoen. - - - gpio_2 force output value for output. - - - gpio_2 pin output value. - - - gpio_2 force outoen value. - - - gpio_2 force enable for pu/pd - - - gpio_2 PUll up - - - gpio_2 PUll down - - - gpio_2 select - - - - - - - gpio_3 force enable for outoen. - - - gpio_3 force output value for output. - - - gpio_3 pin output value. - - - gpio_3 force outoen value. - - - gpio_3 force enable for pu/pd - - - gpio_3 PUll up - - - gpio_3 PUll down - - - gpio_3 select - - - - - - - gpio_4 force enable for outoen. - - - gpio_4 force output value for output. - - - gpio_4 pin output value. - - - gpio_4 force outoen value. - - - gpio_4 force enable for pu/pd - - - gpio_4 PUll up - - - gpio_4 PUll down - - - gpio_4 select - - - - - - - gpio_5 force enable for outoen. - - - gpio_5 force output value for output. - - - gpio_5 pin output value. - - - gpio_5 force outoen value. - - - gpio_5 force enable for pu/pd - - - gpio_5 PUll up - - - gpio_5 PUll down - - - gpio_5 select - - - - - - - gpio_7 force enable for outoen. - - - gpio_7 force output value for output. - - - gpio_7 pin output value. - - - gpio_7 force outoen value. - - - gpio_7 force enable for pu/pd - - - gpio_7 PUll up - - - gpio_7 PUll down - - - gpio_7 select - - - - - - - ap_jtag_tck force enable for outoen. - - - ap_jtag_tck force output value for output. - - - ap_jtag_tck pin output value. - - - ap_jtag_tck force outoen value. - - - ap_jtag_tck force enable for pu/pd - - - ap_jtag_tck PUll up - - - ap_jtag_tck PUll down - - - ap_jtag_tck select - - - - - - - ap_jtag_trst force enable for outoen. - - - ap_jtag_trst force output value for output. - - - ap_jtag_trst pin output value. - - - ap_jtag_trst force outoen value. - - - ap_jtag_trst force enable for pu/pd - - - ap_jtag_trst PUll up - - - ap_jtag_trst PUll down - - - ap_jtag_trst select - - - - - - - ap_jtag_tms force enable for outoen. - - - ap_jtag_tms force output value for output. - - - ap_jtag_tms pin output value. - - - ap_jtag_tms force outoen value. - - - ap_jtag_tms force enable for pu/pd - - - ap_jtag_tms PUll up - - - ap_jtag_tms PUll down - - - ap_jtag_tms select - - - - - - - ap_jtag_tdi force enable for outoen. - - - ap_jtag_tdi force output value for output. - - - ap_jtag_tdi pin output value. - - - ap_jtag_tdi force outoen value. - - - ap_jtag_tdi force enable for pu/pd - - - ap_jtag_tdi PUll up - - - ap_jtag_tdi PUll down - - - ap_jtag_tdi select - - - - - - - ap_jtag_tdo force enable for outoen. - - - ap_jtag_tdo force output value for output. - - - ap_jtag_tdo pin output value. - - - ap_jtag_tdo force outoen value. - - - ap_jtag_tdo force enable for pu/pd - - - ap_jtag_tdo PUll up - - - ap_jtag_tdo PUll down - - - ap_jtag_tdo select - - - - - - - gpio_14 force enable for outoen. - - - gpio_14 force output value for output. - - - gpio_14 pin output value. - - - gpio_14 force outoen value. - - - gpio_14 force enable for pu/pd - - - gpio_14 PUll up - - - gpio_14 PUll down - - - gpio_14 select - - - - - - - gpio_15 force enable for outoen. - - - gpio_15 force output value for output. - - - gpio_15 pin output value. - - - gpio_15 force outoen value. - - - gpio_15 force enable for pu/pd - - - gpio_15 PUll up - - - gpio_15 PUll down - - - gpio_15 select - - - - - - - gpio_18 force enable for outoen. - - - gpio_18 force output value for output. - - - gpio_18 pin output value. - - - gpio_18 force outoen value. - - - gpio_18 force enable for pu/pd - - - gpio_18 PUll up - - - gpio_18 PUll down - - - gpio_18 select - - - - - - - gpio_19 force enable for outoen. - - - gpio_19 force output value for output. - - - gpio_19 pin output value. - - - gpio_19 force outoen value. - - - gpio_19 force enable for pu/pd - - - gpio_19 PUll up - - - gpio_19 PUll down - - - gpio_19 select - - - - - - - gpio_20 force enable for outoen. - - - gpio_20 force output value for output. - - - gpio_20 pin output value. - - - gpio_20 force outoen value. - - - gpio_20 force enable for pu/pd - - - gpio_20 PUll up - - - gpio_20 PUll down - - - gpio_20 select - - - - - - - gpio_21 force enable for outoen. - - - gpio_21 force output value for output. - - - gpio_21 pin output value. - - - gpio_21 force outoen value. - - - gpio_21 force enable for pu/pd - - - gpio_21 PUll up - - - gpio_21 PUll down - - - gpio_21 select - - - - - - - gpio_22 force enable for outoen. - - - gpio_22 force output value for output. - - - gpio_22 pin output value. - - - gpio_22 force outoen value. - - - gpio_22 force enable for pu/pd - - - gpio_22 PUll up - - - gpio_22 PUll down - - - gpio_22 select - - - - - - - gpio_23 force enable for outoen. - - - gpio_23 force output value for output. - - - gpio_23 pin output value. - - - gpio_23 force outoen value. - - - gpio_23 force enable for pu/pd - - - gpio_23 PUll up - - - gpio_23 PUll down - - - gpio_23 select - - - - - - - gpio_8 force enable for outoen. - - - gpio_8 force output value for output. - - - gpio_8 pin output value. - - - gpio_8 force outoen value. - - - gpio_8 force enable for pu/pd - - - gpio_8 PUll up - - - gpio_8 PUll down - - - gpio_8 select - - - - - - - gpio_9 force enable for outoen. - - - gpio_9 force output value for output. - - - gpio_9 pin output value. - - - gpio_9 force outoen value. - - - gpio_9 force enable for pu/pd - - - gpio_9 PUll up - - - gpio_9 PUll down - - - gpio_9 select - - - - - - - gpio_10 force enable for outoen. - - - gpio_10 force output value for output. - - - gpio_10 pin output value. - - - gpio_10 force outoen value. - - - gpio_10 force enable for pu/pd - - - gpio_10 PUll up - - - gpio_10 PUll down - - - gpio_10 select - - - - - - - gpio_11 force enable for outoen. - - - gpio_11 force output value for output. - - - gpio_11 pin output value. - - - gpio_11 force outoen value. - - - gpio_11 force enable for pu/pd - - - gpio_11 PUll up - - - gpio_11 PUll down - - - gpio_11 select - - - - - - - gpio_12 force enable for outoen. - - - gpio_12 force output value for output. - - - gpio_12 pin output value. - - - gpio_12 force outoen value. - - - gpio_12 force enable for pu/pd - - - gpio_12 PUll up - - - gpio_12 PUll down - - - gpio_12 select - - - - - - - keyin_0 force enable for outoen. - - - keyin_0 force output value for output. - - - keyin_0 pin output value. - - - keyin_0 force outoen value. - - - keyin_0 force enable for pu/pd - - - keyin_0 PUll up - - - keyin_0 PUll down - - - keyin_0 select - - - - - - - keyin_1 force enable for outoen. - - - keyin_1 force output value for output. - - - keyin_1 pin output value. - - - keyin_1 force outoen value. - - - keyin_1 force enable for pu/pd - - - keyin_1 PUll up - - - keyin_1 PUll down - - - keyin_1 select - - - - - - - keyin_2 force enable for outoen. - - - keyin_2 force output value for output. - - - keyin_2 pin output value. - - - keyin_2 force outoen value. - - - keyin_2 force enable for pu/pd - - - keyin_2 PUll up - - - keyin_2 PUll down - - - keyin_2 select - - - - - - - keyin_3 force enable for outoen. - - - keyin_3 force output value for output. - - - keyin_3 pin output value. - - - keyin_3 force outoen value. - - - keyin_3 force enable for pu/pd - - - keyin_3 PUll up - - - keyin_3 PUll down - - - keyin_3 select - - - - - - - keyin_4 force enable for outoen. - - - keyin_4 force output value for output. - - - keyin_4 pin output value. - - - keyin_4 force outoen value. - - - keyin_4 force enable for pu/pd - - - keyin_4 PUll up - - - keyin_4 PUll down - - - keyin_4 select - - - - - - - keyin_5 force enable for outoen. - - - keyin_5 force output value for output. - - - keyin_5 pin output value. - - - keyin_5 force outoen value. - - - keyin_5 force enable for pu/pd - - - keyin_5 PUll up - - - keyin_5 PUll down - - - keyin_5 select - - - - - - - keyout_0 force enable for outoen. - - - keyout_0 force output value for output. - - - keyout_0 pin output value. - - - keyout_0 force outoen value. - - - keyout_0 force enable for pu/pd - - - keyout_0 PUll up - - - keyout_0 PUll down - - - keyout_0 select - - - - - - - keyout_1 force enable for outoen. - - - keyout_1 force output value for output. - - - keyout_1 pin output value. - - - keyout_1 force outoen value. - - - keyout_1 force enable for pu/pd - - - keyout_1 PUll up - - - keyout_1 PUll down - - - keyout_1 select - - - - - - - keyout_2 force enable for outoen. - - - keyout_2 force output value for output. - - - keyout_2 pin output value. - - - keyout_2 force outoen value. - - - keyout_2 force enable for pu/pd - - - keyout_2 PUll up - - - keyout_2 PUll down - - - keyout_2 select - - - - - - - keyout_3 force enable for outoen. - - - keyout_3 force output value for output. - - - keyout_3 pin output value. - - - keyout_3 force outoen value. - - - keyout_3 force enable for pu/pd - - - keyout_3 PUll up - - - keyout_3 PUll down - - - keyout_3 select - - - - - - - keyout_4 force enable for outoen. - - - keyout_4 force output value for output. - - - keyout_4 pin output value. - - - keyout_4 force outoen value. - - - keyout_4 force enable for pu/pd - - - keyout_4 PUll up - - - keyout_4 PUll down - - - keyout_4 select - - - - - - - keyout_5 force enable for outoen. - - - keyout_5 force output value for output. - - - keyout_5 pin output value. - - - keyout_5 force outoen value. - - - keyout_5 force enable for pu/pd - - - keyout_5 PUll up - - - keyout_5 PUll down - - - keyout_5 select - - - - - - - debug_host_rx force enable for outoen. - - - debug_host_rx force output value for output. - - - debug_host_rx pin output value. - - - debug_host_rx force outoen value. - - - debug_host_rx force enable for pu/pd - - - debug_host_rx PUll up - - - debug_host_rx PUll down - - - debug_host_rx select - - - - - - - debug_host_tx force enable for outoen. - - - debug_host_tx force output value for output. - - - debug_host_tx pin output value. - - - debug_host_tx force outoen value. - - - debug_host_tx force enable for pu/pd - - - debug_host_tx PUll up - - - debug_host_tx PUll down - - - debug_host_tx select - - - - - - - debug_host_clk force enable for outoen. - - - debug_host_clk force output value for output. - - - debug_host_clk pin output value. - - - debug_host_clk force outoen value. - - - debug_host_clk force enable for pu/pd - - - debug_host_clk PUll up - - - debug_host_clk PUll down - - - debug_host_clk select - - - - - - - sim_1_clk force enable for outoen. - - - sim_1_clk force output value for output. - - - sim_1_clk pin output value. - - - sim_1_clk force outoen value. - - - sim_1_clk force enable for pu/pd - - - sim_1_clk PUll up - - - sim_1_clk PUll down - - - sim_1_clk select - - - - - - - sim_1_dio force enable for outoen. - - - sim_1_dio force output value for output. - - - sim_1_dio pin output value. - - - sim_1_dio force outoen value. - - - sim_1_dio force enable for pu/pd - - - sim_1_dio PUll up - - - sim_1_dio PUll down - - - sim_1_dio select - - - - - - - sim_1_rst force enable for outoen. - - - sim_1_rst force output value for output. - - - sim_1_rst pin output value. - - - sim_1_rst force outoen value. - - - sim_1_rst force enable for pu/pd - - - sim_1_rst PUll up - - - sim_1_rst PUll down - - - sim_1_rst select - - - - - - - sim_2_clk force enable for outoen. - - - sim_2_clk force output value for output. - - - sim_2_clk pin output value. - - - sim_2_clk force outoen value. - - - sim_2_clk force enable for pu/pd - - - sim_2_clk PUll up - - - sim_2_clk PUll down - - - sim_2_clk select - - - - - - - sim_2_dio force enable for outoen. - - - sim_2_dio force output value for output. - - - sim_2_dio pin output value. - - - sim_2_dio force outoen value. - - - sim_2_dio force enable for pu/pd - - - sim_2_dio PUll up - - - sim_2_dio PUll down - - - sim_2_dio select - - - - - - - sim_2_rst force enable for outoen. - - - sim_2_rst force output value for output. - - - sim_2_rst pin output value. - - - sim_2_rst force outoen value. - - - sim_2_rst force enable for pu/pd - - - sim_2_rst PUll up - - - sim_2_rst PUll down - - - sim_2_rst select - - - - - - - rfdig_gpio_0 force enable for outoen. - - - rfdig_gpio_0 force output value for output. - - - rfdig_gpio_0 pin output value. - - - rfdig_gpio_0 force outoen value. - - - rfdig_gpio_0 force enable for pu/pd - - - rfdig_gpio_0 PUll up - - - rfdig_gpio_0 PUll down - - - rfdig_gpio_0 select - - - - - - - rfdig_gpio_1 force enable for outoen. - - - rfdig_gpio_1 force output value for output. - - - rfdig_gpio_1 pin output value. - - - rfdig_gpio_1 force outoen value. - - - rfdig_gpio_1 force enable for pu/pd - - - rfdig_gpio_1 PUll up - - - rfdig_gpio_1 PUll down - - - rfdig_gpio_1 select - - - - - - - rfdig_gpio_2 force enable for outoen. - - - rfdig_gpio_2 force output value for output. - - - rfdig_gpio_2 pin output value. - - - rfdig_gpio_2 force outoen value. - - - rfdig_gpio_2 force enable for pu/pd - - - rfdig_gpio_2 PUll up - - - rfdig_gpio_2 PUll down - - - rfdig_gpio_2 select - - - - - - - rfdig_gpio_3 force enable for outoen. - - - rfdig_gpio_3 force output value for output. - - - rfdig_gpio_3 pin output value. - - - rfdig_gpio_3 force outoen value. - - - rfdig_gpio_3 force enable for pu/pd - - - rfdig_gpio_3 PUll up - - - rfdig_gpio_3 PUll down - - - rfdig_gpio_3 select - - - - - - - rfdig_gpio_4 force enable for outoen. - - - rfdig_gpio_4 force output value for output. - - - rfdig_gpio_4 pin output value. - - - rfdig_gpio_4 force outoen value. - - - rfdig_gpio_4 force enable for pu/pd - - - rfdig_gpio_4 PUll up - - - rfdig_gpio_4 PUll down - - - rfdig_gpio_4 select - - - - - - - rfdig_gpio_5 force enable for outoen. - - - rfdig_gpio_5 force output value for output. - - - rfdig_gpio_5 pin output value. - - - rfdig_gpio_5 force outoen value. - - - rfdig_gpio_5 force enable for pu/pd - - - rfdig_gpio_5 PUll up - - - rfdig_gpio_5 PUll down - - - rfdig_gpio_5 select - - - - - - - rfdig_gpio_6 force enable for outoen. - - - rfdig_gpio_6 force output value for output. - - - rfdig_gpio_6 pin output value. - - - rfdig_gpio_6 force outoen value. - - - rfdig_gpio_6 force enable for pu/pd - - - rfdig_gpio_6 PUll up - - - rfdig_gpio_6 PUll down - - - rfdig_gpio_6 select - - - - - - - rfdig_gpio_7 force enable for outoen. - - - rfdig_gpio_7 force output value for output. - - - rfdig_gpio_7 pin output value. - - - rfdig_gpio_7 force outoen value. - - - rfdig_gpio_7 force enable for pu/pd - - - rfdig_gpio_7 PUll up - - - rfdig_gpio_7 PUll down - - - rfdig_gpio_7 select - - - - - - - secure_boot_mode force enable for outoen. - - - secure_boot_mode force output value for output. - - - secure_boot_mode pin output value. - - - secure_boot_mode force outoen value. - - - secure_boot_mode force enable for pu/pd - - - secure_boot_mode PUll up - - - secure_boot_mode PUll down - - - secure_boot_mode select - - - - - - - nand_flash_sel force enable for outoen. - - - nand_flash_sel force output value for output. - - - nand_flash_sel pin output value. - - - nand_flash_sel force outoen value. - - - nand_flash_sel force enable for pu/pd - - - nand_flash_sel PUll up - - - nand_flash_sel PUll down - - - nand_flash_sel select - - - - - - - - - - - configure whether to check the write id and read id is the same when release the token - - - - - Record Select Control -0: Record ID -1: Record User bits -the configuration of this register, can be ignored in APB bus matrix - - - - - total status register, 32 lock status, indicate if each lock is taken -Read LOCK[i]=0x0, lock i is in the Not Taken status -Read LOCK[i]=1, lock i is in the taken status - - - - - spinlock software flag register0 -this register is used to record message by software - - - - - spinlock software flag register1 -this register is used to record message by software - - - - - spinlock software flag register2 -this register is used to record message by software - - - - - spinlock software flag register3 -this register is used to record message by software - - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - the master id is stored in this register. The value of this reg in APB bus is 0x0 - - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - read 0x0, request and get the lock -read 0x1, reqeust but does not get the lock -write unlock token (0x55aa10c5), to unlock the lock -write any other, no effect - - - - - - hw version id - - - - - - - - - - All 0 check start index - - - All 0 check end index - - - - - write 1 to this bit will trigger all0 check to efuse, this bit is self-clear -,read this bit will always get 0.(use PREADY) - - - - - - Efuse type: 00 TSMC - - - IP version, now is r1p0 - - - - - Clk_efs divider, if this value is n, the frequency of controller will be divided by (n+1) from clk_efs. -In most case, this field not need to change. - - - This counter is used to control STROBE signal low level width in PGM mode, for TSMC efuse memory, no extra requirement for this signal, For 26Mhz efuse controller clock, by default, this width will be: 38.4*28=1075ns > 1us. -If you want to speed up program speed, can configure the register to a smaller value. - - - Program strobe high time. If set n, the Tpgm time will last for (n+1) clk_efuse cycle, only when PGM_EN=1 can write this field. - - - - - - If set the bit, lock bits will be written after PGM process. - - - efuse margin read mode enable - - - efuse double bit enable - - - program read back auto-check enable - - - efuse vdd enable - - - - - the bit indicates all 0 check fail. - - - the bit enk1 and enk2 is not switch correctly. - - - the bit indicates write process without setting magic number. - - - the bit indicates arbiter read block0 which may indicates unexpected access. - - - the bit indicates read process without setting vdd_on to 1. - - - the bit indicates write process without setting pg_en to 1. - - - The bit indicates shadow block is protected and can not be programmed if double_bit_en is set. -If SW send a PGM command to memory block[i], and the controller found this memory block is protected(which means the highest bit is 1), this bit will set to 1. - - - The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. - - - The bit indicates shadow block auto check failed after programming if double_bit_en is set. -If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. - - - The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. - - - - - write 1 will clear SEC_ALL0_CHECK_FLAG - - - write 1 will clear SEC_ENK_ERR_FLAG - - - write 1 will clear SEC_MAGNUM_WR_FLAG - - - write 1 will clear SEC_BLOCK0_RD_FLAG - - - write 1 will clear SEC_VDD_ON_RD_FLAG - - - write 1 will clear SEC_PG_EN_WR_FLAG - - - write 1 will clear SEC_WORD1_PROT_FLAG. Write 0 will do nothing. - - - write 1 will clear SEC_WORD0_PROT_FLAG. Write 0 will do nothing. - - - write 1 will clear SEC_WORD1_ERR_FLAG. Write 0 will do nothing. - - - write 1 will clear SEC_WORD0_ERR_FLAG. Write 0 will do nothing. - - - - - Magic number, only when this field is 0x8910, the efuse programming command can be handle. -Set the magic number right will lock the power switch and PGM enable. -So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : -(1) SEC_EFUSE_MAGIC_NUMBER =0x8910 -(2) PG_EN=1; -(3) Switch the power right; - - - - - 0: SEC access; 1: NON SEC address enable switch - - - SEC/NON-SEC address configure. -1: indicates SEC can access EFUSE_CFG0; -0: indicates NON-SEC can access EFUSE_CFG0; - - - - - set this bit will open static power supply for efuse memory, before any operation towards to efuse memory this bit have to set to 1. once this bit is cleared, the efuse will go to power down mose. - - - VDDQ power switch K2, to safely control this power switch. - - - VDDQ power switch K2, to safely control this power switch. - - - - - AP cortex-a5 dbgen, write once register,Invasive debug enable: -0 = not enabled -1 = enabled. - - - - - AP cortex-a5 niden, write once register,Noninvasive debug enable: -0 = not enabled -1 = enabled. - - - - - AP cortex-a5 spien, write once register,Secure privileged invasive debug enable: -0 = not enabled -1 = enabled. - - - - - AP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable: -0 = not enabled -1 = enabled. - - - - - AP cortex-a5 dap deviceen, write once register,device enable - - - - - RISCV JTAG disable, write once register - - - - - ZSP JTAG disable, write once register - - - - - debug host rx disable, write once register - - - - - uart1 rx disable, write once register - - - - - uart2 rx disable, write once register - - - - - uart3 rx disable, write once register - - - - - uart cp rx disable, write once register - - - - - mbist disable, write once register - - - - - scan disable, write once register - - - - - efuse bist enable, write once register - - - - - CP cortex-a5 dbgen, write once register,Invasive debug enable: -0 = not enabled -1 = enabled. - - - - - CP cortex-a5 niden, write once register,Noninvasive debug enable: -0 = not enabled -1 = enabled. - - - - - CP cortex-a5 spien, write once register,Secure privileged invasive debug enable: -0 = not enabled -1 = enabled. - - - - - CP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable: -0 = not enabled -1 = enabled. - - - - - CP cortex-a5 dcp deviceen, write once register,device enable - - - - - control efuse block0 read/write, write once register: -0 = not enable read/write efuse block0 -1 = enable read/write efuse block0 - - - - - control efuse block1 read/write, write once register: -0 = not enable read/write efuse block1 -1 = enable read/write efuse block1 - - - - - control efuse block2 read/write, write once register: -0 = not enable read/write efuse block2 -1 = enable read/write efuse block2 - - - - - control efuse block3 read/write, write once register: -0 = not enable read/write efuse block3 -1 = enable read/write efuse block3 - - - - - control efuse block4 read/write, write once register: -0 = not enable read/write efuse block4 -1 = enable read/write efuse block4 - - - - - control efuse block5 read/write, write once register: -0 = not enable read/write efuse block5 -1 = enable read/write efuse block5 - - - - - control efuse block6 read/write, write once register: -0 = not enable read/write efuse block6 -1 = enable read/write efuse block6 - - - - - control efuse block7 read/write, write once register: -0 = not enable read/write efuse block7 -1 = enable read/write efuse block7 - - - - - control efuse block8 read/write, write once register: -0 = not enable read/write efuse block8 -1 = enable read/write efuse block8 - - - - - control efuse block9 read/write, write once register: -0 = not enable read/write efuse block9 -1 = enable read/write efuse block9 - - - - - control efuse block10 read/write, write once register: -0 = not enable read/write efuse block10 -1 = enable read/write efuse block10 - - - - - control efuse block11 read/write, write once register: -0 = not enable read/write efuse block11 -1 = enable read/write efuse block11 - - - - - control efuse block12 read/write, write once register: -0 = not enable read/write efuse block12 -1 = enable read/write efuse block12 - - - - - control efuse block13 read/write, write once register: -0 = not enable read/write efuse block13 -1 = enable read/write efuse block13 - - - - - control efuse block14 read/write, write once register: -0 = not enable read/write efuse block14 -1 = enable read/write efuse block14 - - - - - control efuse block15 read/write, write once register: -0 = not enable read/write efuse block15 -1 = enable read/write efuse block15 - - - - - control efuse block16 read/write, write once register: -0 = not enable read/write efuse block16 -1 = enable read/write efuse block16 - - - - - control efuse block17 read/write, write once register: -0 = not enable read/write efuse block17 -1 = enable read/write efuse block17 - - - - - control efuse block18 read/write, write once register: -0 = not enable read/write efuse block18 -1 = enable read/write efuse block18 - - - - - control efuse block19 read/write, write once register: -0 = not enable read/write efuse block19 -1 = enable read/write efuse block19 - - - - - control efuse block20 read/write, write once register: -0 = not enable read/write efuse block20 -1 = enable read/write efuse block20 - - - - - control efuse block21 read/write, write once register: -0 = not enable read/write efuse block21 -1 = enable read/write efuse block21 - - - - - control efuse block22 read/write, write once register: -0 = not enable read/write efuse block22 -1 = enable read/write efuse block22 - - - - - control efuse block23 read/write, write once register: -0 = not enable read/write efuse block23 -1 = enable read/write efuse block23 - - - - - control efuse block24 read/write, write once register: -0 = not enable read/write efuse block24 -1 = enable read/write efuse block24 - - - - - control efuse block25 read/write, write once register: -0 = not enable read/write efuse block25 -1 = enable read/write efuse block25 - - - - - control efuse block26 read/write, write once register: -0 = not enable read/write efuse block26 -1 = enable read/write efuse block26 - - - - - control efuse block27 read/write, write once register: -0 = not enable read/write efuse block27 -1 = enable read/write efuse block27 - - - - - control efuse block28 read/write, write once register: -0 = not enable read/write efuse block28 -1 = enable read/write efuse block28 - - - - - control efuse block29 read/write, write once register: -0 = not enable read/write efuse block29 -1 = enable read/write efuse block29 - - - - - control efuse block30 read/write, write once register: -0 = not enable read/write efuse block30 -1 = enable read/write efuse block30 - - - - - control efuse block31 read/write, write once register: -0 = not enable read/write efuse block31 -1 = enable read/write efuse block31 - - - - - read config bits done status from efuse macro after por, then this bit is set to 1. - - - - - ap_ca5_dbgen status - - - ap_ca5_niden status - - - ap_ca5_spiden status - - - ap_ca5_spniden status - - - ap_ca5_dap_deviceen status - - - riscv_jtag_disable status - - - zsp_jtag_disable status - - - debug_host_rx_disable status - - - uart_1_rx_disable status - - - uart_2_rx_disable status - - - uart_3_rx_disable status - - - uart_cp_rx_disable status - - - mbist_disable status - - - scan_disable status - - - efuse_bist_en status - - - cp_ca5_dbgen status - - - cp_ca5_niden status - - - cp_ca5_spiden status - - - cp_ca5_spniden status - - - cp_ca5_dap_deviceen status - - - - - every block(31~0) read/write enable status - - - - - read block22_23 config bit - - - - - - wcn_jtag_disable, write once register - - - - - wcn_uart_disable, write once register - - - - - rf_uart_disable, write once register - - - - - - the registers are the mapping address to efuse macro. Write the 12'hxxx address means burn the data into block (12'hxxx<<2) of efuse. Read the 12'hxxx address will get the block (12'hxxx<<2) data of efuse. - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- 0000 = use Channel0 -
- 0001 = use Channel1 -
- 0010 = use Channel2 -
- ... -
- 0111 = use Channel7 -
- 1111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- 1111_1111 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Read FIFO data exchange high 8-bit and low 8-bit. -
- 0: Exchange; [31:0] = {b2,b3,b0,b1} -
- 1: No exchange; [31:0] = {b3,b2,b1,b0} - - - - - Write FIFO data exchange high 8-bit and low 8-bit. -
- 0: Exchange; [31:0] = {b3,b2,b1,b0} -
- 1: No exchange; [31:0] = {b2,b3,b0,b1} - - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- This channel works only in fifo mode. - - - - Channel Disable, write one in this bit to disable the channel. - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - Internal fifo level - - - - - - AHB Start Address. -
- This field represent the start address of the fifo. - The start address must 32-bit aligned. - - - - - - - AHB End Address. -
- This field represent the last address of the fifo (it is the first address not used in the fifo). -
- The end address must 32-bit aligned. - - - - - - - Transfer Count, transfer size in bytes. -
- This bit - indicated the transfer size in bytes to perform. Up to 16kbytes per - transfer. -
- During a transfer a write in this register add the new - value to the current TC. A read of this register return the current - current transfer count. - - - - - - - - - - - The Channel 0 conveys data from the AIF to the memory. -
- The Channel 1 conveys data from the memory to the AIF. -
- These Channels only exist with Voice Option. - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. - - - - - When 1 the channel is enabled - - - When 1 the fifo is empty - - - Cause interrupt End of FIFO. - - - Cause interrupt Half of FIFO. - - - Cause interrupt Quarter of FIFO. - - - Cause interrupt Three Quarter of FIFO. - - - Cause interrupt ahb error. - - - End of FIFO interrupt status bit. - - - Half of FIFO interrupt status bit. - - - Quarter of FIFO interrupt status bit. - - - Three Quarter of FIFO interrupt status bit. - - - ahb error interrupt status bit. - - - channel busy status bit. - - - - - AHB Start Address. This field represent the start address of the FIFO located in RAM. - - - - - - Fifo size in bytes, max 1MBytes. -
- The size of the fifo must be a multiple of 16 (The four LSB are always zero). - - - - - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - HALF FIFO Mask interrupt. When one this interrupt is enabled. - - - QUARTER FIFO Mask interrupt. When one this interrupt is - enabled. - - - THREE QUARTER FIFO Mask interrupt. When one this interrupt is - enabled. - - - ahb_error Mask interrupt. When one this interrupt is - enabled. - - - - - Write one to clear end of fifo interrupt. - - - Write one to clear half of fifo interrupt. - - - Write one to clear Quarter fifo interrupt. - - - Write one to clear Three Quarter fifo interrupt. - - - Write one to clear ahb_error interrupt. - - - - - Current AHB address value. The nine MSB bit is constant and - equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- 0000 = use Channel0 -
- 0001 = use Channel1 -
- 0010 = use Channel2 -
- ... -
- 0111 = use Channel7 -
- 1111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- 1111_1111 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Read FIFO data exchange high 8-bit and low 8-bit. -
- 0: Exchange; [31:0] = {b2,b3,b0,b1} -
- 1: No exchange; [31:0] = {b3,b2,b1,b0} - - - - - Write FIFO data exchange high 8-bit and low 8-bit. -
- 0: Exchange; [31:0] = {b3,b2,b1,b0} -
- 1: No exchange; [31:0] = {b2,b3,b0,b1} - - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- This channel works only in fifo mode. - - - - Channel Disable, write one in this bit to disable the channel. - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - Internal fifo level - - - - - - AHB Start Address. -
- This field represent the start address of the fifo. - The start address must 32-bit aligned. - - - - - - - AHB End Address. -
- This field represent the last address of the fifo (it is the first address not used in the fifo). -
- The end address must 32-bit aligned. - - - - - - - Transfer Count, transfer size in bytes. -
- This bit - indicated the transfer size in bytes to perform. Up to 16kbytes per - transfer. -
- During a transfer a write in this register add the new - value to the current TC. A read of this register return the current - current transfer count. - - - - - - - - - - - - - - - - Value loaded to OS timer. - - - - Write '1' to this bit will enable OS timer. -
- When read, the value is what we have written to this bit, it changes immediately after been written. - - - - - Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock. -
-
- '1' indicates OS timer enabled. -
- '0' indicates OS timer not enabled. - - - - - Read this bit will get the information if OS timer interruption clear operation is finished or not. -
-
- '1' indicates OS timer interruption clear operation is on going. -
- '0' indicates no OS timer interruption clear operation is on going. - - - - - Write '1' to this bit will set OS timer to repeat mode. -
- When read, get the information if OS timer is in repeat mode. -
-
- '1' indicates OS timer in repeat mode. -
- '0' indicates OS timer not in repeat mode. - - - - - Write '1' to this bit will set OS timer to wrap mode. -
- When read, get the information if OS timer is in wrap mode. -
-
- '1' indicates OS timer in wrap mode. -
- '0' indicates OS timer not in wrap mode. - - - - Write '1' to this bit will load the initial value to OS timer. - - - - - Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - - - Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal. - - - Write '1' to this bit will stop watchdog timer. - - - - Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer. -
- Use this bit to implement the watchog keep alive. - - - - - Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock. -
-
- '1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted. -
- '0' indicates watchdog timer is not enabled. - - - - - - - Load value of watchdog timer. Number of 32kHz Clock before Reset. -
- - - - - - - This bit enables interval IRQ mode. -
-
- '0': hw delay timer does not generate interval IRQ. -
- '1': hw delay timer generate an IRQ each interval. - - - - - interval of generating an HwTimer IRQ. -
-
- "00": interval of 1/8 second. -
- "01": interval of 1/4 second. -
- "10": interval of 1/2 second. -
- "11": interval of 1 second. - - - - - - Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF. - - - - - Set mask for OS timer IRQ. - - - Set mask for hardwre delay timer wrap IRQ. - - - Set mask for hardwre delay timer interval IRQ. - - - - - Clear mask for OS timer IRQ. - - - Clear mask for hardwre delay timer wrap IRQ. - - - Clear mask for hardwre delay timer interval IRQ. - - - - - Clear OS timer IRQ. - - - Clear hardware delay timer wrap IRQ. - - - Clear hardware delay timer interval IRQ. - - - - - OS timer IRQ cause. - - - hardware delay timer wrap IRQ cause. - - - hardware delay timer interval IRQ cause. - - - OS timer IRQ status. - - - hardware delay timer wrap IRQ status. - - - hardware delay timer interval IRQ status. - - - - - - - - - - - - - Value low 32bits loaded to OS timer. - - - - - Value high 24bits loaded to OS timer. - - - - Write '1' to this bit will enable OS timer. -
- When read, the value is what we have written to this bit, it changes immediately after been written. - - - - - Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock. -
-
- '1' indicates OS timer enabled. -
- '0' indicates OS timer not enabled. - - - - - Read this bit will get the information if OS timer interruption clear operation is finished or not. -
-
- '1' indicates OS timer interruption clear operation is on going. -
- '0' indicates no OS timer interruption clear operation is on going. - - - - - Write '1' to this bit will set OS timer to repeat mode. -
- When read, get the information if OS timer is in repeat mode. -
-
- '1' indicates OS timer in repeat mode. -
- '0' indicates OS timer not in repeat mode. - - - - - Write '1' to this bit will set OS timer to wrap mode. -
- When read, get the information if OS timer is in wrap mode. -
-
- '1' indicates OS timer in wrap mode. -
- '0' indicates OS timer not in wrap mode. - - - - Write '1' to this bit will load the initial value to OS timer. - - - - - Current value low 32bits of OS timer. - - - - - Current value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - - - Current locked value low 32bits of OS timer. - - - - - Current locked value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. - - - - - - This bit enables interval IRQ mode. -
-
- '0': hw delay timer does not generate interval IRQ. -
- '1': hw delay timer generate an IRQ each interval. - - - - - interval of generating an HwTimer IRQ. -
-
- "00": interval of 1/8 second. -
- "01": interval of 1/4 second. -
- "10": interval of 1/2 second. -
- "11": interval of 1 second. - - - - - - Current low 32bits value of the hardware delay timer. - - - - - Current high 32bits value of the hardware delay timer. - - - - - Current locked low 32bits value of the hardware delay timer. - - - - - Current locked high 32bits value of the hardware delay timer. - - - - - Set mask for OS timer IRQ. - - - Set mask for hardwre delay timer wrap IRQ. - - - Set mask for hardwre delay timer interval IRQ. - - - - - Clear mask for OS timer IRQ. - - - Clear mask for hardwre delay timer wrap IRQ. - - - Clear mask for hardwre delay timer interval IRQ. - - - - - Clear OS timer IRQ. - - - Clear hardware delay timer wrap IRQ. - - - Clear hardware delay timer interval IRQ. - - - - - OS timer IRQ cause. - - - hardware delay timer wrap IRQ cause. - - - hardware delay timer interval IRQ cause. - - - OS timer IRQ status. - - - hardware delay timer wrap IRQ status. - - - hardware delay timer interval IRQ status. - - - - - - - - - - - - - transmit data register - - - - - receive data register - - - - - baud rate divider constant N: (N>=4) -0011: N=4 -... -0111: N=8 -... -1111: N=16 - - - baud rate divider coeffcient,baud rate formula is: -BAUD RATE = Fclk/(Nx(BAUD_DIV+1)) -default baud rate is 921.6K, N=4, Ffun=26MHz. - - - - - Stick parity enble -1: enable -0: disable - - - Automatic baud detection complete interrupt enable -1: enable -0: disable - - - software flow control bit -1: enable -0: disable - - - 1: enable software flow XON interrupt -0: disable software flow XON interrupt - - - 1: enable software flow XOFF interrupt -0: disable software flow XOFF interrupt - - - 1: enable automatically detect baud rate -0: disable automatically detect baud rate - - - 1: autobaud BAUD_CONST=4'b1111 -0: autobaud BAUD_CONST=4'b0011 - - - 1: the automatic baud rate detects 2 bytes -0: the automatic baud rate detects 1 byte - - - 2'b00: automatic baud rate detection using odd check -2'b01: automatic baud rate detection using even check - - - 1: automatic baud rate detection has test bit -0: automatic baud rate detection has no test bit - - - RX FIFO reset control -1: RX FIFO reset -0: RX FIFO not reset; or set 1'b1, auto clear to 1'b0 - - - TX FIFO reset control -1: TX FIFO reset -0: TX FIFO not reset;or set to 1'b1,auto clear to 1'b0 - - - TRAIL byte manipulation: - 1: DMA dispose the TRAIL byte of RXFIFO - 0: ARM dispose the TRALL byte of RXFIFO - - - frames stop control -1: enable -0: disable - - - HDLC escape bytes enable control -1: enable add escape bytes(transit data),and remove escape byte(receive data) -0: disable - - - after RX timeout, enable hardware flow control (on condition that HWFC is enable) -1: after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control -0: after RX timeout, disable hardware flow control - - - RX trigger RTS enable control (on condition that HWFC is enable) -1: enable RX TRIG trigger RTS flow signal -0: disable RX TRIG trigger RTS flow signal - - - hardware flow control bit -1: enable -0: disable - - - RX timeout interrupt control bit -1: enable -0: disable - - - TX data interrupt control bit -1: enable TX interrupt -0: disable TX interrupt - - - RX data interrupt control bit -1: enable RX interrupt -0: disable RX interrupt - - - stop bit detection control bit -1: enable stop bit detection -0: disable stop bit detection - - - stop bit control bit -1: 2bit stop bit -0: 1bit stop bit - - - check bit -1: odd check -0: even check - - - check bit enable or not -1: enable -0: disable - - - - - RX FIFO trigger settings -00000000: don't trigger -00000001: 1 byte trigger -00000010: 2 bytes trigger -00000011: 3 bytes trigger -00000100: 4 bytes trigger -...... -01111111: 127bytes trigger -10000000: 128bytes trigger - - - - - TX FIFO trigger setting -00000000: 0 byte trigger -00000001: 1 byte trigger -00000010: 2 bytes trigger -00000011: 3 bytes trigger -00000100: 4 bytes trigger -...... -01111110: 126bytes trigger -01111111: 127bytes trigger -10000000: don't trigger - - - - - configure the time interval between sending data twice -0000: interval 0 baud rate clock -0001: interval 1 baud rate clock -1111: interval 15 baud rate clock - - - configure the threshold value of the UART timeout interrupt counter -00000000: configure the initial value of 0 baud rate clock -00000001: configure the initial value of 1 baud rate clock -00000010: configure the initial value of 2 baud rate clock -...... -11111111: configure the initial value of 255 baud rate clock - - - - - bit type is changed from rw1c to rc. - XON interrupt status bit -1: XON interrupt -0: not XON interrupt - - - bit type is changed from rw1c to rc. - XOFF interrupt status bit -1: XOFF interrupt -0: not XOFF interrupt - - - SWFC status -1: prohbit home terminal to send -0: allow home terminal to send - - - bit type is changed from rw1c to rc. - request to send status bit -1: prohibit far-end to send -0: request far-end to send - - - bit type is changed from rw1c to rc. - clear the sending status bit -1: prohibit home terminal to send -0: allow home terminal to send - - - bit type is changed from rw1c to rc. - the received data stop bit state -1: stop bit error -0: stop bit right - - - bit type is changed from rw1c to rc. - RX data parity status -1: parity error -0: parity right - - - bit type is changed from rw1c to rc. - RX data frame stop bit interrupt status bit -1: received frame stop bit "7E" -0: not received frame stop bit "7E" - - - bit type is changed from rw1c to rc. - RX data timeout interrupt status bit -1: timeout -0: not timeout - - - bit type is changed from rw1c to rc. - RX data interrupt status bit -1: RX_FIFO_CNTRX_TRIG -0: RX_FIFO_CNT<RX_TRIG - - - bit type is changed from rw1c to rc. - TX data interrupt status bit -1: TX_FIFO_CNT TX_TRIG -0: TX_FIFO_CNT >TX_TRIG - - - - - RX FIFO data number -00000000: RX FIFO has 0 data -00000001: RX FIFO has 1 data -...... -01111111: RX FIFO has 127 data -10000000: RX FIFO has 128 data - - - - - TX FIFO data number -00000000: TX FIFO has 0 data -00000001: TX FIFO has 1 data -...... -01111111: TX FIFO has 127 data -10000000: TX FIFO has 128 data - - - - - enable HDLC, the number of RX FIFO data when received at the end of frames(include the end of frames) -00000000: RX FIFO has 0 data -00000001: RX FIFO has 1 data -...... -01111111: RX FIFO has 127 data -10000000: RX FIFO has 128 data -Note: UART_RXFIFO_HDLC only read.Uart automatically updates the register value, after receiving the end of frames "7e". - - - - - After automatic detection, the detective byte is "AT" or "at" -1: "AT" -0: "at" - - - 1: Automatic detection complete,lock baud rate -0: automatic detection is not completed - - - 1: automatic detection failed, no matching bytes detected -0: automatic detection of matching bytes - - - automatic detection of BAUD_DIV values - - - - - XON characteristic parameter - - - XOFF characteristic parameter - - - - - - - - Number of key in the keypad - - - Number of key in the low data register - - - Number of key in the high data register - - - - - For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) : -
- 0 = Released -
- 1 = Pressed - - - - - - - - - - - For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn): -
- 0 = Released -
- 1 = Pressed - - - - - - - - - - - For keys in lines status -
- 0 = Released -
- 1 = Pressed - - - - - - - - - Indicate Key ON pressing status : -
- 0 = Release -
- 1 = Pressed - - - - - - - - - - - - This bit enables key detection. If this bit is '0', the key detection function - is disabled. Key ON is an exception, it can be still detected and generate key interrupt - even if KP_En = '0', however in this case, the debouncing time configuration in key - control register is ignored and the key ON state is considerred to be stable if it keeps - same in consecutive 2 cycles of 16KHz clock. -
-
- 0 = keypad disable -
- 1 = keypad enable - - - - De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms. - - - Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. - - - - each bit masks one input lines. -
- '1' = enabled -
- '0' = disabled -
- The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset. -
- Key_In 0: BOOT_MODE_NO_AUTO_PU. -
- Key_In 1: BOOT_MODE_FORCE_MONITOR. -
- Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE. -
- Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE. -
- Key_In 4: reserved - - - - - each bit masks one output lines. -
- '1' = enabled -
- '0' = disabled - - - - - - - This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1). -
- 0 = keypad event irq disable -
- 1 = keypad event irq enable - - - - - This bit mask keypad irq generated by event1 (all keys release event). -
- 0 = keypad event irq disable -
- 1 = keypad event irq enable - - - - - This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time. -
- 0 = keypad interval irq disable -
- 1 = keypad interval irq enable - - - - - - keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. - - - keypad event1(all keys release event) IRQ cause. - - - keypad interval irq cause. - - - keypad event0(key press or key release event, not including all keys release which is event1) irq status. - - - keypad event1(all keys release event) irq status. - - - keypad interval irq status. - - - - - Write '1' to this bit clears key IRQ. - - - - - - - - - - Enables the Pulse Width Tone output -
- 1 = Enable PWT output -
- 0 = Disable PWT output - - - - The working status of PWT. - - - - The PWT_Duty value can be used to set the approximate volume of the tone. -
- The PWT_Duty value must be less than or equal to half the PWT_Period value and must be at least a value of 8, otherwise no tone will be generated. - - - - - PWT_Period is the divider value to produce a tone of a given frequency. -
- To calculate the PWT_Period value, Use the following formula: -
- PWT_Period = FBASE/FNOTE -
- where FBASE is the frequency of the PWM module clock (it is based on the system frequency, 26, 39, 52, 78 or 104 MHz divided by 5). FNOTE is the frequency of the desired tone. - - - - - - Setting this bit to '0' will reset the Light Pulse Generator internal counters. - - - Setting this bit to '0' will reset the Light Pulse Generator internal counters. - - - Configures the duty cycle for the Light Pulse Generator by setting the ontime for the LPG output. The actual on-time is calculated as: Tick Period * LPG_OnTime * 256 where the Tick Period is nominally 1/16kHz. - - - - - - Configures the main period of the light pulse generator. The period is calculated based on the following configurations: -
- with the Tick Period ~ 1/16kHz -
- - - - - - - - - - - - - - - - - - - Sets the lower boundary for PWL pulse. When pulse mode is not used, this is the threshold value for the PWL0. Reading this value will return the current value used for the threshold. - - - Sets the upper boundary for PWL pulse. When pulse mode is not used, this value is ignored. Reading this value will return the LFSR value used for generating the PWL outputs. - - - When this bit is written with '1', the PWL 0 is enabled and the output is a PRBS whose average on-time is proportional to PWL_Min. This bit is cleared when either of the Force bits are written. Reading this bit will return the current state of the PWL0 enable. - - - Writing a '1' to this bit will force the PWL0 to output a low value. If the PWL0 was previously enabled, this will clear the bit. - - - Writing a '1' to this bit will force the PWL0 to output a high value. If the PWL0 was previously enabled, this will clear the bit. - - - This will enable the PWL pulse mode. The threshold will dynamically sweep between PWL_Min and PWL_Max at a rate depending on PWL_Pulse_Per. - - - Writing '1' to this bit will set the output enable. Reading this bit will return the current status. - - - Writing '1' to this bit will clear the output enable. - - - Writing a '1' to this bit will swap the PWL0 and PWL1 outputs. Reading this bit will return the current status. - - - Writing a '1' to this bit will unswap the PWL0/PWL1 outputs. - - - This value will adjust the pulse period when pulsing is enabled. - - - - - Average duty cycle for the Pulse Width Light 1 output. The average duty cycle is calculated as PWL1_Threshold/256. - - - LFSR value for PWL. - - - When this bit is written with '1', the PWL 1 is enabled and the output is a PRBS whose average on-time is proportional to PWL1_Threshold. This bit is cleared when either of the Force bits are written. Reading this bit will return the current state of the PWL1 enable. - - - Writing a '1' to this bit will force the PWL1 to output a low value. If the PWL1 was previously enabled, this will clear the bit. - - - Writing a '1' to this bit will force the PWL1 to output a high value. If the PWL1 was previously enabled, this will clear the bit. - - - Writing '1' to this bit will set the output enable. Reading this bit will return the current status. - - - Writing '1' to this bit will clear the output enable. - - - - - TSC X Value. - - - TSC X Value valid. - - - TSC Y Value. - - - TSC Y Value valid. - - - - - GPADC Value. - - - GPADC Value valid. - - - - - - - - - - - - These 2 bits configure the interval of generating an IRQ status. - - - - - - When write, command to program calendar with a new value (sec, min, hour, day, month, year, day of week) previously written in registers Calendar_LoadVal_H and Calendar_LoadVal_L. This bit is auto cleared. -
- '1' = load calendar timer. -
-
- When read, Calendar timer load status. -
- '1' = Calendar load has not finished. -
- '0' = Calendar load has finished. - - - - - When write, command to program alarm with a new value (sec, min, hour, day, month, year, day of week) prviously written in registers AlarmVal_H and AlarmVal_L. This bit is auto cleared. -
- '1' = load alarm. -
-
- When read, alarm load status. -
- '1' = alarm load has not finished. -
- '0' = alarm load has finished. - - - - - command to enable alarm. When alarm is triggered, it will generate a wakup. -
- '1' = enable alarm. -
-
- When read, alarm enable status. -
- '1' = alarm enable operation is on going, not finished. -
- '0' = alarm is enabled. - - - - - command to disable alarm. -
- '1' = disable alarm. -
-
- When read, alarm enable status. -
- '1' = alarm disable operation is on going, not finished. -
- '0' = alarm is disabled. - - - - - writing '1', clear Alarm triggered signal (connect to wakeup) and alarm triggered IRQ. -
-
- When read, get alarm clear status. -
- '1' = alarm clear operation is on going, not finished. -
- '0' = alarm is cleared. - - - - writing '1', clear interval IRQ. - - - - When write '1', Set interval Irq Mask. -
- When read, get interval Irq mask. - - - - - When write '1', Clear interval Irq Mask. -
- When read, get inteval Irq mask. - - - - - When write '1', mark calendar value to be not valid. -
-
- When read, Indicate if the Calendar value is valid or not. -
- The calendar value is not valid in case of mismatch between the calendar counter and the APB register, - which is the case of wakeup the phone after shut down. This mismatch disappear after one RTC cycle or - after re-porgramming a new calendar value. -
- '1' = not valid. - - - - - - Interval Irq Cause. - - - Alarm Irq Cause. - - - - Force Wakeup status. After set "Force_Wakeup" to '1' in sys_ctrl, the real - force_wakeup is not set immediatly, this bit indicates when the force wakeup is - really set. This bits also indicates if the interface between Calendar domain and - Core domain is enabled. -
- '1': force wakeup set. - - - - - Charger Mask status. After set "Chg_Mask" to '1' in sys_ctrl, the real - Chg_Mask line is not set immediatly, this bit indicates when the Chg_Mask line is - really set. -
- '1': Chg_Mask line set. - - - - Interval Irq Status. - - - - Alarm Enable Status. -
- Note: When calendar is not programmed, Alarm can be enabled or not. -
- It is suggested to clear Alarm Enable when program RTC. - - - - - '1' = Calendar has not been programmed. -
- This bit keep value '0' after the calendar is programmed once. - - - - - - Second value loaded to calendar, ranged from 0 to 59. - - - Minute value loaded to calendar, ranged from 0 to 59. - - - Hour value loaded to calendar, ranged from 0 to 23. - - - - - Day value loaded to calendar, ranged from 1 to 31. - - - Month value loaded to calendar, ranged from 1 to 12. - - - - Year value loaded to calendar, ranged from 0 to 127. -
- Represent year 2000 to 2127. - - - - - Day of the week value loaded to calendar, ranged from 1 to 7. -
- Represent Monday, Tuesday etc. - - - - - - Current Second value of calendar, ranged from 0 to 59. - - - - - - - - Current Minute value of calendar, ranged from 0 to 59. - - - - - - - - Current Hour value of calendar, ranged from 0 to 23. - - - - - - - - - - - Current Day value of calendar, ranged from 1 to 31. -
- Maximum number of days in each month are stored in the module, - and leap year is supported, so February can have 28 or 29 days. - - - - - - - - - Current Month value of calendar, ranged from 1 to 12. - - - - - - - - - Current Year value of calendar, ranged from 0 to 127. -
- Represent year 2000 to 2127. - - - - - - - - - - Current Day of the week value of calendar, ranged from 1 to 7. -
- Represent Monday, Tuesday etc. - - - - - - - - - - - Second value loaded to alarm, ranged from 0 to 59. - - - Minute value loaded to alarm, ranged from 0 to 59. - - - Hour value loaded to alarm, ranged from 0 to 23. - - - - - Day value loaded to alarm, ranged from 1 to 31. - - - Month value loaded to alarm, ranged from 1 to 12. - - - - Year value loaded to alarm, ranged from 0 to 127. -
- Represent year 2000 to 2127. - - - - - - - - - - - - - - - - - - - - - - - This reg contains data to be read or written by IFC. - In mono mode, data0 is before data1. - In stereo mode, data0 is in left channel. - - - This reg contains data to be read or written by IFC. - In mono mode, data1 is after data0. - In stereo mode, data1 is in right channel. - - - - - - - - - Audio Interface Enable. -
- 0: if AIF_Tone[0] is also 0, AIF is disabled. -
- 1 = AIF Enabled. If AIF_Tone[0] is also '1', Tx fifo continue to fetch and distribute data - from IFC when tone is enable. However, these data are not used. - - - - - - - - Disable AIF Tx functions. Important: if you want to do record only, you must set this bit otherwise AIF state machine will not start. -
- 0 = Both Tx Rx enabled. -
- 1 = Rx enabled only, Tx disabled. - - - - - - - - Selects parallel audio interface connected to analog front-end. -
- 0 = serial output. -
- 1 = parallel output. - - - - - - - - Selects parallel audio interface connected to analog front-end. -
- 0 = serial output. -
- 1 = parallel output. - - - - - - - - Selects parallel audio interface connected to analog front-end. -
- 0 = serial input. -
- 1 = parallel input. - - - - - - - - Selects parallel audio interface connected to analog front-end. -
- 0 = serial input. -
- 1 = parallel input. - - - - - In parallel mode, select AIF Tx Strobe mode. Reserved in serial mode. -
- 0 = Tx STB edge is in middle of data. -
- 1 = Tx STB edge is aligned to data edge. - - - - - This bit indicates if the AIF had needed some data while the Out Fifo was empty. - In case of data famine, the last available data will be sent again. -
- Write one to clear the out_underflow status bit. This bit is auto clear. - - - - - This bit indicates if the AIF had received some data while the Input Fifo was full. - If the Fifo In is full, the newly received data will be lost. -
- Write one to clear the in_overflow status bit. This bit is auto clear. - - - - - - - Sets the loop back mode. The feature is for debug only and can not work in DAI mode. - - - - - - - - - Configure serial AIF mode. "11" is reserved. -
-
- When mode is set DAI, the bit Master Mode should be set to '1', - bit Endian_L set to '0'. Data should be sent out on falling edge, which - requires either Bclk_Pol = '0' and Half_Cycle_DLY = '1' or Bclk_Pol = '1' - and Half_Cycle_DLY = '0'. Bits Tx_DLY and BCKOut_Gate must be configured - to '0' and '1'. -
- The DAI mode must NOT be modified after AIF is enabled. -
- - - - - - - Select AIF I2S input. - - - - - - configure AIF works in master mode (LRCLK and BCK timing signals are generated internally) - or slave mode (LRCLK and BCK timing signals are generated externally). - - - - - - When high, the output data format is with the least significant bit first. - - - - - - - configure LRCK polarity. -
- 0 = high level on LRCK means left channel, low level on LRCK means right channel. -
- 1 = high level on LRCK means right channel, low level on LRCK means left channel. -
-
- Note: this bit should be set to '0' (LEFT_H_RIGHT_L) in voice mode. - - - - - - . - - - - - - - Indicates the delay between serial data in MSB and LRCK edge. -
- "00" = Digital audio in MSB is aligned with LRCLK edge. -
- "01" = Digital audio in MSB is 1 cycle delayed to LRCLK edge. -
- "10" = Digital audio in MSB is 2 cycle delayed to LRCLK edge. -
- "11" = Digital audio in MSB is 3 cycle delayed to LRCLK edge. - - - - - - - - configure the delay between serial data out MSB and LRCK edge. -
- "0" = Digital audio out MSB is aligned with LRCLK edge. -
- "1" = Digital audio out MSB is 1 cycle delayed to LRCLK edge. - - - - - - - - ONLY for slave mode: configure 1 cycle supplementary Tx delay. -
- "0" = No supplementary Tx delay. -
- "1" = One Cycle supplementary Tx delay. - - - - - - - - Configure mono or stereo format for Audio data out. - This field is used both in serial mode or in parallel EXT mode. -
- "00" = stereo input from IFC, stereo output to pin. -
- "01" = mono input from IFC, stereo output in left channel to pin. - This value is reserved in parallel EXT mode. -
- "10" = mono input from IFC, stereo output duplicate in both channels to pin. -
- "11" = stereo input from IFC, mono output to left and right channel. This mode is only used for parallel stereo interface. -
-
- if AIF works in DAI or Voice mode, always select "00" mode STEREO_STEREO. - - - - - - - - Configure mono or stereo format for Audio data in. -
- 0 = stereo input from pin, stereo output to IFC. -
- 1 = stereo input from pin, mono input to IFC selected from left channel. -
-
- Users can change LRCK polarity to choose mono input from right channel. - - - - - - - - configure the ratio of BCK and LRCK cycle from 16 to 31. -
- Voice_Mode: "XXXX": each sample takes 16 + "XXXX" BCLK cycle. -
- Audio_Mode: "XXXX": each sample takes 2*(16 + "XXXX) BCLK cycle. 2 times than Voice Mode because in audio mode each sample occupies two channels. - - - - - - - if Master Mode, invert BCLK out. if slave Mode, invert BCLK in. - - - - - - delayed Audio output data or LRCK by half cycle. - - - - - - delayed Audio input data by half cycle. - - - - - - Sets the BckOut gating. This bit decide if AIF continue to output BCK clock after 16-bit data has been sent. - - - - - - - - - When this bit is set, the audio interface is enabled and a comfort tone or DTMF tone is output - on the audio interface instead of the regular data, even if the AIF_CTRL[0] enable bit is 0. -
- 0 = AIF is disabled if the AIF_CTRL[0] is also 0. -
- 1 = AIF is enabled and generates a tone. - - - - - - - Select whether a DTMF of a comfort tone is generated. - - - - - - Frequency of the first DTMF sine wave. - - - - - - Frequency of the second DTMF sine wave. - - - - - - Frequency of comfort tone. - - - Tone attenuation. The Comfort Tone or DTMF is attenuated according to this programmable gain. - - - - - - - - - Side Tone attenuation. The side tone is attenuated according to this programmable gain. -
- 0000 = mute. -
- 0001 = -36 dB. -
- 0010 = -33 dB. -
- 0011 = -30 dB. -
- 0100 = -27 dB. -
- 0101 = -24 dB. -
- 0110 = -21 dB. -
- 0111 = -18 dB. -
- 1000 = -15 dB. -
- 1001 = -12 dB. -
- 1010 = -9 dB. -
- 1011 = -6 dB. -
- 1100 = -3 dB. -
- 1101 = 0 dB. -
- 1110 = +3 dB. -
- 1111 = +6 dB. - - - - - - set rx load position delay, the range is 0 to 15. - - - - - "1" enable fm record. - - - "1" swap fm left and right channel. - - - - - - - - - - - - - - - - - [9:8]=='b00: select adc input data ; - [9:8]=='b01: select dac output loop data ; - [9:8]=='b1x: force to zero ; - - - [6]==0: fm input to aif1; [6]=1: audio codec input to aif1; - [7]==0: fm input to aif2; [7]=1: audio codec input to aif2; - - - [5:4]=='bx1: aif1 output to audio codec ; - [5:4]=='b10: aif2 output to audio codec ; - [5:4]=='b00: zero output to audio codec ; - - - ==1: enable adc left channel; - - - ==1: enable dac right channel; - - - ==1: enable adc left channel; - - - ==1: enable adc right channel; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ==1: enable mute; - - - ==1: enable soft mute; - - - dac mute counter1 threshold, step is countrolled by counter 0; - - - dac mute counter0 threshold - - - dac fs frequency - 0:96K - 1:48K - 2:44.1K - 3:32K - 4:24K - 5:22.05K - 6:16K - 7:12K - 8:11.025K - 9:9.6K - 10:8K - - - - - - - - - - - - - - - - - - - - - - - - - adc src upsample tap, sample rate=N*4K - - - - - - - - - - - - - ==1: enable audio adc parallel data loop to dac parallel data path; - - - - - - - - - - - - - - - - - - - - - - - - - - - ==0: force to 0 to select 26m audio clock; - - - - - - - ==1: invert output mclk ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - left adc channel dgain - 4'hf: 16dB - 4'he: 14dB - 4'hd: 12dB - 4'hc: 10dB - 4'hb: 8dB - 4'ha: 6dB - 4'h9: 4dB - 4'h8: 2dB - 4'h7: 0dB - 4'h6:-2dB - 4'h5:-4dB - 4'h4:-6dB - 4'h3:-8dB - 4'h2:-10dB - 4'h1:-12dB - 4'h0:mute - - - right adc channel dgain - 4'hf: 16dB - 4'he: 14dB - 4'hd: 12dB - 4'hc: 10dB - 4'hb: 8dB - 4'ha: 6dB - 4'h9: 4dB - 4'h8: 2dB - 4'h7: 0dB - 4'h6:-2dB - 4'h5:-4dB - 4'h4:-6dB - 4'h3:-8dB - 4'h2:-10dB - 4'h1:-12dB - 4'h0:mute - - - - - - - right adc channel dgain - 1:sel tone dac tone dgain - 0:sel normal dac dgain - - - - - - - left dac channel dgain - [5:1] = - 5'h1f: 05dB - 5'h1e: 04dB - 5'h1d: 03dB - 5'h1c: 02dB - 5'h1b: 01dB - 5'h1a: 00dB - 5'h19: -01dB - 5'h18: -02dB - 5'h17: -03dB - 5'h16: -04dB - 5'h15: -05dB - 5'h14: -06dB - 5'h13: -07dB - 5'h12: -08dB - 5'h11: -09dB - 5'h10: -10dB - 5'h0f: -11dB - 5'h0e: -12dB - 5'h0d: -13dB - 5'h0c: -14dB - 5'h0b: -15dB - 5'h0a: -16dB - 5'h09: -17dB - 5'h08: -18dB - 5'h07: -19dB - 5'h06: -20dB - 5'h05: -21dB - 5'h04: -22dB - 5'h03: -23dB - 5'h02: -24dB - 5'h01: -25dB - 5'h00: -26dB - [0]:1'b1,+0.5dB - [7]:1'b1,+12dB - [6]:1'b1,+6dB - - - right dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - - - left dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - right dac channel dgain - detail see dac_l_nor_dgain[7:0] - - - - - - - - OTG Control and Status Register -The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the controller. - - -
Mode: Device only
-
Session Request Success (SesReqScs)
-
The core sets this bit when a session request initiation is successful.
-
- 1'b0: Session request failure
-
- 1'b1: Session request success
- - - - -
Mode: Device only
-
Session Request (SesReq)
-
The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The core clears this bit when the HstNegSucStsChng bit is cleared.
-
If you use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the session request, the application must wait until the VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This discharge time varies between different PHYs and can be obtained from the PHY vendor.
-
- 1'b0: No session request
-
- 1'b1: Session request
- - - - -
Mode: Host only
-
VBUS Valid Override Enable (VbvalidOvEn)
-
This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.VbvalidOvVal.
-
- 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.VbvalidOvVal.
-
- 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller.
- - - - -
Mode: Host only
-
VBUS Valid OverrideValue (VbvalidOvVal)
-
This bit is used to set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn is set.
-
- 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1
-
- 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1
- - - - -
Mode: Host only
-
A-Peripheral Session Valid Override Enable (AvalidOvEn)
-
This bit is used to enable/disable the software to override the Avalid signal using the GOTGCTL.AvalidOvVal.
-
- 1'b1: Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal.
-
- 1'b0: Override is disabled and avalid signal from the respective PHY selected is used internally by the core
- - - - -
Mode: Host only
-
A-Peripheral Session Valid OverrideValue (AvalidOvVal)
-
This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is set.
-
- 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1
-
- 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1
- - - - -
Mode: Device only
-
B-Peripheral Session Valid Override Value (BvalidOvEn)
-
This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.BvalidOvVal.
-
- 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal.
-
- 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the force
- - - - -
Mode: Device only
-
B-Peripheral Session Valid OverrideValue (BvalidOvVal)
-
This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is set.
-
- 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
-
- 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
- - - - -
Mode: HNP-capable Device
-
Host Negotiation Success (HstNegScs)
-
The controller sets this bit when host negotiation is successful. The controller clears this bit when the HNP Request (HNPReq) bit in this register is set.
-
- 1'b0: Host negotiation failure
-
- 1'b1: Host negotiation success
- - - - -
Mode: HNP Capable OTG Device
-
HNP Request (HNPReq)
-
The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The controller clears this bit when the HstNegSucStsChng bit is cleared.
-
- 1'b0: No HNP request
-
- 1'b1: HNP request
- - - - -
Mode: HNP Capable OTG Host
-
Host Set HNP Enable (HstSetHNPEn)
-
The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device.
-
- 1'b0: Host Set HNP is not enabled
-
- 1'b1: Host Set HNP is enabled
- - - - -
Mode: HNP Capable OTG Device
-
Device HNP Enabled (DevHNPEn)
-
The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host.
-
- 1'b0: HNP is not enabled in the application
-
- 1'b1: HNP is enabled in the application
- - - - -
Mode: SRP Capable Host
-
Embedded Host Enable (EHEn)
-
It is used to select between OTG A Device state Machine and Embedded Host state machine.
-
- 1'b0: OTG A Device state machine is selected
-
- 1'b1: Embedded Host State Machine is selected
-
Note:
-
This field is valid only in SRP-Capable OTG Mode (OTG_MODE=0,1).
- - - - -
Mode: Host and Device
-
Debounce Filter Bypass
-
Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled.
-
- 1'b0: Disabled
-
- 1'b1: Enabled
-
-

-
Note: This register bit is valid only when debounce filters are present in core.
-
- - - - -
Mode: Host and Device
-
Connector ID Status (ConIDSts)
-
Indicates the connector ID status on a connect event.
-
- 1'b0: The core is in A-Device mode.
-
- 1'b1: The core is in B-Device mode.
-
-
Note:
-
The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.
-
Reset:
-
- 1'b0: in host only mode (OTG_MODE = 5 or 6)
-
- 1'b1: in all other configurations
- - - - -
Mode: Host only
-
Long/Short Debounce Time (DbncTime)
-
Indicates the debounce time of a detected connection.
-
- 1'b0: Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)
-
- 1'b1: Short debounce time, used for soft connections (2.5 micro-sec)
- - - - -
Mode: Host only
-
A-Session Valid (ASesVld)
-
Indicates the Host mode transceiver status.
-
- 1'b0: A-session is not valid
-
- 1'b1: A-session is valid
-
Note: If you do not enabled OTG features (such as SRP and HNP), the read reset value will be 1. The vbus assigns the values internally for non-SRP or non-HNP configurations.
-
In case of OTG_MODE=0, the reset value of this bit is 1'b0.
- - - - -
Mode: Device only
-
B-Session Valid (BSesVld)
-
Indicates the Device mode transceiver status.
-
- 1'b0: B-session is not valid.
-
- 1'b1: B-session is valid.
-
In OTG mode, you can use this bit to determine if the device is connected or disconnected.
-
-
Note:
-
- If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations.
-
- In case of OTG_MODE=0, the reset value of this bit is 1'b0.
-
- The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.
- - - - -
OTG Version (OTGVer)
-
Indicates the OTG revision.
-
- 1'b0: OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP.
-
- 1'b1: OTG Version 2.0. In this version the core supports only Data line pulsing for SRP.
- - - - -
Current Mode of Operation (CurMod)
-
Mode: Host and Device
-
Indicates the current mode.
-
- 1'b0: Device mode
-
- 1'b1: Host mode
-
Reset:
-
- 1'b1 in Host-only mode (OTG_MODE=5 or 6)
-
- 1'b0 in all other configurations
-
Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.
- - - - - OTG Interrupt Register -The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. - - -
Mode: Host and Device
-
Session End Detected (SesEndDet)
-
The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode: Host and Device
-
Session Request Success Status Change (SesReqSucStsChng)
-
The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode: Host and Device
-
Host Negotiation Success Status Change (HstNegSucStsChng)
-
The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode:Host and Device
-
Host Negotiation Detected (HstNegDet)
-
The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode: Host and Device
-
A-Device Timeout Change (ADevTOUTChg)
-
The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode: Host only
-
Debounce Done (DbnceDone)
-
The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit can be set only by the core and the application should write 1 to clear it.
- - - - - AHB Configuration Register -This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. - - -
Mode: Host and device
-
Global Interrupt Mask (GlblIntrMsk)
-
The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the controller.
-
- 1'b0: Mask the interrupt assertion to the application.
-
- 1'b1: Unmask the interrupt assertion to the application.
- - - - -
Mode: Host and device
-
Burst Length/Type (HBstLen)
-
This field is used in both External and Internal DMA modes. In External DMA mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the External DMA Controller interface to Synopsys DW_ahb_dmac or ARM PrimeCell.
-
External DMA Mode defines the DMA burst length in terms of 32-bit words:
-
- 4'b0000: 1 word
-
- 4'b0001: 4 words
-
- 4'b0010: 8 words
-
- 4'b0011: 16 words
-
- 4'b0100: 32 words
-
- 4'b0101: 64 words
-
- 4'b0110: 128 words
-
- 4'b0111: 256 words
-
- Others: Reserved
-
Internal DMA Mode AHB Master burst type:
-
- 4'b0000 Single
-
- 4'b0001 INCR
-
- 4'b0011 INCR4
-
- 4'b0101 INCR8
-
- 4'b0111 INCR16
-
- Others: Reserved
- - - - -
Mode: Host and device
-
DMA Enable (DMAEn)
-
-
This bit is always 0 when Slave-Only mode has been selected.
-
-
Reset: 1'b0
- - - - -
Mode: Host and device
-
Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
-
This bit is used only in Slave mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
-
With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered.
-
Host mode and with Shared FIFO with device mode:
-
- 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty
-
- 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty
-
Dedicated FIFO in device mode:
-
- 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
-
- 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty
- - - - -
Mode: Host only
-
Periodic TxFIFO Empty Level (PTxFEmpLvl)
-
Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode.
-
- 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty
-
- 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty
- - - - -
Mode: Host and Device
-
Remote Memory Support (RemMemSupp)
-
This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers.
-
- GAHBCFG.RemMemSupp=1
-
The int_dma_req output signal is asserted when the DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from the controller. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint.
-
- GAHBCFG.RemMemSupp=0
-
The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the Core Boundary and it does not wait for the sys_dma_done signal to complete the DATA transfers.
- - - - -
Mode: Host and Device
-
Notify All DMA Write Transactions (NotiAllDmaWrit)
-
This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1.
-
- GAHBCFG.NotiAllDmaWrit = 1
-
The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint.
-
- GAHBCFG.NotiAllDmaWrit = 0
-
The core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.
- - - - -
Mode: Host and Device
-
AHB Single Support (AHBSingle)
-
This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode.
-
- 1'b0: The remaining data in the transfer is sent using INCR burst size.
-
- 1'b1: The remaining data in the transfer is sent using Single burst size.
-
Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type. Enable this feature when the AHB Slave connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus).
- - - - -
Mode: Host and Device
-
Invert Descriptor Endianess (InvDescEndianess)
-
- 1'b0: Descriptor Endianness is same as AHB Master Endianness.
-
- 1'b1:
-
-- If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little Endian.
-
-- If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big Endian.
- - - - - USB Configuration Register -This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. - - -
Mode: Host and Device
-
HS/FS Timeout Calibration (TOutCal)
-
-
The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another.
-
-
The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
-
-
High-speed operation:
-
- One 30-MHz PHY clock = 16 bit times
-
- One 60-MHz PHY clock = 8 bit times
-
Full-speed operation:
-
- One 30-MHz PHY clock = 0.4 bit times
-
- One 60-MHz PHY clock = 0.2 bit times
-
- One 48-MHz PHY clock = 0.25 bit times
-
- - - - -
Mode: Host and Device
-
PHY Interface (PHYIf)
-
The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode.
-
- 1'b0: 8 bits
-
- 1'b1: 16 bits
-
This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit returns the value for the power-on interface selected during configuration.
- - - - -
Mode: Host and Device
-
ULPI or UTMI+ Select (ULPI_UTMI_Sel)
-
-
The application uses this bit to select either a UTMI+ interface or ULPI Interface.
-
- 1'b0: UTMI+ Interface
-
- 1'b1: ULPI Interface
- - - - -
Mode: Host and Device
-
Full-Speed Serial Interface Select (FSIntf)
-
-
The application uses this bit to select either a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface.
-
- 1'b0: 6-pin unidirectional full-speed serial interface
-
- 1'b1: 3-pin bidirectional full-speed serial interface
-
If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write.
-
-
Note: For supporting the new 4-pin bi-directional interface, you need to select 6-pin unidirectional FS serial mode, and add an external control to convert it to a 4-pin interface.
- - - - -
PHYSel
-
-
Mode: Host and Device
-
-
USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel)
-
The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a full-speed transceiver.
-
- 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
-
- 1'b1: USB 1.1 full-speed serial transceiver
-
If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit is always 0, with Write Only access.
-
If a high-speed PHY interface was not selected in, this bit is always 1, with Write Only access.
-
If both interface types were selected (parameters have non-zero values), the application uses this bit to select which interface is active, and access is Read and Write.
- - - - -
Mode: Host and Device
-
SRP-Capable (SRPCap)
-
The application uses this bit to control the controller's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to
-
activate VBUS and start a session.
-
- 1'b0: SRP capability is not enabled.
-
- 1'b1: SRP capability is enabled.
-
If SRP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.
- - - - -
Mode: Host and Device
-
HNP-Capable (HNPCap)
-
The application uses this bit to control the controller's HNP capabilities.
-
- 1'b0: HNP capability is not enabled.
-
- 1'b1: HNP capability is enabled.
-
If HNP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.
- - - - -
Mode: Device only
-
USB Turnaround Time (USBTrdTim)
-
Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). This must be programmed to
-
- 4'h5: When the MAC interface is 16-bit UTMI+ .
-
- 4'h9: When the MAC interface is 8-bit UTMI+ .
-
Note: The previous values are calculated for the minimum AHB frequency of 30 MHz. USB turnaround time is critical for certification where long cables and 5-Hubs are used. If you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, these bits can be programmed to a larger value.
- - - - -
PHY Low-Power Clock Select (PhyLPwrClkSel)
-
Mode: Host and Device
-
Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.
-
- 1'b0: 480-MHz Internal PLL clock
-
- 1'b1: 48-MHz External Clock
-
In 480 MHz mode, the UTMI interface operates at either 60 or 30-MHz, depending upon whether 8- or 16-bit data width is selected.
-
In 48-MHz mode, the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode (depending on the PHY vendor). This bit drives the utmi_fsls_low_power core output signal, and is valid only for UTMI+ PHYs.
- - - - -
Mode: Device only
-
TermSel DLine Pulsing Selection (TermSelDLPulse)
-
This bit selects utmi_termselect to drive data line pulse during SRP.
-
- 1'b0: Data line pulsing using utmi_txvalid (Default).
-
- 1'b1: Data line pulsing using utmi_termsel.
- - - - -
Mode: Host and Device
-
IC_USB-Capable (IC_USBCap)
-
The application uses this bit to control the core's IC_USB capabilities.
-
- 1'b0: IC_USB PHY Interface is not selected.
-
- 1'b1: IC_USB PHY Interface is selected.
-
This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0.
-
The reset value depends on the configuration parameter OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is read only.
- - - - -
Mode: Device only
-
Tx End Delay (TxEndDelay)
-
Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup.
-
- 1'b0 : Normal Mode.
-
- 1'b1 : Tx End delay.
- - - - -
Mode: Host and device
-
Force Host Mode (ForceHstMode)
-
Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig input pin.
-
- 1'b0 : Normal Mode.
-
- 1'b1 : Force Host Mode.
-
After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.
- - - - -
Mode:Host and device
-
Force Device Mode (ForceDevMode)
-
Writing a 1 to this bit forces the controller to device mode irrespective of utmiotg_iddig input pin.
-
- 1'b0 : Normal Mode.
-
- 1'b1 : Force Device Mode.
-
After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.
- - - - -
Mode: Host and device
-
Corrupt Tx packet (CorruptTxPkt)
-
This bit is for debug purposes only. Never Set this bit to 1. The application should always write 1'b0 to this bit.
- - - - - Reset Register -The application uses this register to reset various hardware features inside the controller. - - -
Mode: Host and Device
-
Core Soft Reset (CSftRst)
-
Resets the hclk and phy_clock domains as follows:
-
- Clears the interrupts and all the CSR registers except the following register bits:
-
-- PCGCCTL.RstPdwnModule
-
-- PCGCCTL.GateHclk
-
-- PCGCCTL.PwrClmp
-
-- PCGCCTL.StopPPhyLPwrClkSelclk
-
-- GUSBCFG.ForceDevMode
-
-- GUSBCFG.ForceHstMode
-
-- GUSBCFG.PhyLPwrClkSel
-
-- GUSBCFG.DDRSel
-
-- GUSBCFG.PHYSel
-
-- GUSBCFG.FSIntf
-
-- GUSBCFG.ULPI_UTMI_Sel
-
-- GUSBCFG.PHYIf
-
-- GUSBCFG.TxEndDelay
-
-- GUSBCFG.TermSelDLPulse
-
-- GUSBCFG.ULPIClkSusM
-
-- GUSBCFG.ULPIAutoRes
-
-- GUSBCFG.ULPIFsLs
-
-- GGPIO
-
-- GPWRDN
-
-- GADPCTL
-
-- HCFG.FSLSPclkSel
-
-- DCFG.DevSpd
-
-- DCTL.SftDiscon
-
- All module state machines
-
- All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed.
-
- Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately.
-
- When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset.
-
The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after
-
all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay). Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.
-
-
Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.
- - - - -
Mode: Host and Device
-
PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)
-
-
Resets the PIU FS Dedicated Controller
-
All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary.
-
This is a self clearing bit and core clears this bit after all the necessary logic is reset in the core.
- - - - -
Mode: Host only
-
Host Frame Counter Reset (FrmCntrRst)
-
The application writes this bit to reset the (micro)Frame number counter inside the core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0.
-
When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.
- - - - -
Mode: Host and Device
-
RxFIFO Flush (RxFFlsh)
-
The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction.
-
The application must only write to this bit after checking that the controller is neither reading from the RxFIFO nor writing to the RxFIFO.
-
-
The application must wait until the bit is cleared before performing any other operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear.
- - - - -
Mode: Host and Device
-
TxFIFO Flush (TxFFlsh)
-
This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction.
-
The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO.
-
Verify using these registers:
-
- ReadNAK Effective Interrupt ensures the core is not reading from the FIFO
-
- WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO.
-
Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.
- - - - -
Mode: Host and Device
-
TxFIFO Number (TxFNum)
-
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.
-
- 5'h0:
-
-- Non-periodic TxFIFO flush in Host mode
-
-- Non-periodic TxFIFO flush in device mode when in shared FIFO operation
-
-- Tx FIFO 0 flush in device mode when in dedicated FIFO mode
-
- 5'h1:
-
-- Periodic TxFIFO flush in Host mode
-
-- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation
-
-- TXFIFO 1 flush in device mode when in dedicated FIFO mode
-
- 5'h2:
-
-- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation
-
-- TXFIFO 2 flush in device mode when in dedicated FIFO mode
-
...
-
- 5'hF
-
-- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation
-
-- TXFIFO 15 flush in device mode when in dedicated FIFO mode
-
- 5'h10: Flush all the transmit FIFOs in device or host mode
- - - - -
Mode: Host and Device
-
DMA Request Signal (DMAReq)
-
Indicates that the DMA request is in progress. Used for debug.
- - - - -
Mode: Host and Device
-
AHB Master Idle (AHBIdle)
-
Indicates that the AHB Master State Machine is in the IDLE condition.
- - - - - Interrupt Register -This register interrupts the application for system-level events in the current mode (Device mode or Host mode). -Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit. -The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. -The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. -Note: Read the reset value of GINTSTS.CurMod only after the following conditions: - - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - - If IDDIG_FILTER is enabled, read only after the filter timer expires. - - -
Mode: Host and Device
-
Current Mode of Operation (CurMod)
-
Indicates the current mode.
-
- 1'b0: Device mode
-
- 1'b1: Host mode
-
-

-
Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.
-
- - - - -
Mode: Host and Device
-
Mode Mismatch Interrupt (ModeMis)
-
The core sets this bit when the application is trying to access:
-
- A Host mode register, when the controller is operating in Device mode
-
- A Device mode register, when the controller is operating in Host mode
-
The register access is completed on the AHB with an OKAY response, but is ignored by the controller internally and does not affect the operation of the controller.
-
This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Mode: Host and Device
-
OTG Interrupt (OTGInt)
-
The controller sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the GOTGINT register to clear this bit.
- - - - -
Mode: Host and Device
-
Start of (micro)Frame (Sof)
-
-
In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.
-
-
In Device mode, the controller sets this bit to indicate that an SOF token has been received on the USB. The application can read the Device Status register to get the current (micro)Frame number. This interrupt is seen only when the core is operating at either HS or FS. This bit can be set only by the core and the application must write 1 to clear it.
-
-
Note: This register may return 1'b1 if read immediately after power-on reset.
-
If the register bit reads 1'b1 immediately after power-on reset, it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode).
-
The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit.
- - - - -
Mode: Host and Device
-
RxFIFO Non-Empty (RxFLvl)
-
-
Indicates that there is at least one packet pending to be read from the RxFIFO.
- - - - -
Mode: Host and Device
-
Non-periodic TxFIFO Empty (NPTxFEmp)
-
This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least one Entry to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl).
-
In host mode, the application can use GINTSTS.NPTxFEmp with the OTG_EN_DED_TX_FIFO parameter set to either 1 or 0.
-
In device mode, the application uses GINTSTS.NPTxFEmp when OTG_EN_DED_TX_FIFO=0. When OTG_EN_DED_TX_FIFO=1, the application uses DIEPINTn.TxFEmp.
- - - - -
Mode: Device only
-
Global IN Non-periodic NAK Effective (GINNakEff)
-
Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit Set by the application. This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). This interrupt does not necessarily mean that a NAK handshake
-
is sent out on the USB. The STALL bit takes precedence over the NAK bit.
- - - - -
Mode: Device only
-
Global OUT NAK Effective (GOUTNakEff)
-
Indicates that the Set Global OUT NAK bit in the Device Control register (DCTL.SGOUTNak), Set by the application, has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (DCTL.CGOUTNak).
- - - - -
Mode: Device only
-
Early Suspend (ErlySusp)
-
The controller sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
- - - - -
Mode: Device only
-
USB Suspend (USBSusp)
-
The controller sets this bit to indicate that a suspend was detected on the USB. The controller enters the Suspended state when there is no activity on the linestate signal for an extended period of time.
- - - - -
Mode: Device only
-
USB Reset (USBRst)
-
The controller sets this bit to indicate that a reset is detected on the USB.
- - - - -
Mode: Device only
-
Enumeration Done (EnumDone)
-
The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (DSTS) register to obtain the enumerated speed.
- - - - -
Mode: Device only
-
Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
-
The controller sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.
- - - - -
Mode: Device only
-
End of Periodic Frame Interrupt (EOPF)
-
Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG.PerFrInt) has been reached in the current microframe.
- - - - -
Mode: Device only
-
Endpoint Mismatch Interrupt (EPMis)
-
Note: This interrupt is valid only in shared FIFO operation.
-
Indicates that an IN token has been received for a non-periodic endpoint, but the data for another endpoint is present in the top of the Non-periodic Transmit FIFO and the IN endpoint mismatch count programmed by the application has expired.
- - - - -
Mode: Device only
-
IN Endpoints Interrupt (IEPInt)
-
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding DIEPINTn register to
-
clear this bit.
- - - - -
Mode: Device only
-
OUT Endpoints Interrupt (OEPInt)
-
The controller sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the interrupt. The application must
-
clear the appropriate status bit in the corresponding DOEPINTn register to clear this bit.
- - - - -
Mode: Device only
-
Incomplete Isochronous IN Transfer (incompISOIN)
-
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.
-
Note: This interrupt is not asserted in Scatter/Gather DMA mode.
- - - - -
Incomplete Periodic Transfer (incomplP)
-
Mode: Host only
-
In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current microframe.
-
Incomplete Isochronous OUT Transfer (incompISOOUT)
-
Mode: Device only
-
The Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.
- - - - -
Mode: Device only
-
Data Fetch Suspended (FetSusp)
-
This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data. For IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.
-
-
For example, after detecting an endpoint mismatch, the application:
-
- Sets a Global non-periodic IN NAK handshake
-
- Disables IN endpoints
-
- Flushes the FIFO
-
- Determines the token sequence from the IN Token Sequence Learning Queue
-
- Re-enables the endpoints
-
- Clears the Global non-periodic IN NAK handshake
-
If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received. The core generates an 'IN token received when FIFO empty' interrupt. The DWC_otg then sends the host a NAK response. To avoid this scenario, the application can check the GINTSTS.FetSusp interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake.
-
-
Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a Global IN NAK handshake.
- - - - -
Mode: Device only
-
Reset detected Interrupt (ResetDet)
-
In Device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in Suspend.
-
-
In Host mode, this interrupt is not asserted.
- - - - -
Mode: Host only
-
Host Port Interrupt (PrtInt)
-
The core sets this bit to indicate a change in port status of one of the controller ports in Host mode. The application must read the Host Port Control and Status (HPRT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the Host Port
-
Control and Status register to clear this bit.
- - - - -
Mode: Host only
-
Host Channels Interrupt (HChInt)
-
The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The application must read the Host All Channels Interrupt (HAINT) register to determine the exact number of the channel on which the interrupt occurred, and Then read the corresponding Host
-
Channel-n Interrupt (HCINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the HCINTn register to clear this bit.
- - - - -
Mode: Host only
-
Periodic TxFIFO Empty (PTxFEmp)
-
This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.PTxFEmpLvl).
- - - - -
Mode: Host and Device
-
Connector ID Status Change (ConIDStsChng)
-
The core sets this bit when there is a change in connector ID status.
- - - - -
Mode: Host only
-
Disconnect Detected Interrupt (DisconnInt)
-
Asserted when a device disconnect is detected.
- - - - -
Mode: Host and Device
-
Session Request/New Session Detected Interrupt (SessReqInt)
-
In Host mode, this interrupt is asserted when a session request is detected from the device. In Host mode, this interrupt is asserted when a session request is detected from the device.
-
In Device mode, this interrupt is asserted when the utmisrp_bvalid signal goes high.
-
For more information on how to use this interrupt, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.
- - - - -
Mode: Host and Device
-
Resume/Remote Wakeup Detected Interrupt (WkUpInt)
-
Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
-
- During Suspend(L2):
-
-- Device Mode: This interrupt is asserted only when Host Initiated Resume is detected on USB.
-
-- Host Mode: This interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB.
-
For more information, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.
-
- During LPM(L1):
-
-- Device Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.
-
-- Host Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.
-
For more information, see 'LPM Entry and Exit Programming Model' in the Programming Guide.
- - - - - Interrupt Mask Register -This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit corresponding to that interrupt is still set. -Note: The fields of this register change depending on host or device mode. - - -
Mode: Host and Device
-
Mode Mismatch Interrupt Mask (ModeMisMsk)
- - - - -
Mode: Host and Device
-
OTG Interrupt Mask (OTGIntMsk)
- - - - -
Mode: Host and Device
-
Start of (micro)Frame Mask (SofMsk)
- - - - -
Mode: Host and Device
-
Receive FIFO Non-Empty Mask (RxFLvlMsk)
- - - - -
Mode: Host and Device
-
Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)
- - - - -
Mode: Device only,
-
Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)
- - - - -
Mode: Device only
-
Global OUT NAK Effective Mask (GOUTNakEffMsk)
- - - - -
Mode: Device only
-
Early Suspend Mask (ErlySuspMsk)
- - - - -
Mode: Device only
-
USB Suspend Mask (USBSuspMsk)
- - - - -
Mode: Device only
-
USB Reset Mask (USBRstMsk)
- - - - -
Mode: Device only
-
Enumeration Done Mask (EnumDoneMsk)
- - - - -
Mode: Device only
-
Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)
- - - - -
Mode: Device only
-
End of Periodic Frame Interrupt Mask (EOPFMsk)
- - - - -
Mode: Device only
-
Endpoint Mismatch Interrupt Mask (EPMisMsk)
- - - - -
Mode: Device only
-
IN Endpoints Interrupt Mask (IEPIntMsk)
- - - - -
Mode: Device only
-
OUT Endpoints Interrupt Mask (OEPIntMsk)
- - - - -
Incomplete Periodic Transfer Mask (incomplPMsk)
-
Mode: Host only
-
Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk)
-
Mode: Device only
- - - - -
Mode: Device only
-
Data Fetch Suspended Mask (FetSuspMsk)
- - - - -
Mode: Device only
-
Reset detected Interrupt Mask (ResetDetMsk)
- - - - -
Mode: Host only
-
Host Port Interrupt Mask (PrtIntMsk)
- - - - -
Mode: Host only
-
Host Channels Interrupt Mask (HChIntMsk)
- - - - -
Mode: Host only
-
Periodic TxFIFO Empty Mask (PTxFEmpMsk)
- - - - -
Mode: Host and Device
-
Connector ID Status Change Mask (ConIDStsChngMsk)
- - - - -
Mode: Host and Device
-
Disconnect Detected Interrupt Mask (DisconnIntMsk)
- - - - -
Mode: Host and Device
-
Session Request/New Session Detected Interrupt Mask (SessReqIntMsk)
- - - - -
Mode: Host and Device
-
Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)
-
The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in suspend state.
- - - - - Receive Status Debug Read Register -A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. -The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status read when the receive FIFO is empty and returns a value of 32'h0000_0000. -Note: - - Use of these fields vary based on whether the core is functioning as a host or a device. - - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation. - - -
Channel Number (ChNum)
-
Mode: Host only
-
Indicates the channel number to which the current received packet belongs.
-
Endpoint Number (EPNum)
-
Mode: Device only
-
Indicates the endpoint number to which the current received packet belongs.
- - - - -
Byte Count (BCnt)
-
-
In host mode, indicates the byte count of the received IN data packet.
-
-
In device mode, indicates the byte count of the received data packet.
- - - - -
Data PID (DPID)
-
-
In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.
-
- 2'b00: DATA0
-
- 2'b10: DATA1
-
- 2'b01: DATA2
-
- 2'b11: MDATA
-
Reset: 2'h0
- - - - -
Packet Status (PktSts) indicates the status of the received packet.
-
In host mode,
-
- 4'b0010: IN data packet received
-
- 4'b0011: IN transfer completed (triggers an interrupt)
-
- 4'b0101: Data toggle error (triggers an interrupt)
-
- 4'b0111: Channel halted (triggers an interrupt)
-
- Others: Reserved
-
Reset:4'b0
-
-
In device mode,
-
- 4'b0001: Global OUT NAK (triggers an interrupt)
-
- 4'b0010: OUT data packet received
-
- 4'b0011: OUT transfer completed (triggers an interrupt)
-
- 4'b0100: SETUP transaction completed (triggers an interrupt)
-
- 4'b0110: SETUP data packet received
-
- Others: Reserved
-
Reset:4'h0
- - - - -
Mode: Device only
-
Frame Number (FN)
-
This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.
- - - - - Receive Status Read/Pop Register -A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and additionally pops the top data entry out of the RxFIFO. -The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 32'h0000_0000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. -Note: - - Use of these fields vary based on whether the core is functioning as a host or a device. - - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation. - - -
Channel Number (ChNum)
-
Mode: Host only
-
Indicates the channel number to which the current received packet belongs.
-
Endpoint Number (EPNum)
-
Mode: Device only
-
Indicates the endpoint number to which the current received packet belongs.
- - - - -
Byte Count (BCnt)
-
-
In host mode, indicates the byte count of the received IN data packet.
-
-
In device mode, indicates the byte count of the received data packet.
- - - - -
Data PID (DPID)
-
-
In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.
-
- 2'b00: DATA0
-
- 2'b10: DATA1
-
- 2'b01: DATA2
-
- 2'b11: MDATA
-
Reset: 2'h0
- - - - -
Packet Status (PktSts) indicates the status of the received packet.
-
In host mode,
-
- 4'b0010: IN data packet received
-
- 4'b0011: IN transfer completed (triggers an interrupt)
-
- 4'b0101: Data toggle error (triggers an interrupt)
-
- 4'b0111: Channel halted (triggers an interrupt)
-
- Others: Reserved
-
Reset:4'b0
-
-
In device mode,
-
- 4'b0001: Global OUT NAK (triggers an interrupt)
-
- 4'b0010: OUT data packet received
-
- 4'b0011: OUT transfer completed (triggers an interrupt)
-
- 4'b0100: SETUP transaction completed (triggers an interrupt)
-
- 4'b0110: SETUP data packet received
-
- Others: Reserved
-
Reset:4'h0
- - - - -
Mode: Device only
-
Frame Number (FN)
-
This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.
- - - - - Receive FIFO Size Register -The application can program the RAM size that must be allocated to the RxFIFO. - - -
Mode: Host and Device
-
RxFIFO Depth (RxFDep)
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth during configuration.
-
If Enable Dynamic FIFO Sizing is selected in coreConsultant, these flops are optimized, and reads return the power-on value.
-
If Enable Dynamic FIFO Sizing is selected in coreConsultant, you can write a new value in this field. Programmed values must not exceed the power-on value.
- - - - - Non-periodic Transmit FIFO Size Register -The application can program the RAM size and the memory start address for the Non-periodic TxFIFO -Note: The fields of this register change depending on host or device mode. - - -
Non-periodic Transmit RAM Start Address (NPTxFStAddr)
-
For host mode, this field is always valid.
-
This field contains the memory start address for Non-periodic Transmit FIFO RAM.
-
- This field is determined during coreConsultant configuration by "Enable Dynamic FIFO Sizing?" (OTG_DFIFO_DYNAMIC):OTG_DFIFO_DYNAMIC = 0
-
These flops are optimized, and reads return the power-on value.
-
- OTG_DFIFO_DYNAMIC = 1 The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.
-
Programmed values must not exceed the power-on value set in coreConsultant.
-
The power-on reset value of this field is specified during coreConsultant configuration by Largest Rx Data FIFO Depth (parameter OTG_RX_DFIFO_DEPTH).
- - - - -
Mode: Host only
-
Non-periodic TxFIFO Depth (NPTxFDep)
-
For host mode, this field is always valid.
-
For device mode, this field is valid only when OTG_EN_DED_TX_FIFO=0.
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
This attribute of field is determined during coreConsultant configuration by "Enable Dynamic FIFO Sizing?" (OTG_DFIFO_DYNAMIC):
-
- OTG_DFIFO_DYNAMIC = 0: These flops are optimized, and reads return the power-on value.
-
- OTG_DFIFO_DYNAMIC = 1: The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.
-
The power-on reset value of this field is specified during coreConsultant configuration as Largest IN Endpoint FIFO 0 Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_0).
- - - - - Non-periodic Transmit FIFO/Queue Status Register -In Device mode, this register is valid only in Shared FIFO operation. -This read-only register contains the free space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request Queue. - - -
Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)
-
Indicates the amount of free space available in the Non-periodic TxFIFO.
-
Values are in terms of 32-bit words.
-
- 16'h0: Non-periodic TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 <= n <= 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
-
Reset: Configurable
- - - - -
Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)
-
Indicates the amount of free space available in the Non-periodic Transmit Request Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only IN requests.
-
- 8'h0: Non-periodic Transmit Request Queue is full
-
- 8'h1: 1 location available
-
- 8'h2: 2 locations available
-
- n: n locations available (0 <= n <= 8)
-
- Others: Reserved
-
Reset: Configurable
- - - - -
Top of the Non-periodic Transmit Request Queue (NPTxQTop)
-
Entry in the Non-periodic Tx Request Queue that is currently being processed by the MAC.
-
-
- Bits [30:27]: Channel/endpoint number
-
- Bits [26:25]:
-
- 2'b00: IN/OUT token
-
-- 2'b01: Zero-length transmit packet (device IN/host OUT)
-
-- 2'b10: PING/CSPLIT token
-
-- 2'b11: Channel halt command
-
- Bit [24]: Terminate (last Entry for selected channel/endpoint)
-
Reset: 7'h0
- - - - - - General Purpose Input/Output Register -The application can use this register for general purpose input/output ports or for debugging. - - -
-
General Purpose Input (GPI)
-
-
This field's read value reflects the gp_i[15:0] core input value.
- - - - -
-
General Purpose Output (GPO)
-
-
This field is driven as an output from the core, gp_o[15:0]. The
-
application can program this field to determine the
-
corresponding value on the gp_o[15:0] output.
- - - - - User ID Register -This is a read/write register containing the User ID. It is implemented only if Remove Optional Features? was deselected during coreConsultant configuration (parameter OTG_RM_OPT_FEATURES = 0). The power-on value for this register is specified as the Power-on Value of User ID Register User Identification Register during coreConsultant configuration (parameter OTG_USERID). This register can be used in the following ways: - - To store the version or revision of your system - - To store hardware configurations that are outside the DWC_otg core - - As a scratch register - - -
User ID (UserID)
-
Application-programmable ID field.
-
Reset: Configurable
- - - - - Synopsys ID Register -This read-only register contains the release number of the core being used. - - -
Release number of the controller being used currently.
- - - - - User Hardware Configuration 1 Register -This register contains the logical endpoint direction(s) selected using coreConsultant. - - -
This 32-bit field uses two bits per
-
endpoint to determine the endpoint direction.
-
-
Endpoint
-
- Bits [31:30]: Endpoint 15 direction
-
- Bits [29:28]: Endpoint 14 direction
-
...
-
- Bits [3:2]: Endpoint 1 direction
-
- Bits[1:0]: Endpoint 0 direction (always BIDIR)
-
Direction
-
- 2'b00: BIDIR (IN and OUT) endpoint
-
- 2'b01: IN endpoint
-
- 2'b10: OUT endpoint
-
- 2'b11: Reserved
-
Note: This field is configured using the OTG_EP_DIR_1(n) parameter.
- - - - - User Hardware Configuration 2 Register -This register contains configuration options selected using coreConsultant. - - -
Mode of Operation (OtgMode)
-
- 3'b000: HNP- and SRP-Capable OTG (Host & Device)
-
- 3'b001: SRP-Capable OTG (Host & Device)
-
- 3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device)
-
- 3'b011: SRP-Capable Device
-
- 3'b100: Non-OTG Device
-
- 3'b101: SRP-Capable Host
-
- 3'b110: Non-OTG Host
-
- Others: Reserved
-
Note: This field is configured using the OTG_MODE parameter.
- - - - -
Architecture (OtgArch)
-
- 2'b00: Slave-Only
-
- 2'b01: External DMA
-
- 2'b10: Internal DMA
-
- Others: Reserved
-
Note: This field is configured using the OTG_ARCHITECTURE parameter.
- - - - -
Point-to-Point (SingPnt)
-
- 1'b0: Multi-point application (hub and split support)
-
- 1'b1: Single-point application (no hub and split support)
-
Note: This field is configured using the OTG_SINGLE_POINT parameter.
- - - - -
High-Speed PHY Interface Type (HSPhyType)
-
- 2'b00: High-Speed interface not supported
-
- 2'b01: UTMI+
-
- 2'b10: ULPI
-
- 2'b11: UTMI+ and ULPI
-
Note: This field is configured using the OTG_HSPHY_INTERFACE parameter.
- - - - -
Full-Speed PHY Interface Type (FSPhyType)
-
- 2'b00: Full-speed interface not supported
-
- 2'b01: Dedicated full-speed interface
-
- 2'b10: FS pins shared with UTMI+ pins
-
- 2'b11: FS pins shared with ULPI pins
-
Note: This field is configured using the OTG_FSPHY_INTERFACE parameter.
- - - - -
Number of Device Endpoints (NumDevEps)
-
-
Indicates the number of device endpoints supported by the core in Device mode.
-
-
The range of this field is 0-15.
-
-
Note: This field is configured using the OTG_NUM_EPS parameter.
- - - - -
Number of Host Channels (NumHstChnl)
-
Indicates the number of host channels supported by the core in Host mode. The range of this field is 0-15: 0 specifies 1 channel, 15 specifies 16 channels.
-
-
Note: This field is configured using the OTG_NUM_HOST_CHAN parameter.
- - - - -
Periodic OUT Channels Supported in Host Mode (PerioSupport)
-
- 1'b0: No
-
- 1'b1: Yes
-
Note: This field is configured using the OTG_EN_PERIO_HOST parameter.
- - - - -
Dynamic FIFO Sizing Enabled (DynFifoSizing)
-
- 1'b0: No
-
- 1'b1: Yes
-
Note: This field is configured using the OTG_DFIFO_DYNAMIC parameter.
- - - - -
Multi Processor Interrupt Enabled (MultiProcIntrpt)
-
- 1'b0: No
-
- 1'b1: Yes
-
Note: This field is configured using the OTG_MULTI_PROC_INTRPT parameter.
- - - - -
Non-periodic Request Queue Depth (NPTxQDepth)
-
- 2'b00: 2
-
- 2'b01: 4
-
- 2'b10: 8
-
- Others: Reserved
-
Note: This field is configured using the OTG_NPERIO_TX_QUEUE_DEPTH parameter.
- - - - -
Host Mode Periodic Request Queue Depth (PTxQDepth)
-
- 2'b00: 2
-
- 2'b01: 4
-
- 2'b10: 8
-
- 2'b11:16
-
Note: This field is configured using the OTG_PERIO_TX_QUEUE_DEPTH parameter.
- - - - -
Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)
-
Range: 0-30
-
-
Note: This field is configured using the OTG_TOKEN_QUEUE_DEPTH parameter.
- - - - - User Hardware Configuration 3 Register - - -
Width of Transfer Size Counters (XferSizeWidth)
-
- 4'b0000: 11 bits
-
- 4'b0001: 12 bits
-
...
-
- 4'b1000: 19 bits
-
- Others: Reserved
-
Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.
- - - - -
Width of Packet Size Counters (PktSizeWidth)
-
- 3'b000: 4 bits
-
- 3'b001: 5 bits
-
- 3'b010: 6 bits
-
- 3'b011: 7 bits
-
- 3'b100: 8 bits
-
- 3'b101: 9 bits
-
- 3'b110: 10 bits
-
- Others: Reserved
-
Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.
- - - - -
OTG Function Enabled (OtgEn)
-
-
The application uses this bit to indicate the OTG capabilities of the controller .
-
- 1'b0: Not OTG capable
-
- 1'b1: OTG Capable
-
Note: This field is configured using the OTG_MODE parameter.
- - - - -
I2C Selection (I2CIntSel)
-
- 1'b0: I2C Interface is not available on the controller.
-
- 1'b1: I2C Interface is available on the controller.
-
Note: This field is configured using the OTG_I2C_INTERFACE parameter.
- - - - -
Vendor Control Interface Support (VndctlSupt)
-
-
- 1'b0: Vendor Control Interface is not available on the core.
-
- 1'b1: Vendor Control Interface is available.
-
Note: This field is configured using the OTG_VENDOR_CTL_INTERFACE parameter.
- - - - -
Optional Features Removed (OptFeature)
-
Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed for gate count optimization by enabling Remove Optional Features.
-
- 1'b0: No
-
- 1'b1: Yes
-
Note: This field is configured using the OTG_RM_OPT_FEATURES parameter.
- - - - -
Reset Style for Clocked always Blocks in RTL (RstType)
-
- 1'b0: Asynchronous reset is used in the controller
-
- 1'b1: Synchronous reset is used in the controller
-
Note: This field is configured using the OTG_SYNC_RESET_TYPE parameter.
- - - - -
This bit indicates whether ADP logic is present within or external to the controller
-
- 0: No ADP logic present with the controller
-
- 1: ADP logic is present along with the controller.
- - - - -
HSIC mode specified for Mode of Operation
-
Value Range: 0 - 1
-
- 1: HSIC-capable with shared UTMI PHY interface
-
- 0: Non-HSIC-capable
- - - - -
This bit indicates the controller support for Battery Charger.
-
- 0 - No Battery Charger Support
-
- 1 - Battery Charger support present
-
- - - - -
LPM mode specified for Mode of Operation.
- - - - -
DFIFO Depth (DfifoDepth - EP_LOC_CNT)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 32
-
- Maximum value is 32,768
-
Note: This field is configured using the OTG_DFIFO_DEPTH parameter. For more information on EP_LOC_CNT, see the "Endpoint Information Controller (EPINFO_CTL)" section.
- - - - - User Hardware Configuration 4 Register -Note Bit [31] is available only when Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this field is reserved. - - -
Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)
-
-
Range: 0-15
- - - - -
Enable Partial Power Down (PartialPwrDn)
-
- 1'b0: Partial Power Down Not Enabled
-
- 1'b1: Partial Power Down Enabled
- - - - -
Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
-
- 1'b0: No
-
- 1'b1: Yes
- - - - -
Enable Hibernation (Hibernation)
-
- 1'b0: Hibernation feature not enabled
-
- 1'b1: Hibernation feature enabled
- - - - -
Enable Hibernation
-
- 1'b0: Extended Hibernation feature not enabled
-
- 1'b1: Extended Hibernation feature enabled
- - - - -
Active Clock Gating Support
-
-
This bit indicates that the controller supports the Dynamic (Switching) Power Reduction during periods
-
when there is no USB and AHB Traffic.
-
- 1'b0: Active Clock Gating is not enabled.
-
- 1'b1: Active Clock Gating Enabled.
-
- - - - -
Enhanced LPM Support (EnhancedLPMSupt)
-
-
This bit indicates that the controller supports the following behavior:
-
L1 Entry Behavior based on FIFO Status
-
- TX FIFO
-
- Accept L1 Request even if ISOC OUT TX FIFO is not empty.
-
- Reject L1 Request if Non-Periodic TX FIFO is not empty.
-
- Ensure application can flush the TX FIFO while the Controller is in L1.
-
- RX FIFO
-
- Accept L1 Request even if RX FIFO (common to Periodic and Non-Periodic) is not empty.
-
- Accept L1 Request but delay SLEEPM assertion until RX SINK Buffer is empty.
-
-
Prevent L1 Entry if a Control Transfer is in progress on any Control Endpoint.
-
Ability to Flush TxFIFO even if PHY Clock is gated.
-

-
- - - - -
UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
-
(PhyDataWidth)<vr>When a ULPI PHY is used, an internal wrapper converts ULPI to
-
UTMI+.
-
- 2'b00: 8 bits
-
- 2'b01: 16 bits
-
- 2'b10: 8/16 bits, software selectable
-
- Others: Reserved
- - - - -
Number of Device Mode Control Endpoints in Addition to
-
Endpoint 0 (NumCtlEps)
-
Range: 0-15
- - - - -
IDDIG Filter Enable (IddgFltr)
-
- 1'b0: No filter
-
- 1'b1: Filter
- - - - -
VBUS Valid Filter Enabled (VBusValidFltr)
-
- 1'b0: No filter
-
- 1'b1: Filter
- - - - -
a_valid Filter Enabled (AValidFltr)
-
- 1'b0: No filter
-
- 1'b1: Filter
- - - - -
b_valid Filter Enabled (BValidFltr)
-
- 1'b0: No filter
-
- 1'b1: Filter
- - - - -
session_end Filter Enabled (SessEndFltr)
-
- 1'b0: No filter
-
- 1'b1: Filter
- - - - -
Enable Dedicated Transmit FIFO for device IN Endpoints
-
(DedFifoMode)
-
- 1'b0 : Dedicated Transmit FIFO Operation not enabled.
-
- 1'b1 : Dedicated Transmit FIFO Operation enabled.
- - - - -
Number of Device Mode IN Endpoints Including Control Endpoints (INEps)
-
- 0: 1 IN Endpoint
-
- 1: 2 IN Endpoints
-
....
-
- 15: 16 IN Endpoints
-
- - - - -
Scatter/Gather DMA configuration
-
- 1'b0: Non-Scatter/Gather DMA configuration
-
- 1'b1: Scatter/Gather DMA configuration
- - - - -
Scatter/Gather DMA configuration
-
- 1'b0: Non Dynamic configuration
-
- 1'b1: Dynamic configuration
-
Note: This field is configured using the OTG_EN_DESC_DMA parameter.
- - - - - - Global Power Down register -This is the external Hibernation control register. This register is active only during hibernation and ADP. The application can get the status of the wakeup_logic and control it through this register. - - -
PMU Interrupt Select (PMUIntSel)
-
-
A write to this bit with 1'b1 enables the PMU to generate interrupts to the application. During this state all interrupts from the DWC_otg_core module are blocked to the application.
-
-
Note: This bit must be set to 1'b1 before the core is put into hibernation.
-
- 1'b0: Internal DWC_otg_core interrupt is selected
-
- 1'b1: External DWC_otg_pmu interrupt is selected
-
Note: This bit must not be written to during normal mode of operation.
- - - - -
PMU Active (PMUActv)
-
-
This is bit is to enable or disable the PMU logic.
-
- 1'b0: Disable PMU module
-
- 1'b1: Enable PMU module
-
Note: This bit must not be written to during normal mode of operation.
-
- - - - -
Power Down Clamp (PwrDnClmp)
-
-
The application must program this bit to enable or disable the clamps to all the outputs of the core module to prevent the corruption of other active logic.
-
- 1'b0: Disable PMU power clamp
-
- 1'b1: Enable PMU power clamp
- - - - -
Power Down ResetN (PwrDnRst_n)
-
-
The application must program this bit to reset the core during the Hibernation exit process or during ADP when powering up the core (in case the core was powered off during ADP process).
-
- 1'b1: The controller is in normal operation
-
- 1'b0: reset the controller
-
Note: This bit must not be written to during normal mode of operation.
- - - - -
Power Down Switch (PwrDnSwtch)
-
-
This bit indicates to the controller whether the VDD switch is in ON/OFF state.
-
- 1'b0: The controller is in ON state
-
- 1'b1: The controller is in OFF state
-
Note: This bit must not be written to during normal mode of operation.
- - - - -
DisableVBUS
-
-
Host Mode:
-
-
The application should program this bit if HPRT0.PrtPwr was programmed to 0 before entering Hibernation. This is to indicate PMU whether session was ended before entering Hibernation.
-
- 1'b0: HPRT0.PrtPwr was not programed to 0.
-
- 1'b1: HPRT0.PrtPwr was programmed to 0.
-
Device Mode:
-
-
The application must program this bit to inform the PMU whether the bvalid valid signal is high (session valid) or low (session end) whenever the core is switched off.
-
- 1'b0: bvalid signal is High (Session Valid)
-
- 1'b1: bvalid signal is Low (Session End)
-
This bit is valid only when GPWRDN.PMUActv is 1.
-
- - - - -
SRPDetect
-
-
This field indicates that SRP has been detected by the PMU. This field generates an interrupt. After detecting SRP during hibernation the application should not restore the core. The application should get into the initialization process.
-
- 1'b0: SRP not detected
-
- 1'b1: SRP detected
- - - - -
SRPDetectMsk
-
-
Mask for SRPDetect Interrupt
- - - - -
Status Change Interrupt (StsChngInt)
-
-
This field indicates a status change in either the IDDIG or BSessVld signal.
-
- 1'b0: No Status change
-
- 1'b1: Status change detected
-
After receiving this interrupt the application should read the GPWRDN register and interpret the change in IDDIG or BSesVld with respect to the previous value stored by the application.
-
-
Note: When Battery Charger is enabled and the ULPI interface is used, if StsChngInt is received and the application reads GPWRDN register and determines that it is because of a change in the value of IDDIG, then StsChngInt may be generated once again within the next few clock cycles.
-
-
This occurs because of an ambiguity in the implementation of Battery Charger Support over the ULPI interface. After receiving the StsChngInt for the second time the application can once again read the GPWRDN register. However, this time the valueIDDIG (or BSesVld) will not have changed. The application then processes the second interrupt but no further action will be required as a result.
- - - - -
StsChngIntMsk
-
-
Mask for StsChng Interrupt
- - - - -
LineState
-
-
This field indicates the current linestate on USB as seen by the PMU module.
-
- 2'b00: DM = 0, DP = 0.
-
- 2'b01: DM = 0, DP = 1.
-
- 2'b10: DM = 1, DP = 0.
-
- 2'b11: Not-defined.
-
This bit is valid only when GPWRDN.PMUActv is 1.
- - - - -
This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application.
-
-
Indicates the current mode.
-
- 1'b0: Host mode
-
- 1'b1: Device mode
-
This bit is valid only when GPWRDN.PMUActv is 1.
- - - - -
B Session Valid (BSessVld)
-
-
This field reflects the B session valid status signal from the PHY.
-
- 1'b0: B-Valid is 0.
-
- 1'b1: B-Valid is 1.
-
This bit is valid only when GPWRDN.PMUActv is 1.
- - - - -
ADP Interrupt (ADPInt)
-
-
This bit is set whenever there is a ADP event.
- - - - - Global DFIFO Configuration Register - - -
GDFIFOCfg
-
-
This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.
- - - - -
EPInfoBaseAddr
-
-
This field provides the start address of the EP info controller.
-
- - - - - ADP Timer, Control and Status Register -This register is maintained in the PMU module. These register values are used for deciding the timing values by the ADP controller. This register is available only if the ADP controller logic is present within the HS OTG Controller. If the ADP logic is external to the HS OTG Controller, this register is reserved and the register contents are zero. For more information about ADP controller options, see "ADP Programming Flow when ADP Controller Logic is Supplied with the Core " in the Programming Guide. - - -
Probe Discharge (PrbDschg)
-
-
These bits set the times for TADP_DSCHG. These bits are defined as follows:
-
- 2'b00: 4 msec (Scaledown 2 32Khz clock cycles)
-
- 2'b01: 8 msec (Scaledown 4 32Khz clock cycles)
-
- 2'b10: 16 msec (Scaledown 8 32Khz clock cycles)
-
- 2'b11: 32 msec (Scaledown 16 32Khz clock cycles)
- - - - -
Probe Delta (PrbDelta)
-
-
These bits set the resolution for RTIM value. The bits are defined in units of 32 kHz clock cycles as follows:
-
- 2'b00: 1 cycles
-
- 2'b01: 2 cycles
-
- 2'b10: 3 cycles
-
- 2'b11: 4 cycles
-
For example, if this value is chosen to 2'b01, it means that RTIM increments for every three 32Khz clock cycles.
- - - - -
Probe Period (PrbPer)
-
-
These bits sets the TadpPrd as follows:
-
- 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
-
- 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
-
- 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
-
- 2'b11 - Reserved
-
(PrbPer is also scaledown
-
- prb_per== 2'b00 => 400 ADP clocks
-
- prb_per== 2'b01 => 600 ADP clocks
-
- prb_per== 2'b10 => 800 ADP clocks
-
- prb_per==2'b11 => 1000 ADP clocks)
- - - - -
RAMP TIME (RTIM)
-
-
These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows:
-
- 0x000 - 1 cycles
-
- 0x001 - 2 cycles
-
- 0x002 - 3 cycles, and so on till
-
- 0x7FF - 2048 cycles
-
A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
-
(Note for scaledown ramp_timeout =
-
- prb_delta == 2'b00 => 200 cycles.
-
- prb_delta == 2'b01 => 100 cycles.
-
- prb_delta == 2'b01 => 50 cycles.
-
- prb_delta == 2'b01 => 25 cycles.)
- - - - -
Enable Probe (EnaPrb)
-
-
When programmed to 1'b1, the core performs a probe operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).
- - - - -
Enable Sense (EnaSns)
-
-
When programmed to 1'b1, the core performs a sense operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).
-
- - - - -
ADP Reset (ADPRes)
-
-
When set, ADP controller is reset. This bit is auto-cleared after the reset procedure is complete in ADP controller. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).
- - - - -
ADP Enable (ADPEn)
-
-
When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns.
-
This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).
- - - - -
ADP Probe Interrupt (AdpPrbInt)
-
-
When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VadpPrb is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).
-
- - - - -
ADP Sense Interrupt (AdpSnsInt)
-
-
When this bit is set, it means that the VBUS voltage is greater than VadpSns value or VadpSns is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).
-
- - - - -
ADP Timeout Interrupt (AdpToutInt)
-
-
This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.
- - - - -
ADP Probe Interrupt (AdpPrbInt)
-
-
This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.
-
- - - - -
ADP Sense Interrupt Mask (AdpSnsIntMsk)
-
-
When this bit is set, it unmasks the interrupt due to AdpSnsInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).
-
- - - - -
ADP Timeout Interrupt Mask (AdpToutMsk)
-
-
When this bit is set, it unmasks the interrupt because of AdpTmouInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).
- - - - -
Access Request (AR)
-
- 2'b00 Read/Write Valid (updated by the core)
-
- 2'b01 Read
-
- 2'b10 Write
-
- 2'b11 - Reserved
- - - - - - Host Periodic Transmit FIFO Size Register -This register holds the size and the memory start address of the Periodic TxFIFO. -Note: Read the reset value of this register only after the following conditions: - - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - - If IDDIG_FILTER is enabled, read only after the filter timer expires. - - -
Host Periodic TxFIFO Start Address (PTxFStAddr)
-
-
The power-on reset value of this register is the sum of the Largest Rx Data FIFO Depth and Largest Non-periodic Tx Data FIFO Depth.These parameters are:
-
-
In shared FIFO operation:
-
- OTG_RX_DFIFO_DEPTH + OTG_TX_NPERIO_DFIFO_DEPTH
-
-
In dedicated FIFO mode:
-
- OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value. If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field.
-
-
Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
Host Periodic TxFIFO Depth (PTxFSize)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest Host Mode Periodic Tx Data FIFO Depth.
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field.
-
Programmed values must not exceed the power-on value set in coreConsultant.
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - Device IN Endpoint Transmit FIFO Size Register $i -This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address. - - -
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)
-
-
This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).
-
The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.
-
- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.
-
- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.
- - - - -
IN Endpoint TxFIFO Depth (INEPnTxFDep)
-
-
This value is in terms of 32-bit words.
-
- Minimum value is 16
-
- Maximum value is 32,768
-
The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).
-
- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.
-
- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .
-
Programmed values must not exceed the power-on value
- - - - - - Host Configuration Register - - -
FS/LS PHY Clock Select (FSLSPclkSel)
-
-
When the core is in FS Host mode
-
- 2'b00: PHY clock is running at 30/60 MHz
-
- 2'b01: PHY clock is running at 48 MHz
-
- Others: Reserved
-
When the core is in LS Host mode
-
- 2'b00: PHY clock is running at 30/60 MHz. When the UTMI+/ULPI PHY Low Power mode is not selected, use 30/60 MHz.
-
- 2'b01: PHY clock is running at 48 MHz. When the UTMI+ PHY Low Power mode is selected, use 48MHz If the PHY supplies a 48 MHz clock during LS mode.
-
- 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, use 6 MHz when the UTMI+ PHY Low Power mode is selected and the PHY supplies a 6 MHz clock during LS mode. If you select a 6 MHz clock during LS mode, you must do a soft reset.
-
- 2'b11: Reserved
-
Notes:
-
- When Core in FS mode, the internal and external clocks have the same frequency.
-
- When Core in LS mode,
-
-- If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency
-
-- If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of external 48 MHz clock
-
- - - - -
FS- and LS-Only Support (FSLSSupp)
-
-
The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core
-
enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial
-
programming.
-
- 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device
-
- 1'b1: FS/LS-only, even If the connected device can support HS
- - - - -
Enable 32 KHz Suspend mode (Ena32KHzS)
-
-
This bit can be set only in FS PHY interface is selected.
-
Else, this bit needs to be set to zero.
-
When FS PHY interface is chosen and this bit is set,
-
the core expects that the PHY clock during Suspend is switched
-
from 48 MHz to 32 KHz.
- - - - -
Resume Validation Period (ResValid)
-
-
This field is effective only when HCFG.Ena32KHzS is set.
-
It will control the resume period when the core resumes from suspend.
-
The core counts for 'ResValid' number of clock cycles to detect a
-
valid resume when this is set.
- - - - -
Enable Scatter/gather DMA in Host mode (DescDMA)
-
-
When the Scatter/Gather DMA option selected during configuration of the RTL, the application can set this bit during initialization
-
to enable the Scatter/Gather DMA operation.
-
-
Note: This bit must be modified only once after a reset.
-
-
The following combinations are available for programming:
-
- GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode
-
- GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid
-
- GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode
-
- GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode
- - - - -
Frame List Entries(FrListEn)
-
-
The value in the register specifies the number of entries in the Frame list.
-
This field is valid only in Scatter/Gather DMA mode.
-
- 2'b00: 8 Entries
-
- 2'b01: 16 Entries
-
- 2'b10: 32 Entries
-
- 2'b11: 64 Entries
- - - - -
Enable Periodic Scheduling (PerSchedEna):
-
-
Applicable in host DDMA mode only.
-
Enables periodic scheduling within the core. Initially, the bit is reset.
-
The core will not process any periodic channels.
-
-
As soon as this bit is set,
-
the core will get ready to start scheduling periodic channels and
-
sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core
-
has enabled periodic scheduling. Once HCFG.PerSchedEna is set,
-
the application is not supposed to again reset the bit unless HCFG.PerSchedStat
-
is set.
-
-
As soon as this bit is reset, the core will get ready to
-
stop scheduling periodic channels and resets HCFG.PerSchedStat.
- - - - -
Mode Change Ready Timer Enable (ModeChTimEn)
-
-
This bit is used to enable/disable the Host core to wait 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00
-
after Suspend or LPM.
-
- 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00
-
- 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to change the opmode from 2'b10 to 2'b00.
- - - - - Host Frame Interval Register - - -
Frame Interval (FrInt)
-
-
The value that the application programs to this field specifies
-
the interval between two consecutive SOFs (FS) or micro-
-
SOFs (HS) or Keep-Alive tokens (HS). This field contains the
-
number of PHY clocks that constitute the required frame
-
interval. The Default value set in this field is for FS operation
-
when the PHY clock frequency is 60 MHz. The application can
-
write a value to this register only after the Port Enable bit of the
-
Host Port Control and Status register (HPRT.PrtEnaPort) has
-
been Set. If no value is programmed, the core calculates the
-
value based on the PHY clock specified in the FS/LS PHY
-
Clock Select field of the Host Configuration register
-
(HCFG.FSLSPclkSel). Do not change the value of this field
-
after the initial configuration.
-
- 125 s * (PHY clock frequency for HS)
-
- 1 ms * (PHY clock frequency for FS/LS)
- - - - -
Reload Control (HFIRRldCtrl)
-
-
This bit allows dynamic reloading of the HFIR register during run time.
-
- 1'b0 : The HFIR cannot be reloaded dynamically
-
- 1'b1: the HFIR can be dynamically reloaded during runtime.
-
This bit needs to be programmed during initial configuration and its value should not be changed during runtime.
-
- - - - - Host Frame Number/Frame Time Remaining Register -This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current (micro)frame. -Note: Read the reset value of this register only after the following conditions: - - If IDDIG_FILTER is disabled, read only when the PHY clock is stable. - - If IDDIG_FILTER is enabled, read only after the filter timer expires. - - -
Frame Number (FrNum)
-
-
This field increments when a new SOF is transmitted on the
-
USB, and is reset to 0 when it reaches 16'h3FFF.
-
- - - - -
Frame Time Remaining (FrRem)
-
-
Indicates the amount of time remaining in the current
-
microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This
-
field decrements on each PHY clock. When it reaches zero, this
-
field is reloaded with the value in the Frame Interval register and
-
a new SOF is transmitted on the USB.
- - - - - - Host Periodic Transmit FIFO/Queue Status Register - - -
Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
-
-
Indicates the number of free locations available to be written to in the Periodic TxFIFO.
-
-
Values are in terms of 32-bit words
-
- 16'h0 : Periodic TxFIFO is full
-
- 16'h1 : 1 word available
-
- 16'h2 : 2 words available
-
- 16'hn : n words available (where 0 n 32,768)
-
- 16'h8000 : 32,768 words
-
- Others : Reserved
- - - - -
Periodic Transmit Request Queue Space Available (PTxQSpcAvail)
-
-
Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds both IN and OUT requests.
-
- 8'h0: Periodic Transmit Request Queue is full
-
- 8'h1: 1 location available
-
- 8'h2: 2 locations available
-
- n: n locations available (0 <= n <= 16)
-
- Others: Reserved
- - - - -
Top of the Periodic Transmit Request Queue (PTxQTop)
-
-
This indicates the Entry in the Periodic Tx Request Queue that is
-
currently being processes by the MAC.
-
-
This register is used for debugging.
-
- Bit [31]: Odd/Even (micro)Frame
-
-- 1'b0: send in even (micro)Frame
-
-- 1'b1: send in odd (micro)Frame
-
- Bits [30:27]: Channel/endpoint number
-
- Bits [26:25]: Type
-
-- 2'b00: IN/OUT
-
-- 2'b01: Zero-length packet
-
-- 2'b10: CSPLIT
-
-- 2'b11: Disable channel command
-
- Bit [24]: Terminate (last Entry for the selected channel/endpoint)
- - - - - Host All Channels Interrupt Register -When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is shown in the "Interrupt Hierarchy" figure in the databook. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host Channel-n Interrupt register. - - -
-
Channel Interrupt for channel no.
- - - - - Host All Channels Interrupt Mask Register -The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. - - -
Channel Interrupt Mask (HAINTMsk)
-
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
- - - - - Host Frame List Base Address Register -This register is present only in case of Scatter/Gather DMA. It is implemented as flops. This register holds the starting address of the Frame list information. - - -
The starting address of the Frame list.
-
This register is used only for Isochronous and Interrupt Channels.
- - - - - - Host Port Control and Status Register -This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in the "Interrupt Hierarchy" figure in the databook. The R_SS_WC bits in this register can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit to clear the interrupt. - - -
Port Connect Status (PrtConnSts)
-
- 0: No device is attached to the port.
-
- 1: A device is attached to the port.
- - - - -
Port Connect Detected (PrtConnDet)
-
-
The core sets this bit when a device connection is detected
-
to trigger an interrupt to the application using the Host Port
-
Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set only by the core and the application should write 1 to clear it.The application must write a 1 to this bit to clear the
-
interrupt.
- - - - -
Port Enable (PrtEna)
-
-
A port is enabled only by the core after a reset sequence,
-
and is disabled by an overcurrent condition, a disconnect
-
condition, or by the application clearing this bit. The
-
application cannot Set this bit by a register write. It can only
-
clear it to disable the port by writing 1. This bit does not trigger any
-
interrupt to the application.
-
- 1'b0: Port disabled
-
- 1'b1: Port enabled
- - - - -
Port Enable/Disable Change (PrtEnChng)
-
-
The core sets this bit when the status of the Port Enable bit [2] of this register changes.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Port Overcurrent Active (PrtOvrCurrAct)
-
-
Indicates the overcurrent condition of the port.
-
- 1'b0: No overcurrent condition
-
- 1'b1: Overcurrent condition
- - - - -
Port Overcurrent Change (PrtOvrCurrChng)
-
-
The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes.This bit can be set only by the core and the application should write 1 to clear it
- - - - -
Port Resume (PrtRes)
-
-
The application sets this bit to drive resume signaling on the
-
port. The core continues to drive the resume signal until the
-
application clears this bit.
-
-
If the core detects a USB remote wakeup sequence, as
-
indicated by the Port Resume/Remote Wakeup Detected
-
Interrupt bit of the Core Interrupt register
-
(GINTSTS.WkUpInt), the core starts driving resume
-
signaling without application intervention and clears this bit
-
when it detects a disconnect condition. The read value of
-
this bit indicates whether the core is currently driving
-
resume signaling.
-
- 1'b0: No resume driven
-
- 1'b1: Resume driven
-
When LPM is enabled, In L1 state the behavior of this bit is as follows:
-
The application sets this bit to drive resume signaling on the port.
-
The core continues to drive the resume signal until a pre-determined time
-
specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote
-
wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected
-
Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt),
-
the core starts driving resume signaling without application intervention
-
and clears this bit at the end of resume.This bit can be set by both core or application
-
and also cleared by core or application. This bit is cleared by the core even if there is
-
no device connected to the Host.
- - - - -
Port Suspend (PrtSusp)
-
-
The application sets this bit to put this port in Suspend
-
mode. The core only stops sending SOFs when this is Set.
-
To stop the PHY clock, the application must Set the Port
-
Clock Stop bit, which asserts the suspend input pin of the
-
PHY.
-
-
The read value of this bit reflects the current suspend status
-
of the port. This bit is cleared by the core after a remote
-
wakeup signal is detected or the application sets the Port
-
Reset bit or Port Resume bit in this register or the
-
Resume/Remote Wakeup Detected Interrupt bit or
-
Disconnect Detected Interrupt bit in the Core Interrupt
-
register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
-
respectively).This bit is cleared by the core even if there is
-
no device connected to the Host.
-
- 1'b0: Port not in Suspend mode
-
- 1'b1: Port in Suspend mode
- - - - -
Port Reset (PrtRst)
-
-
When the application sets this bit, a reset sequence is
-
started on this port. The application must time the reset
-
period and clear this bit after the reset sequence is
-
complete.
-
- 1'b0: Port not in reset
-
- 1'b1: Port in reset
-
The application must leave this bit set for at least a
-
minimum duration mentioned below to start a reset on the
-
port. The application can leave it set for another 10 ms in
-
addition to the required minimum duration, before clearing
-
the bit, even though there is no maximum limit Set by the
-
USB standard.This bit is cleared by the core even if there is
-
no device connected to the Host.
-
- High speed: 50 ms
-
- Full speed/Low speed: 10 ms
- - - - -
Port Line Status (PrtLnSts)
-
-
Indicates the current logic level USB data lines
-
- Bit [10]: Logic level of D+
-
- Bit [11]: Logic level of D-
- - - - -
Port Power (PrtPwr)
-
-
The application uses this field to control power to this port (write 1'b1 to set to 1'b1
-
and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current
-
condition.
-
- 1'b0: Power off
-
- 1'b1: Power on
-
-
Note: This bit is interface independent. The application needs to program this bit for all interfaces as described in the host programming flow in the Programming Guide.
- - - - -
Port Test Control (PrtTstCtl)
-
-
The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.
-
- 4'b0000: Test mode disabled
-
- 4'b0001: Test_J mode
-
- 4'b0010: Test_K mode
-
- 4'b0011: Test_SE0_NAK mode
-
- 4'b0100: Test_Packet mode
-
- 4'b0101: Test_Force_Enable
-
- Others: Reserved
-
-
To move the DWC_otg controller to test mode, you must set this field. Complete the following steps to move the DWC_otg core to test mode:
-
- 1. Power on the core.
-
- 2. Load the DWC_otg driver.
-
- 3. Connect an HS device and enumerate to HS mode.
-
- 4. Access the HPRT register to send test packets.
-
- 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core continues sending out test packets.
-
- 6. Test the eye diagram.
- - - - -
Port Speed (PrtSpd)
-
-
Indicates the speed of the device attached to this port.
-
- 2'b00: High speed
-
- 2'b01: Full speed
-
- 2'b10: Low speed
-
- 2'b11: Reserved
- - - - - - Host Channel 0 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 0 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 0 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 1 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 1 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 1 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 2 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 2 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 2 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 3 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 3 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 3 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 4 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 4 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 4 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 5 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 5 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 5 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 6 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 6 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 6 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 7 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 7 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 7 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 8 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 8 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 8 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 9 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 9 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 9 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 10 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 10 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 10 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 11 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 11 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 11 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 12 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 12 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 12 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 13 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 13 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 13 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 14 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 14 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 14 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - Host Channel 15 Characteristics Register - - -
Maximum Packet Size (MPS)
-
-
Indicates the maximum packet size of the associated endpoint.
- - - - -
Endpoint Number (EPNum)
-
-
Indicates the endpoint number on the device serving as the data source or sink.
- - - - -
Endpoint Direction (EPDir)
-
-
Indicates whether the transaction is IN or OUT.
-
- 1'b0: OUT
-
- 1'b1: IN
- - - - -
Low-Speed Device (LSpdDev)
-
-
This field is Set by the application to indicate that this channel is communicating to a low-speed device.
-
-
The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.
-
-
Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.
- - - - -
Endpoint Type (EPType)
-
-
Indicates the transfer type selected.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
Multi Count (MC) / Error Count (EC)
-
-
When the Split Enable bit of the Host Channel-n Split Control
-
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
-
the host the number of transactions that must be executed per
-
microframe for this periodic endpoint. For non periodic transfers,
-
this field is used only in DMA mode, and specifies the number
-
packets to be fetched for this channel before the internal DMA
-
engine changes arbitration.
-
- 2'b00: Reserved This field yields undefined results.
-
- 2'b01: 1 transaction
-
- 2'b10: 2 transactions to be issued for this endpoint per microframe
-
- 2'b11: 3 transactions to be issued for this endpoint per microframe
-
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
-
number of immediate retries to be performed for a periodic split
-
transactions on transaction errors. This field must be Set to at
-
least 2'b01.
- - - - -
Device Address (DevAddr)
-
-
This field selects the specific device serving as the data source
-
or sink.
- - - - -
Odd Frame (OddFrm)
-
-
This field is set (reset) by the application to indicate that the OTG host must perform
-
a transfer in an odd (micro)Frame. This field is applicable for only periodic
-
(isochronous and interrupt) transactions.
-
- 1'b0: Even (micro)Frame
-
- 1'b1: Odd (micro)Frame
-
- - - - -
Channel Disable (ChDis)
-
-
The application sets this bit to stop transmitting/receiving data
-
on a channel, even before the transfer for that channel is
-
complete. The application must wait for the Channel Disabled
-
interrupt before treating the channel as disabled.
- - - - -
Channel Enable (ChEna)
-
-
When Scatter/Gather mode is enabled
-
- 1'b0: Indicates that the descriptor structure is not yet ready.
-
- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.
-
When Scatter/Gather mode is disabled
-
-
This field is set by the application and cleared by the OTG host.
-
- 1'b0: Channel disabled
-
- 1'b1: Channel enabled
- - - - - Host Channel 15 Split Control Register - - -
Port Address (PrtAddr)
-
-
This field is the port number of the recipient transaction translator.
- - - - -
Hub Address (HubAddr)
-
-
This field holds the device address of the transaction translator's hub.
- - - - -
Transaction Position (XactPos)
-
-
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.
-
- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).
-
- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).
-
- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).
-
- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).
- - - - -
Do Complete Split (CompSplt)
-
-
The application sets this field to request the OTG host to perform a complete split transaction.
- - - - -
Split Enable (SpltEna)
-
-
The application sets this field to indicate that this channel is enabled to perform split transactions.
- - - - - "Host Channel $i Interrupt Register" -This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. - - -
Transfer Completed (XferCompl)
-
-
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
-
- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.
-
- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.
-
- - - - -
Channel Halted (ChHltd)
-
-
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
-
-
In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
-
- EOL being set in descriptor
-
- AHB error
-
- Excessive transaction errors
-
- Babble
-
- Stall
-
- - - - -
AHB Error (AHBErr)
-
-
This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.
- - - - -
STALL Response Received Interrupt (STALL)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NAK Response Received Interrupt (NAK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
ACK Response Received/Transmitted Interrupt (ACK)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
NYET Response Received Interrupt (NYET)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Transaction Error (XactErr)
-
-
Indicates one of the following errors occurred on the USB.
-
- CRC check failure
-
- Timeout
-
- Bit stuff error
-
- False EOP
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Babble Error (BblErr)
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.
- - - - -
Frame Overrun (FrmOvrun).
-
-
In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core. This bit can be set only by the core and the application should write 1 to clear
-
it.
- - - - -
-
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
-
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
-
in the core.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process. BNA will not be generated
-
for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Excessive Transaction Error (XCS_XACT_ERR)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
-
not be generated for Isochronous channels.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - -
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit
-
when the corresponding channel's descriptor list rolls over.
-
For non Scatter/Gather DMA mode, this bit is reserved.
- - - - - "Host Channel $i Interrupt Mask Register" -This register reflects the mask for each channel status described in the previous section. - - -
-
Transfer Completed Mask (XferComplMsk)
- - - - -
-
Channel Halted Mask (ChHltdMsk)
- - - - -
-
AHB Error Mask (AHBErrMsk)
-
In scatter/gather DMA mode for host,
-
interrupts will not be generated due to the corresponding bits set in
-
HCINTn.
- - - - -
-
BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - -
-
Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
- - - - - Host Channel 15 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
For an OUT, this field is the number of data bytes the host sends during the transfer.
-
-
For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).
-
-
The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).
- - - - -
Packet Count (PktCnt)
-
-
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
-
-
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.
-
-
The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).
- - - - -
PID (Pid)
-
-
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA (non-control)/SETUP (control)
- - - - -
Do Ping (DoPng)
-
-
This bit is used only for OUT transfers.
-
Setting this field to 1 directs the host to do PING protocol.
-
-
Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
- - - - - "Host Channel $i DMA Address Register" -This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned. - - -
In Buffer DMA Mode:
-
-
[31:0]: DMA Address (DMAAddr)
-
-
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.
-
-
Reset: X if not programmed as the register is in SPRAM.
-
-
In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:
-
-
[31:9]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.
-
-
[8:3]: Current Transfer Desc(CTD)
-
-
This value is in terms of number of descriptors. The values can be from 0 to 63.
-
- 0 - 1 descriptor.
-
- 63 - 64 descriptors.
-
This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.
-
-
Reset: 6'h0
-
-
[2:0]: Reserved
-
-
In Scatter-Gather DMA (DescDMA) Mode for Isochronous:
-
-
[31:N]: DMA Address (DMAAddr)
-
-
The start address must be 512-bytes aligned.
-
-
This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:
-
- [31:N]: Base Address
-
- [N-1:3]: Offset
-
- [2:0]: 000
-
For HS ISOC, if nTD is,
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
- 127, N=10
-
- 255, N=11
-
For FS ISOC, if nTD is,
-
- 1, N=4
-
- 3, N=5
-
- 7, N=6
-
- 15, N=7
-
- 31, N=8
-
- 63, N=9
-
[N-1:3]: Current Transfer Desc(CTD)
-
-
CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.
-
-
Reset: (N+1:3)'h0
-
-
[2:0]: Reserved
- - - - - - "Host Channel $i DMA Buffer Address Register" -This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address. - - -
Holds the current buffer address.
-
This register is updated as and when the data transfer for the corresponding end point
-
is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this
-
field is reserved.
- - - - - - Device Configuration Register -This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. - - -
Device Speed (DevSpd)
-
-
Indicates the speed at which the application requires the core to
-
enumerate, or the maximum speed the application can support.
-
However, the actual bus speed is determined only after the connect
-
sequence is completed, and is based on the speed of the USB
-
host to which the core is connected.
- - - - -
Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
-
-
The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage.
-
- 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.
-
- 1'b0: Send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.
- - - - -
Enable 32 KHz Suspend mode (Ena32KHzSusp)
-
-
This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend must be switched from 48 MHz to 32 KHz.
-
- - - - -
Device Address (DevAddr)
-
-
The application must program this field after every SetAddress control command.
- - - - -
Periodic Frame Interval (PerFrInt)
-
-
Indicates the time within a (micro)Frame at which the application
-
must be notified using the End Of Periodic Frame Interrupt. This
-
can be used to determine If all the isochronous traffic for that
-
(micro)Frame is complete.
-
- 2'b00: 80% of the (micro)Frame interval
-
- 2'b01: 85% of the (micro)Frame interval
-
- 2'b10: 90% of the (micro)Frame interval
-
- 2'b11: 95% of the (micro)Frame interval
- - - - -
Enable Device OUT NAK (EnDevOutNak)
-
-
This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed for Device mode Descriptor DMA
-
- 1'b0 : The core does not set NAK after Bulk OUT transfer complete
-
- 1'b1 : The core sets NAK after Bulk OUT transfer complete
-
It bit is one time programmable after reset like any other DCFG register bits.
- - - - -
XCVRDLY
-
-
Enables or disables delay between xcvr_sel and txvalid during device chirp
-
- - - - -
Erratic Error Interrupt Mask
-
- - - - -
Enable Scatter/gather DMA in device mode (DescDMA).
-
-
When the Scatter/Gather DMA option selected during configuration of the RTL, the application can Set this bit during initialization to enable the Scatter/Gather DMA operation.
-
-
Note: This bit must be modified only once after a reset. The following combinations are available for programming:
-
- GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode
-
- GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid
-
- GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA mode
-
- GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode
- - - - -
Periodic Scheduling Interval (PerSchIntvl)
-
-
PerSchIntvl must be programmed for Scatter/Gather DMA mode.
-
-
This field specifies the amount of time the Internal
-
DMA engine must allocate for fetching periodic IN endpoint data.
-
Based on the number of periodic endpoints, this value must be
-
specified as 25,50 or 75% of (micro)Frame.
-
- When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data .
-
- When no periodic endpoints are active, Then the internal DMA engine services non-periodic endpoints, ignoring this field.
-
- After the specified time within a (micro)Frame, the DMA switches to fetching for non-periodic endpoints.
-
-- 2'b00: 25% of (micro)Frame.
-
-- 2'b01: 50% of (micro)Frame.
-
-- 2'b10: 75% of (micro)Frame.
-
-- 2'b11: Reserved.
-
Reset: 2'b00
-
- - - - -
Resume Validation Period (ResValid)
-
-
This field is effective only when DCFG.Ena32KHzSusp is set.
-
It controls the resume period when the core resumes from
-
suspend. The core counts for ResValid number of clock cycles
-
to detect a valid resume when this bit is set
- - - - - Device Control Register - - -
Remote Wakeup Signaling (RmtWkUpSig)
-
-
When the application sets this bit, the core initiates remote
-
signaling to wake up the USB host. The application must Set this
-
bit to instruct the core to exit the Suspend state. As specified in
-
the USB 2.0 specification, the application must clear this bit
-
1-15 ms after setting it.
-
-
-
If LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 microseconds (TL1DevDrvResume) after being set by the application. The application must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is zero.
- - - - -
Soft Disconnect (SftDiscon)
-
-
The application uses this bit to signal the controller to do a soft disconnect. As long as this bit is Set, the host does not see that the device is connected, and the device does not receive
-
signals on the USB. The core stays in the disconnected state until the application clears this bit.
-
- 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the
-
UTMI+ to 2'b00, which generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.
-
- 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host.
-
The following is the minimum duration under various conditions for which this bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is
-
recommended that the application adds some extra delay to the specified minimum duration.
-
-
For high speed, if the device state is,
-
- Suspended, the minimum duration is 1ms + 2.5us
-
- Idle, the minimum duration is 3ms + 2.5us
-
- Not Idle or Suspended (performing transactions), the minimum duration 125 us
-
For full speed/low speed, if the device state is,
-
- Suspended, the minimum duration is 1ms + 2.5us
-
- Idle, the minimum duration is 2.5us
-
- Not Idle or Suspended (performing transactions), the minimum duration 125 us
-
Note:
-
- This bit can be also used for ULPI/FS Serial interfaces.
-
- This bit is not impacted by a soft reset.
- - - - -
Global Non-periodic IN NAK Status (GNPINNakSts)
-
- 1'b0: A handshake is sent out based on the data availability in the transmit FIFO.
-
- 1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
- - - - -
Global OUT NAK Status (GOUTNakSts)
-
- 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
-
- 1'b1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.
- - - - -
Test Control (TstCtl)
-
- 3'b000: Test mode disabled
-
- 3'b001: Test_J mode
-
- 3'b010: Test_K mode
-
- 3'b011: Test_SE0_NAK mode
-
- 3'b100: Test_Packet mode
-
- 3'b101: Test_Force_Enable
-
- Others: Reserved
- - - - -
Set Global Non-periodic IN NAK (SGNPInNak)
-
-
A write to this field sets the Global Non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints.
-
The core can also Set this bit when a timeout condition is detected on a non-periodic endpoint in shared FIFO operation.
-
The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared
- - - - -
Clear Global Non-periodic IN NAK (CGNPInNak)
-
-
A write to this field clears the Global Non-periodic IN NAK.
- - - - -
Set Global OUT NAK (SGOUTNak)
-
-
A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.
-
The application must set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared.
- - - - -
Clear Global OUT NAK (CGOUTNak)
-
-
A write to this field clears the Global OUT NAK.
- - - - -
Power-On Programming Done (PWROnPrgDone)
-
-
The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.
- - - - -
Global Multi Count (GMC)
-
-
GMC must be programmed only once after initialization.
-
Applicable only for Scatter/Gather DMA mode. This indicates the number of packets to be serviced for that end point before moving to the next end point. It is only for non-periodic endpoints.
-
- 2'b00: Invalid.
-
- 2'b01: 1 packet.
-
- 2'b10: 2 packets.
-
- 2'b11: 3 packets.
-
The value of this field automatically changes to 2'h1 when DCFG.DescDMA is set to 1. When Scatter/Gather DMA mode is disabled, this field is reserved. and reads 2'b00.
- - - - -
Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)
-
-
This field is also used to control the Periodic Transfer Interrupt (PTI) feature.
-
-
Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode.
-
-
Slave Mode (GAHBCFG.DMAEn=0):
-
-
This bit is not valid in Slave mode and should not be programmed to 1.
-
-
Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1):
-
-
Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers.
-
-
When this bit is enabled, there must be only one packet per descriptor.
-
- 0: The core transmits the packets only in the frame number in which they are intended to be transmitted.
-
- 1: The core ignores the frame number, sending packets immediately as the packets are ready.
-
In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame.
-
-
Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=0):
-
-
When Scatter/Gather DMA mode is disabled, this field is used by the application to enable Periodic Transfer Interrupt (PTI) Mode.
-
-
The application can program Periodic Endpoint transfers for multiple (micro)Frames.
-
- 0: Periodic Transfer Interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)Frame
-
- 1: Periodic Transfer Interrupt feature is enabled, application can program transfers for multiple (micro)Frames for periodic endpoints.
-
In the PTI mode, the application will receive Transfer Complete Interrupt after transfers for multiple (micro)Frames are completed.
- - - - -
NAK on Babble Error (NakOnBble)
-
-
Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the endpoint on which babble is received.
- - - - -
Enable Continue on BNA (EnContOnBNA)
-
-
This bit enables the core to continue on BNA for Bulk OUT endpoints.
-
With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA interrupt
-
the core starts processing the descriptor that caused the BNA interrupt after
-
the endpoint re-enables the endpoint.
-
- 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the endpoint is re-enabled by the application,the core starts processing from the DOEPDMA descriptor.
-
- 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt.
-
-
This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like any other DCTL register bits.
- - - - - Device Status Register -This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register. - - -
Suspend Status (SuspSts)
-
-
In Device mode, this bit is set as long as a Suspend condition is
-
detected on the USB. The core enters the Suspend state
-
when there is no activity on the phy_line_state_i signal for an
-
extended period of time. The core comes out of the suspend under the following conditions :
-
- If there is any activity on the phy_line_state_i signal, or
-
- If the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig).
-
When the core comes out of the suspend, this bit is set to 1'b0.
- - - - -
Enumerated Speed (EnumSpd)
-
-
Indicates the speed at which the controller has come up
-
after speed detection through a connect or reset sequence.
-
- 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
-
- 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
-
- 2'b10: Low speed (PHY clock is running at 6 MHz)
-
- 2'b11: Full speed (PHY clock is running at 48 MHz)
-
Low speed is not supported for devices using a UTMI+ PHY.
- - - - -
Erratic Error (ErrticErr)
-
-
The core sets this bit to report any erratic errors
-
(phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
-
least 2 ms, due to PHY error) seen on the UTMI+.
-
Due to erratic errors, the DWC_otg core goes into Suspended
-
state and an interrupt is generated to the application with Early
-
Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
-
If the early suspend is asserted due to an erratic error, the
-
application can only perform a soft disconnect recover.
- - - - -
Frame or Microframe Number of the Received SOF (SOFFN)
-
-
When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number.
-
-
Note: This register may return a non-zero value if read immediately after power-on reset.
-
In case the register bit reads non-zero immediately after power-on reset, it does not
-
indicate that SOF has been received from the host. The read value of this interrupt is
-
valid only after a valid connection between host and device is established.
- - - - -
Device Line Status (DevLnSts)
-
-
Indicates the current logic level USB data lines
-
- DevLnSts[1]: Logic level of D+
-
- DevLnSts[0]: Logic level of D-
- - - - - - Device IN Endpoint Common Interrupt Mask Register -This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. - - -
Transfer Completed Interrupt Mask (XferComplMsk)
- - - - -
Endpoint Disabled Interrupt Mask (EPDisbldMsk)
- - - - -
AHB Error Mask (AHBErrMsk)
- - - - -
Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)
- - - - -
IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)
- - - - -
IN Token received with EP Mismatch Mask (INTknEPMisMsk)
- - - - -
IN Endpoint NAK Effective Mask (INEPNakEffMsk)
- - - - -
Fifo Underrun Mask (TxfifoUndrnMsk)
- - - - -
BNA interrupt Mask (BNAInIntrMsk)
- - - - -
NAK interrupt Mask (NAKMsk)
- - - - - Device OUT Endpoint Common Interrupt Mask Register -This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. - - -
Transfer Completed Interrupt Mask (XferComplMsk)
- - - - -
Endpoint Disabled Interrupt Mask (EPDisbldMsk)
- - - - -
AHB Error (AHBErrMsk)
- - - - -
SETUP Phase Done Mask (SetUPMsk)
-
-
Applies to control endpoints only.
- - - - -
OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)
-
-
Applies to control OUT endpoints only.
- - - - -
Status Phase Received Mask (StsPhseRcvdMsk)
-
-
Applies to control OUT endpoints only.
- - - - -
Back-to-Back SETUP Packets Received Mask (Back2BackSETup)
-
-
Applies to control OUT endpoints only.
- - - - -
OUT Packet Error Mask (OutPktErrMsk)
- - - - -
BNA interrupt Mask (BnaOutIntrMsk)
- - - - -
Babble Error interrupt Mask (BbleErrMsk)
- - - - -
NAK interrupt Mask (NAKMsk)
- - - - -
NYET interrupt Mask (NYETMsk)
- - - - - Device All Endpoints Interrupt Register -When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the -application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core -Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2. There is -one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. -For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are -set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt -register (DIEPINTn/DOEPINTn). - - -
IN Endpoint 0 Interrupt Bit
- - - - -
IN Endpoint 1 Interrupt Bit
- - - - -
IN Endpoint 2 Interrupt Bit
- - - - -
IN Endpoint 3 Interrupt Bit
- - - - -
IN Endpoint 4 Interrupt Bit
- - - - -
IN Endpoint 5 Interrupt Bit
- - - - -
IN Endpoint 6 Interrupt Bit
- - - - -
IN Endpoint 7 Interrupt Bit
- - - - -
IN Endpoint 8 Interrupt Bit
- - - - -
IN Endpoint 9 Interrupt Bit
- - - - -
IN Endpoint 10 Interrupt Bit
- - - - -
IN Endpoint 11 Interrupt Bit
- - - - -
IN Endpoint 12 Interrupt Bit
- - - - -
OUT Endpoint 0 Interrupt Bit
- - - - -
OUT Endpoint 1 Interrupt Bit
- - - - -
OUT Endpoint 2 Interrupt Bit
- - - - -
OUT Endpoint 3 Interrupt Bit
- - - - -
OUT Endpoint 4 Interrupt Bit
- - - - -
OUT Endpoint 5 Interrupt Bit
- - - - -
OUT Endpoint 6 Interrupt Bit
- - - - -
OUT Endpoint 7 Interrupt Bit
- - - - -
OUT Endpoint 8 Interrupt Bit
- - - - -
OUT Endpoint 9 Interrupt Bit
- - - - -
OUT Endpoint 10 Interrupt Bit
- - - - -
OUT Endpoint 11 Interrupt Bit
- - - - -
OUT Endpoint 12 Interrupt Bit
- - - - - Device All Endpoints Interrupt Mask Register - The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set. - - -
IN Endpoint 0 Interrupt mask Bit
- - - - -
IN Endpoint 1 Interrupt mask Bit
- - - - -
IN Endpoint 2 Interrupt mask Bit
- - - - -
IN Endpoint 3 Interrupt mask Bit
- - - - -
IN Endpoint 4 Interrupt mask Bit
- - - - -
IN Endpoint 5 Interrupt mask Bit
- - - - -
IN Endpoint 6 Interrupt mask Bit
- - - - -
IN Endpoint 7 Interrupt mask Bit
- - - - -
IN Endpoint 8 Interrupt mask Bit
- - - - -
IN Endpoint 9 Interrupt mask Bit
- - - - -
IN Endpoint 10 Interrupt mask Bit
- - - - -
IN Endpoint 11 Interrupt mask Bit
- - - - -
IN Endpoint 12 Interrupt mask Bit
- - - - -
OUT Endpoint 0 Interrupt mask Bit
- - - - -
OUT Endpoint 1 Interrupt mask Bit
- - - - -
OUT Endpoint 2 Interrupt mask Bit
- - - - -
OUT Endpoint 3 Interrupt mask Bit
- - - - -
OUT Endpoint 4 Interrupt mask Bit
- - - - -
OUT Endpoint 5 Interrupt mask Bit
- - - - -
OUT Endpoint 6 Interrupt mask Bit
- - - - -
OUT Endpoint 7 Interrupt mask Bit
- - - - -
OUT Endpoint 8 Interrupt mask Bit
- - - - -
OUT Endpoint 9 Interrupt mask Bit
- - - - -
OUT Endpoint 10 Interrupt mask Bit
- - - - -
OUT Endpoint 11 Interrupt mask Bit
- - - - -
OUT Endpoint 12 Interrupt mask Bit
- - - - - - Device VBUS Discharge Time Register - This register specifies the VBUS discharge time after VBUS pulsing during SRP. - - -
Device VBUS Discharge Time (DVBUSDis)
-
-
Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals (VBUS discharge time in PHY clocks) / 1, 024.
-
-
The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).
-
-
Depending on your VBUS load, this value can need adjustment.
- - - - - Device VBUS Pulsing Time Register - - -
Device VBUS Pulsing Time (DVBUSPulse)
-
-
Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in PHY clocks) / 1, 024
-
-
The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).
- - - - - Device Threshold Control Register - - -
Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)
-
-
When this bit is Set, the core enables thresholding for Non Isochronous IN endpoints.
- - - - -
-
ISO IN Endpoints Threshold Enable. (ISOThrEn)
-

-
When this bit is Set, the core enables thresholding for isochronous IN
-
endpoints.
- - - - -
Transmit Threshold Length (TxThrLen)
-
-
This field specifies Transmit thresholding size in DWORDS. This also forms
-
the MAC threshold and specifies the amount of data in bytes to be in the
-
corresponding endpoint transmit FIFO, before the core can start transmit
-
on the USB. The threshold length has to be at least eight DWORDS when the
-
value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the
-
application needs to ensure that the AHB Threshold value does not go below
-
the recommended eight DWORD. This field controls both isochronous and
-
non-isochronous IN endpoint thresholds. The recommended value for ThrLen
-
is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).
-
-
Note:
-
- When OTG_ARCHITECTURE=0, the reset value of this register field is 0.
-
- When OTG_ARCHITECTURE=2, the reset value of this register field is 8.
-
- - - - -
AHB Threshold Ratio (AHBThrRatio)
-
-
These bits define the ratio between the AHB threshold and the MAC threshold for the
-
transmit path only. The AHB threshold always remains less than or equal to the USB
-
threshold, because this does not increase overhead. Both the AHB and the MAC
-
threshold must be DWORD-aligned. The application needs to program TxThrLen and the
-
AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold
-
value is not DWORD aligned, the core might not behave correctly. When programming
-
the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB
-
threshold value does not go below 8 DWORDS to meet the USB turnaround time
-
requirements.
-
- 2'b00: AHB threshold = MAC threshold
-
- 2'b01: AHB threshold = MAC threshold / 2
-
- 2'b10: AHB threshold = MAC threshold / 4
-
- 2'b11: AHB threshold = MAC threshold / 8
- - - - -
Receive Threshold Enable (RxThrEn)
-
-
When this bit is set, the core enables thresholding in the receive direction.
-
-
Note: We recommends that you do not enable RxThrEn, because it may cause issues in the RxFIFO especially during error conditions such as RxError and Babble.
- - - - -
Receive Threshold Length (RxThrLen)
-
-
This field specifies Receive thresholding size in DWORDS.
-
This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB.
-
The threshold length has to be at least eight DWORDS.
-
The recommended value for ThrLen is to be the same as the programmed
-
AHB Burst Length (GAHBCFG.HBstLen).
- - - - -
Arbiter Parking Enable (ArbPrkEn)
-
-
This bit controls internal DMA arbiter parking for IN endpoints. If thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default, arbiter parking is enabled.
- - - - - Device IN Endpoint FIFO Empty Interrupt Mask Register -This register is valid only in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp). - - -
IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)
-
-
These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint:
-
-
Bit 0 for IN EP 0, bit 15 for IN EP 15
- - - - - - Device Control IN Endpoint 0 Control Register - - -
Maximum Packet Size (MPS)
-
-
Applies to IN and OUT endpoints.
-
-
The application must program this field with the maximum packet size for the current logical endpoint.
-
- 2'b00: 64 bytes
-
- 2'b01: 32 bytes
-
- 2'b10: 16 bytes
-
- 2'b11: 8 bytes
- - - - -
USB Active Endpoint (USBActEP)
-
-
This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When this bit is set, either by the application or core, the core stops
-
transmitting data, even If there is data available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data
-
packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
Hardcoded to 00 for control.
- - - - -
STALL Handshake (Stall)
-
-
The application can only set this bit, and the core clears it, when a
-
SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic
-
IN NAK, or Global OUT NAK is set along with this bit, the STALL
-
bit takes priority.
- - - - -
TxFIFO Number (TxFNum)
-
- For Shared FIFO operation, this value is always set to 0, indicating that control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO.
-
- For Dedicated FIFO operation, this value is set to the FIFO number that is assigned to IN Endpoint.
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
-
Set NAK (SNAK)
-
A write to this bit sets the NAK bit for the endpoint.
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Endpoint Disable (EPDis)
-
-
The application sets this bit to stop transmitting data on an endpoint,
-
even before the transfer for that endpoint is complete. The application
-
must wait for the Endpoint Disabled interrupt before treating the endpoint
-
as disabled. The core clears this bit before setting the Endpoint Disabled
-
Interrupt. The application must Set this bit only if Endpoint Enable is
-
already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-
When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) this bit indicates that data is ready to be transmitted on the endpoint.
-
The core clears this bit before setting the following interrupts on this endpoint:
-
- Endpoint Disabled
-
- Transfer Completed
- - - - - - Device IN Endpoint 0 Interrupt Register - This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core).
-
-
The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN Endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints only.
-
-
The core generates this interrupt when it detects a transmit FIFO underrun condition in threshold mode for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
<brIn case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 0 Transfer Size Register -The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 115. When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros. - - -
Transfer Size (XferSize)
-
-
This field contains the transfer size in bytes for the current endpoint. The transfer size (XferSize) = Sum of buffer sizes across all descriptors in the list for the endpoint.
-
In Buffer DMA, the core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.
-
- IN Endpoints: The core decrements this field every time a packet from the external memory is written to the TxFIFO.
-
- OUT Endpoints: The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.
-
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the
-
-
Transfer Size amount of data for endpoint 0.
-
- IN Endpoints : This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
-
- OUT Endpoints: This field is decremented every time a packet (maximum size or short packet) is written to the RxFIFO.
- - - - - Device IN Endpoint 0 DMA Address Register - - -
DMAAddr
-
-
This field holds the start address of the external memory for storing or fetching endpoint data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address.
-
-
When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
-
When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 0 - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 16 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control IN Endpoint 1 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 1 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 1 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 1 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 1 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 1 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 2 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 2 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 2 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 2 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 2 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 2 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 3 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 3 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 3 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 3 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 3 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 3 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 4 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 4 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 4 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 4 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 4 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 4 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 5 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 5 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 5 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 5 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 5 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 5 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 6 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 6 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 6 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 6 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 6 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 6 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 7 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 7 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 7 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 7 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 7 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 7 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 8 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 8 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 8 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 8 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 8 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 8 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 9 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 9 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 9 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 9 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 9 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 9 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 10 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 10 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 10 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 10 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 10 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 10 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 11 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 11 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 11 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 11 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 11 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 11 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control IN Endpoint 12 Control Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
-
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
-
DMA mode.
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
-
Applies to isochronous IN and OUT endpoints only.
-
-
Indicates the (micro)frame number in which the core transmits/receives isochronous
-
data for this endpoint. The application must program the even/odd (micro)frame
-
number in which it intends to transmit/receive isochronous data for this endpoint using
-
the SetEvnFr and SetOddFr fields in this register.
-
- 1'b0: Even (micro)frame
-
- 1'b1: Odd (micro)frame
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number
-
in which to send data is provided in the transmit descriptor structure. The frame in
-
which data is received is updated in receive descriptor structure.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
TxFIFO Number (TxFNum)
-
-
Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
-
endpoints must map this to the corresponding Periodic TxFIFO number.
-
- 4'h0: Non-Periodic TxFIFO
-
- Others: Specified Periodic TxFIFO.number
-
Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
-
applications such as mass storage. The core treats an IN endpoint as a non-periodic
-
endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be
-
allocated for an interrupt IN endpoint, and the number of this
-
FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
-
endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
-
-
Dedicated FIFO Operation: These bits specify the FIFO number associated with this
-
endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
-
This field is valid only for IN endpoints.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.
- - - - -
SetD0PID
-
- Set DATA0 PID (SetD0PID)
-
-- Applies to interrupt/bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.
-
When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to
-
receive data is updated in receive descriptor structure.
- - - - -
SetD1PID
-
- Set DATA1 PID (SetD1PID)
-
-- Applies to interrupt and bulk IN and OUT endpoints only.
-
-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.
-
- Set odd (micro)Frame (SetOddFr)
-
-- Applies to isochronous IN and OUT endpoints only.
-
-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.
-
-- This field is not applicable for Scatter-Gather DMA mode.
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled,
-
-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device IN Endpoint 12 Interrupt Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
Timeout Condition (TimeOUT)
-
- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.
-
- In dedicated FIFO mode, applies only to Control IN endpoints.
-
- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.
-
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
- - - - -
IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Token Received with EP Mismatch (INTknEPMis)
-
-
Applies to non-periodic IN endpoints only.
-
-
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.
- - - - -
IN Endpoint NAK Effective (INEPNakEff)
-
-
Applies to periodic IN endpoints only.
-
-
This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.
-
-
This interrupt indicates that the core has sampled the NAK bit
-
-
Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.
-
-
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
- - - - -
Transmit FIFO Empty (TxFEmp)
-
-
This bit is valid only for IN endpoints
-
-
This interrupt is asserted when the TxFIFO for this endpoint is
-
either half or completely empty. The half or completely empty
-
status is determined by the TxFIFO Empty Level bit in the Core
-
AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
- - - - -
Fifo Underrun (TxfifoUndrn)
-
-
Applies to IN endpoints Only
-
-
This bit is valid only If thresholding is enabled. The core generates this interrupt when
-
it detects a transmit FIFO underrun condition for this endpoint.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - - - Device IN Endpoint 12 Transfer Size Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet from the
-
external memory is written to the TxFIFO.
- - - - -
Packet Count (PktCnt)
-
-
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
-
-
This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.
- - - - -
MC
-
-
Applies to IN endpoints only.
-
-
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
-
For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
- - - - - Device IN Endpoint 12 DMA Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
-
- - - - - Device IN Endpoint Transmit FIFO Status Register 12 -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
-
-
Indicates the amount of free space available in the Endpoint TxFIFO.
-
-
Values are in terms of 32-bit words.
-
- 16'h0: Endpoint TxFIFO is full
-
- 16'h1: 1 word available
-
- 16'h2: 2 words available
-
- 16'hn: n words available (where 0 n 32,768)
-
- 16'h8000: 32,768 words available
-
- Others: Reserved
- - - - - Device IN Endpoint 12 Buffer Address Register -Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint. - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - - Device Control OUT Endpoint 0 Control Register - - -
Maximum Packet Size (MPS)
-
-
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.
-
- 2'b00: 64 bytes
-
- 2'b01: 32 bytes
-
- 2'b10: 16 bytes
-
- 2'b11: 8 bytes
- - - - -
USB Active Endpoint (USBActEP)
-
-
This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit, the core
-
stops receiving data, even If there is space in the RxFIFO to
-
accommodate the incoming packet. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with
-
an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
Hardcoded to 2'b00 for control.
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
The application can only set this bit, and the core clears it, when
-
a SETUP token is received for this endpoint. If a NAK bit or
-
Global OUT NAK is Set along with this bit, the STALL bit takes
-
priority. Irrespective of this bit's setting, the core always
-
responds to SETUP data packets with an ACK handshake.
- - - - -
Clear NAK (CNAK)
-
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
Using this bit, the application can control the transmission of NAK handshakes on an endpoint.
-
The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.
- - - - -
Endpoint Disable (EPDis)
-
-
The application cannot disable control OUT endpoint 0.
- - - - -
Endpoint Enable (EPEna)
-
- When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup.
-
- When Scatter/Gather DMA mode is disabled (such as for buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
- The core clears this bit before setting any of the following interrupts on this endpoint:
-
-- SETUP Phase Done
-
-- Endpoint Disabled
-
-- Transfer Completed
-
Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.
-
- - - - - - Device OUT Endpoint 0 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled
-
- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint
-
was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled.
-
-
This interrupt is asserted when the core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the core to process, such as Host busy or DMA
-
done.
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 0 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
SETUP Packet Count (SUPCnt)
-
-
This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 0 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 16 Buffer Address Register - - -
-
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is
-
reserved.
- - - - - Device Control OUT Endpoint 1 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 1 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 1 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 1 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 1 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 2 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 2 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 2 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 2 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 2 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 3 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 3 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 3 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 3 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 3 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 4 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 4 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 4 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 4 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 4 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 5 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 5 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 5 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 5 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 5 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 6 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 6 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 6 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 6 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 6 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 7 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 7 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 7 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 7 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 7 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 8 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 8 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 8 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 8 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 8 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 9 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 9 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 9 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 9 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 9 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 10 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 10 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 10 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 10 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 10 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 11 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 11 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 11 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 11 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 11 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - Device Control OUT Endpoint 12 Control Register - - -
Maximum Packet Size (MPS)
-
-
The application must program this field with the maximum packet size for the current
-
logical endpoint. This value is in bytes.
- - - - -
USB Active Endpoint (USBActEP)
-
-
Indicates whether this endpoint is active in the current configuration and interface. The
-
core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After
-
receiving the SetConfiguration and SetInterface commands, the application must
-
program endpoint registers accordingly and set this bit.
- - - - -
Endpoint Data PID (DPID)
-
-
Applies to interrupt/bulk IN and OUT endpoints only.
-
-
Contains the PID of the packet to be received or transmitted on this endpoint. The
-
application must program the PID of the first packet to be received or transmitted on
-
this endpoint, after the endpoint is activated. The applications use the SetD1PID and
-
SetD0PID fields of this register to program either DATA0 or DATA1 PID.
-
- 1'b0: DATA0
-
- 1'b1: DATA1
-
This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
-
Reset: 1'b0
-
-
Even/Odd (Micro)Frame (EO_FrNum)
-
-
In non-Scatter/Gather DMA mode:
-
- Applies to isochronous IN and OUT endpoints only.
-
- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.
-
-- 1'b0: Even (micro)frame
-
-- 1'b1: Odd (micro)frame
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
NAK Status (NAKSts)
-
-
Indicates the following:
-
- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
-
- 1'b1: The core is transmitting NAK handshakes on this endpoint.
-
When either the application or the core sets this bit:
-
- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
-
- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
-
- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
-
Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
- - - - -
Endpoint Type (EPType)
-
-
This is the transfer type supported by this logical endpoint.
-
- 2'b00: Control
-
- 2'b01: Isochronous
-
- 2'b10: Bulk
-
- 2'b11: Interrupt
- - - - -
RESERVED
- - - - -
STALL Handshake (Stall)
-
-
Applies to non-control, non-isochronous IN and OUT endpoints only.
-
-
The application sets this bit to stall all tokens from the USB host to this endpoint. If a
-
NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the
-
STALL bit takes priority. Only the application can clear this bit, never the core.
-
-
Applies to control endpoints only.
-
-
The application can only set this bit, and the core clears it, when a SETUP token is
-
received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT
-
NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's
-
setting, the core always responds to SETUP data packets with an ACK handshake.
-
- - - - -
-
Clear NAK (CNAK)
-
A write to this bit clears the NAK bit for the endpoint.
- - - - -
Set NAK (SNAK)
-
-
A write to this bit sets the NAK bit for the endpoint.
-
-
Using this bit, the application can control the transmission of NAK
-
handshakes on an endpoint. The core can also set this bit for an
-
endpoint after a SETUP packet is received on that endpoint.
- - - - -
Set DATA0 PID (SetD0PID)
-
- Applies to interrupt/bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.
-
- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.
-
Reset: 1'b0
-
-
In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.
-
- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.
-
Reset: 1'b0
- - - - -
Set DATA1 PID (SetD1PID)
-
- Applies to interrupt and bulk IN and OUT endpoints only.
-
- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.
-
- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.
-
Reset: 1'b0
-
-
Set Odd (micro)frame (SetOddFr)
-
- Applies to isochronous IN and OUT endpoints only.
-
- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.
-
Reset: 1'b0
- - - - -
Endpoint Disable (EPDis)
-
-
Applies to IN and OUT endpoints.
-
-
The application sets this bit to stop transmitting/receiving data on an endpoint, even
-
before the transfer for that endpoint is complete. The application must wait for the
-
Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears
-
this bit before setting the Endpoint Disabled interrupt. The application must set this bit
-
only if Endpoint Enable is already set for this endpoint.
- - - - -
Endpoint Enable (EPEna)
-
-
Applies to IN and OUT endpoints.
-
-
When Scatter/Gather DMA mode is enabled,
-
- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
-
- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
-
When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
-
- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
-
- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
-
The core clears this bit before setting any of the following interrupts on this endpoint:
-
- SETUP Phase Done
-
- Endpoint Disabled
-
- Transfer Completed
-
Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
- - - - - - Device OUT Endpoint 12 Interrupt Register - - -
Transfer Completed Interrupt (XferCompl)
-
-
Applies to IN and OUT endpoints.
-
- When Scatter/Gather DMA mode is enabled
-
-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.
-
-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.
-
- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
- - - - -
Endpoint Disabled Interrupt (EPDisbld)
-
-
Applies to IN and OUT endpoints.
-
-
This bit indicates that the endpoint is disabled per the application's request.
- - - - -
AHB Error (AHBErr)
-
-
Applies to IN and OUT endpoints.
-
-
This is generated only in Internal DMA mode when there is an
-
AHB error during an AHB read/write. The application can read
-
the corresponding endpoint DMA address register to get the
-
error address.
- - - - -
SETUP Phase Done (SetUp)
-
-
Applies to control OUT endpoints only.
-
-
Indicates that the SETUP phase for the control endpoint is
-
complete and no more back-to-back SETUP packets were
-
received for the current control transfer. On this interrupt, the
-
application can decode the received SETUP data packet.
- - - - -
OUT Token Received When Endpoint Disabled (OUTTknEPdis)
-
-
Applies only to control OUT endpoints.
-
-
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.
- - - - -
Status Phase Received for Control Write (StsPhseRcvd)
-
-
This interrupt is valid only for Control OUT endpoints and only in
-
Scatter Gather DMA mode.
-
-
This interrupt is generated only after the core has transferred all
-
the data that the host has sent during the data phase of a control
-
write transfer, to the system memory buffer.
-
-
The interrupt indicates to the application that the host has
-
switched from data phase to the status phase of a Control Write
-
transfer. The application can use this interrupt to ACK or STALL
-
the Status phase, after it has decoded the data phase. This is
-
applicable only in Case of Scatter Gather DMA mode.
- - - - -
Back-to-Back SETUP Packets Received (Back2BackSETup)
-
-
Applies to Control OUT endpoints only.
-
-
This bit indicates that the core has received more than three
-
back-to-back SETUP packets for this particular endpoint. For
-
information about handling this interrupt,
- - - - -
OUT Packet Error (OutPktErr)
-
-
Applies to OUT endpoints Only
-
-
This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the
-
core detects an overflow or a CRC error for non-Isochronous OUT packet.
- - - - -
BNA (Buffer Not Available) Interrupt (BNAIntr)
-
-
This bit is valid only when Scatter/Gather DMA mode is enabled.
-
-
The core generates this interrupt when the descriptor accessed
-
is not ready for the Core to process, such as Host busy or DMA
-
done
- - - - -
Packet Drop Status (PktDrpSts)
-
-
This bit indicates to the application that an ISOC OUT packet has been dropped. This
-
bit does not have an associated mask bit and does not generate an interrupt.
-
-
Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer
-
interrupt feature is selected.
- - - - -
NAK Interrupt (BbleErr)
-
-
The core generates this interrupt when babble is received for the endpoint.
- - - - -
NAK Interrupt (NAKInterrupt)
-
-
The core generates this interrupt when a NAK is transmitted or received by the device.
-
-
In case of isochronous IN endpoints the interrupt gets generated when a zero length
-
packet is transmitted due to un-availability of data in the TXFifo.
- - - - -
NYET Interrupt (NYETIntrpt)
-
-
The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
- - - - -
Setup Packet Received
-
-
Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
-
-
Set by the controller, this bit indicates that this buffer holds 8 bytes of
-
setup data. There is only one Setup packet per buffer. On receiving a
-
Setup packet, the controller closes the buffer and disables the
-
corresponding endpoint. The application has to re-enable the endpoint to
-
receive any OUT data for the Control Transfer and reprogram the buffer
-
start address.
-
-
Note: Because of the above behavior, the controller can receive any
-
number of back to back setup packets and one buffer for every setup
-
packet is used.
-
- 1'b0: No Setup packet received
-
- 1'b1: Setup packet received
-
Reset: 1'b0
- - - - - - Device OUT Endpoint 12 Transfer Size Register - - -
Transfer Size (XferSize)
-
-
Indicates the transfer size in bytes for endpoint 0. The core
-
interrupts the application only after it has exhausted the transfer
-
size amount of data. The transfer size can be Set to the
-
maximum packet size of the endpoint, to be interrupted at the
-
end of each packet.
-
-
The core decrements this field every time a packet is read from
-
the RxFIFO and written to the external memory.
- - - - -
Packet Count (PktCnt)
-
This field is decremented to zero after a packet is written into the RxFIFO.
- - - - -
RxDPID
-
-
Applies to isochronous OUT endpoints only.
-
-
This is the data PID received in the last packet for this endpoint.
-
- 2'b00: DATA0
-
- 2'b01: DATA2
-
- 2'b10: DATA1
-
- 2'b11: MDATA
-
SETUP Packet Count (SUPCnt)
-
-
Applies to control OUT Endpoints only.
-
-
This field specifies the number of back-to-back SETUP data
-
packets the endpoint can receive.
-
- 2'b01: 1 packet
-
- 2'b10: 2 packets
-
- 2'b11: 3 packets
- - - - - Device OUT Endpoint 12 DMA Address Register - - -
Holds the start address of the external memory for storing or fetching endpoint
-
data.
-
-
Note: For control endpoints, this field stores control OUT data packets as well as
-
SETUP transaction data packets. When more than three SETUP packets are
-
received back-to-back, the SETUP data packet in the memory is overwritten.
-
-
This register is incremented on every AHB transaction. The application can give
-
only a DWORD-aligned address.
-
- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.
-
- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
- - - - - - Device OUT Endpoint 12 Buffer Address Register - - -
Holds the current buffer address.This register is updated as and when the data
-
transfer for the corresponding end point is in progress.
-
-
This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
- - - - - - Power and Clock Gating Control Register - - -
Stop Pclk (StopPclk)
-
- The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected.
-
- The application clears this bit when the USB is resumed or a new session starts.
- - - - -
Reset Power-Down Modules (RstPdwnModule)
-
-
This bit is valid only in Partial Power-Down mode.
-
- The application sets this bit when the power is turned off.
-
- The application clears this bit after the power is turned on and the PHY clock is up.
-
-
Note: The R/W of all core registers are possible only when this bit is set to 1b0.
- - - - -
PHY In Sleep
-
-
Indicates that the PHY is in Sleep State.
- - - - -
L1 Deep Sleep
-
-
Indicates that the PHY is in deep sleep when in L1 state.
- - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1 to rw. - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from othr to rw. - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from ru to rw. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - - - bit type is changed from ru to rw. - - - - - - - bit type is changed from ru to rw. - - - - - - - bit type is changed from ru to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - - bit type is changed from othr to rw. - - - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - bit type is changed from othr to rw. - - - bit type is changed from othr to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from w1 to rw. - - - bit type is changed from othr to rw. - - - - - - - - - - - - - - - - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - bit type is changed from w1c to rc. - - - - - - - - - - - - - - - - - - - bit type is changed from ru to rw. - - - - - - - - - - - - - - - - - - - - - Controls the big endian or little endian of the FIFO data. -
- Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0. -
- "000": the order is not changed. -
- Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D". -
- "001": reversed on byte. -
- Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A". -
- "010": reversed on half word. -
- Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B". -
- "010": reversed on bit. -
- Byte3="B0",Byte2="30,Byte1="D0",Byte0="50". -
- "100": reversed on bit. -
- Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". - - - - - For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind. -
- Active Low. - - - - - - - Write to the transmit FIFO - - - Read in the receive FIFO - - - - - - - SD/MMC operation begin register, active high. -
- When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. - - - - SD/MMC operation suspend register, active high. - - - '1'indicates having a response,'0'indicates no response. - - - - - - Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. - - - '1' indicates data operation, which includes read and write. - - - - - - '1' means write operation,'0' means read operation. - - - - - - '1'means multiple block data operation. - - - - - - - '1' means the SD/MMC operation is not over. - - - '1' means SD/MMC is busy. - - - '1' means the data line is busy. - - - '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. - - - Response CRC checks error register '1' means response CRC check error. - - - '1' means the card has no response to command. - - - - CRC check for SD/MMC write operation -
- "101" transmission error -
- "010" transmission right -
- "111" flash programming error - - - - 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. - - - SDMMC DATA 3 value. - - - - - SD/MMC command register. - - - - - SD/MMC command argument register, write data to the SD/MMC card. - - - - - SD/MMC response index register. - - - - - Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. - - - - - 95 to 64 bit response argument of R2. - - - - - 63 to 32 bit response argument of R2. - - - - - 31 to 0 bit response argument of R2. - - - - - - SD/MMC data width: -
- 0x1: 1 data line -
- 0x2: 2 reserved -
- 0x4: 4 data lines -
- 0x8: 8 data lines - - - - - - - SD/MMC size of one block: -
- 0-1:reserved -
- 2: 1 word -
- 3: 2 words -
- 4: 4 words -
- 5: 8 words -
- 6: 16 words -
-
- 11: 512 words -
- 12-15 reserved - - - - - - Block number that wants to transfer. - - - - - '1' means no response. - - - '1' means CRC error of response. - - - '1' means CRC error of reading data. - - - '1' means CRC error of writing data. - - - '1' means data transmission is over. - - - '1' means tx dma done. - - - '1' means rx dma done. - - - '1' means no response is the source of interrupt. - - - '1' means CRC error of response is the source of interrupt. - - - '1' means CRC error of reading data is the source of interrupt. - - - '1' means CRC error of writing data is the source of interrupt. - - - '1' means the end of data transmission is the source of interrupt. - - - '1' means tx dma done is the source of interrupt. - - - '1' means rx dma done is the source of interrupt. - - - - - When no response, '1' means INT is disable. - - - When CRC error of response, '1' means INT is disable. - - - When CRC error of reading data, '1' means INT is disable. - - - When CRC error of writing data, '1' means INT is disable. - - - When data transmission is over, '1' means INT is disable. - - - when tx dma done, '1' means INT is disabled. - - - '1' means rx dma done, '1' means INT is disabled. - - - - - Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. - - - Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. - - - Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. - - - Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. - - - Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. - - - - - Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). - - - - - This register may delay the mclk output. - When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. - - - Invert Mclk. - - - - - - - - - - - - - Enable camera controller,high active. - - - Enable camera controller,high active. - - - - - - - - - - - "0" = RGB565. -
- "1" = YUV422. -
- "2" = Compressed Data. -
- "3" = Reserved. - - - - - - - - - - '0' = keep output camera reset polarity. -
- '1' = invert output camera reset polarity. - - - - - - - - '0' = keep output camera power down polarity. -
- '1' = invert output camera power down polarity. - - - - - - - - '0' = keep input VSYNC polarity. -
- '1' = invert input VSYNC polarity. - - - - - - - - '0' = keep input HREF polarity so data is sampled when HREF high. -
- '1' = invert input HREF polarity so data is sampled when HREF low. - - - - - - - - '0' = keep pix clk polarity. -
- '1' = invert pix clk polarity. - - - - - - - - '0' = VSYNC irq always exists when Frame decimation is enabled. -
- '1' = VSYNC irq will drop when Frame data are dropped in decipation. - - - - - - - - "0"= All frame data will be sent. -
- "1"= only one frame out of two (1/2) will be sent. -
- "2"= only one frame out of three (1/3) will be sent. -
- "3"= only one frame out of four (1/4) will be sent. - - - - - - - - "0"= Pixel Decimation Disabled. -
- "1"= Pixel Decimation 1/2. -
- "2"= Pixel Decimation 1/3. -
- "3"= Pixel Decimation 1/4. - - - - - - - - "0"= line Decimation Disabled. -
- "1"= line Decimation 1/2. -
- "2"= line Decimation 1/3. -
- "3"= line Decimation 1/4. - - - - - Controls the Re-ordering of the FIFO data. -
- In following table, for input data, right comes before left. So YUYV means V comes first. -
- for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word. -
-
- If Bit 26 is '1', byte2 and byte0 is Y. -
- If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange. -
- If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26). -
-
- input YUYV, output YUYV: "000" -
- input YVYU, output YUYV: "001" -
- input UYVY, output YUYV: "110" -
- input VYUY, output YUYV: "111" -
-
- input YUYV, output UYVY: "010" -
- input YVYU, output UYVY: "011" -
- input UYVY, output UYVY: "100" -
- input VYUY, output UYVY: "101" -
-
- input YUYV, output YVYU: "001" -
- input YVYU, output YVYU: "000" -
- input UYVY, output YVYU: "111" -
- input VYUY, output YVYU: "110" -
-
- input YUYV, output VYUY: "011" -
- input YVYU, output VYUY: "010" -
- input UYVY, output VYUY: "101" -
- input VYUY, output VYUY: "100" -
-
- Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation. - This reorder is corrected using Bit 26 infomation. - - - - - - - - "0"= Cropping Disabled. -
- "1"= Cropping Enabled. -
- Note: this bit should set to '0' when bit field "DataFormat" is "10" (compressed data) - - - - - - - In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled. - - - - - - Debug only. A RGB565 test card is sent to system bus instead of real data from sensor. - - - - - - '1' = FIFO over-write IRQ status. -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = VSYNC rising edge IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = VSYNC falling edge IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - - '1' = DMA Done IRQ status -
- Write to corresponding bit in IRQ CLEAR register will clear this bit. - - - - '1' = FIFO Empty status, not clear-able. - - - - - - - Read in the receive FIFO - - - - - '1' = FIFO over-write enable - - - '1' = VSYNC rising edge enable - - - '1' = VSYNC falling edge enable - - - '1' = DMA Done enable - - - - - Write '1' to clear FIFO over-write interrupt - - - Write '1' to clear VSYNC rising edge interrupt - - - Write '1' to clear VSYNC falling edge interrupt - - - Write '1' to clear DMA Done interrupt - - - - - '1' = FIFO over-write cause - - - '1' = VSYNC rising edge cause - - - '1' = VSYNC falling edge cause - - - '1' = DMA Done cause - - - - - Power down pin of CMOS sensor . - - - - Reset pin of CMOS sensor. -
- Active Low. - - - - For the software to clear FIFO. This bit is auto-reset to 0. - - - - - Power down pin of CMOS sensor . - - - Reset pin of CMOS sensor. - - - - - start pixel of cropped window. - - - end pixel of cropped window. - - - - - start line of cropped window. - - - end line of cropped window. - - - - - - - swap camera data output [15:0],[31:16]. - - - - - - - - - spi slave enable. - - - spi master enable. - - - yuv out format. - 3'b000: data_serial_mux = {Y0,U0,Y1,V0}; - 3'b001: data_serial_mux = {Y0,V0,Y1,U0}; - 3'b010: data_serial_mux = {U0,Y0,V0,Y1}; - 3'b011: data_serial_mux = {U0,Y1,V0,Y0}; - 3'b100: data_serial_mux = {V0,Y1,U0,Y0}; - 3'b101: data_serial_mux = {V0,Y0,U0,Y1}; - 3'b110: data_serial_mux = {Y1,V0,Y0,U0}; - 3'b111: data_serial_mux = {Y1,U0,Y0,V0}; - - - overflow rstn only vsync low. - - - overflow_observe_only_vsync_low. - - - overflow_rstn enable - - - big_end_dis - - - overflow inv control - - - href inv control - - - vsync inv control - - - block_num_per_line[9:0] pixels num of a line - - - line_num_per_frame[9:0] lines num of a frame - - - - - camera_clk_div_num - - - cts_spi_master_reg - - - ssn_cm inv control - - - sck_cm inv control - - - ssn_spi_oen select, 1:from reg 0: from logic - - - ssn_spi_oenb reg - - - sck_spi_oenb select, 1:from reg 0:from logic - - - sck_spi_oenb reg - - - sdo_spi_swap reg,swap camera_spi_0 and camera_spi_1 - - - clk inv control - - - sck double edge enable - - - - - ssn_wait_length[7:0] - - - init_wait_length[7:0] - - - word_num_per_block[7:0] - - - ssn_cs_delay[1:0] - - - data_receive_choose_bit[1:0] - - - ready_cs_inv - - - ssn_cs_inv - - - eco_bypass_isp - - -line_wait_length[15:0] - - - line_wait_length - - - block_wait_length[7:0] - - - ssn_high_length[7:0] - - - - - camera_spi_master no ssn mode enable - - - sdo_line_choose_bit[1:0] 0:1 line 1: 2lines 2:4lines - - - data_size_choose_bit 1: from reg 0:from logic - - - image_height_choose_bit 1: from reg 0:from logic - - - image_width_choose_bit 1: from reg 0:from logic - - - block_num_per_packet[9:0] - - - 0: spi data0 delay 0 - 1: spi data0 delay 2 cycles spi_cam_clk - 2: spi data0 delay 3 cycles spi_cam_clk - 3: spi data0 delay 4 cycles spi_cam_clk - - - 0: spi data1 delay 0 - 1: spi data1 delay 2 cycles spi_cam_clk - 2: spi data1 delay 3 cycles spi_cam_clk - 3: spi data1 delay 4 cycles spi_cam_clk - - - - - sync code - - - - - packet_id_data_start - - - packet_id_line_start - - - packet_id_frame_end - - - packet_id_frame_start - - - - - line_id[15:0] - - - data_id[7:0] - - - observe_data_size_wrong - - - observe_image_height_wrong - - - observe_image_width_wrong - - - observe_line_num_wrong - - - observe_data_id_wrong - - - - - image_height[15:0] - - - image_width[15:0] - - - - - num_d_term_en[7:0] term time reg - - - cur_frame_line_num[12:0] - - - data_lp_in_choose_bit[1:0] - - - clk_lp inv - - - trail_data_wrong_choose_bit 1:secelt trail1 0:select trail0 - - - sync_bypass - - - rdata_bit_inv en - - - hs_sync_find en - - - line_packet_enable - - - ecc_bypass - - - data_lane_choose_bit 1:select lane2 0:select lane1 - - - csi_module_enable - - - - - num_hs_settle[7:0] set hs settle time - - - lp_data_length_choose_bit[2:0] set data length - - - data_clk_lp_posedge_choose[2:0] select delay cycles - - - clk_lp_ck_inv - - - rclr_mask_en - - - rinc_mask_en - - - hs_enable_mask_en - - - den_csi_inv_bit - - - hsync_csi_inv_bit - - - vsync_csi_inv_bit - - - hs_data2_enable_reg - - - hs_data1_enable_reg - - - hs_data1_enable_choose_bit - - - hs_data1_enable_dr 1:select reg 0:select logic - - - data2_terminal_enable_reg - - - data1_terminal_enable_reg - - - data1_terminal_enable_dr 1:select reg 0:select logic - - - lp_data_interrupt_clr, clear flag - - - lp_cmd_interrupt_clr, clear flag - - - lp_data_clr, clear data out - - - lp_cmd_clr, clear cmd out - - - - - num_hs_settle_clk[15:0], set hs settle counter - - - num_c_term_en[15:0],set clk term counter - - - - - clk_lp_in_choose_bit - - - pu_lprx_reg - - - pu_hsrx_reg - - - pu_dr, 1:select reg 0:select logic - - - data_pnsw_reg - - - hs_clk_enable_reg - - - hs_clk_enable_choose_bit - - - hs_clk_enable_dr 1:select reg 0:select logic - - - clk_terminal_enable_reg - - - clk_terminal_enable_dr 1:select reg 0:select logic - - - observe_reg_5_low8_choose - - - ecc_error_flag_reg - - - ecc_error_dr - - - csi_channel_sel - - - two_lane_bit_reverse, reverse high and low 8bit - - - data2_lane_bit_reverse 1:select revert data - - - data1_lane_bit_reverse 1:select revert data - - - data2_hs_no_mask 1:data only valid when sync assert - - - data1_hs_no_mask 1:data only valid when sync assert - - - pu_lprx_d2_reg - - - pu_lprx_d1_reg - - - clk_edge_sel - - - clk_x2_sel - - - single_data_lane_en 1:1lane 0:2lanes - - - - - num_hs_clk_useful[30:0] hs clk useful counter - - - num_hs_clk_useful_en - - - - - vc_id_set[1:0] - - - data_lp_inv - - - fifo_rclr_8809p_reg - - - fifo_wclr_8809p_reg - - - hs_sync_16bit_8809p_mode - - - d_term_small_8809p_en - - - data_line_inv_8809p_en - - - hs_enable_8809p_mode - - - sp_to_trail_8809p_en - - - trail_wrong_8809p_bypass - - - rinc_trail_8809p_bypass - - - hs_data_enable_8809p_mode - - - hs_clk_enable_8809p_mode - - - data_type_re_check_en - - - sync_id_reg - - - sync_id_dr - - - csi_observe_choose_bit - - - crc_error_flag_reg - - - crc_error_flag_dr 1:select reg 0:select logic - - - csi_rinc_new_mode_dis - - - - - data_type_dp_reg[5:0], set data type - - - data_type_le_reg line end type - - - data_type_ls_reg line start type - - - data_type_fe_reg frame end type - - - data_type_fs_reg frame start type - - - 1: only support raw8 0:support more type - - - 1:select reg value - - - - - data_lane_16bits_mode - - - terminal_2_hs_exchage_8809p - - - terminal_1_hs_exchage_8809p - - - data2_terminal_enable_8809p_dr - - - hs_data2_enable_8809p_dr - - - csi_dout_test_8809p_en - - - csi_dout_test_8809p[7:0] - - - num_d_term_en[15:8] - - - num_hs_settle[15:8] - - - - - hs_data_state[13:0] - - - phy_data_state[14:0] - - - fifo_wfull_almost - - - fifo_wfull - - - fifo_wempty - - - - - if observe_reg_5_low8_choose=1, out is data_id[7:0], else out is lp_cmd_out[7:0] - - - lp_data_interrupt_flag - - - lp_data_interrupt_flag - - - phy_clk_state[8:0] - - - fifo_rcount[8:0] - - - crc_error - - - err_ecc_corrected_flag - - - err_data_corrected_flag - - - err_data_zero_flag - - - - - if observe_reg_5_low8_choose=1, out is csi_observe_mon, else out is lp_data_out[63:32] - - - - - csi_observe_reg_7[31:0] - - - - - csi_enable - - - - - dly_sel_clkn_reg,set clkn delay,to csi analog phy - - - dly_sel_clkp_reg,set clkp delay,to csi analog phy - - - dly_sel_data2_reg,set data2 delay,to csi analog phy - - - dly_sel_data1_reg,set data1 delay,to csi analog phy - - - vth_sel,to csi analog phy - - - - - - - Direct FIFO Ram Access. They are enabled only in Bist Mode. - - - - - - - - - - - - rstn of dsp - - - - - - for A ctd block, u2.7 format - awb_x1_min[8:0]=[awb_ctd_msb[0],awb_x1_min[7:0]] - - - - - for A ctd block, u2.7 format - awb_x1_max[8:0]=[awb_ctd_msb[1],awb_x1_max[7:0]] - - - - - for A ctd block, u1.7 format - - - - - for A ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for TL84 ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for CWF ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for Indoor ctd block, u1.7 format - - - - - for D65 ctd block, u1.7 format - - - - - for D65 ctd block, u1.7 format - - - - - for D65 ctd block, u2.7 format - awb_y5_min[8:0]=[awb_ctd_msb[2],awb_y5_min[7:0]] - - - - - for D65 ctd block, u2.7 format - awb_y5_max[8:0]=[awb_ctd_msb[3],awb_y5_max[7:0]] - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for TL84 skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - for CWF skin ctd block, u1.7 format - - - - - awb_x1_min[8:0]=[awb_x1_min_msb,awb_x1_min[7:0]] - - - awb_x1_max[8:0]=[awb_x1_max_msb,awb_x1_max[7:0]] - - - awb_y5_min[8:0]=[awb_y5_min_msb,awb_y5_min[7:0]] - - - awb_y5_max[8:0]=[awb_y5_max_msb,awb_y5_max[7:0]] - - - 2d0: awb_adj_sig=1 - 2d1: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 or cbsum_abs>vld_cnt_cb_thr x2 - 2d2: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x3 or cbsum_abs>vld_cnt_cb_thr x3 - 2d3: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 and cbsum_abs>vld_cnt_cb_thr x2 - - - 2d3: awb_ratio_lmax=4 - 2d2: awb_ratio_lmax=2 - 2d1: awb_ratio_lmax=0 - 2d0: awb_ratio_lmax= according to the proportion of cnt_max and cnt_lmax - - - - - - - - - - - - - - - vsync_end_reg=[vsync_end_high,vsync_end_low] - - - - - vsync_end_reg=[vsync_end_high,vsync_end_low] - - - - - line_num = [line_numH,line_numL] - - - - - pix_num = [pix_numH,pix_numL] - - - - - - - - not used here - - - - - - not used here - - - - - - - - - - - - - - - - - - - 00:YUV/RAW8(para) - 01:RAW8(mipi) - 10:RAW10(mipi) - - - - - - - - - - - - - - - - - - line_cnt=[line_cnt_H[1:0], [7:0]] - - - - - line_cnt=[line_cnt_H[1:0], line_cnt_L] - - - - - - - - - - - - - - - - - - - 1: kl 0: kldci () - - - 1: kl 0: kldci - - - 1: ku 0: kudci () - - - 1: ku 0: kudci - - - hist 2 - - - 00: 0x98regae_dark_hist_reg - 01: 0x98regyave_target_RO_reg - other: 0x98regyave_contr_reg - - - - - kl_ofstx1[4:0] = [kl_ofstx1, 1b0] (kl0x80) - - - ku_ofstx1[4:0] = [ku_ofstx1, 1b0] (kl0x80) - - - - - dk_histx1[4:0] = [dk_histx1, 1b0] (dhist) - - - br_histx1[4:0] = [br_histx1, 1b0] (bhist) - - - - - swaeswexp/gainnexphw// - - - sw/hwae,SWae, - - - - - THR_dark[4:0] = [THR_dark, 1'b0] (ytarget-yave THR_darkae) - - - THR_bright[4:0] = [THR_bright,1'b0](yave-ytargetTHR_brightae) - - - - - ytarget_dec - 2d3:4indexytargetregd[3:0]8index08 - 2d2:2indexytargetregd[3:0]8index016 - 2d1:1indexytargetregd[3:0]8index032 - 2d0:1indexytargetregd[3:0]8index064 - - - ytarget_dec - 2d3:4indexytargetregc[7:4]8index_max8 - 2d2:2indexytargetregc[7:4]8index_max16 - 2d1:1indexytargetregd[7:4]8index_max32 - 2d0:1indexytargetregd[7:4]8index_max64 - - - 1yave_diff_2frame - - - 1THR_big - - - 1bhist>0@is_dark - - - 1index_ofst - - - - - @nexp - - - @nexp - - - - - low_th = [[0], lsc_blc_gain_th[7:6]](nexp=low_th) - - - nexp>(8+high_th) - - - Fixed Ythr of contr = [[7:4], 4d0] - - - - - - - - 1: dynamic yave (Yave) - 0: fixed ythr contr_ythr_reg - - - YaveYthrofst (01) - - - - - upper@Low gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@Low gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - upper@Mid gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@Mid gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - upper@High gain - Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) - - - 1: 0 - - - - - lower@High gain - Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) - - - 1: 0 - - - - - @Low gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - @Mid gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - @High gain - - - 1: Yout = (256-offset)*Yin/256 + offset - 0: Yout = Yin + offset - - - 0 1 - - - - - Cb@Low gain0x80 just x1.0 - - - - - Cr@Low gain0x80 just x1.0 - - - - - Cb@Mid gain0x80 just x1.0 - - - - - Cr@Mid gain0x80 just x1.0 - - - - - Cb@High gain0x80 just x1.0 - - - - - Cr@High gain0x80 just x1.0 - - - - - @luma/contr/satur(nexp=low_th) - - - not used here - - - @luma/contr/satur(nexp>(8+high_th)) - - - - - 4'd0: cc_type = 0; //D65 - 4'd1: cc_type = 1; //U30 - 4'd2:if(is_outdoor) cc_type = 0; - else cc_type = 1; - 4'd3:if(ana_gain>=cc_gain_th) cc_type = 0; - else cc_type = 1; - 4'd4:if(rgain_bigger) cc_type = 0; //D65 - else if(bgain_bigger) cc_type = 1; //U30 - 4'd5: if(is_outdoor) cc_type = 0; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd6: if(is_outdoor) cc_type = 0; - else if(ana_gain=cc_gain_th) cc_type = 0; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd7: if(is_outdoor) cc_type = 0; - else if(ana_gain=cc_gain_th) cc_type = 1; - else if(rgain_bigger) cc_type = 0; - else if(bgain_bigger) cc_type = 1; - 4'd8: if(r_awb_gain_outr_low_non_A)cc_type = 1; - else if(r_awb_gain_out(r_low_non_A+8)) cc_type = 0; - 4d9: if(awb_idx_max2) cc_type = 1; - else if(awb_idx_max2) cc_type = 0; - other: SW driven ( reg1c2) - - - nexp>(8+high_th) - - - 1: 0: - - - - - r_big_th=[awb_cc_type_th_reg[3:0], 2d0] - - - b_big_th=[awb_cc_type_th_reg[7:4], 2d0] - - - - - 00: YUV422 01: RGB565 - 10: raw bayer 11: clip out - - - 00:YUYV 01:YVYU - 10:UYVY 11:VYUY - (Note:[2] uv_sel 0:UV 1:VU) - - - - - - - - - - - - - - - - - - - - - - - - Case(rgb_mode_reg) @clip out - 3'd0: to_n_clp_data 3'd1: y_data - 3'd2: cnr_1d_cb 3'd3: cnr_1d_cr - 3'd4: c_data 3'd5: yc2r_data - 3'd6: yc2g_data 3'd7: yc2b_data - Note:rgb_mode_reg[0] is also used to - 1, select the line of sub_YUV output - - - not used, sca_reg=1:sub mode - - - bypass vsync_in and hsync_in - - - - - - - - - - - Line_num=[lin_num_l_reg[5:0], 3d0] - - - - - Pix_num=[pix_num_l_reg[6:0], 3d0] - - - - - - - - HsyncNvsync - - - Mvsync - top_dummy>16, vtop_dummy=top_dummy-[7:4] - - - - - 1blc[ku, kl] - - - 1:nexp[3:0] 0:mono_color - - - 1: dpc_out 0: bayer_data - - - - - - 1: enable 0: disable - y_gamma_en = is_outdoor ? scg_reg[5] : scg_reg[4] - - - 1: SDI 0: BT.601 - - - 1: [ae_ok, nexp_sel[1:0], awb_ok, exp[11:8]] - 0: [ae_ok, 1b0, nexp_sel[1:0], awb_ok, exp[10:8]] - labview - - - - - (0x00)0 (0x00)0 (0x00)0 - - - - - (0x13)19 (0x10)16 (0x08)8 - - - - - (0x20)32 (0x1c)28 (0x10)16 - - - - - (0x36)54 (0x30)48 (0x20)32 - - - - - (0x49)73 (0x43)67 (0x30)48 - - - - - (0x5a)90 (0x54)84 (0x40)64 - - - - - (0x6b)107 (0x65)101 (0x50)80 - - - - - (0x7b)123 (0x75)117 (0x60)96 - - - - - RW(0x98)152 (0x93)147 (0x80)128 - - - - - (0xb4)180 (0xb0)176 (0xa0)160 - - - - - (0xce)206 (0xcb)203 (0xc0)192 - - - - - (0xe7)231 (0xe6)230 (0xe0)224 - - - - - 0.75 0.8 1.0 - - - - - r_gain_manual 2.6 format - - - - - g_gain_manual 2.6 format - - - - - b_gain_manual 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - 2.6 format - - - - - - - - also update cc_type,gamma_type,is_outdoor - - - - - - - - 00: AWB - 01: AWB - 10: yaveAWB - 11: nexpAWB - - - - - - - - - - - - 1: mon ae index 0:mon awb_debug - - - - - 0yave 1yave - 2yave 3yave - - - 07/0f/17/1f Yave - - - 00: y2ave x1.0 01: y2ave x1.5 - 10: y3ave x1.0 11: y3ave x1.5 - - - 1:plus bh 0: only yave - - - 1:plus bh 0: only ywave - - - - - - - - - - - - - - - - - - - - - - pcnt_left =[ae_win_start_reg[3:0] ,1'd0] - - - lcnt_top =[ae_win_start_reg[7:4] ,1'd0] - - - - - ae(yave) win_width = [ae_win_width[7:0], 2'd0] - - - - - ae(yave) ae_win_height = [ae_win_height[7:0], 1'd0] - - - - - exp[7:0](ae_enMCUexp_init[6:0]indexae) - - - - - exp[11:8] - - - - - 10msexp - - - - - (ytarget) - THR_dark(reg41) - THR22index1 - THR24index2 - THR26index4+ofst0 - THR28index8+ofst1 - index16 - - - (ytarget) - THR_bright(reg41) - THR22index1 - THR24index2 - THR26index4+ofst0 - THR28index8+ofst1 - index16 - - - - - - - - Bh = Bh_mean * bh_factor /8 - bh_factor = is_outdoor? bh_factor_outdoor : bh_factor_indoor - - - 00: curr frame 01: 2 frame ave - 10: 3 frame ave 11: 4 frame ave - - - - - awb_mon_out[7:0][cbsum_abs_eq, crsum_abs_eq]SWAWB - - - 2.0xr/b - - - 4.0xr/b - - - 0: 1frame or 2frame - - - - - - - - - - - [ 2] 0:readback blc 1: readback awb - [1:0] 0: crsum_abs 1:cbsum_abs - 2: vld_cnt 3:awb_idx_lmax and max - - - AWB - - - 3'd0:awb_vld=vld_max||(vld_lmax and awb_ratio_lmax); - 3'd1: awb_vld = awb_vld1; - 3'd2: awb_vld = awb_vld2; - 3'd3: awb_vld = awb_vld3; - 3'd4: awb_vld = awb_vld4; - 3'd5: awb_vld = awb_vld5; - 3'd6: awb_vld =!skin_vld; - 3'd7: awb_vld = awb_vld1|awb_vld2|awb_vld3| awb_vld4 | awb_vld5; - - - - - - - - Y Y_maxAWB - - - - - Levelawb_stop - - - Levelawb_stop - - - Levelawb_stop - - - Levelawb_stop - - - - - [7:0]awb_algo_thr - Y > cr_abs+cb_abs+awb_algo_reg - // - - - - - - - - - - - - - - - - - 0: (vld_cntawb_vld_thr) - 1: (vld_cntawb_vld_thr)and(crsum_absawb_vld_thr)and(cbsum_absawb_vld_thr) - - - 0: awb_stopcb/cr - 1: - - - 0: use CTD block to detect skin - 1: use cb,cr to detect skin - - - 0: cb+cr - 1: cb/cr - - - - - awb_vld_thr = [awb_ctrl4[7:0], 4'hf] - - - - - - - - - - 1: 0 - - - - - - - - - y_low_thr = [1h0, y_thr_reg[7:3], 2'h0] - y_high_thr = ~y_low_thr - - - - - - - - - - Only for awb_adj, yaveAWB - y_low_limit = y_ave_target - [y_lmt_offset_reg[2:0],4'd0] - - - not used here - - - Only for awb_adj, yaveAWB - y_high_limit = y_ave_target+ [y_lmt_offset_reg[6:4],4'd0] - - - - - nexp=low_th - - - not used here - - - nexp>(8+high_th) - - - - - yave_target (yave_target0) - - - yave_target (yave_target0) - - - - - - - - - - - - - - - - - not used here - - - 1reg93vbright_hist - - - 1reg94vdark_hist - - - display edge pixel for sharpness - - - - - Ywave+bhist histYwave - - - - - bright hist - - - - - Yave+bhisthistYave - - - - - - - - - - exp_out[10:8] - - - - - - nexp_selbnr/dpc/int_dif - - - - - - - - - - - 00: cr_lt_1x 01: cr_gt_1x - 10: cr_gt_2x 11: cr_gt_4x - - - 00: cb_lt_1x 01: cb_gt_1x - 10: cb_gt_2x 11: cb_gt_4x - - - 0:crsum (5R B+4G) - 1:crsum (5R B+4G) - - - 0:cbsum (3B R+2G) - 1:cbsum (3B R+2G) - - - 0: crsum_abs cbsum_abs (crsum) - 1: crsum_abs cbsum_abs (cbsum) - - - ae_index - Note: regd[5]? ae_vbright_hist : - reg75[7]? ae_index[6:0] : awb_debug; - - - - - YUVnexp vdark_hist - Note: regd[6]? ae_vdark_hist : - reg5F[1]? nexp[3:0] : mono_color - - - - - - - - - - - - - - - - - - - - - - - - - - yavehist - Vbh_sel[1]? Yave_contr_reg : - Vbh_sel[0]? Yave_target_RO_reg : ae_dark_hist - NoteVbh_sel[1:0] = reg3d[7:6] - - - - - 3d0: gamma_type=0 - 3d1: gamma_type=1 - 3d2: gamma_type=is_outdoor - 3d3: gamma_type=ana_gain>=gamma_gain_th - default:gamma_type=gamma_type_sw - - - nexp>(8+high_th) - - - 00:QVGA 240x320 01:QVGA 320x240 - 10:CIF 352x288 11:VGA 640x480 - - - - - line_sel = [line_init_H, blc_line_reg[7:0]] - - - - - lsc gain@ - - - lsc gain@ - - - - - nexp=low_th - - - nexp>(8+high_th) - - - low_th = [csup_gain_low_th_H, [7:6]](nexp=low_th) - - - - - 2'd0: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_01] - 2'd1: [blc_out0_reg,blc_out1_reg] = [blc_10, blc_11] - 2'd2: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_10] - 2'd3: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_11] - - - - - - 0: plus 1: minus - - - 00: 1frame 01: 2frame ave - 10: 3frame ave 11: 4frame ave - - - - - - - - - - - blc00_ofst =[blc_init_reg[3:0] , 1'b0] - - - blc01_ofst =[blc_init_reg[7:4] , 1'b0] - - - - - blc10_ofst =[blc_offset_reg[3:0] , 1'b0] - - - blc11_ofst =[blc_offset_reg[7:4] , 1'b0] - - - - - High limit of black level pixel - blcofst - - - - - y_cent=[3:0]+240 - - - x_cent=[7:4]+320 - - - - - CNR - - - CNR - - - 1: 0: - - - edge monitor - - - 3d0: never skip 3d1: skip 2/8 skin point - 3d2: skip 3/8 skin point 3d3: skip 4/8 skin point - 3d4: skip 5/8 skin point 3d5: skip 6/8 skin point - 3d6: skip 7/8 skin point 3d7: skip 8/8 skin point - - - - - - - - cnr_thr_v = [cnr_thr[2:0], 2'd3] - - - enable - - - cnr_thr_h = [cnr_thr[6:4], 2'd3] - - - enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~awb_mon_sel? blc_out0_reg : kukl_sel ? kl : awb_mon_out[7:0] - - - - - ~awb_mon_sel? blc_out1_reg : kukl_sel ? ku : awb_mon_out[15:8] - Note: awb_mon_sel = reg1[2] Kukl_sel = reg5F[0] - - - - - dpc on - - - 1: median 0:adp_median - sel=(nexp[3:0]>dpc_ctrl0[3:2])? 1 : dpc_ctrl0[1] - This adp_med is used in int_dif_data and nrf_data_out - - - - - - not used here - - - 1:gausian filter 0:median filter - - - bayer nr on - - - cc on - - - - - 00: always not meet - 01: all round point must meet - 10: can be one except point - 11: can be two except point - - - 00: can be three sign diff with other - 01: can be two sign diff with other - 10: can be one sign diff with other - 11: 8 same sign - - - 1: gausian filter 0:median filter - - - - - Y_thr @ - - - - - Y_thr @mid - - - - - Y_thr @ - - - - - cfa_v_thr[2:0] - - - not used here - - - cfa_h_thr[2:0] - - - not used here - - - - - - - - - - - - - - - - - 0: inc 1:dec - - - - - - - - - - - - - - - - - - - - - - - - nexp=low_th @bnr/dpc/int_dif/sharp/cnr - - - not used here - - - nexp>(8+high_th) @bnr/dpc/int_dif/sharp/cnr - - - - - bnr low frequency str @Low gain @ - (ff) - - - - - bnr high frequency str @Low gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @Low gain - HF - - - - - bnr low frequency str @Mid gain - (ff) - - - - - bnr high frequency str @Mid gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @Mid gain - HF - - - - - bnr low frequency str @high gain @ - (ff) - - - - - bnr high frequency str @high gain - (ff) - - - - - 4.4 format, 16x ~ 1/16x @high gain - HF - - - - - - - - - - - - - - - - - - - - 0: 9 1:7 - 2: 5 3:3 - 4: median 5: adp_median - - - - - cfa_h_thr=[intp_cfa_h_thr[7:0], intp_cfa_hv[6:4]] - - - - - cfa_v_thr=[intp_cfa_v_thr[7:0], intp_cfa_hv[2:0]] - - - - - - - - - - gf_lmt_thr=[3d0, intp_gf_lmt_thr_reg] - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S1.6 format, x1=64, cc00+cc01+cc02=1 - - - - - - - - - - S1.6 format, x1=64, cc10+cc11+cc12=1 - - - - - - - - - - S1.6 format, x1=64, cc20+cc21+cc22=1 - - - - - - - - - - S7 format, after cc - - - - - S7 format, after cc - - - - - S7 format, after cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S7 format, before cc - - - - - S1.6 format, x1=64, cc00+cc01+cc02=1 - - - - - - - - - - S1.6 format, x1=64, cc10+cc11+cc12=1 - - - - - - - - - - S1.6 format, x1=64, cc20+cc21+cc22=1 - - - - - - - - - - sharp data - - - db/da/d9 - - - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - 0: delay_df - 1: delay_de - 2: delay_dd - 3: delay_dc - - - 1:ppdif_sum - 0:pp_dif (8) - - - - - - - - plus @Low gain (2.6 format)@ - - - - - Sharp@Low gain - (edge) - - - - - plus @Mid gain (2.6 format) - - - - - Sharp@Mid gain - (edge) - - - - - plus @high gain (2.6 format)@ - - - - - Sharp@high gain - (edge) - - - - - - - - (Ey) - 2d0:Ey_H/V/D1/D2 - 2d1: - 2d2: - 2d3: - - - - - - (sharpness) - 00: - if(i_y_data8'ha0) sharp_data = sharp_out[6:2]; - else if(i_y_data8'h80) sharp_data = sharp_out[6:1]; - else sharp_data = sharp_out[6:0]; - 01: 0x80pixelsharpness - 10: 0x90pixelsharpness - 11: No change - - - AEYin - 00:y=yuv_y - 01:y=y_gamma // after ygamma - 10:y=luma_y_out // after y_luma - 11:y=contr_y_out // after y_contr - - - - - GMYc - - - - - @low gain - GMYc128Ey - - - - - @low gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @low gain - HF - - - - - @Mid gain - GMYc128Ey - - - - - @Mid gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @Mid gain - HF - - - - - @high gain - GMYc128Ey - - - - - @high gain - GMYc128Ey - - - - - 4.4 format, 16x ~ 1/16x @high gain - HF - - - - - sinx[7:0]=256*sin(x*pi/180) - - - - - cosx[7:0]=256*cos(x*pi/180) - cosx[7] fixed as 1, As abs(x) = pi/4 - - - 1: sinx is negative - 0: sinx is positive - - - - - CNR@Mid gain - - - - - - - - - - - - - - CNR@Low gain - - - CNR@High gain - - - - - Center point smaller than around, black point - - - - - Center point bigger than around, white point - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - E00 - - - - - E00 - - - E00 max is 3Line - - - - - E01 - - - - - E01 - - - E01 max is 7Line - - - - - E02max is 7F - - - - - E02 - - - E02 max is 15Line - - - - - E1 (64) - - - - - E1 (1E) - - - - - E2 (64) - - - - - E2 (2E) - - - - - E3 (64) - - - - - E3 (3E) - - - - - E4 (64) - - - - - E4 (4E) - - - - - E5 (64) - - - - - E5 (5E) - - - - - E6 (64) - - - - - E6 (6E) - - - - - E7 (64) - - - - - E7 (7E) - - - - - E8 (64) - - - - - E8 (8E) - - - - - E9 (64) - - - - - E9 (9E) - - - - - Ea (64) - - - - - Ea (aE) - - - - - Eb (64) - - - - - Eb (bE) - - - - - Ec (64) - - - - - Ec (cE) - - - - - Ed (64) - - - - - Ed (dE) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Y_thr7 (for 2 dead point) @ - - - - - Y_thr7 (for 2 dead point) @ mid - - - - - Y_thr7 (for 2 dead point) @ - - - - - 0: check one black dead point - 1: don't check one black dead point - - - 0: check 2 black dead point - 1: don't check 2 black dead point - - - 0: don't check 2 dead point - 1: check 2 dead point - - - - - (Note) - 0: check one black dead point - 1: don't check one black dead point - - - (Note) - 0: check 2 black dead point - 1: don't check 2 black dead point - - - (Note) - 0: don't check 2 dead point - 1: check 2 dead point - - - not used here - - - - - 2E 12 - - - 3E 12 - - - 4E 12 - - - 5E 12 - - - 6E 12 - - - 7E 12 - - - 8E 12 - - - 9E 12 - - - - - awb_win_height = [[7:0],1'd0] - //4:3 and keep height as even number - - - - - - - - - - - - - - - - - - - - - - - - - blue: 0x72 red: 0xD4 brown:0xAB - - - - - blue: 0xD4 red: 0x64 brown:0x60 - - - - - - - - - - 0x20~ff (x1~8) () - - - - - - - - - - 0x20~ff (x1~8) () - - - - - If bhist>bhist_too_big_thr, then bhist_too_big - - - - - If bhist>bhist_big_thr, then bhist_big - - - - - Y level of bhist and 4pbhist - - - - - outdoor_th=[outdoor_th_reg[3:0], 4'd0] - - - non_outdoor_th=[outdoor_th_reg[7:4], 4'd0] - - - - - Low limit of rgain = [[7:2], 2d0] - - - - - High limit of rgain = [[7:2], 2d0] - - - - - Low limit of bgain = [[7:2], 2d0] - - - - - High limit of bgain = [[7:2], 2d0] - - - - - awb_win_y_start = [[3:0], 2'd0]; - - - awb_win_x_start = [[7:4], 2'd0]; - - - - - awb_win_width =[[7:0],2'd0]; - //4:3 and keep height as even number - - - - - Y level of dark_hist - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for skin - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - for mono color - - - - - 0yave 1yave - 2yave 3yave - - - 0yave 1yave - 2yave 3yave - - - 0: win yave 1: ywave - - - - - - - - - - - - - - ae ywave - - - ae ywave - - - - - QVGA 240x320 :8d60 QVGA 320x240: 8d80 - CIF 352x288: 8d88 VGA 640x480: 8d160 - - - - - QVGA 240x320 :8d80 QVGA 320x240: 8d60 - CIF 352x288: 8d72 VGA 640x480: 8d120 - - - 0: x1(CIFx1) 1:x1.5 - - - - - yave pcnt_sta=[[3:0], 1b0] - - - yave lcnt_sta=[[7:4], 1b0] - - - - - yave Width=[[7:0], 2d0] - QVGA 240x320 :10d216 QVGA 320x240: 10d304 - CIF 352x288: 10d304 VGA 640x480: 10d596 - - - - - yave Height=[[7:0], 1d0] - QVGA 240x320 :10d304 QVGA 320x240: 10d216 - CIF 352x288: 10d216 VGA 640x480: 10d440 - - - - - - - - - - - - - - not used here - - - 3'd0: is_outdoor = 0; - 3'd1: is_outdoor = 1; - 3'd2: - if(ana_gain==0) begin - if(expoutdoor_th) is_outdoor = 1; - else if(expnon_outdoor_th) is_outdoor = 0; end - else is_outdoor = 0; - 3'd3: - if(ana_gain==0 and rgain_bigger) begin - if(expoutdoor_th) is_outdoor = 1; - else if(expnon_outdoor_th) is_outdoor = 0; end - else is_outdoor = 0; - default: - if(vsync_rp_d and sw_update_en) is_outdoor = is_outdoor_sw; - - - 1: when is_outdoor=1, only detect white point at D65 and Indoor CTD block - 0: dont care is_outdoor, detect white point at all ctd block - - - - - - - - - - awb_stop_cr_pos_level =[[3],awb_stop_reg[7:6]]; - awb_stop_cr_neg_level =[[2],awb_stop_reg[5:4]]; - awb_stop_cb_pos_level =[[1],awb_stop_reg[3:2]]; - awb_stop_cb_neg_level =[[0],awb_stop_reg[1:0]]; - - - awb_adj_again = [2'b11, [5:4]] - - - 1: add awb_algo_thr condition to detect white point@A - 0: detect white point according to A ctd block - - - - - - - - 0: normal(no scale) - 1: sub(yuv sub mode) - 2: sca_320x240(1/2) - 3: sca_176x144(1/3) - 4: sca_160x120(1/4) - 5: sca352x288(2/3) - 6: sca352x288(3/5) - 7: 3/4 - - - - - Ee (64) - - - - - Ee (eE) - - - - - Ef (64) - - - - - Ef (fE) - - - - - ae_thr_big = [reg1CA[3:0],2d0]@dark - - - ae_thr_big = [reg1CA[7:4],2d0]@bright - - - - - sharp gain @low gain(2.6 format) - - - - - sharp gain @medium gain(2.6 format) - - - - - sharp gain @high gain(2.6 format) - - - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) - - - - - - - - - - Y = Y_min ( AWB) - - - - - - - - - - - - - - - - - - - - - - - - - Y level of vbright_hist - - - - - Y level of vdark_hist - - - - - - - - - - adi low bits version. - - - adi high bits version,read only. - - - - - addr mode for access. "00" word mode,means addr[x:2],"01" half word,means addr[x:1], "1x" byte mode, means addr[x:0]. - - - configure write bit flag. - - - addr bit number configure, "00" address is 12 bits, "01" address is 10 bits, "10" address is 15 bits. - - - "1" write uses command mode, in this mode, must first configure channel addr, then data. - - - - - write channel 0 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 1 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 2 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 3 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 4 priority. 0 has lowest priority, 4 has highest priority. - - - read channel 5 priority. 0 has lowest priority, 4 has highest priority. - - - - - - "1" write command fifo enable. - - - fifo overfolow interrupt mask. - - - - - fifo overfolow interrupt without mask status. - - - - - fifo overfolow interrupt with mask status. - - - - - fifo overfolow interrupt clear. - - - - - total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len. - - - total adi cmd length = rf_gssi_addr_len + read/write flag. - - - total adi data length . - - - write bit position in frame stream . - - - "1" write means 1, "0" write means 0. - - - "1" hardware auto generate sync, "0" software generates sync. - - - "1" sync is pulse, "0" sync is level. - - - "1" software generates sync. - - - "1" invert output sck. - - - output oen : "1" oen add dummy cycle, "0" oen not add dummy cycle. - - - reserved. - - - "1" output dummy_clock, "0" gate dummy clock. - - - "1" rx sample delay 1 adi clk cycle, "0" delay 0 adi clk cycle. - - - "1" sck always on, "0" audo gate clock. - - - "1" write bit disable, "0" write bit enable. - - - - - "1" tx data at negedge of sck."0" tx data at posedge of sck. - - - "1" rx data at negedge of sck."0" rx data at posedge of sck. - - - F_sck = F_clk/(2*(rf_gssi_clk_div+1)) - - - sync before data transfer - - - sync end data transfer - - - extral dummy sck - - - extral dummy sck - - - start sequence condition, only used in RFFE - - - master turn around to salve length , only used in RFFE - - - slave turn around to master length , only used in RFFE - - - "1" 2 wires enable - - - - - configure read address and start a read operation. - - - - - read data from analog die. - - - read address map to arm_red_cmd[16:2]. - - - 1 means has not been read back. - - - - - "1" write channel is busy - - - "1" read channel is busy - - - "1" adi operation is busy - - - wfifo full status - - - wfifo empty status - - - wfifo fill data number - - - adi fsm status - - - event 0 wr status - - - event 1 wr status - - - event 2 wr status - - - event 3 wr status - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - the address map to the PMIC chip space, just for write operation - - - - - the dat to the PMIC chip space, just for write operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - freq/26*2^25 768Mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 800Mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1: clk_datarx -0: inv of clk_datarx - - - 1: enable rst intepolator by squelch -0: disable rst by squelch - - - default: 1'h0 - - - tx clk samle data phase - - - set cdr gain - - - - - internal bias current - - - internal bias voltage - - - squelch threshold voltage - - - disconnect threshold voltage - - - hi-speed differential signal voltage - - - - - if charged(1: squelch threshold voltage is reduced;0 hold) - - - 1: differential signal -0: single-end signal - - - 1: differential signal - 0: single-end signal - - - 1: internal reference voltage - 0: bandgap voltage - - - 1: enable otg - 0: disable otg - - - 1: set vbusvld to 1'h1; 0: not set - - - if pwr_on=01:pullup and pulldown circuit power on;0 off) - - - 1:pullup and pulldown circuit power always on -0:power is controled by pu_usb_dev - - - 1:enable disconnect dectector circuit -0:dsiable - - - 1:enable 1.8V voltage -0:dsiable - - - 1:enable 1.2V voltage -0:dsiable - - - 1:enable current generator circuit -0:disable - - - 1:enable hi-speed rx -0 disable - - - 1:enable hi-speed tx -0 disable - - - 1:enable full/low-speed tx -0 disable - - - - - enable charger ac detect - - - 1: loopback data to tx -0: hi-speed data to tx - - - enable loopback; - - - loopback data RW - - - - - 1:enable lptx bias -0: disable lptx bias(should lead power up of avdd3v3) - - - hi-speed term res - - - full/low-speed tx driver strength; - - - - - internal regulator's voltage bit,default:4'h1000 - - - internal regulator rout bit - - - loop filter R2 bit - - - loop filter c2 bit - - - loop filter r2 bit - - - - - pll_presc mode selectdefault:1'h0 - - - reference frequency select - - - PLL TEST mode enable - - - output clk select: -0 VCO -1 sdm_clk - - - force VCO run at highest frequency - - - force VCO run at lowest frequency - - - enable 960MHz clk output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - loopback test output - - - pll lock signal - - - pll lock signal to UTMI - - - - - reserved for USB - - - - - - - - - - - - - - - - - - - - - 960Mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - freq/26*2^25 1000Mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 dedicated enable for 2 DL HSSBs, bit0-lane0, bit1-lane1 - - - - - 2 dedicated enable for 2 UL HSSBs, bit0-lane0, bit1-lane1 - - - - - DL FIFO reset and clear - - - - - UL FIFO reset and clear - - - - - SYNC WORD for lvds dest - - - - - SYNC WORD for lvds src - - - - - bit reverse enable - - - - - - bit offset index used in byte training stage for lane0 - - - - - bit offset index used in byte training stage for lane1 - - - - - - Byte Training Done from SW - - - - - Bit Training Done from SW - - - - - data ready from DFE for ulfifo to lvds - - - - - Payload max length for timeout check, 0-disabled - - - - - Sync max length for timeout check, 0-disabled - - - - - LVDS tx fixed pattern instead of data from ulfifo - - - - - LVDS tx fixed pattern0[31:0] - - - - - LVDS tx fixed pattern1[31:0] - - - - - - [1]: 0-2 cycles per word , 1-1cycle per word for LVDS_TX -[0]: 0-2 cycles per word , 1-1cycle per word for LVDS_RX - - - - - 0-mode0, 1-mode1, 2-mode2, 3-mode3 for tx - - - 0-mode0, 1-mode1, 2-mode2, 3-mode3 for rx - - - number of cycles to read from Fifo under MT mode for both tx - - - number of cycles to read from Fifo under MT mode for both rx - - - [3]: 0- Non-MT mode, 1-MT enable for rx -[2]: 0- Non-MT mode, 1-MT enable for tx - - - [1]: 0-1x clock, 1-2x clock for rx -[0]: 0-1x clock, 1-2x clock for tx - - - - - bit training Done for lvds tx - - - - - byte training Done for lvds tx - - - - - report bit or byte training results word0 for lane0 - - - - - report bit or byte training results word1 for lane0 - - - - - report bit or byte training results word0 for lane1 - - - - - report bit or byte training results word1 for lane1 - - - - - dest_lane1_fstate - - - dest_lane0_fstate - - - dest_lane1_state - - - dest_lane1_mstate - - - dest_lane0_state - - - dest_lane0_mstate - - - src_lane1_state - - - src_lane1_mstate - - - src_lane0_state - - - src_lane0_mstate - - - - - - reserved register for lvds bb -[15]: for RX, 1-use SW configure Sync index enable, 0-use HW anto sync detection -[14]: for TX, 1-use SW configure Sync index enable, 0-use HW anto sync detection -[13]: for RX, 1-use LFSR for BIST , 0-use normal data for RX -[12]: for TX, 1-use LFSR for BIST , 0-use normal data for TX - - - - - configure register for lvds used by IQMUX: -[15:12]: reserved -[11]: software reset for LVDS digital TX -[10]: software reset for LVDS digital RX -[9]: software reset for LVDS analog TX -[8]: software reset for LVDS analog RX -[7:3]: reserved -[2]: clock gating enable for MT clock divided from mt2lvds@61.44MHz clock. -[1]: clock gating enable to LVDS digital rx related clocks -[0]: clock gating enable to LVDS digital tx related clocks - - - - - - Latch trigger for capturing 8 lvds received Bytes - - - - - header to be received or transmitted for LVDS - - - number of header to be received or transmitted for LVDS - - - - - mstate and fstate machine rerport for lvds_rx debug purpose - - - - - mstate and state machine rerport for lvds_tx debug purpose - - - - - 16 bit counter for LVDS_RX PLL stable time wait - - - - - 16 bit counter for LVDS_TX PLL stable time wait - - - - - raw interrupt status, write 1 to clear - - - interrupt status after masked raw interrupt status - - - - - write 1 to clear interrupt - - - raw interrupt source select - - - raw interrupt mask for latch done - - - - - number of errors for lvds lane0 bist enabled period - - - 1: bist fail for lane0, 0: bist pass for lane0 - - - - - number of errors for lvds lane1 bist enabled period - - - 1: bist fail for lane1, 0: bist pass for lane0 - - - - - - reset for LVDS RX path, active low - - - soft reset for LVDS TX path, active low - - - - - reg for PLL divisor -lvds_clk_band=3'b0001 with pll_din=7'h08 -lvds_clk_band=3'b0010 with pll_din=7'h10 -lvds_clk_band=3'b0100 with pll_din=7'h20 -lvds_clk_band=3'b1000 with pll_din=7'h40 - - - - - 1st phase coarse tuning between TX_DATA and TX_CLOCK - - - - - input P and N switch - - - - - phase fine tuning between RX_DATA and RX_CLOCK - - - - - - phase coarse tuning between RX_DATA and RX_CLOCK - - - - - RX BUFFER enable - - - - - RX BUFFER select - - - - - phase fine tuning between TX_DATA and TX_CLOCK - - - - - 2nd phase coarse tuning between TX_DATA and TX_CLOCK - - - - - LVDS DRIVER tri-state enable - - - - - LVDS DRIVER strength adjust - - - - - LVDS DRIVER output common mode voltage adjust - - - - - LVDS DRIVER output difference mode voltage adjust - - - - - LVDS reserved register -[2:0]:pll_rx_clk_ref_dig -[4]:pll_rx_clk_ref_dig_enable -[20:18]:pll_rx_clk_ref_xtal -[17]:pll_rx_clk_ref_xtal_enable - - - - - enable for PLL reference clock being input clock divided by 2 - - - - - PLL output clock enable - - - - - - set with lvds_clk_band - - - - - PLL divisor decimal part,fixed to 0 - - - - - PLL refmulit2 enable - - - - - - PLL Regulator voltage adjust - - - - - PLL power up - - - - - PLL lock status -0:unlock -1:lock - - - - - PLL 1st reserved register - - - - - PLL 2nd reserved register - - - - - - - - - LVDS tx fixed pattern0[31:0] - - - - - LVDS tx fixed pattern1[31:0] - - - - - LVDS2DFE latch reg0 - - - - - LVDS2DFE latch reg1 - - - - - top bist en - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Internal Bootrom Space - - - - - Internal SRam Space - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Number of Watchpoint Register Pairs: -For the Cortex-A5 processor, this field reads as b0001 to indicate two WRPs are -implemented. - - - Number of Breakpoint Register Pairs: -For the Cortex-A5 processor, this field reads as b0010 to indicate three BRPs are -implemented. - - - Number of Breakpoint Register Pairs with context ID comparison capability: -For the Cortex-A5 processor, this field reads as b0000 to indicate one BRP has context ID -capability. - - - Debug architecture version: -b0011 = ARMv7 Debug with Extended CP14 interface implemented. - - - For the Cortex-A5 processor, this field reads as b1 to indicate that the Debug Device ID -Register, DBGDEVID is implemented - - - For the Cortex-A5 processor, this field reads as b1 to indicate that Secure User halting debug -is not supported - - - Program Counter Sample Register, DBGPCSR. -For the Cortex-A5 processor, this field reads as b1 to indicate that DBGPCSR is -implemented as debug register 33. - - - Security extensions bit: -For the Cortex-A5 processor, this field reads as b1 to indicate that the debug security -extensions are implemented. - - - Implementation-defined variant number. This number is incremented on functional changes. -The value matches bits [23:20] of the ID Code Register in CP15 c0. - - - Implementation-defined revision number. This number is incremented on bug fixes. The -value matches bits [3:0] of the ID Code Register in CP15 c0. - - - - - The DBGDTRRX Register full flag: -0 = DBGDTRRX empty, reset value -1 = DBGDTRRX full. -When set, this flag indicates that there is data available in the Receive Data Transfer Register, -DBGDTRRX. It is automatically set on writes to the DBGDTRRXext by the debugger, and is cleared -when the processor reads the CP14 DBGDTRRXint. If the flag is not set, reads of the DBGDTRRX return -an Unpredictable value. - - - The DBGDTRTX Register full flag: -0 = DBGDTRTX empty, reset value -1 = DBGDTRTX full. -When clear, this flag indicates that the Transmit Data Transfer Register, DBGDTRTX is ready for data -write. It is automatically cleared on reads of the DBGDTRTXext by the debugger, and is set when the -processor writes to the CP14 DBGDTRTXint. If this bit is set and the processor attempts to write to the -DBGDTRTXint, results are Unpredictable. - - - The latched DBGDTRRX Register full flag. This flag is read in one of the following ways: -? in DBGDSCRint using a CP14 instruction -? in DBGDSCRext using the APB interface or CP14 instruction. -Reads of DBGDSCRint return an Unpredictable value for this bit. -Reads of DBGDSCRext return the same value as RXfull. -If a write to the DBGDTRRXext address succeeds, RXfull_l is set to 1. - - - The latched DBGDTRTX Register full flag. This flag is read in one of the following ways: -? in DBGDSCRint using a CP14 instruction -? in DBGDSCRext using the APB interface or CP14 instruction. -Reads of DBGDSCRint return an Unpredictable value for this bit. -Reads of DBGDSCRext return the same value as TXfull. -If a read to the DBGDTRTXext address succeeds, TXfull_l is cleared. - - - Sticky pipeline advance bit. This bit enables the debugger to detect whether the processor is idle. In some -situations, this might mean that the system bus port is deadlocked. This bit is set to 1 every time the -processor pipeline retires one instruction. A write to DBGDRCR[3] clears this bit. See Debug Run Control -Register on page 9-19. -0 = no instruction has completed execution since the last time this bit was cleared, reset value -1 = an instruction has completed execution since the last time this bit was cleared. - - - The latched InstrCompl flag. This flag is read in one of the following ways: -? in DBGDSCRint using CP14 instructions -? in DBGDSCRext using the APB interface. -When in Non-debug state, all reads of DBGDSCR return an Unpredictable value for this bit. Otherwise, -reads through the CP14 interface return an Unpredictable value for this bit. -Reads of the DBGDSCRext APB address return the same value as InstrCompl. -If a write to the DBGITR APB address succeeds while in Stall or Nonblocking mode, InstrCompl_l and -InstrCompl are cleared. -If a write to the DBGDTRRXext APB address or a read to the DBGDTRTXext APB address succeeds -while in Fast mode, InstrCompl_l and InstrCompl are cleared. -InstrCompl is the instruction complete bit. This internal flag determines whether the processor has -completed execution of an instruction issued through the APB interface. -0 = the processor is currently executing an instruction fetched from the DBGITR Register, reset value -1 = the processor is not currently executing an instruction fetched from the DBGITR Register. - - - External DCC access mode. This is a read and write field. You can use this field to optimize DTR and -DBGITR traffic between a debugger and the processor: -b00 = Nonblocking mode, reset value -b01 = Stall mode -b10 = Fast mode -b11 = reserved. -Note -? This field only affects the behavior of DBGDSCR, DTR, and DBGITR accesses through the APB -port, and not through CP14 debug instructions. -? Nonblocking mode is the default setting. Improper use of the other modes might result in the debug -access bus becoming jammed. -See External DCC and DBGITR access mode on page 9-17 for more information. - - - Discard asynchronous abort. This read-only bit is set while the processor is in debug state and is cleared -on exit from debug state. While this bit is set, the processor does not record asynchronous Data Aborts. -However, the sticky asynchronous Data Abort bit is set to 1. -0 = asynchronous Data Aborts not discarded, reset value -1 = asynchronous Data Aborts discarded. - - - Non-secure state status bit: -0 = the processor is in Secure state or the processor is in Monitor mode -1 = the processor is in Non-secure state and is not in Monitor mode. - - - Secure privileged noninvasive debug disabled: -0 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is HIGH -1 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is LOW. -This value is the inverse of bit [6] of the Authentication Status Register. See Authentication Status Register -on page 9-33. - - - Secure privileged invasive debug disabled: -0 = (DBGEN && SPIDEN) is HIGH -1 = (DBGEN && SPIDEN) is LOW. -This value is the inverse of bit [4] of the Authentication Status Register. See Authentication Status Register -on page 9-33. - - - The Monitor debug-mode enable bit. This is a read and write bit. -0 = Monitor debug-mode disabled, reset value -1 = Monitor debug-mode enabled. -If Halting debug-mode is enabled, bit [14] is set, then the processor is in Halting debug-mode regardless -of the value of bit [15]. If the external interface input DBGEN is LOW, DBGDSCR[15] reads as 0. If -DBGEN is HIGH, then the read value reverts to the programmed value. - - - The Halting debug-mode enable bit. This is a read and write bit. -0 = Halting debug-mode disabled, reset value -1 = Halting debug-mode enabled. -If the external interface input DBGEN is LOW, DBGDSCR[14] reads as 0. If DBGEN is HIGH, then the -read value reverts to the programmed value. - - - Execute ARM instruction enable bit. This is a read and write bit. -0 = disabled, reset value -1 = enabled. -If this bit is set and a DBGITR write succeeds, the processor fetches an instruction from the DBGITR for -execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is -Unpredictable. - - - CP14 debug user access disable control bit. This is a read and write bit. -0 = CP14 debug user access enable, reset value -1 = CP14 debug user access disable. -If this bit is set and a User mode process tries to access any CP14 debug registers, the Undefined -instruction exception is taken. - - - Interrupts disable bit. This is a read and write bit. -0 = interrupts enabled, reset value -1 = interrupts disabled. -If this bit is set, the IRQ and FIQ input signals are disabled. The external debugger can set this bit before -it executes code in normal state as part of the debugging process. If this bit is set to 1, an interrupt does -not take control of the program flow. For example, the debugger might use this bit to execute an OS service -routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the -routine execution. -This bit is ignored when either: -? DBGDSCR[15:14] == 0b00 -? DBGEN is LOW. - - - Debug Acknowledge bit. This is a read and write bit. If this bit is set to 1, both the DBGACK and -DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The external debugger -can use this bit if it wants the system to behave as if the processor is in debug state. Some systems rely on -DBGACK to determine whether the application or debugger generates the data accesses. The reset value -is 0. - - - Sticky Undefined bit: -0 = No Undefined instruction exception occurred in debug state since the last time this bit was cleared. -This is the reset value. -1 = An Undefined instruction exception has occurred while in debug state since the last time this bit was -cleared. -This flag detects Undefined instruction exceptions generated by instructions issued to the processor -through the DBGITR. This bit is set to 1 when an Undefined instruction exception occurs while the -processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register -on page 9-19. - - - Sticky asynchronous Data Abort bit: -0 = no asynchronous Aborts occurred since the last time this bit was cleared, reset value -1 = an asynchronous Abort occurred since the last time this bit was cleared. -This flag detects asynchronous Aborts triggered by instructions issued to the processor through the -DBGITR. This bit is set to 1 when an asynchronous Abort occurs while the processor is in debug state. -Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19. - - - Sticky synchronous Data Abort bit: -0 = no synchronous Data Abort occurred since the last time this bit was cleared, reset value -1 = a synchronous Data Abort occurred since the last time this bit was cleared. -This flag detects synchronous Data Aborts generated by instructions issued to the processor through the -DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state. -Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19. -When this is set, no instructions are issued through the DBGITR. Writes to DBGITR are ignored and, if -ExtDCCmode is configured for Fast mode, reads of DBGDTRTXext and writes of DBGDTRRXext are -ignored. - - - MOE, Method of entry bits. This is a read and write field. -b0000 = a DRCR[0] halting debug event occurred, reset value -b0001 = a breakpoint occurred -b0010 = not supported -b0011 = a BKPT instruction occurred -b0100 = an EDBGRQ halting debug event occurred -b0101 = a vector catch debug event occurred -b1010 = a synchronous watchpoint debug event occurred -other = reserved. -These bits are set to indicate any of: -? the cause of a debug exception -? the cause for entering debug state. -A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to -determine whether a debug exception occurred and then use these bits to determine the specific debug -event. - - - Core restarted bit: -0 = The processor is exiting debug state. -1 = The processor has exited debug state. This is the reset value. -The debugger can poll this bit to determine when the processor responds to a request to leave debug state - - - Core halted bit: -0 = The processor is in normal state. This is the reset value. -1 = The processor is in debug state. -The debugger can poll this bit to determine when the processor has entered debug state. - - - - - - DBGVCR - - - - - - dtrrx - - - - - old location of PCSR - - - - - - dtrrx - - - - - Cancel BIU request - - - Clear sticky pipeline advance. Writing a 1 to this bit clears DBGDSCR[25]. - - - Clear sticky exceptions. Writing a 1 to this bit clears DBGDSCR[8:6]. - - - Restart request. Writing a 1 to this bit requests that the processor leaves debug state. This request -is held until the processor exits debug state. When the debugger makes this request, it polls -DBGDSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor -is not in debug state. - - - Halt request. Writing a 1 to this bit triggers a halting debug event, that is, a request that the -processor enters debug state. This request is held until the debug state entry occurs. When the -debugger makes this request, it polls DBGDSCR[0] until it reads 1. This bit always reads as zero. -Writes are ignored when the processor is already in debug state. - - - - - - The sampled value of bits [31:2] of the Program Counter - - - Meaning of Program Counter Sample value: -b00 = References an ARM state instruction. -bx1 = References a Thumb or ThumbEE state instruction. -b10 = Jazelle-DBX. - - - - - context ID - - - - - - Breakpoint value. The reset value is Unpredictable -Contains the breakpoint value that corresponds to either an instruction -address or a context ID. Breakpoints can be set on: -? an instruction address -? a context ID value -? an instruction address and context ID pair. -For an instruction address and context ID pair, two BRPs must be linked. -A debug event is generated when both the instruction address and the -context ID pair match at the same time. -Note -? Only BRP2 supports context ID comparison. -? DBGBVR0[1:0] and DBGBVR1[1:0] are SBZP on writes and RAZ on reads because -these registers do not support context ID comparisons. -? The context ID value for DBGBVR2 to match with is given by the contents of the CP15 -Context ID Register. See Chapter 4 System Control for information on the Context ID -Register. - - - - - Breakpoint value. The reset value is Unpredictable - - - - - Breakpoint value. The reset value is Unpredictable - - - - - - Breakpoint address mask. -RAZ/WI -b00000 = no mask - - - Meaning of DBGBVR: -b000 = instruction virtual address match -b001 = linked instruction virtual address match -b010 = unlinked context ID -b011 = linked context ID -b100 = instruction virtual address mismatch -b101 = linked instruction virtual address mismatch -b11x = reserved. -Note -DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID -comparison capability. - - - Linked BRP number. The binary number encoded here indicates another BRP to link this one with. -Note -? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated -? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is -Unpredictable whether a breakpoint debug event is generated. - - - Secure state access control. This field enables the breakpoint to be conditional on the security state of the -processor. -b00 = breakpoint matches in both Secure and Non-secure state -b01 = breakpoint only matches in Non-secure state -b10 = breakpoint only matches in Secure state -b11 = reserved. - - - Byte address select. For breakpoints programmed to match an instruction address, you must write a -word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits -only if you access certain byte addresses. -If you program the BRP for instruction address match: -b0000 = the breakpoint never hits -b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed -b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is -accessed -b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed. -If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding -instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction -address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. -If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint -and watchpoint debug events might not be generated as expected. - - - Supervisor access control. The breakpoint can be conditioned on the mode of the processor. -b00 = User, System, or Supervisor -b01 = privileged -b10 = User -b11 = any. - - - Breakpoint enable: -0 = breakpoint disabled, reset value -1 = breakpoint enabled. - - - - - Breakpoint address mask. -RAZ/WI -b00000 = no mask - - - Meaning of DBGBVR: -b000 = instruction virtual address match -b001 = linked instruction virtual address match -b010 = unlinked context ID -b011 = linked context ID -b100 = instruction virtual address mismatch -b101 = linked instruction virtual address mismatch -b11x = reserved. -Note -DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID -comparison capability. - - - Linked BRP number. The binary number encoded here indicates another BRP to link this one with. -Note -? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated -? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is -Unpredictable whether a breakpoint debug event is generated. - - - Secure state access control. This field enables the breakpoint to be conditional on the security state of the -processor. -b00 = breakpoint matches in both Secure and Non-secure state -b01 = breakpoint only matches in Non-secure state -b10 = breakpoint only matches in Secure state -b11 = reserved. - - - Byte address select. For breakpoints programmed to match an instruction address, you must write a -word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits -only if you access certain byte addresses. -If you program the BRP for instruction address match: -b0000 = the breakpoint never hits -b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed -b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is -accessed -b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed. -If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding -instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction -address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. -If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint -and watchpoint debug events might not be generated as expected. - - - Supervisor access control. The breakpoint can be conditioned on the mode of the processor. -b00 = User, System, or Supervisor -b01 = privileged -b10 = User -b11 = any. - - - Breakpoint enable: -0 = breakpoint disabled, reset value -1 = breakpoint enabled. - - - - - Breakpoint address mask. -RAZ/WI -b00000 = no mask - - - Meaning of DBGBVR: -b000 = instruction virtual address match -b001 = linked instruction virtual address match -b010 = unlinked context ID -b011 = linked context ID -b100 = instruction virtual address mismatch -b101 = linked instruction virtual address mismatch -b11x = reserved. -Note -DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID -comparison capability. - - - Linked BRP number. The binary number encoded here indicates another BRP to link this one with. -Note -? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated -? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is -Unpredictable whether a breakpoint debug event is generated. - - - Secure state access control. This field enables the breakpoint to be conditional on the security state of the -processor. -b00 = breakpoint matches in both Secure and Non-secure state -b01 = breakpoint only matches in Non-secure state -b10 = breakpoint only matches in Secure state -b11 = reserved. - - - Byte address select. For breakpoints programmed to match an instruction address, you must write a -word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits -only if you access certain byte addresses. -If you program the BRP for instruction address match: -b0000 = the breakpoint never hits -b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed -b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is -accessed -b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is -accessed. -If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding -instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction -address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. -If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint -and watchpoint debug events might not be generated as expected. - - - Supervisor access control. The breakpoint can be conditioned on the mode of the processor. -b00 = User, System, or Supervisor -b01 = privileged -b10 = User -b11 = any. - - - Breakpoint enable: -0 = breakpoint disabled, reset value -1 = breakpoint enabled. - - - - - - Watchpoint address - - - - - Watchpoint address - - - - - Watchpoint address - - - - - - This field watches a range of addresses by masking lower order address bits out of the watchpoint -comparison: -b00000 = no mask -b00001 = reserved -b00010 = reserved -b00011 = 0x00000007 mask for data address -b00100 = 0x0000000F mask for data address -b00101 = 0x0000001F mask for data address -. -. -. -b11111 = 0x7FFFFFFF mask for data address. -Note -? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is -Unpredictable. -? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the -comparison SBZ. Otherwise the behavior is Unpredictable. -To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a -debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 -debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those -that have a 4-bit byte address select field (bits [8:5]). - - - Enable linking bit: -0 = linking disabled -1 = linking enabled. -When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP -field. - - - Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP -with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is -Unpredictable whether a watchpoint debug event is generated. - - - Secure state access control. This field enables the watchpoint to be conditioned on the security state of the -processor. -b00 = watchpoint matches in both Secure and Non-secure state -b01 = watchpoint only matches in Non-secure state -b10 = watchpoint only matches in Secure state -b11 = reserved - - - Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to -program the watchpoint so it only hits if certain byte addresses are accessed. - - - Load/store access. The watchpoint can be conditioned to the type of access being done. -b00 = reserved -b01 = load, load exclusive, or swap -b10 = store, store exclusive or swap -b11 = either. -SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint -on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local -monitor within the processor. - - - Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: -b00 = reserved -b01 = privileged, match if the processor does a privileged access to memory -b10 = User, match only on nonprivileged accesses -b11 = either, match all accesses - - - Watchpoint enable: -0 = watchpoint disabled, reset value -1 = watchpoint enabled. - - - - - This field watches a range of addresses by masking lower order address bits out of the watchpoint -comparison: -b00000 = no mask -b00001 = reserved -b00010 = reserved -b00011 = 0x00000007 mask for data address -b00100 = 0x0000000F mask for data address -b00101 = 0x0000001F mask for data address -. -. -. -b11111 = 0x7FFFFFFF mask for data address. -Note -? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is -Unpredictable. -? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the -comparison SBZ. Otherwise the behavior is Unpredictable. -To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a -debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 -debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those -that have a 4-bit byte address select field (bits [8:5]). - - - Enable linking bit: -0 = linking disabled -1 = linking enabled. -When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP -field. - - - Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP -with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is -Unpredictable whether a watchpoint debug event is generated. - - - Secure state access control. This field enables the watchpoint to be conditioned on the security state of the -processor. -b00 = watchpoint matches in both Secure and Non-secure state -b01 = watchpoint only matches in Non-secure state -b10 = watchpoint only matches in Secure state -b11 = reserved - - - Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to -program the watchpoint so it only hits if certain byte addresses are accessed. - - - Load/store access. The watchpoint can be conditioned to the type of access being done. -b00 = reserved -b01 = load, load exclusive, or swap -b10 = store, store exclusive or swap -b11 = either. -SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint -on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local -monitor within the processor. - - - Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: -b00 = reserved -b01 = privileged, match if the processor does a privileged access to memory -b10 = User, match only on nonprivileged accesses -b11 = either, match all accesses - - - Watchpoint enable: -0 = watchpoint disabled, reset value -1 = watchpoint enabled. - - - - - This field watches a range of addresses by masking lower order address bits out of the watchpoint -comparison: -b00000 = no mask -b00001 = reserved -b00010 = reserved -b00011 = 0x00000007 mask for data address -b00100 = 0x0000000F mask for data address -b00101 = 0x0000001F mask for data address -. -. -. -b11111 = 0x7FFFFFFF mask for data address. -Note -? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is -Unpredictable. -? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the -comparison SBZ. Otherwise the behavior is Unpredictable. -To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a -debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 -debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those -that have a 4-bit byte address select field (bits [8:5]). - - - Enable linking bit: -0 = linking disabled -1 = linking enabled. -When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP -field. - - - Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP -with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is -Unpredictable whether a watchpoint debug event is generated. - - - Secure state access control. This field enables the watchpoint to be conditioned on the security state of the -processor. -b00 = watchpoint matches in both Secure and Non-secure state -b01 = watchpoint only matches in Non-secure state -b10 = watchpoint only matches in Secure state -b11 = reserved - - - Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to -program the watchpoint so it only hits if certain byte addresses are accessed. - - - Load/store access. The watchpoint can be conditioned to the type of access being done. -b00 = reserved -b01 = load, load exclusive, or swap -b10 = store, store exclusive or swap -b11 = either. -SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint -on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local -monitor within the processor. - - - Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: -b00 = reserved -b01 = privileged, match if the processor does a privileged access to memory -b10 = User, match only on nonprivileged accesses -b11 = either, match all accesses - - - Watchpoint enable: -0 = watchpoint disabled, reset value -1 = watchpoint enabled. - - - - - - Write 0xC5ACCE55 to this field to unlock the DBG. -Write any other value to this field to lock the DBG - - - - - OSLM[0] - - - OSLM[1] -OS Lock Model implemented field. This field identifies the form of OS Save and Restore -mechanism implemented. -The possible values are: -0b00 No OS Save and Restore mechanism implemented. OS Lock not implemented. -v7 Debug only. -0b01 OS Lock and DBGOSSRR implemented. v7 Debug only. -0b10 OS Lock implemented. DBGOSSRR not implemented. v7.1 Debug only. -0b11 Reserved. -Note -This field is split across two non-contiguous bits in the register. - - - Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key -to the OS Lock Access Register. - - - OS Lock Status. The possible values are: -0 OS Lock not set. -1 OS Lock set. -If the OS Save and Restore mechanism is not implemented this bit is UNK. -The OS Lock is set or cleared by writing to the DBGOSLAR. - - - - - - Hold non-debug logic reset: -0 = Do not hold the non-debug logic reset on power-up or warm reset. -1 = Hold the non-debug logic of the processor in reset on power-up or warm reset. -The processor is held in this state until this flag is cleared to 0. - - - Warm reset request, RAZ - - - When set to 1, the DBGNOPWRDWN output signal is HIGH. This output is connected to the system -power controller and is interpreted as a request to operate in emulate mode. In this mode, the -Cortex-A5 processor and ETM are not actually powered down when requested by software or -hardware handshakes. -0 = DBGNOPWRDWN is LOW. This is the reset value. -1 = DBGNOPWRDWN is HIGH. - - - - - Sticky reset status - - - Reset status - - - Sticky power-down status. RAZ - - - Power up status. RAO - - - - - - Set value of the DBGRESTARTED output pin - - - Set value of PMUIRQ output pin. - - - Set value of the DBGACK output pin. - - - - - Read value of the DBGRESTART input pin - - - Read value of nFIQ input pin. - - - Read value of nIRQ input pin. - - - Read value of EDBGRQ input pin. - - - - - Controls whether the processor is in normal operating mode or integration mode: -b0 = normal operation -b1 = integration mode enabled. - - - - - - Indicates the claim tags. -Writing 1 to a bit in this register sets that particular claim. You can read the claim status at the Claim Tag Clear -Register. For example, if you write 1 to bit [3] of this register, bit [3] of the Claim Tag Clear Register is read as 1. -Writing 0 to a specific claim tag bit has no effect. This register always reads 0xFF, indicating that up to eight -claims can be set. - - - - - Indicates the claim tag status. Writing 1 to a specific claim tag clear bit clears that claim tag. Reading this -register returns the current claim tag value. For example, if you write 1 to bit [3] of this register, it is read as 0. -The reset value is 0. - - - - - - Lock access control. To unlock the debug registers, write a 0xC5ACCE55 key to this register. To lock the debug -registers, write any other value. Accesses to locked debug registers are ignored. The reset value is 0 - - - - - Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register - - - This bit indicates the status of the debug registers lock. -0 = Lock clear. Debug register writes are permitted. -1 = Lock set. Debug register writes are ignored. -The Debug reset value of this bit is 1. - - - Read-as-One - - - - - Secure noninvasive debug enable field - - - DBGEN || NIDEN) && (SPIDEN || SPNIDEN - - - Secure invasive debug enable field - - - DBGEN && SPIDEN - - - Non-secure noninvasive debug field - - - DBGEN || NIDEN - - - Non-secure invasive debug enable - - - DBGEN - - - - - - - - Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1. - - - Indicates that the main class of the Cortex-A5 processor is debug logic. This value is 0x5. - - - - - Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0. - - - Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4. - - - - - - - - - - - Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0x05. - - - - - Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB. - - - Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0xC - - - - - Indicates the revision number for the Cortex-A5 processor. This value changes based on the -product major and minor revision. This value is set to 1 indicating revision r0p1. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3. - - - - - Indicates the manufacturer revision number. This value changes based on the manufacturer -metal fixes. This value is set to 0. - - - For the Cortex-A5 processor, this value is set to 0. - - - - - Component identifier, bits [7:0]. - - - - - Component class (component identifier, bits [15:12]). - - - Component identifier, bits [11:8]. - - - - - Component identifier, bits [23:16]. - - - - - Component identifier, bits [31:24]. - - - - - - - - - PMU Event counter 0 - - - - - PMU Event counter 1 - - - - - - Counts processor clock cycles - - - - - - Specifies the event selected as described in the ARM Architecture Reference Manual. -Event EVNTBUS -bit position Description -0x00 - Software increment. The register is incremented only on writes to the Software Increment Register. See -Software Increment Register on page 10-7. -0x01 [0] Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache. Includes the -speculative linefills in the count. -0x02 [1] Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB. Includes the speculative -requests in the count. -0x03 [2] Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache. Counts -the number of allocations performed in the Data Cache because of a read or a write -0x04 [3] Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache. -This includes speculative reads. -0x05 [4] Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB. This does not -include micro TLB misses because of PLD, PLI, CP15 Cache operation by MVA and CP15 VA to PA -operations. -0x06 [5] Data read architecturally executed. Counts the number of data read instructions accepted by the Load Store -Unit. This includes counting the speculative and aborted LDR/LDM, and the reads because of the SWP -instructions. -0x07 [6] Data write architecturally executed. Counts the number of data write instructions accepted by the Load -Store Unit. This includes counting the speculative and aborted STR/STM, and the writes because of the SWP -instructions. -0x08 [7] Instruction architecturally executed. -0x09 [8] Exception taken. Counts the number of exceptions architecturally taken. -0x0A [9] Exception return architecturally executed. The following instructions are reported on this event: -0x0B [10] Change to ContextID retired. Counts the number of instructions architecturally executed writing into the -ContextID Register. -0x0C [11] Software change of PC. -0x0D [12] Immediate branch architecturally executed (taken or not taken). This includes the branches which are -flushed due to a previous load/store which aborts late. -0x0E [13] Procedure return (other than exception returns) architecturally executed. -0x0F [14] Unaligned load-store. -0x10 [15] Branch mispredicted/not predicted. Counts the number of mispredicted or not-predicted branches executed. -This includes the branches which are flushed because of a previous load/store which aborts late. -0x11 - Cycle counter. -0x12 [16] Branches or other change in program flow that could have been predicted by the branch prediction resources -of the processor. This includes the branches which are flushed because of a previous load/store which aborts -late. -0x13 [17] Data memory access. -0x14 [18] Instruction Cache access. -0x15 [19] Data cache eviction. -0x86 [20] IRQ exception taken. -0x87 [21] FIQ exception taken. -0xC0 [22] External memory request. -0xC1 [23] Non-cacheable external memory request. -0xC2 [24] Linefill because of prefetch. -0xC3 [25] Prefetch linefill dropped. -0xC4 [26] Entering read allocate mode. -0xC5 [27] Read allocate mode. -0xC6 [28] Reserved. -0xC7 - ETM Ext Out[0]. -0xC8 - ETM Ext Out[1]. -0xC9 [29] Data Write operation that stalls the pipeline because the store buffer is full. - - - - - - - - - - - - - - - - - Cycle counter enable set: -0 = disable -1 = enable. - - - Counter 1 enable - - - Counter 0 enable - - - - - - Cycle counter enable clear: -0 = disable -1 = enable. - - - Counter 1 enable - - - Counter 0 enable - - - - - - PMCCNTR overflow interrupt request enable. -When reading this register: -0 = interrupt request disabled -1 = interrupt request enabled. -When writing to this register: -0 = no action -1 = interrupt request enabled. - - - PMC1 overflow interrupt request enable - - - PMC0 overflow interrupt request enable. - - - - - - PMCCNTR overflow interrupt clear bit. -When reading this register: -0 = interrupt request disabled -1 = interrupt request enabled. -When writing to this register: -0 = no action -1 = interrupt request cleared. - - - Clear interrupt request on PMC1 overflow. - - - Clear interrupt request on PMC0 overflow - - - - - - Cycle counter overflow flag: -0 = disable -1 = enable. - - - Counter 1 overflow flag - - - Counter 0 overflow flag - - - - - - Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing. - - - Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing. - - - - - - User mode enable supported (using PMUSERENR) - - - Event export supported - - - Cycle counter pre-scale supported - - - Cycle counter implemented - - - 32-bit counters implemented - - - 2 event counters implemented - - - - - Specifies the implementor code: -0x41 = ARM. -This field is read-only and write ignored. - - - Specifies the identification code: -0x5 -This field is read-only and write ignored. - - - Specifies the number of counters implemented: -0x2 = two counters implemented. -This field is read-only and write ignored. - - - Disables cycle counter, PMCCNTR, when prohibited: -0 = count is enabled in prohibited regions. This is the reset value. -1 = count is disabled in prohibited regions. - - - Enables export of the events from the event bus to an external monitoring block, such as an ETM: -0 = export disabled. This is the reset value. -1 = export enabled. - - - Cycle count divider: -0 = count every clock cycle when enabled. This is the reset value. -1 = count every 64th clock cycle when enabled. - - - Cycle counter reset, write only bit, RAZ: -0 = no action -1 = reset cycle counter, PMCCNTR, to zero. - - - Performance counter reset, write only bit, RAZ: -0 = no action -1 = reset all performance counters to zero, not including PMCCNTR. - - - Enable bit: -0 = disable all counters, including PMCCNTR. This is the reset value. -1 = enable all counters including PMCCNTR. - - - - - User mode enable. 0 is the reset value - - - - - - Bus cycle - - - Write to translation table base - - - Instruction speculatively executed - - - Local memory error - - - Bus access - - - Level 2 data cache write-back - - - Level 2 data cache refill - - - Level 2 data cache access - - - Level 1 data cache write-back - - - Level 1 instruction cache access - - - Data memory access - - - Predictable branch speculatively executed - - - Cycle - - - Mispredicted or not predicted branch speculatively executed - - - Unaligned load or store - - - Procedure return - - - Immediate branch - - - Software change of the PC - - - Write to CONTEXTIDR - - - Exception return - - - Exception taken - - - Instruction architecturally executed - - - Store - - - Load - - - Level 1 data TLB refill - - - Level 1 data cache access - - - Level 1 data cache refill - - - Level 1 instruction TLB refill - - - Level 1 instruction cache refill - - - Software increment - - - - - - Lock access control. To unlock the performance monitor registers, write a 0xC5ACCE55 key to this register. To -lock the performance monitor registers, write any other value. Accesses to locked performance monitor -registers are ignored. The reset value is 0. - - - - - Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register - - - This bit indicates the status of the debug registers lock. -0 = Lock clear. Debug register writes are permitted. -1 = Lock set. Debug register writes are ignored. -The Debug reset value of this bit is 1. - - - Read-as-One - - - - - Secure noninvasive debug enable field - - - DBGEN || NIDEN) && (SPIDEN || SPNIDEN - - - Secure invasive debug enable field - - - DBGEN && SPIDEN - - - Non-secure noninvasive debug field - - - DBGEN || NIDEN - - - Non-secure invasive debug enable - - - - - - Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1. - - - Indicates that the main class of the Cortex-A5 processor is performance monitor. This value is 0x6. - - - - - Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0. - - - Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4. - - - - - - - - - - - Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0xA5. - - - - - Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB. - - - Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0x9. - - - - - Indicates the revision number for the Cortex-A5 processor. This value changes based on the -product major and minor revision. This value is set to 1 indicating revision r0p1. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3. - - - - - Indicates the manufacturer revision number. This value changes based on the manufacturer -metal fixes. This value is set to 0. - - - For the Cortex-A5 processor, this value is set to 0. - - - - - Component identifier, bits [7:0]. - - - - - Component class (component identifier, bits [15:12]). - - - Component identifier, bits [11:8]. - - - - - Component identifier, bits [23:16]. - - - - - Component identifier, bits [31:24]. - - - - - - - - - Set to 1 to enable timestamping. -On an ETM reset this bit is 0. - - - If an ETM is shared between multiple cores, selects which core to trace. For the maximum value permitted, see bits [14:12] of the System Configuration Register. See the Embedded Trace Macrocell Architecture Specification for more information. -To guarantee that the ETM is correctly synchronized to the new core, you must update these bits as follows: -1:Set bit [10], ETM programming, and bit [0], ETM power down, to 1. -2:Change the core select bits. -3:Clear bit [0], ETM power down, to 0. -4:Perform other programming required as normal. On an ETM reset this field is zero. - - - Instrumentation resources access control, ETM-A5 does not implement any instrumentation resources and therefore this bit is RAZ. - - - Disable software writes. ETM-A5 does not support this feature and therefore this bit is RAZ. - - - Disable register writes from the debugger. ETM-A5 does not support this feature and therefore this bit is RAZ. - - - Port size[3].Use this bit in conjunction with bits [6:4].On an ETM reset this bit is 0, corresponding to the 32-bit port size. - - - 0:Instruction trace enabled. -1:Instruction trace disabled. Data-only tracing is possible in this mode. On an ETM reset this bit is 0. - - - Use this bit in conjunction with bit [1], the MonitorCPRT bit. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. - - - Use this bit with bit [7] to suppress data. For details see Data suppression in the Embedded Trace Macrocell Architecture Specification.On an ETM reset this bit is 0. - - - These bits are used, in conjunction with bit [13], to set the trace port clocking mode. ETM-A5 supports only dynamic mode, corresponding to the value b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit [11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode.On an ETM reset these bits are zero. - - - b00 No Context ID tracing. -b01 Context ID bits [7:0] traced. -b10 Context ID bits [15:0] -b11 Context ID bits [31:0] traced. -Note Only the number of bytes specified is traced even if the new value is larger than this.On an ETM reset this field is zero. - - - See the description of bits [17:16].On an ETM reset this bit is 0. - - - Set this bit to 1 if you want the trace to include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive.On an ETM reset this bit is 0. - - - This bit controls an external output, ETMEN. The possible values are: -0 ETMEN is LOW. -1 ETMEN is HIGH. -You can use the ETMEN signal to control the routing of trace port signals to shared GPIO pins on your SoC, under the control of logic external to the ETM.Trace software tools must set this bit to 1 to ensure that trace output is enabled from this ETM. - - - When set to 1, the ETM is being programmed. For more information, see ETM Programming bit and associated state in the Embedded Trace Macrocell Architecture Specification. - - - If you set this bit to 1, when the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the Cortex-A5 processor to be forced into Debug state. On an ETM reset this bit is 0. - - - Set this bit to 1 if you want the ETM to output all branch addresses, even if the branch isbecause of a direct branch instruction. Setting this bit to 1 enables reconstruction of the program flow without having access to the memory image of the code being executed.On an ETM reset this bit is 0. - - - ETM-A5 does not implement FIFOFULL stalling of the processor, and therefore this bit is RAZ. - - - Use this field with bit [21] to specify the port size.The port size determines how many external pins are available to output the trace information on ATDATA[31:0]. ETM-A5 supports only the 32-bit port size, corresponding to a Port size[3:0] value of b0100, but you can write other values to these bits, and a read of the register returns the value written. Writing other values to these bits has no effect on the ETM.Bit [10] of the System Configuration Register indicates if these bits are set to select an unsupported port size.For more information see the Embedded Trace Macrocell Architecture Specification. On an ETM reset this field is b100, corresponding to the 32-bit port size. - - - This field configures the data tracing mode. The possible values are: -b00 No data tracing. -b01 Trace only the data portion of the access. -b10 Trace only the address portion of the access. -b11 Trace both the address and the data of the access. On an ETM reset this field is zero. - - - This field controls whether CPRTs are traced. The possible values are: -0 CPRTs not traced. -1 CPRTs traced. -This bit is used with bit [19]. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. - - - A pin controlled by this bit enables the ETM power to be controlled externally, see Control of ETM power down. The sense of this bit is inverted, and drives the ETMPWRUP signal. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, ETM tracing is disabled and accesses to any registers other than this register and the Lock Access Register are ignored.On an ETM reset this bit is set to 1. - - - - - ETMIDR present. - - - Software access is supported. - - - Trace start/stop block is present. - - - Number of Context ID comparators. - - - FIFOFULL logic absent. - - - Number of external outputs. Determined by the MAXEXTOUT[1:0] inputs.The value of these bits is the minimum of MAXEXTOUT[1:0] and 2, because ETM-A5 supports a maximum of 2 external outputs. - - - Number of external inputs. Determined by the MAXEXTIN[2:0] inputs. The value of these bits is the minimum of MAXEXTIN[2:0] and 4, because ETM-A5 supports a maximum of 4 external inputs. - - - The sequencer is present. - - - Number of counters. - - - Number of memory map decoders. - - - Number of data comparators. - - - Number of pairs of address comparators. - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - ASICCTL[7:0]: -when a bit in this field is set to 0 the corresponding bit of ASICCTL[7:0] is LOW -when a bit in this field is set to 1 the corresponding bit of ASICCTL[7:0] is HIGH. - - - - - v3.1 Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the -ETM is programmed again. This bit exists in all architecture versions, but can -only be accessed in ETMv3.1 and later as described in ETM Programming bit and -associated state on page 3-97. - - - Holds the current status of the trace start/stop resource. If set to 1, it indicates that -a trace on address has been matched, without a corresponding trace off address match - - - The current effective value of the ETM Programming bit, bit [10] of the ETMCR. -You must wait for this bit to go to 1 before you start to program the ETM as -described in ETM Programming bit and associated state on page 3-97. -If you read other bits in the ETMSR while this bit is 0, some instructions might -not have taken effect. ARM recommends that you set the ETM Programming bit -and wait for this bit to go to 1 before reading the overflow bit. -In ETMv3.2 and later this bit remains 0 if there is any data in the FIFO. This -ensures that the FIFO is empty before the ETM programming is changed. -In ETMv3.5 this bit is set when the OS Lock is set. See OS Lock Status Register, -ETMOSLSR, ETMv3.3 and later on page 3-166. -In ETMv3.5 this bit must be polled before saving or restoring state. See Access -permissions for ETMv3.5, multiple power domains on page 3-224 - - - If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 -when either: -? trace is restarted. -? the ETM Power Down bit, bit [0] of ETMCR, is set to 1. -Setting or clearing the ETM Programming bit does not cause this bit to be cleared -to 0. - - - - - No Fetch comparisons. If this bit is set to 1, address comparators cannot perform -fetch-stage comparisons. Setting bits [2:0] of an ETMACTR to b000, instruction fetch -causes the comparator to have UNPREDICTABLE behavior. - - - Number of supported processors minus 1. -The value given here is the maximum value that can be written to bits [27:25] of the -ETMCR, register 0x000. This field must be b000 if the ETM supports Direct JTAG access - - - Port mode supported. -Set to 1 if the currently selected port mode is supported internally or externally. - - - Port size supported. -Set to 1 if the currently selected port size is supported internally or externally for the -currently selected port mode. Enables more complex port sizes to be supported - - - Maximum port size[3]. This bit is used in conjunction with bits [2:0]. - - - If set to 1, FIFOFULL is supported. This bit is used in conjunction with bit [23] of the -ETMCCR, register 0x001. - - - Maximum port size[2:0]. This bit is used in conjunction with bit [9]. The value given here -is the maximum size supported by both the ETM and the ASIC. Smaller sizes might or -might not be supported. Check bit [10] for precise information on supported modes. See -bits [6:4] in ETMCR bit assignments on page 3-101. - - - - - When a bit is set to 1, it selects a single address comparator 16-1 as stop addresses. For -example, bit [16] set to 1 selects single address comparator 1 as a stop address. - - - When a bit is set to 1, it selects a single address comparator 16-1 as start addresses. For -example, bit [0] set to 1 selects single address comparator 1 as a start address. - - - - - When a bit is set to 1, it selects a single address comparator 16-1 for include/exclude -control. For example, bit [0] set to 1 selects single address comparator 1. - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - Trace start/stop enable. The possible values of this bit are: -0 Tracing is unaffected by the trace start/stop logic. -1 Tracing is controlled by the trace on and off addresses configured for the -trace start/stop logic. See The trace start/stop block on page 2-40. -The trace start/stop resource (resource 0x5F) is unaffected by the value of this bit. - - - Include/exclude control. The possible values of this bit are: -0 Include. The specified resources indicate the regions where tracing can -occur. When outside this region tracing is prevented. -1 Exclude. The resources, specified in bits [23:0] and in the ETMTECR2, -indicate regions to be excluded from the trace. When outside an exclude -region, tracing can occur. - - - When a bit is set to 1, it selects memory map decode 16-1 for include/exclude control. For -example, bit [8] set to 1 selects MMD 1. - - - When a bit is set to 1, it selects address range comparator 8-1 for include/exclude control. -For example, bit [0] set to 1 selects address range comparator 1. - - - - - - The number of bytes left in the FIFO, below which the FIFOFULL or -SuppressData signal is asserted. For example, setting this value to 15 causes data -trace suppression or processor stalling, if enabled, when there are less than 15 free -bytes in the FIFO. - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - When a bit is set to 1, it selects single address comparator 16 to 1 for exclude control. For -example, bit [16] set to 1 selects single address comparator 1. - - - When a bit is set to 1, it selects single address comparator 16 to 1 for include control. For -example, bit [0] set to 1 selects single address comparator 1. - - - - - - Exclude-only control. The possible values of this bit are: -0 Mixed mode. ViewData operates in a mixed mode, and both include and -exclude resources can be programmed. -1 Exclude-only mode. ViewData is programmed only in an excluding mode. -If none of the excluding resources match, tracing can occur. - - - When a bit is set to 1, it selects address range comparator 8-1 for exclude control. For -example, bit [8] set to 1 selects address range comparator 1. - - - When a bit is set to 1, it selects address range comparator 8-1 for include control. For -example, bit [0] set to 1 selects address range comparator 1. - - - - - Address value - - - - - Address value - - - - - Address value - - - - - Address value - - - - - Address value - - - - - Address value - - - - - Address value - - - - - Address value - - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - Virtual Machine ID (VMID) comparison enable, if the processor implements the -Virtualization Extensions.b -A value of 1 means that the address comparator matches only if the current VMID matches -the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, -ETMVMIDCVR, ETMv3.5 on page 3-164. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions - - - Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b -A value of 1 means that the address comparator also matches if the processor is operating -in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. -This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. - - - State and mode comparison control. The assignment of these bits is: -Bit [13, 11] Non-secure state comparison control. -Bit [12, 10] Secure state comparison control. -For each pair of bits, the encoding is: -b00 Match in all modes in this state. -b01 Do not match in any modes in this state. -b10 Match in all modes except User mode in this state. -b11 Match only in User mode in this state. -If the processor does not implement the Security Extensions, bits [13, 11] are reserved, -RAZ/WI. -See Filtering by state and mode, in ETMv3.5 on page 3-131 - - - Context ID comparator control. The permitted values of this field are: -b00 Ignore Context ID comparator. -b01 Address comparator matches only if Context ID comparator value 1 -matches. -b10 Address comparator matches only if Context ID comparator value 2 -matches. -b11 Address comparator matches only if Context ID comparator value 3 -matches. - - - Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses -occur. See Exact matching, in ETMv2.0 and later on page 2-54. - - - Data value comparison control. The permitted values of this field are: -b00 No data value comparison is made. -b01 Comparator can match only if data value matches. -b11 Comparator can match only if data value does not match. -The value of b10 is reserved and must not be used. -Note: -The b11 encoding was introduced in ETM architecture version 1.2. Previously this value -was reserved. -For details of the effect of this field on data value comparison, see Exact matching for data -address comparisons on page 2-56. - - - Comparison access size. The permitted values of this field are: -b00 Java instruction (from ETM architecture version 1.3 only) or byte data. -b01 Thumb instruction or halfword data. -b11 ARM instruction or word data. -The value of b10 is reserved and must not be used. -For more information, see Comparator access size on page 2-49. - - - Access type. The permitted values of this field are: -b000c Instruction fetch. -b001 Instruction execute. -b010 Instruction executed and passed condition code test. -b011 Instruction executed and failed condition code test. -b100 Data load or store. -b101 Data load. -b110 Data store. -The value of b111 is reserved and must not be used. -Note: -? The b010 and b011 encodings were introduced in ETM architecture version 1.2. -Previously these values were reserved. -? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 -or b110 to this field causes UNPREDICTABLE behavior. See No data address -comparator option, ETMv3.3 and later on page 2-25 for more information. - - - - - - Data value for comparison - - - - - - Data value for comparison - - - - - - Data mask - - - - - - Data mask - - - - - - Initial count - - - - - Initial count - - - - - - Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and -decrements every cycle regardless of the count enable event. When set to 1, the count -enable event is used to enable the counter. ARM recommends that bit [17] is always set to -1 and that the count enable event is used to control counter operation, using 0x6F (TRUE) -if a free running counter is required. -Note -This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM -architecture versions. - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and -decrements every cycle regardless of the count enable event. When set to 1, the count -enable event is used to enable the counter. ARM recommends that bit [17] is always set to -1 and that the count enable event is used to control counter operation, using 0x6F (TRUE) -if a free running counter is required. -Note -This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM -architecture versions. - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - - Current counter value. From ETM v3.1, when the Programming bit is set to 1 you -can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information. - - - - - Current counter value. From ETM v3.1, when the Programming bit is set to 1 you -can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information. - - - - - - Sequencer state transition event - - - - - Sequencer state transition event - - - - - Sequencer state transition event - - - - - Sequencer state transition event - - - - - Sequencer state transition event - - - - - Sequencer state transition event - - - - - - Current sequencer state.The permitted values of this field are: -b00 Sequencer currently in state 1. -b01 Sequencer currently in state 2. -b10 Sequencer currently in state 3. -The value of b11 is reserved. -From ETMv3.1, when the Programming bit is set to 1, software can write to this -field to force the sequencer to a particular state. The effect of writing b11 to this -field is UNPREDICTABLE, and software must not write this value. - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - function: -0: A -1: NOT(A) -2: A AND B -3: NOT(A) AND B -4: NOT(A) AND NOT(B) -5: A OR B -6: NOT(A) OR B -7: NOT(A) OR NOT(B) - - - Resource B -[13:11]: resource type -[10:7]: resource index - - - Resource A - - - - - - Context ID value - - - - - - Context ID mask value - - - - - - Synchronization frequency. Default value is 1024. - - - - - Branch packet encoding implemented. The possible values of this bit are: -0 The ETM implements the original branch packet encoding. See Branch -packet formats with the original address encoding scheme on page 7-310. -1 The ETM implements the alternative branch packet encoding. See Branch -packet formats with the alternative address encoding scheme on -page 7-313. - - - Support for Security Extensions. The possible values of this bit are: -0 The ETM behaves as if the processor is in Secure state at all times. -1 The ARM architecture Security Extensions are implemented by the -processor - - - Support for 32-bit Thumb instructions. The possible values of this bit are: -0: A 32-bit Thumb instruction is traced as two instructions, and exceptions -might occur between these two instructions. -1: A 32-bit Thumb instruction is traced as a single instruction. See 32-bit -Thumb instructions on page 4-240 for more information. - - - Load PC first. If this bit is set to 1, LSMs with the PC in the list load the PC first, followed -by the other registers in the normal order. This can be decompressed by using the following -procedure: -1. Calculate the number of items transferred by the LSM by looking at the code image. -2. As each item is read, assign an address equal to 4 greater than the previous one as -normal. -3. When the number of items read equals the total number of items transferred, subtract -(4 * number of items) from each address other than the first. -Note -This means that a branch address can be traced before the remaining data values of an -instruction. While this has never been prohibited in the protocol, care must be taken to -ensure that this case is correctly handled. - - - Processor family. The meaning of this field depends on the value of the Implementer -code.The following apply if Implementer code = 0x41, for ARM Limited: -b0000 ARM7 processor. -b0001 ARM9 processor. -b0010 ARM10 processor. -b0011 ARM11 processor -b1111 Processor family is defined elsewhere. See The Processor family field on -page 3-157 for more information. -When the Implementer code = 0x41, all other values are reserved by ARM Limited. -For any other Implementer code the permitted values of this field are defined by the -implementer. - - - Major ETM architecture version number. See The ETM architecture version. Possible -values of this field are: -b0000 ETMv1. -b0001 ETMv2. -b0010 ETMv3. -All other values are reserved. - - - Minor ETM architecture version number. See The ETM architecture version. - - - Implementation revision. See Implementation revision on page 3-157 - - - - - Timestamp packet size. -This bit is 0 if the size of the packet is 48 bits. This bit is 1 if the size of the packet is 64 bits. - - - Timestamp packet encoding. -This bit is 1 if the timestamp packet is encoded as a natural binary number. This bit is 0 if -the packet is gray coded. For more information see Encoding of the timestamp value on -page 7-343. - - - Reduced function counter. -This bit is 1 if counter 1 is implemented as a reduced function counter. This bit is 0 if all -counters are implemented as full-function counters. - - - The Virtualization Extensions are implemented. -This bit is 1 if the Virtualization Extensions are implemented, and 0 if not implemented. - - - Timestamping implemented. -This bit is 1 if timestamping is implemented, and 0 if it is not implemented - - - ETMEIBCR implemented. -This bit is 1 if the register is implemented, and 0 if it is not implemented. - - - Trace Start/Stop block can use EmbeddedICE watchpoint inputs. -This bit is 1 if the Trace Start/Stop block can use these inputs, and is 0 otherwise. - - - Number of EmbeddedICE watchpoint inputs implemented. -This field can take any value from b0000 (0 inputs) to b1000 (8 inputs). - - - Number of Instrumentation resources supported. The maximum value of this field is b100, -for four Instrumentation resources. -For more information see Instrumentation resources, from ETMv3.3 on page 2-69. - - - Set to 1 if data address comparisons are not supported. -For more information see No data address comparator option, ETMv3.3 and later on -page 2-25. - - - Set to 1 if all registers are readable - - - Size of extended external input bus. -This field must be 0 if bits [2:0] are 0. - - - Number of extended external input selectors. - - - - - Extended external input selector 4 - - - Extended external input selector 3 - - - Extended external input selector 2 - - - Extended external input selector 1 - - - - - - Stop resource selection. Setting a bit in this field to 1 selects the corresponding -EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to -input 1, bit [17] to input 2, and this pattern continues up to bit [23] corresponding to -input 8. - - - Start resource selection. Setting a bit in this field to 1 selects the corresponding -EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to -input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8. - - - - - - - - - Trace ID to output onto the trace bus. -On an ETM reset this field is cleared to 0x00. - - - - - - Identifies the order of transfers for a SWP or SWPB instruction: -0 = the Load transfer is traced before the Store transfer -1 = the Store transfer is traced before the Load transfer - - - Identifies the order of transfers for the RFE instruction: -0 = the PC transfer is traced before the CPSR transfer -1 = the CPSR transfer is traced before the PC transfer - - - - - - OS lock status. The value of this bit is the same as the value of bit [1] of the ETMOSLSR, -which indicates whether the ETM trace registers are locked. See OS Lock Status Register, -ETMOSLSR, ETMv3.3 and later on page 3-166. -This bit is UNKNOWN when the ETM is powered down - - - Sticky Register state bit. The possible values of this bit are: -0 ETM Trace Registers have not been powered down since this register was -last read. -1 ETM Trace Registers have been powered down since this register was last -read, and have lost their state. -When the core power domain of the ETM is powered down or reset, this bit is set to 1. -Reads of this register when the core power domain is powered down or held in reset return -1 for this bit, and do not change the value of this bit. -Reads of this register when the core power domain is powered up and not held in reset -return the current value of this bit, and then clear this bit to 0. If the Software Lock -mechanism is locked and the ETMPDSR read is made through the memory mapped -interface, this bit is not cleared. -In ETMv3.3 and ETMv3.4,when this bit is set, accesses to any ETM Trace Registers return -an error response. -In ETMv3.5, the value of this bit has no effect on accesses to the ETM Trace Registers. - - - ETM powered up bit. The value of this bit indicates whether you can access the ETM Trace -Registers. The possible values are: -0 ETM Trace Registers cannot be accessed. -1 ETM Trace Registers can be accessed. -When this bit is set to 0, accesses to any ETM Trace Registers return an error response. - - - - - - Drives the EXTOUT[1:0] output pins - - - Drives the nETMWFXREADY output pin - - - Drives the ETMDBGRQ output pina - - - - - Returns the value of the ETMWFXPENDING input pin - - - Returns the value of the DBGACK input pin - - - Returns the value of the EXTIN[3:0] input pins - - - - - - Drives the TRIGGER output pin - - - - - Drives the ATDATA[31, 23, 15, 7, 0] output pins - - - - - Returns the value of the SYNCREQ input pin - - - Returns the value of the AFVALID input pin - - - Returns the value of the ATREADY input pin - - - - - Drives the ATID[6:0] output pins - - - - - Drives the ATBYTES[1:0] output pins - - - Drives the AFREADY output pin - - - Drives the ATVALID output pin - - - - - - When this bit is set to 1, the device enters an integration mode to enable Topology Detection -or Integration Testing to be checked. -On an ETM reset this bit is cleared to 0. - - - - - - On reads, returns 0xFF. -On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be set. - - - - - On reads, returns the current claim tag value. -On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be -cleared to 0. -On an ETM reset this field is cleared to 0x00. - - - - - - Write 0xC5ACCE55 to this field to unlock the ETM. -Write any other value to this field to lock the ETM - - - - - Reads as b0. Indicates that the ETMLAR is 32 bits - - - Indicates whether the ETM is locked. The possible values of this bit are: -0 Writes are permitted. -1 ETM locked. Writes are ignored. -If this register is accessed from an interface where the lock registers are ignored, this field -reads as 0 regardless of whether the ETM is locked. - - - Indicates whether the lock registers are implemented for this interface. The possible values -of this bit are: -0 This access is from an interface that ignores the lock registers. -1 This access is from an interface that requires the ETM to be unlocked. - - - - - Permission for Secure non-invasive debug. - - - Reads as b00, Secure invasive debug not supported by the ETM - - - Permission for Non-secure non-invasive debug. -This field is only implemented if the processor implemented with the ETM implements the -Security Extensions. When this field is implemented the possible values of the field are: -b10 Non-secure non-invasive debug disabled. -b11 Non-secure non-invasive debug enabled. -This field is a logical OR of the NIDEN and DBGEN signals. It takes the value b11 when -the OR is TRUE, and b10 when the OR is FALSE. -If the processor does not support the Security Extensions, bits [3:2] are reserved, RAZ. - - - Reads as b00, Non-secure invasive debug not supported by the ETM. - - - - - - - - 0x1 Sub type, processor trace - - - 0x3 Main type, trace source - - - - - n, where 2n is number of 4KB blocks used. - - - JEP 106 continuation code - - - - - - - - - - - Part Number[7:0]. -Middle and Lower BCD value of Device Number. - - - - - JEP 106 identity code[3:0] - - - Part Number[11:8]. -Upper Binary Coded Decimal (BCD) value of Device Number. - - - - - Revision Number of Peripheral. This value is the same as the -Implementation revision field of the ETMIDR, see ETM ID Register on -page 3-19. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - JEP 106 identity code[6:4]. - - - - - RevAnd (at top level). Manufacturer revision number. - - - Customer Modified. -0x0 indicates from ARM - - - - - Component identifier, bits [7:0]. - - - - - Component class (component identifier, bits [15:12]). - - - Component identifier, bits [11:8]. - - - - - Component identifier, bits [23:16]. - - - - - Component identifier, bits [31:24]. - - - - - - - - - Enables or disables the CTI. -0 When this bit is 0, all cross-triggering mapping logic functionality is disabled. -1 When this bit is 1, cross-triggering mapping logic functionality is enabled. - - - - - - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout -output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing -it to be cleared. - - - - - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the -register for each channel. -Reads as follows: -0 Application trigger is inactive. -1 Application trigger is active. -Writes as follows: -0 No effect. -1 Generate channel event. - - - - - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each -channel. On writes, for each bit: -0 Has no effect. -1 Clears the corresponding channel event. - - - - - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of -the register for each channel. On writes, for each bit: -0 Has no effect. -1 Generate an event pulse on the corresponding channel. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[0], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[1], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[2], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[3], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[4], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 0, ctitrigin[5], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 6, ctitrigin[6], generate an event on the -channel corresponding to this bit. - - - - - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. -There is one bit of the field for each of the four channels. On writes, for each bit: -0 Input trigger 0 events are ignored by the corresponding channel. -1 When an event is received on input trigger 7, ctitrigin[7], generate an event on the -channel corresponding to this bit. - - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 0, ctitrigout[0]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 1, ctitrigout[1]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 2, ctitrigout[2]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 3, ctitrigout[3]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 4, ctitrigout[4]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 5, ctitrigout[5]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 6, ctitrigout[6]. - - - - - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is -one bit of the field for each of the four channels. On writes, for each bit -0 The corresponding channel is ignored by the output trigger 0. -1 When an event occurs on the channel corresponding to this bit, generate an event -on output event 7, ctitrigout[7]. - - - - - - Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input. -1 ctitrigin is active. -0 ctitrigin is inactive. -Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. - - - - - Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. -1 ctitrigout is active. -0 ctitrigout is inactive. - - - - - Shows the status of the ctichin inputs. There is one bit of the field for each channel input. -0 ctichin is inactive. -1 ctichin is active. -Because the register provides a view of the raw ctichin inputs, the reset value is UNKNOWN. - - - - - Shows the status of the ctichout outputs. There is one bit of the field for each channel output. -0 ctichout is inactive. -1 ctichout is active. - - - - - Enable ctichout3. Set to 0 to disable channel propagation. - - - Enable ctichout2. Set to 0 to disable channel propagation. - - - Enable ctichout1. Set to 0 to disable channel propagation. - - - Enable ctichout0. Set to 0 to disable channel propagation. - - - - - When external multiplexing is implemented for trigger signals, then the number of multiplexed signals on -each trigger must be shown in the Device ID Register. This is done using a Verilog define EXTMUXNUM. - - - - - - Sets the value of the ctichinack outputs - - - - - Sets the value of the ctitriginack outputs. - - - - - Sets the value of the ctichout outputs - - - - - Sets the value of the ctitrigout outputs. - - - - - Reads the values of the ctichoutack inputs - - - - - Reads the value of the ctitrigoutack inputs - - - - - Reads the value of the ctichin inputs - - - - - Reads the values of the ctitrigin inputs. - - - - - - Integration Mode Enable. -0 Disable integration mode. -1 Enable integration mode. -Note -The CTI must also be enabled using the CTICONTROL register for integration mode operation. - - - - - - On reads, for each bit: -1 Claim tag bit is implemented -On writes, for each bit: -0 Has no effect. -1 Sets the relevant bit of the claim tag. - - - - - On reads, for each bit: -0 Claim tag bit is not set. -1 Claim tag bit is set. -On writes, for each bit: -0 Has no effect. -1 Clears the relevant bit of the claim tag. - - - - - - Software lock key value. -0xC5ACCE55 Clear the software lock. -All other write values set the software lock. - - - - - Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. - - - 0 Indicates that write operations are permitted from this interface. -1 Indicates that write operations are not permitted from this interface. Read -operations are permitted. - - - Software Lock Implemented. Indicates that a lock control mechanism is present from this -interface. -0 Indicates that a lock control mechanism is not present from this interface. Write -operations to the LAR are ignored. -1 Indicates that a lock control mechanism is present from this interface - - - - - Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled -elsewhere. - - - Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. - - - Indicates the security level for Non-secure non-invasive debug: -0b10 Disabled. -0b11 Enabled. - - - Indicates the security level for Non-secure invasive debug: -0b10 Disabled. -0b11 Enabled. - - - - - - Number of ECT channels available. - - - Number of ECT triggers available. - - - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are -using asicctl. The default value of 0b00000 indicates that no multiplexing is present. -This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. - - - - - Sub-classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification within the major classification as specified in the MAJOR field. -0b0001 Indicates that this component is a cross-triggering component. - - - Major classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification for this debug and trace component. -0b0100 Indicates that this component allows a debugger to control other components in a -CoreSight SoC-400 system. - - - - - Always 0b0000. Indicates that the device only occupies 4KB of memory. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b0100 JEDEC continuation code. - - - - - - - - - - - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0x06 Indicates bits[7:0] of the part number of the component - - - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. - - - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0b1001 Indicates bits[11:8] of the part number of the component. - - - - - 0b0101 This device is at r1p0. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. - - - - - Indicates minor errata fixes specific to the revision of the component being used, for example -metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the -component designers ensure that a metal fix can change this field if required, for example, by -driving it from registers that reset to 0b0000. -0b0000 Indicates that there are no errata fixes to this component. - - - Customer Modified. Indicates whether the customer has modified the behavior of the component. -In most cases, this field is 0b0000. Customers change this value when they make authorized -modifications to this component. -0b0000 Indicates that the customer has not modified this component. - - - - - Preamble[0]. Contains bits[7:0] of the component identification code. -0x0D Bits[7:0] of the identification code. - - - - - Class of the component, for example, whether the component is a ROM table or a generic -CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. -0b1001 Indicates that the component is a CoreSight SoC-400 component. - - - Preamble[1]. Contains bits[11:8] of the component identification code. -0b0000 Bits[11:8] of the identification code. - - - - - Preamble[2]. Contains bits[23:16] of the component identification code. -0x05 Bits[23:16] of the identification code. - - - - - Preamble[3]. Contains bits[31:24] of the component -identification code. -0xB1 Bits[31:24] of the identification code. - - - - - - - - - - Defines the depth, in words, of the trace RAM. - - - - - - Formatter pipeline is empty. All data is stored to RAM. -0 Formatter pipeline is not empty. -1 Formatter pipeline is empty. - - - The acquisition complete flag indicates that the capture is completed when the formatter stops -because of any of the methods defined in the FFCR, or CTL.TraceCaptEn is 0. This sets -FFSR.FtStopped to 1. -0 Acquisition is not complete. -1 Acquisition is complete. - - - The Triggered bit is set when the component observes a trigger during programming the FFCR. -Note -This field does not indicate that the formatter embedded a trigger in the trace data. -0 A trigger is not observed. -1 A trigger is observed. - - - The flag indicates whether the RAM is full or not. -0 The RAM write pointer is not wrapped around. The RAM is not full. -1 The RAM write pointer is wrapped around. The RAM is full. - - - - - Data read from the ETB Trace RAM. - - - - - Sets the read pointer to the required value. The read pointer reads entries from the Trace RAM -through the APB interface. - - - - - The RAM Write Pointer Register sets the write pointer to the required value. The write pointer -writes entries from the CoreSight bus to the Trace RAM. - - - - - The counter is used as follows: -Trace after The counter is set to a large value, slightly less than the number of entries -in the RAM. -Trace before The counter is set to a small value. -Trace about The counter is set to half the depth of the trace RAM. -You must not write to this register when trace capture is enabled, FFSR.FtStopped is 0, and -CTL.TraceCaptEn is 1. When a write is attempted, then the register is not updated. A read -operation is permitted when trace capture is enabled. - - - - - ETB Trace Capture Enable. This is the master enable bit that sets FtStopped to HIGH when -TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is -stored to RAM. When all of the data is stored, the formatter outputs FtStopped. Capture is fully -disabled, or complete, when FtStopped goes HIGH. See ETB Formatter and Flush Status -Register. -0 Disable trace capture. -1 Enable trace capture. - - - - - When CTL.TraceCaptEn is 0: -? Writes to this register write the data to the ETB trace RAM. The RAM Write Pointer -Register value is incremented. -? Reads of this register return an UNKNOWN value. -When CTL.TraceCaptEn is 1: -? Writes to this register are ignored. The data is not written to the ETB trace RAM and the -RAM Write Pointer is not affected. -? Reads of this register return an UNKNOWN value. - - - - - - Formatter stopped. The formatter has received a stop request signal and all trace data and -post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes -HIGH. -0 Formatter is not stopped. -1 Formatter is stopped. - - - Flush In Progress. This is an indication of the current state of afvalids. -0 afvalids is LOW. -1 afvalids is HIGH. - - - - - Stops trace capture after a trigger event is observed. The reset value is 0. -0 Disable stopping of the formatter after a trigger event is observed. -1 Enable stopping of the formatter after a trigger event is observed. - - - Stops trace capture after the next flush completes. The reset value is 0. -0 Disable stopping the formatter when a flush completes. -1 Enable stopping the formatter when a flush completes. - - - Indicates a Trigger-on-Flush completion. -0 Disable trigger indication on flush completion. -1 Enable trigger indication on flush completion. - - - Indicates a trigger on a trigger event. -0 Disable trigger indication on a trigger event. -1 Enable trigger indication on a trigger event. - - - Indicates a trigger when trigin is asserted. -0 Disable trigger indication when trigin is asserted. -1 Enable trigger indication when trigin is asserted. - - - Initiates a manual flush. This bit is set to 0 after the flush has been serviced. The reset value is 0. -0 Manual flush is not initiated. -1 Manual flush is initiated. - - - Flushes the data in the system when a trigger event occurs. The reset value is 0. -0 Disable flush generation when a trigger event occurs. -1 Enable flush generation when a trigger event occurs. - - - Enables use of the flushin input. The reset value is 0. -0 Disable flush generation using the flushin interface. -1 Enable flush generation using the flushin interface. - - - When EnFTC is 1, this bit controls whether triggers are recorded in the trace stream. Most usage -models require Continuous mode, where this bit is set to 1. The reset value is 0. See Modes of -operation on page 10-5 for more information. -Note -This bit can only be changed when FtStopped is HIGH. -0 Triggers are not embedded in the trace stream. -1 Triggers are embedded in the trace stream. - - - Enable formatting. Most usage models require Continuous mode, where this bit is set to 1. The -reset value is 0. See Modes of operation on page 10-5 for more information. -Note -This bit can only be changed when FtStopped is HIGH. -0 Formatting is disabled. -1 Formatting is enabled. - - - - - - Sets the value of full output. -0 Sets the value to 0. -1 Sets the value to 1. - - - Sets the value of acqcomp output. -0 Sets the value to 0. -1 Sets the value to 1. - - - - - Sets the value of flushinack. -0 Sets the value of FLUSHINACK to 0. -1 Sets the value of FLUSHINACK to 1. - - - Sets the value of triginack. -0 Sets the value of TRIGINACK to 0. -1 Sets the value of TRIGINACK to 1. - - - - - Reads the value of flushin. -0 flushin is LOW. -1 flushin is HIGH. - - - TRIGIN Reads the value of trigin. -0 trigin is LOW. -1 trigin is HIGH. - - - - - Reads the value of atdatas[31]. -0 atdatas[31] is 0. -1 atdatas[31] is 1. - - - Reads the value of atdatas[23]. -0 atdatas[23] is 0. -1 atdatas[23] is 1. - - - Reads the value of atdatas[15]. -0 atdatas[15] is 0. -1 atdatas[15] is 1. - - - Reads the value of atdatas[7]. -0 atdatas[7] is 0. -1 atdatas[7] is 1. - - - Reads the value of atdatas[0]. -0 atdatas[0] is 0. -1 atdatas[0] is 1. - - - - - Sets the value of afvalids. -0 Sets the value of afvalids to 0. -1 Sets the value of afvalids to 1. - - - Sets the value of atreadys. -0 Sets the value of atreadys to 0. -1 Sets the value of atreadys to 1. - - - - - Reads the value of atids - - - - - Reads the value of atbytess - - - Reads the value of afreadys. -0 afreadys is 0. -1 afreadys is 1. - - - Reads the value of atvalids. -0 atvalids is 0. -1 atvalids is 1. - - - - - - Integration Mode Enable. -0 Disable integration mode. -1 Enable integration mode. - - - - - - On reads, for each bit: -1 Claim tag bit is implemented -On writes, for each bit: -0 Has no effect. -1 Sets the relevant bit of the claim tag. - - - - - On reads, for each bit: -0 Claim tag bit is not set. -1 Claim tag bit is set. -On writes, for each bit: -0 Has no effect. -1 Clears the relevant bit of the claim tag. - - - - - - Software lock key value. -0xC5ACCE55 Clear the software lock. -All other write values set the software lock. - - - - - Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. - - - 0 Indicates that write operations are permitted from this interface. -1 Indicates that write operations are not permitted from this interface. Read -operations are permitted. - - - Software Lock Implemented. Indicates that a lock control mechanism is present from this -interface. -0 Indicates that a lock control mechanism is not present from this interface. Write -operations to the LAR are ignored. -1 Indicates that a lock control mechanism is present from this interface - - - - - Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled -elsewhere. - - - Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. - - - Indicates the security level for Non-secure non-invasive debug: -0b10 Disabled. -0b11 Enabled. - - - Indicates the security level for Non-secure invasive debug: -0b10 Disabled. -0b11 Enabled. - - - - - - This bit returns 0 on reads to indicate that the ETB RAM operates synchronously to atclk. -0 The ETB RAM operates synchronously to atclk. - - - Number of external multiplexing available. Non-zero values indicate the type of ATB -multiplexing on the input to the ATB. -0b0000 Only 0x00 is supported, that is, no multiplexing is present. This value helps detect -the ATB structure. - - - - - Sub-classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification within the major classification as specified in the MAJOR field. -0b0010 This component is a trace buffer, ETB. - - - Major classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification for this debug and trace component. -0b0001 This component is a trace sink component. - - - - - Always 0b0000. Indicates that the device only occupies 4KB of memory. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b0100 JEDEC continuation code. - - - - - - - - - - - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0x07 Indicates bits[7:0] of the part number of the component. - - - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. - - - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0b1001 Indicates bits[11:8] of the part number of the component. - - - - - 0b0100 This device is at r0p5. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. - - - - - Indicates minor errata fixes specific to the revision of the component being used, for example -metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the -component designers ensure that a metal fix can change this field if required, for example, by -driving it from registers that reset to 0b0000. -0b0000 Indicates that there are no errata fixes to this component. - - - Customer Modified. Indicates whether the customer has modified the behavior of the component. -In most cases, this field is 0b0000. Customers change this value when they make authorized -modifications to this component. -0b0000 Indicates that the customer has not modified this component. - - - - - Preamble[0]. Contains bits[7:0] of the component identification code. -0x0D Bits[7:0] of the identification code. - - - - - Class of the component, for example, whether the component is a ROM table or a generic -CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. -0b1001 Indicates that the component is a CoreSight SoC-400 component. - - - Preamble[1]. Contains bits[11:8] of the component identification code. -0b0000 Bits[11:8] of the identification code. - - - - - Preamble[2]. Contains bits[23:16] of the component identification code. -0x05 Bits[23:16] of the identification code. - - - - - Preamble[3]. Contains bits[31:24] of the component -identification code. -0xB1 Bits[31:24] of the identification code. - - - - - - - - - Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you -can use this setting to minimize switching. When a source has nothing to transmit, then another -source is selected irrespective of the minimum number of transactions. The ATB funnel holds for -the minimum hold time and one additional transaction. The actual hold time is the register value -plus 1. The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 -is reserved. -0b0000 1 transaction hold time. -0b0001 2 transactions hold time. -0b0010 3 transactions hold time. -0b0011 4 transactions hold time. -0b0100 5 transactions hold time. -0b0101 6 transactions hold time. -0b0110 7 transactions hold time. -0b0111 8 transactions hold time. -0b1000 9 transactions hold time. -0b1001 10 transactions hold time. -0b1010 11 transactions hold time. -0b1011 12 transactions hold time. -0b1100 13 transactions hold time. -0b1101 14 transactions hold time. -0b1110 15 transactions hold time. - - - Enable slave port 7. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 6. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 5. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 4. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 3. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 2. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 1. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - Enable slave port 0. -The reset value is 0. -0 Slave port disabled. -This excludes the port from the priority selection scheme. -1 Slave port enabled. - - - - - Priority value of the eighth slave port. - - - Priority value of the seventh slave port. - - - Priority value of the sixth slave port. - - - Priority value of the fifth slave port. - - - Priority value of the fourth slave port. - - - Priority value of the third slave port. - - - Priority value of the second slave port. - - - Priority value of the first slave port. - - - - - - A read access returns the value of atdatas<x>[127] of the enabled port. A write access writes to -atdatam[127] of the enabled port. -0 atdata[127] of the enabled port is LOW. -1 atdata[127] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[119] of the enabled port. A write access writes to -atdatam[119] of the enabled port. -0 atdata[119] of the enabled port is LOW. -1 atdata[119] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[111] of the enabled port. A write access writes to -atdatam[111] of the enabled port. -0 atdata[111] of the enabled port is LOW. -1 atdata[111] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[103] of the enabled port. A write access writes to -atdatam[103] of the enabled port. -0 atdata[103] of the enabled port is LOW. -1 atdata[103] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[95] of the enabled port. A write access writes to -atdatam[95] of the enabled port. -0 atdata[95] of the enabled port is LOW. -1 atdata[95] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[87] of the enabled port. A write access writes to -atdatam[87] of the enabled port. -0 atdata[87] of the enabled port is LOW. -1 atdata[87] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[79] of the enabled port. A write access writes to -atdatam[79] of the enabled port. -0 atdata[79] of the enabled port is LOW. -1 atdata[79] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[71] of the enabled port. A write access writes to -atdatam[71] of the enabled port. -0 atdata[71] of the enabled port is LOW. -1 atdata[71] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[63] of the enabled port. A write access writes to -atdatam[63] of the enabled port. -0 atdata[63] of the enabled port is LOW. -1 atdata[63] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[55] of the enabled port. A write access writes to -atdatam[55] of the enabled port. -0 atdata[55] of the enabled port is LOW. -1 atdata[55] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[47] of the enabled port. A write access writes to -atdatam[47] of the enabled port. -0 atdata[47] of the enabled port is LOW. -1 atdata[47] of the enabled port is HIGH. - - - A read access returns the value of atdatas<x>[39] of the enabled port. A write access writes to -atdatam[39] of the enabled port. -0 atdata[39] of the enabled port is LOW. -1 atdata[39] of the enabled port is HIGH. - - - Reads the value of atdatas[31]. -0 atdatas[31] is 0. -1 atdatas[31] is 1. - - - Reads the value of atdatas[23]. -0 atdatas[23] is 0. -1 atdatas[23] is 1. - - - Reads the value of atdatas[15]. -0 atdatas[15] is 0. -1 atdatas[15] is 1. - - - Reads the value of atdatas[7]. -0 atdatas[7] is 0. -1 atdatas[7] is 1. - - - Reads the value of atdatas[0]. -0 atdatas[0] is 0. -1 atdatas[0] is 1. - - - - - A read access returns the value of afvalidm. -A write access outputs the data to afvalidsn, where the value of the Ctrl_Reg at 0x000 defines n. -0 Pin is at logic 0. -1 Pin is at logic 1. - - - A read access returns the value of atreadym. -A write access outputs the data to atreadysn, where the value of the Ctrl_Reg at 0x000 defines n. -0 Pin is at logic 0. -1 Pin is at logic 1. - - - - - A read returns the value of the atidsn signals, where the value of the Control Register at 0x000 -defines n. -A write outputs the value to the atidm port. - - - - - A read returns the value of the atbytessn signal, where the value of the Ctrl_Reg at 0x000 defines n. -A write outputs the value to atbytesm. - - - A read returns the value of the afreadysn signal, where the value of the Ctrl_Reg at 0x000 defines -n. -A write outputs the value to afreadym. - - - A read returns the value of the atvalidsn signal, where the value of the Ctrl_Reg at 0x000 defines n. -A write outputs the value to atvalidm. - - - - - - Integration Mode Enable. -0 Disable integration mode. -1 Enable integration mode. - - - - - - On reads, for each bit: -1 Claim tag bit is implemented -On writes, for each bit: -0 Has no effect. -1 Sets the relevant bit of the claim tag. - - - - - On reads, for each bit: -0 Claim tag bit is not set. -1 Claim tag bit is set. -On writes, for each bit: -0 Has no effect. -1 Clears the relevant bit of the claim tag. - - - - - - Software lock key value. -0xC5ACCE55 Clear the software lock. -All other write values set the software lock. - - - - - Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. - - - 0 Indicates that write operations are permitted from this interface. -1 Indicates that write operations are not permitted from this interface. Read -operations are permitted. - - - Software Lock Implemented. Indicates that a lock control mechanism is present from this -interface. -0 Indicates that a lock control mechanism is not present from this interface. Write -operations to the LAR are ignored. -1 Indicates that a lock control mechanism is present from this interface - - - - - Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled -elsewhere. - - - Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. - - - Indicates the security level for Non-secure non-invasive debug: -0b10 Disabled. -0b11 Enabled. - - - Indicates the security level for Non-secure invasive debug: -0b10 Disabled. -0b11 Enabled. - - - - - - Indicates the priority scheme implemented in this component. -0b0011 Program the slave ports to have higher or lower priority with respect to each other. - - - Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. -0b0010 Two ATB slave ports. -0b0011 Three ATB slave ports. -0b0100 Four ATB slave ports. -0b0101 Five ATB slave ports. -0b0110 Six ATB slave ports. -0b0111 Seven ATB slave ports. -0b1000 Eight ATB slave ports. - - - - - Sub-classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification within the major classification as specified in the MAJOR field: -0b0001 This component arbitrates ATB inputs mapping to ATB outputs. - - - Major classification of the type of the debug component as specified in the ARM? CoreSight? -Architecture Specification for this debug and trace component: -0b0010 This component has both ATB inputs and ATB outputs. - - - - - Always 0b0000. Indicates that the device only occupies 4KB of memory. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b0100 JEDEC continuation code. - - - - - - - - - - - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0x08 Indicates bits[7:0] of the part number of the component. - - - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. - - - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this -part number. -0b1001 Indicates bits[11:8] of the part number of the component. - - - - - 0b0011, This device is at r1p1. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. - - - - - Indicates minor errata fixes specific to the revision of the component being used, for example -metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the -component designers ensure that a metal fix can change this field if required, for example, by -driving it from registers that reset to 0b0000. -0b0000 Indicates that there are no errata fixes to this component. - - - Customer Modified. Indicates whether the customer has modified the behavior of the component. -In most cases, this field is 0b0000. Customers change this value when they make authorized -modifications to this component. -0b0000 Indicates that the customer has not modified this component. - - - - - Preamble[0]. Contains bits[7:0] of the component identification code. -0x0D Bits[7:0] of the identification code. - - - - - Class of the component, for example, whether the component is a ROM table or a generic -CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. -0b1001 Indicates that the component is a CoreSight SoC-400 component. - - - Preamble[1]. Contains bits[11:8] of the component identification code. -0b0000 Bits[11:8] of the identification code. - - - - - Preamble[2]. Contains bits[23:16] of the component identification code. -0x05 Bits[23:16] of the identification code. - - - - - Preamble[3]. Contains bits[31:24] of the component -identification code. -0xB1 Bits[31:24] of the identification code. - - - - - - - - - Halt on Debug. -0 Do not halt on debug, HLTDBG signal into the counter has no -effect. -1 Halt on debug, when HLTDBG is driven HIGH, the count value is -held static. - - - Enable. -0 The counter is disabled and not incrementing. -1 The counter is enabled and is incrementing. - - - - - Debug Halted. - - - - - Current value of the timestamp counter, lower 32 bits. To change the current timestamp value, -write the lower 32 bits of the new value to this register before writing the upper 32 bits to -CNTCVU. The timestamp value is not changed until the CNTCVU register is written to. - - - - - Current value of the timestamp counter, upper 32 bits. To change the current timestamp value, -write the lower 32 bits of the new value to CNTCVL before writing the upper 32 bits to this -register. The 64-bit timestamp value is updated with the value from both writes when this register -is written to. - - - - - - Frequency in number of ticks per second. You can specify up to 4GHz. - - - - - - Always 0b0000. Indicates that the device only occupies 4KB of memory. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b0100 JEDEC continuation code. - - - - - - - - - - - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. -0x01 Indicates bits[7:0] of the part number of the component. - - - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the -component. -0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. - - - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. -0b0001 Indicates bits[11:8] of the part number of the component. - - - - - 0b0001 This device is at r0p1. - - - Always 1. Indicates that a JEDEC assigned value is used. - - - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. -0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. - - - - - Indicates minor errata fixes specific to the revision of the component being used, for example -metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the -component designers ensure that a metal fix can change this field if required, for example, by -driving it from registers that reset to 0b0000. -0b0000 Indicates that there are no errata fixes to this component. - - - Customer Modified. Indicates whether the customer has modified the behavior of the component. -In most cases, this field is 0b0000. Customers change this value when they make authorized -modifications to this component. -0b0000 Indicates that the customer has not modified this component. - - - - - Preamble[0]. Contains bits[7:0] of the component identification code. -0x0D Bits[7:0] of the identification code. - - - - - Class of the component, for example, whether the component is a ROM table or a generic -CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. -0b1001 Indicates that the component is a CoreSight SoC-400 component. - - - Preamble[1]. Contains bits[11:8] of the component identification code. -0b0000 Bits[11:8] of the identification code. - - - - - Preamble[2]. Contains bits[23:16] of the component identification code. -0x05 Bits[23:16] of the identification code. - - - - - Preamble[3]. Contains bits[31:24] of the component -identification code. -0xB1 Bits[31:24] of the identification code. - - - - - - - - - transmit data register - - - - - receive data register - - - - - baud rate divider constant N: (N>=4) -0011: N=4 -... -0111: N=8 -... -1111: N=16 - - - baud rate divider coeffcientbaud rate formula is: -BAUD RATE = Fclk/(Nx(BAUD_DIV+1)) -default baud rate is 115.2K, N=16, Ffun=26MHz. - - - - - choose big or little endian -0: little endian -1: big endian - - - RX FIFO reset control -1: RX FIFO reset -0: RX FIFO not reset; or set 1'b1, auto clear to 1'b0 - - - TX FIFO reset control -1: TX FIFO reset -0: TX FIFO not reset;or set to 1'b1,auto clear to 1'b0 - - - after RX timeout, enable hardware flow control (on condition that HWFC is enable) -1: after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control -0: after RX timeout, disable hardware flow control - - - RX trigger RTS enable control (on condition that HWFC is enable) -1: enable RX TRIG trigger RTS flow signal -0: disable RX TRIG trigger RTS flow signal - - - hardware flow control bit -1: enable -0: disable - - - RX timeout interrupt control bit -1: enable -0: disable - - - TX data interrupt control bit -1: enable TX interrupt -0: disable TX interrupt - - - RX data interrupt control bit -1: enable RX interrupt -0: disable RX interrupt - - - stop bit detection control bit -1: enable stop bit detection -0: disable stop bit detection - - - stop bit control bit -1: 2bit stop bit -0: 1bit stop bit - - - check bit -1: odd check -0: even check - - - check bit enable or not -1: enable -0: disable - - - - - TX FIFO trigger setting -00000000: 0 byte trigger -00000001: 1 byte trigger -00000010: 2 bytes trigger -00000011: 3 bytes trigger -00000100: 4 bytes trigger -01111110: 126bytes trigger -01111111: 127bytes trigger -10000000: don't trigger - - - - - RX FIFO trigger settings -00000000: don't trigger -00000001: 1 byte trigger -00000010: 2 bytes trigger -00000011: 3 bytes trigger -00000100: 4 bytes trigger -01111111: 127bytes trigger -10000000: 128bytes trigger - - - - - configure the time interval between sending data twice -0000: interval 0 baud rate clock -0001: interval 1 baud rate clock -1111: interval 15 baud rate clock - - - configure the threshold value of the UART timeout interrupt counter -00000000: configure the initial value of 0 baud rate clock -00000001: configure the initial value of 1 baud rate clock -00000010: configure the initial value of 2 baud rate clock -11111111: configure the initial value of 255 baud rate clock - - - - - bit type is changed from w1c to rc. - request to send status bit -1: prohibit far-end to send -0: request far-end to send - - - bit type is changed from w1c to rc. - clear the sending status bit -1: prohibit home terminal to send -0: allow home terminal to send - - - bit type is changed from w1c to rc. - the received data stop bit state -1: stop bit error -0: stop bit right - - - bit type is changed from w1c to rc. - RX data parity status -1: parity error -0: parity right - - - bit type is changed from w1c to rc. - RX data timeout interrupt status bit -1: timeout -0: not timeout - - - bit type is changed from w1c to rc. - RX data interrupt status bit -1: RX_FIFO_CNTRX_TRIG -0: RX_FIFO_CNT<RX_TRIG - - - bit type is changed from w1c to rc. - TX data interrupt status bit -1: TX_FIFO_CNT TX_TRIG -0: TX_FIFO_CNT >TX_TRIG - - - - - TX FIFO data number -00000000: TX FIFO has 0 data -00000001: TX FIFO has 1 data -01111111: TX FIFO has 127 data -10000000: TX FIFO has 128 data - - - - - RX FIFO data number -00000000: RX FIFO has 0 data -00000001: RX FIFO has 1 data -01111111: RX FIFO has 127 data -10000000: RX FIFO has 128 data - - - - - - - - - IP version r6p0 - - - - - Auxadc offset function enable 0: disable offset calibration function 1: enable offset calibration function When set 1, the adc inner offset is calibrated and not include in output data - - - auxadc convert data out average control: 000: disable adc average, output 12bit data and valid after once conversion; 001: adc convert twice and output the average data; 010: adc convert 4 times and output the average data; 011: adc convert 8 times and output the average data; 100: adc convert 16 times and output the average data; 101: adc convert 32 times and output the average data; 110: adc convert 64 times and output the average data; 111: adc convert 128 times and output the average data; - - - the number of SW channel accessing, N+1. - - - No use, reserved - - - SW channel run, Write 1 to run a SW channel accessing, it is cleared by HW. - - - ADC global enable, 0: ADC module disable; 1: ADC module enable. - - - - - ADC scale setting for current ADC channel, more detail see 7.6.6.3 Application note - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC software config channel ID. ADC software config channel ID. 4h0:for BAT_DET 4h1:for general ADCI1 4h2:for general ADCI2 4h3:for general ADCI3 5h4: for general ADCI4 5h5: for VBAT_SENSE 5h6: no use 5h7 TYPEC_CC1 5h8 for THM sensor 5h9: for TYPEC_CC2 5hA-5hC: no use 5hD: for DCDC_CALOUT 5hE, for VCHGSEN 5hF, for VCHG_BG 5h10, for PROG2ADC 5h11, 5h12: no use 5h13: for SD_AVDD 5h14: for AUDIO_HEADMIC 5h15: for LDO_CALOUT0 5h16: for LDO_CALOUT1 5h17: for LDO_CALOUT2 5h18-5h1C: no use 5h1D: for DAC self offset calibretion 5h1E: for DP 5h1F: for DM - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC scale setting for current ADC channel, more detail see 7.7.6 Application note - - - current channel delay enable, 0-diable; 1-enable. - - - ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. - - - ADC channel ID Same as ADC_SW_CH_CFG adc_cs - - - - - ADC HW channel accessing delay, its unit is ADC clock. It can be use for signal without enough setup time - - - - - ADC conversion result. When with one more result, each read gets one result. - - - - - ADC interrupt enable, 0: interrupt disable; 1: interrupt enable. - - - - - ADC interrupt clear. Write "1" to clear. - - - - - ADC masked interrupt. - - - - - ADC raw interrupt. - - - - - Current accessing channel, 0~7: fast HW channel 0~7; 8: SW channel; 9~16: slow HW channel 0~7; 31: NO request; - - - ADC state machine status, 0: idle; 1: fast HW req; 2: SW req; 3: slow HW req; 4: fast HW wait; 5: slow HW wait; Others: reserved - - - ADC internal counter status, 0: idle; 1~n: work or wait counter; - - - - - ADC fast HW channel7 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel6 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel5 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel4 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel3 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel2 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel1 timer enable, 0: disable; 1: enable; - - - ADC fast HW channel0 timer enable, 0: disable; 1: enable; - - - - - ADC fast HW channel timer working clock divider - - - - - ADC fast HW channel0 timer threshold - - - - - ADC fast HW channel1 timer threshold - - - - - ADC fast HW channel2 timer threshold - - - - - ADC fast HW channel3 timer threshold - - - - - ADC fast HW channel4 timer threshold - - - - - ADC fast HW channel5 timer threshold - - - - - ADC fast HW channel6 timer threshold - - - - - ADC fast HW channel7 timer threshold - - - - - ADC fast HW channel0 data - - - - - ADC fast HW channel1 data - - - - - ADC fast HW channel2 data - - - - - ADC fast HW channel3 data - - - - - ADC fast HW channel4 data - - - - - ADC fast HW channel5 data - - - - - ADC fast HW channel6 data - - - - - ADC fast HW channel7 data - - - - - output to analog 0: adc reference voltage is generated by local resister devider 1: adc reference voltage is direct from bandgap 1.25v voltage. - - - output to analog THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration - - - output to analog Aux ADC current sense enable signal, active high, default 0. - - - - - ADC fast HW channel7 data valid. - - - ADC fast HW channel6 data valid. - - - ADC fast HW channel5 data valid. - - - ADC fast HW channel4 data valid. - - - ADC fast HW channel3 data valid. - - - ADC fast HW channel2 data valid. - - - ADC fast HW channel1 data valid. - - - ADC fast HW channel0 data valid. - - - - - - - - - bit type is changed from wc to rc. - ear shut down clear - - - bit type is changed from wc to rc. - hp shut down clear - - - bit type is changed from wc to rc. - pa shut down clear - - - bit type is changed from wc to rc. - [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} - - - - - [0]: audio HEAD_INSERT debounce enable [1]: audio HEAD_BUTTON_OUT debounce enable - - - - - - - low debounce threshold(clock 1k), for HEAD_INSERT signal - - - high debounce threshold(clock 1k), for HEAD_INSERT signal - - - - - head insert detect T1/T2 timer step (clock 1k) - - - head insert detect T0 timer , (clock 1k) - - - - - head insert detect T1 timer ,step: HID_TMR_T1T2_STEP - - - - - head insert detect T2 timer ,step: HID_TMR_T1T2_STEP - - - - - low debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal - - - high debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal - - - - - ear_shutdown - - - hp_shutdown - - - pa_shutdown - - - head insert detect out: AUDIO_HEAD_INSERT_OUT state - - - head button detect out : AUDIO_HEAD_BUTTON_OUT state - - - u1 debounce state machine status - - - u0 debounce state machine status - - - - - ear_shutdown_enable - - - hp_shutdown_enable - - - pa_shutdown_enable2 - - - pa_shutdown_enable1 - - - pa_shutdown_enable0 - - - 1:32k_clk 0:1k_clk - - - protect enable - - - over-temperature protection threshold - - - - - over-temperature protection precis - - - overvoltage protection threshold - - - overvoltage protection precis - - - overcurrent protection threshold - - - overcurrent protection precis - - - - - int status: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} - - - int mask = aud_irq_raw & aud_int_en - - - - - int enable: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} - - - - - adc right enable - - - dac right enable - - - adc left enable - - - adc right enable - - - - - - - - - bypass DEM - - - Audio DACL & DACR output mixer select 00 = R/L 01 = R/0 10 = 0/L 11 = 0/0 - - - Audio DACL & DACR output mixer select 00 = L + R 01 = 2 x L 10 = 2 x R 11 = 0 - - - - - - - - - - - - - - - - - - - bit type is changed from wc to rc. - - - bit type is changed from wc to rc. - - - bit type is changed from wc to rc. - - - bit type is changed from wc to rc. - - - bit type is changed from wc to rc. - - - bit type is changed from wc to rc. - - - - - - - - - Audio LDO VB enable signal 0 = disable 1 = enable - - - Audio LDO VB prevent reverse flow back power down signal 0 = power up 1 = power down - - - Audio LDO VB SLEEP MODE PD signal 0 = EN 1 = PD - - - Audio BG EN 0 = disable 1 = enable - - - Audio BIAS EN 0 = disable 1 = enable - - - Audio Microphone bias enable signal 0 = disable 1 = enable - - - Audio Headset Micbias enable signal 0 = disable 1 = enable - - - Audio HeadMic SLEEP MODE EN signal 0 = disable 1 = enable - - - Audio MIC SLEEP MODE EN signal 0 = disable 1 = enable - - - Audio BG Voltage 0 :BG=1.55V 1: BG=1.5V - - - Audio BG Bias option 0 = normal 1 = debug mode - - - Audio BG tune TC option 00: normal 01: TC reduce 10: TC reduce more 11: TC enhance - - - Audio MICBIAS power down signal (do not control discharge circuit) 0 = power up 1 = power down - - - Audio Headmic VREF 0 = main-BG 1 = AUD_BG - - - HMIC_COMP_MODE_EN: 0 = disable 1 = headmicbias filter RC integrated in chip - - - - - Audio LDO_VB output voltage calibration signal 00000 = -13.3% 00001 = -12.5% 00010 = -11.7% 00011 = -10.8% 00100 = -10% 00101 = -9.2% 00110 = -8.4% 00111 = -7.5% 01000 = -6.7% 01001 = -5.8% 01010 =-5% 01011 = -4.2% 01100 = -3.3% 01101 = -2.5% 01110 = -1.67% 01111 = -0.83% 10000 = 0 10001 = 0.83% 10010 = 1.67% 10011 = 2.5% 10100 = 3.3% 10101 = 4.2% 10110 = 5% 10111 =5.8% 11000 = 6.7% 11001 = 7.5% 11010 = 8.4% 11011 = 9.2% 11100 = 10% 11101 = 10.8% 11110 = 11.7% 11111 = 12.5% - - - Audio ADC/DAC/DRV VCM & LDO VB output voltage control bit (VB should be set larger than 3.0V) 00000 -00011 = forbidden 00100 = 3.0V 00101 = 3.025V 00110 = 3.05V 00111 = 3.075V 01000 = 3.1V 01001 = 3.125V 01010 =3.15V 01011 = 3.175V 01100 = 3.2V 01101 = 3.225V 01110 = 3.25V 01111 = 3.275V 10000 = 3.3V 10001 = 3.325V 10010 = 3.35V 10011 = 3.375V 10100 = 3.4V 10101 = 3.425V 10110 = 3.45V 10111 =3.475V 11000 = 3.5V 11001 = 3.525V 11010 = 3.55V 11011 = 3.575V 11100 = 3.6V 11101 - 11111 = forbidden - - - Audio headmicbias output voltage control bit 000 = 2.2V 001 = 2.4V 010 = 2.5V 011 = 2.6V 100 = 2.7V 101 = 2.8V 110 = 2.9V 111 = 3.0V - - - Audio MICBIAS output voltage select signal 000 = 2.2V 001 = 2.4V 010 = 2.5V 011 = 2.6V 100 = 2.7V 101 = 2.8V 110 = 2.9V 111 = 3.0V - - - - - AUD HP-PGA BIAS current: 00:X1 11:X2 - - - AUD HP-PGA 3rd stage BIAS current: 000: 5uA 001:7.5uA 010:10uA 011: 12.5uA 100: 15uA 101: 17.5uA 110:20uA 111: 22.5uA - - - Audio PA class-AB mode Quiescent current decreasing level 00=3.5mA, 01=2.5mA, 10=1.9mA, 11=1.6mA - - - Audio ADC & PGA ibias current control bit <3:2> control the ibias of the PGA 00 = 10uA 01 = 7.5uA 10 = 5uA 11 = 5uA <1:0> control the ibias of the modulator 00 = 5uA 01 = 3.75uA 10 = 2.5uA 11 = 2.5uA - - - Audio DACL & DACR output gain control bit 00 = 0dB 01 = -0.75dB 1x=-1.5dB - - - HP&RCV DRV SEL 00: input gm/2, miller cap cut 01: input gm/2, miller cap normal 10: input gm normal, miller cap cut 11: input gm normal, miller cap normal - - - - - Audio PA over temperature protection circuit power down signal 0 = power up 1 = power down - - - Audio PA over temperature protection circuit temperature select 000: 4C -> -14C 001: 25C -> 8C 010: 47C -> 31C 011: 68C -> 52C 100: 89C -> 74C 101: 110C -> 95C 110: 130C -> 115C 111: 150C -> 135C - - - Audio VBAT_PA over voltage protection circuit power down signal 0 = power up 1 = power down - - - Audio VBAT_PA over voltage protection circuit threshold select 0 = 0.3V 1 = 0.6V - - - Audio VBAT_PA over voltage protection circuit voltage select RG_AUD_PA_OVP_THD = 0/1 000 = 5.8 -> 5.5/5.2 001 = 6.0 -> 5.7/5.4 010 = 6.2 -> 5.9/5.6 011 = 6.4 -> 6.1/5.8 100 = 6.6 -> 6.3/6.0 101 = 6.8 -> 6.5/6.2 110 = 7.0 -> 6.7/6.4 111 = 7.2 -> 6.9/6.6 - - - Audio PA over current protection circuit power down signal 0 = power up,1 = power down - - - Audio PA class-AB mode over current protection circuit current select 0=800mA 1=1000mA - - - Audio PA over current protection circuit power down signal 0 = power up,1 = power down - - - Audio Driver over current protection current select HP mode: 00--108mA 01--150mA 10--156mA 11--195mA RCV mode: 00--209mA 01300mA 10310mA 11-- 400mA - - - Audio PA VCOM voltage control bit 00 = 0.55xVDD 01 = 0.5xVDD 10 = 0.45xVDD 11 = 0.4xVDD - - - - - Audio PA class-D mode PWM Gain select 00 = 1 01 = 1.5 10 = 1.67 11 = 2 - - - Audio PA class-D mode PWM logic delay time select 00 = 7ns 01 = 14ns 10 =24ns 11 = 29ns - - - Audio PA class-D output edge slew rate control 000 = 2ns 001 = 4ns 010 = 6ns 011 = 8ns 100 = 10ns 101=12ns 110 = 14ns 111 = 16ns - - - Audio PA class-D mode spread spectrum enable signal 0 = disable 1 = enable - - - Audio PA class-D mode spread spectrum reset enable signal 0 = disable 1 = enable - - - Audio PA class-D mode spread spectrum dither level select signal when PA_DTRI_F<1:0> = 00/01/10/11 00 = 3.2%/1.6%/0.8%/0.4% 01 = 9%/4.7%/2.3%/1.2% 10 = 22%/ 11%/5.5%/2.7% 11 = 47%/ 23%/ 12%/ 6% - - - Audio PA class-D mode spread spectrum 32k dither clock select signal 0 = disable 1 = enable - - - Audio PA class-D mode spread spectrum dither clock divider select signal 000 = 1 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 1/32 110 = 1/64 111 = 1/128 - - - - - Audio Speaker PA class-D mode enable signal 0 = disable (CLASS-AB mode) 1 = enable(CLASS-D mode) - - - Audio Speaker PA class-D mode switching frequency locking enable signal 0 = disable 1 = enable - - - Audio Speaker PA class-D mode switching frequency locking resolution select 0 = 1X 1 = 2X - - - Audio Speaker PA class-D mode switching frequency select 000 = 330kHz 001 = 490kHz 010 = 650KHz 011 = 810KHz 100 = 970kHz 101 = 1.12MHz 110 = 1.27MHz 111 = 1.42MHz - - - Audio PA class-D mode Switching frequency hopping level 000000=0Hz 000001=1*2.5KHz 000010=2*2.5KHz 000011=3*2.5KHz 000100=4*2.5KHz 000101=5*2.5KHz 000110=6*2.5KHz 000111=7*2.5KHz 001000=8*2.5KHz 001001=9*2.5KHz 001010=10*2.5KHz 001011=11*2.5KHz 001100=12*2.5KHz 001101=13*2.5KHz 001110=14*2.5KHz 001111=15*2.5KHz 010000=16*2.5KHz 010001=17*2.5KHz 010010=18*2.5KHz 010011=19*2.5KHz 010100=20*2.5KHz 010101=21*2.5KHz 010110=22*2.5KHz 010111=23*2.5KHz 011000=24*2.5KHz 011001=25*2.5KHz 011010=26*2.5KHz 011011=27*2.5KHz 011100=28*2.5KHz 011101=29*2.5KHz 011110=30*2.5KHz 011111=31*2.5KHz 100000=32*2.5KHz 100001=33*2.5KHz 100010=34*2.5KHz 100011=35*2.5KHz 100100=36*2.5KHz 100101=37*2.5KHz 100110=38*2.5KHz 100111=39*2.5KHz 101000=40*2.5KHz 101001=41*2.5KHz 101010=42*2.5KHz 101011=43*2.5KHz 101100=44*2.5KHz 101101=45*2.5KHz 101110=46*2.5KHz 101111=47*2.5KHz 110000=48*2.5KHz 110001=49*2.5KHz 110010=50*2.5KHz 110011=51*2.5KHz 110100=52*2.5KHz 110101=53*2.5KHz 110110=54*2.5KHz 110111=55*2.5KHz 111000=56*2.5KHz 111001=57*2.5KHz 111010=58*2.5KHz 111011=59*2.5KHz 111100=60*2.5KHz 111101=61*2.5KHz 111110=62*2.5KHz 111111=63*2.5KHz - - - Audio PA Driver stop output enable signal 0 = disable, 1 = enable - - - Audio PA output short to VBAT detect enable signal 0 = disable 1 = enable - - - Audio PA output short to GND detect enable signal 0 = disable 1 = enable - - - - - Audio digital core clcok input enable signal 0 = disable 1 = enable - - - Audio digital loop clcok input enable signal 0 = disable 1 = enable - - - Audio analog core clcok input enable signal 0 = disable 1 = enable - - - Audio analog ADC clock input enable signal 0 = disable 1 = enable - - - Audio analog ADC clock reset enable signal 0 = EN 1 = RESET - - - Audio DAC clock input enable signal 0 = disable 1 = enable - - - Audio DRV clock input enable signal 0 = disable 1 = enable - - - Audio DCDC GEN clock input enable signal 0 = disable 1 = enable - - - Audio DCDC MEM clock input enable signal 0 = disable 1 = enable - - - Audio DCDC CORE clock input enable signal 0 = disable 1 = enable - - - Audio VAD enable signal 0 = disable 1 = enable - - - Audio ADC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk 01 = Fclk / 2 - - - Audio DAC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk 01/11 = Fclk x 2 10 = Fclk / 2 - - - - - Audio PGA&ADC BIAS en signal 0 = disable 1 = enable - - - Audio PGA & ADC VCM buffer enable signal 0 = disable 1 = enable - - - Audio ADC PGAL enable signal 0 = disable 1 = enable - - - Audio ADC PGAR enable signal 0 = disable 1 = enable - - - Audio ADC PGAL bypass select signal 00 = normal input 01 = HEADMIC to ADCL 10/11 = All disconnected - - - Audio ADC PGAR bypass select signal 00 = normal input 01 = HEADMIC to ADCR 10/11 = All disconnected - - - Audio ADCL enable signal 0 = disable 1 = enable - - - Audio ADCL reset enable signal 0 = disable 1 = enable - - - Audio ADCR enable signal 0 = disable 1 = enable - - - Audio ADCR reset enable signal 0 = disable 1 = enable - - - Audio ADC VREF current drv increasing by 1.3 times enable signal 0 = disable 1 = enable - - - Headmic button release depop signal 0 = disable 1 = depop - - - Headmic button release depop signal to VCM enable 0 = disable 1 = depop - - - Reserved - - - - - ADPGA_Internal common voltage select 00: 0.5*VB 01: 0.45*VB 10: 0.425*VB 11:0.4*VB - - - Audio ADC PGAL Gain control 000 = 0dB 001 = 3dB 010 = 6dB 011 = 12dB 100 = 18dB 101 = 24dB 110 = 30dB 111 = 36dB - - - Audio ADC PGAR Gain control 000 = 0dB 001 = 3dB 010 = 6dB 011 = 12dB 100 = 18dB 101 = 24dB 110 = 30dB 111 = 36dB - - - Audio DACL/R dc offset trim bit 000 = 0 001 = +1/20*VFS 010 = +2/20*VFS 011 = +1/20*VFS 100 = 0 101 = -1/20*VFS 110 = -2/20*VFS 111 = -1/20*VFS - - - Audio DACS dc offset trim bit 000 = 0 001 = +1/20*VFS 010 = +2/20*VFS 011 = +1/20*VFS 100 = 0 101 = -1/20*VFS 110 = -2/20*VFS 111 = -1/20*VFS - - - - - Audio DACS enable signal 0 = disable 1 = enable - - - Audio DACL enable signal 0 = disable 1 = enable - - - Audio DACR enable signal 0 = disable 1 = enable - - - Audio Driver HPL dummy loop enable signal 0 = disable 1 = enable - - - Audio Driver HPL dummy loop end enable signal 0 = disable 1 = enable: true loop fade in - - - Audio Driver HPR dummy loop enable signal 0 = disable 1 = enable - - - Audio Driver HPR dummy loop end enable signal 0 = disable 1 = enable: true loop fade in - - - Audio Driver RCV dummy loop enable signal 0 = disable 1 = enable - - - Audio Driver RCV dummy loop end enable signal 0 = disable 1 = enable: true loop fade in - - - Audio Driver HPL output enable signal 0 = disable 1 = enable - - - Audio Driver HPR output enable signal 0 = disable 1 = enable - - - Audio Driver vcm buffer enable signal 0 = disable 1 = enable - - - Audio Driver RCV output enable signal 0 = disable 1 = enable - - - Audio Speaker PA (Driver SPKL) enable signal 0 = disable 1 = enable - - - - - Audio DACL/R dc offset enable signal 0 = disable 1 = enable - - - Audio DACS dc offset enable signal 0 = disable 1 = enable - - - NG_PA enable control 0 = mute disable 1 = mute enable - - - Audio DACL to HPL enable signal 0 = disable 1 = enable - - - Audio DACR to HPR enable signal 0 = disable 1 = enable - - - Audio DACL to Receiver/Earpiece enable signal 0 = disable 1 = enable - - - Audio DACS to PA enable signal 0 = disable 1 = enable - - - Audio HMIC to PA enable signal 0 = disable 1 = enable when debug=1, HMIC to PA path on, no matter "RG_AUD_SDAPA" when debug=0, HMIC to PA path off, "RG_AUD_SDAPA" is enable - - - Audio MIC to HPL enable signal 0 = disable 1 = enable when debug=1, MIC to HPL path on , "RG_AUD_SDALHPL"/"RG_AUD_SDALRCV" is dis-enable when debug=0, MIC to HPL path off , "RG_AUD_SDALHPL"/"RG_AUD_SDALRCV" is enable - - - MIC1 to Audio ADC PGAL enable signal 0 = disable 1 = enable - - - MIC2 to Audio ADC PGAR enable signal 0 = disable 1 = enable - - - HEADMIC to Audio ADC PGAL enable signal 0 = disable 1 = enable - - - HEADMIC to Audio ADC PGAR enable signal 0 = disable 1 = enable - - - - - Audio Speaker Driver PGA Gain control <3:2>For Class-D PGA, dft=00 00 = 0dB 01 = 1.5dB 10 = 3dB 11 = 3dB <1:0>For Class-AB PGA 00 = -3dB(20K) 01 = 0dB(28K) 10 = 1.16dB(32K) 11 = 1.16dB(32K) - - - Audio Receiver/Earpiece Driver RCV_P/RCV_N PGA Gain control 0010 = 6dB 0011 = 3dB 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute - - - Audio Headphone left channel Gain control 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute - - - Audio Headphone right channel Gain control 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute - - - - - MUX2ADC SEL PD 0 = power up 1 = power down - - - Audio signal input to AuxADC enable signal 0 = disable 1 = enable - - - Audio headset button detect circuit enable signal 0 =disable 1 = enable - - - Audio headset detect signal RG_HP_DRIVER_EN software control enable signal 0 = DG_HP_DRIVER_EN work 1 = RG_HP_DRIVER_EN work - - - Audio headset detect reference voltage circuit enable signal 0 =disable 1 = enable - - - Audio headset mic detect circuit power enable signal 0 =disable 1 = enable - - - Audio signal input to AuxADC scale select signal 0 =little scale 1 =large scale(4:1) - - - Audio headset_LINT low detect filter enable signal 0 = no filter 1 = filter - - - Audio signal input to AuxADC buffer chop signal (1kHz) - - - Audio signal input to AuxADC select 000 = HEADMIC_IN_DET 001 = HEADSET_L_INT 010 = HP_L 011 = HP_R 100 = AVDD_VB 101 = VDDPA 110 = MICBIAS 111 = HEADMIC_BIAS - - - Audio headset detect circuit current select signal 0000 =0 0001 = 0.5u 0010 =1u 0011 = 1.5u 0100 =2u 0101 = 2.5u 0110 =3u 0111 = 3.5u 1000 =4u 1001 = 4.5u 1010 =5u 1011 = 5.5u - - - - - Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 2V 001 =2.1V 010 = 2.2V 011 =2.3V 100 = 2.4V 100 =2.5V 110 = 2.6V 111 = 2.7V - - - Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden - - - Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 25mV 001 =50mV 010 = 100mV 011 = 150mV 100 = 200mV 100 =250mV 110 = 300mV 111 = 350mV - - - Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 00 = 1.7V 01 = 1.8V 10 = 1.9V 11 = 2V - - - Audio L_DET pull up power down signal 00 = power up 01 = power down 10/11 = high-z - - - Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden - - - Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden - - - - - BYPASS CHG_STS signal 1 = bypass CHG_EN 0 = dis-bypass CHG_EN - - - Audio Headphone jack type select (Head_L_INT) 00 = Tie High 01 = Tie Low 10 = No Spring 11 = forbidden - - - Audio head microphone button pressed detect voltage select signal (VDDIO=2.8V) 0000 = 1.0V 0001 = 0.95V 0010 = 0.9V 0011 = 0.85V 0100 = 0.8V 0101 = 0.75V 0110 = 0.7V 0111 = 0.65V 1000 = 0.6V 1001 = 0.55V 1010 =0.5V 1011 = 0.45V 1100 = 0.4V 1101/1110/1111 = forbidden - - - Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden - - - Audio headset plug out detect enable signal 0 = disable 1 = enable - - - Audio headset detect signal LDRV_ENB software control signal, it should be set from 0->1 several ms (ex. 5ms) after audio driver HPL output enable signal (RG_AUD_HPL_EN) set from 1-> 0 - - - Audio Driver HPL output enable signal to headset detect delay function enable signal 0 = disable delay-reg(RG_AUD_HPL_EN_D2HDT_T) 1 = enable delay-reg(RG_AUD_HPL_EN_D2HDT_T) - - - Audio Driver HPL output enable signal (RG_AUD_HPL_EN) to headset detect delay time 00 = 8*Tclk 01 = 16*Tclk 10 = 32*Tclk 11 = 64*Tclk - - - - - Audio digital control logic enable signal 0 = disable 1 = enable - - - Audio digital control logic reset enable signal 0 = disable 1 = enable - - - Audio DRV delay timer control signal 000 = 0us 001 = 30us 010 = 60us 011 = 90us 100 = 120us 101 = 150us 110 = 180us 111 = 210us - - - Audio DRV soft start enable signal 0 = disable 1 = enable - - - Soft reset dpop module . 0:disable , 1:enable - - - - - Audio PA calibration clock input enable signal 0 = disable 1 = enable - - - Audio PA PWM clock divider select signal 00 = 1/128 01 = 1/64 10 = 1/256 11 = 1/1 - - - Audio VBAT_PA over voltage protection circuit mode change signal 0 = enable Class-AB mode 1 = keep the previous mode - - - Audio PA over current protection circuit mute timer control signal 000 = 0ms 001 = 1ms 010 = 4ms 011 = 16ms 100 = 64ms 101 = 256ms 110 = 1s 111 = 4s - - - Audio VBAT_PA over voltage protection circuit alert deglitch enable signal 0 = disable 1 = enable - - - Audio VBAT_PA over voltage protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms - - - - - Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable 1 = enable - - - Audio PA over temperature protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms - - - Audio PA over temperature protection circuit mute enable signal 0 = disable 1 = enable - - - Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable 1 = enable - - - Audio PA over temperature protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms - - - Audio PA over current protection circuit mute power down signal 1 = enable mute 0 = disable mute - - - Audio PA over current protection circuit mute timer control signal 000 = 0ms 001 = 1ms 010 = 4ms 011 = 16ms 100 = 64ms 101 = 256ms 110 = 1s 111 = 4s - - - - - - HPL depop DAC current setting - - - HPR depop DAC current setting - - - - - Reserved, always=1 - - - Reserved, always=1 - - - Audio HP de-pop fade in function enable signal 0 = disable 1 = enable - - - Audio HP de-pop fade out function enable signal 0 = disable 1 = enable - - - Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 - - - Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1 001 = 2 010 = 3 011 = 4 100 = 5 101 = 6 110 = 7 111 = 8 - - - Audio HP de-pop gain time step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 30us 001 = 60us 010 = 120us 011 = 250us 100 = 500us 101 = 1ms 110 = 2ms 111 = 4ms - - - Audio HPL_RDAC status signal 0 = unfinish/have never done 1 = finish - - - Audio HPR_RDAC status signal 0 = unfinish/have never done 1 = finish - - - - - Audio dc-calibration waiting time, every data change 000 = 2Tclk 001 = 3Tclk 010 = 4Tclk 011 = 5Tclk 100 = 6Tclk 101 = 7Tclk 110 = 8Tclk 111 = 9Tclk - - - Audio DePOP HPL DAC clock(start-up) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk - - - Audio DePOP HPL DAC data increase step(start-up) 00 = +1 01 = +2 10 = +4 11 = +8 - - - Audio DePOP HPL DAC data final value(start-up) 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 =256 - - - Audio DePOP HPL DAC clock(rising/falling) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk - - - Audio DePOP HPL DAC data increase step(rising/falling) 00 = +1 01 = +2 10 = +4 11 = +8 - - - - - depop_hpl_current_sel 00: X2 01:X1 10:X2/3 11:X1/2 - - - depop_hpr_current_sel 00: X2 01:X1 10:X2/3 11:X1/2 - - - Audio DePOP HPR DAC clock(start-up) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk - - - Audio DePOP HPR DAC data increase step(start-up) 00 = +1 01 = +2 10 = +4 11 = +8 - - - Audio DePOP HPR DAC data final value(start-up) 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 =256 - - - Audio DePOP HPR DAC clock(rising/falling) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk - - - Audio DePOP HPR DAC data increase step(rising/falling) 00 = +1 01 = +2 10 = +4 11 = +8 - - - - - depop_runing time 000: 10ms 001: 20ms 010: 40ms 011: 80ms 100:160ms 101: 320ms 110: 640ms 111: 1280ms - - - depop_finish waiting time 000: 10ms 001: 20ms 010: 40ms 011: 80ms 100:160ms 101: 320ms 110: 640ms 111: 1280ms - - - CHG_EN_Delay time 00: 1Tclk 01: 2Tclk 10: 4Tclk 11: 8Tclk - - - depop path on delay time 00: 1Tclk 01: 2Tclk 10: 4Tclk 11: 8Tclk - - - DCCALI_IDAC_repeat_goal 000: 8 001: 9 010: 10 011:11 100:12 101:13 110:14 111:7 - - - IDAC LSB SETTING: 00: 10nA 01:15nA 10:5nA 11:10nA - - - RDAC current enhancement 0 = X1 1 = X2 - - - - - - DC-calibraion start signal 0 ---> 1 start calibration - - - DC-calibraion enable signal (digital) 0: disable 1: enable - - - DC-calibraion enable signal (analog) 0: disable 1: enable - - - Audio DC-calibration status signal 0 = unfinish/have never done 1 = finish - - - DCCALI_STS_BYPASS=0, not bypass DCCALI_process DCCALI_STS_BYPASS=1, bypass DCCALI_process - - - Audio DC-calibration finish insert signal 0 = unfinish 1 = finish - - - depop start signal 0 ---> 1 start calibration - - - depop charge en 0: disable 1:enable - - - plug_in=1, headphone has been inserted - - - depop_ana_en 0: disable 1:enable - - - Audio plug-in depop status signal 0 = depop not finish 1 = depop finish - - - Audio plug-in depop charge finish insert signal 0 = unfinish 1 = finish - - - HPL_pull_up enable 0: pull up enable 1: pull up disable - - - HPR_pull_up enable 0: pull up enable 1: pull up disable - - - INSBUF_EN 0: disable 1:enable - - - - - Reserved - - - AUD_DRV_DEPOP_BIAS_CURRENT SEL 00: 1.25uA 01:2.5uA 10:3.75uA 11:5uA - - - AUD_DRV_DEPOP_OPA_CURRENT SEL 00: LS_I=5uA, LS_R=100K 01: LS_I=10uA, LS_R=100K 10: LS_I=5uA, LS_R=50K 11: LS_I=10uA,LS_R=50K - - - Hardware control/software control sel <3>: 0: depend on analog comp value 1: bypass analog comp value <2>: 0: RG_AUD_VCMI_SEL change, repeat dccali 1: change RG_AUD_VCMI_SEL, get two dccali value, choose any according RG_AUD_VCMI_SEL =0/=1 <1>: 0: hw control DC_CALI_IDAC_CURSEL, 1: sw control DC_CALI_IDAC_CURSEL <0>: 0: hw control RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN 1: sw control RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN - - - - - HPL_DCCALI_RDAC_VALUE - - - HPR_DCCALI_RDAC_VALUE - - - HPL_DCCALI_IDAC_path - - - HPR_DCCALI_IDAC_path - - - - - HPL_DCCALI_IDAC_VALUE - - - HPR_DCCALI_IDAC_VALUE - - - HPL_DCCALI_IDAC_VALUE - - - HPR_DCCALI_IDAC_VALUE - - - - - Audio PA clock calibration data delta output - - - Audio PA clock calibration data valid signal 0 = not valid 1 = data valid - - - - - Audio headset insert alert signal (need software anti-dither) 0 = normal 1 = plug in - - - Audio headset-H insert alert signal (need software anti-dither) 0 = normal 1 = plug in - - - Audio headset-L insert alert signal (need software anti-dither) 0 = normal 1 = plug in - - - Audio headset microphone insert alert signal (need software anti-dither) 0 = normal 1 = plug in - - - Audio headset microphone button press alert signal (need software anti-dither) 0 = normal 1 = button press - - - Audio PA output short to VBAT detect ALERT signal 0 = normal 1 = short - - - Audio PA output short to GND detect ALERT signal 0 = normal 1 = short - - - Audio PA over voltage protection circuit alert signal 0 = normal 1 = over temperature - - - Audio PA over temperature protection circuit alert signal 0 = normal 1 = over temperature - - - Audio Driver over current protection circuit alert signal <3:2> for SPK <1:0> for Headphone/Earpiece - - - - - DCDC GEN/MEM clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 - - - DCDC CORE clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 - - - DCDC CHG clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 - - - Audio PA clock frequency select (based on ADC Clock) 00 = 1/2 01 = 1/4 10 = 1/8 11 = 1/16 - - - Audio clock PN select (If RG_AUD_AD_CLK_F[1:0]=00 or 10 & RG_AUD_DA_CLK_F[1:0]=00, RG_AUD_CLK_PN_SEL) <0> CLK_AUD_DIG_LOOP <1> CLK_AUD_DIG_6P5M <2> CLK_AUD_DAC <3> CLK_AUD_ADC <4> CLK_AUD_DCDCGEN <5> CLK_AUD_VAD_CLK_SEL <6> CLK_AUD_DCDCCORE <7> RG_AUD_VB_V<5> - - - - - - - - - - - ADC FIFO almost full signal - - - ADC FIFO real empty. There is no data in ADC FIFO - - - ADC FIFO real full. - - - ADC FIFO read address - - - ADC FIFO write address - - - - - DAC FIFO real empty. There is no data in ADC FIFO - - - DAC FIFO real full. - - - DAC FIFO read address - - - DAC FIFO write address - - - - - Internal fsm state - - - Internal counter - - - Internal counter - - - If 1, begin to receive data from A-die - - - - - - - - - - - - - BLTC WLED output value when by SW. - - - BLTC WLED output selection 1: output by SW; 0: output by HW. - - - BLTC WLED output type 1: Normal PWM; 0: Breath light. - - - BLTC WLED run 1: start BLTC WLED; 0: stop BLTC WLED. - - - BLTC B output value when by SW. - - - BLTC B output selection 1: output by SW; 0: output by HW. - - - BLTC B output type 1: Normal PWM; 0: Breath light. - - - BLTC B run 1: start BLTC B; 0: stop BLTC B. - - - BLTC G output value when by SW. - - - BLTC G output selection 1: output by SW; 0: output by HW. - - - BLTC G output type 1: Normal PWM; 0: Breath light. - - - BLTC G run 1: start BLTC G; 0: stop BLTC G. - - - BLTC R output value when by SW. - - - BLTC R output selection 1: output by SW; 0: output by HW. - - - BLTC R output type 1: Normal PWM; 0: Breath light. - - - BLTC R run 1: start BLTC R; 0: stop BLTC R. - - - - - BLTC prescale coefficient. - - - - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - - BLTC prescale coefficient. - - - - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - - BLTC prescale coefficient. - - - - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - - BLTC WLED busy, active high. - - - BLTC B busy, active high. - - - BLTC G busy, active high. - - - BLTC R busy, active high. - - - - - Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) - - - - - Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) - - - - - Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) - - - - - Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) - - - - - BLTC prescale coefficient. - - - - - PWM duty counter,duty cycle = duty /(mod+1) - - - PWM mod counter. - - - - - Output falling time, its unit is 0.125s, it should be >0. - - - Output rising time, its unit is 0.125s, it should be >0. - - - - - Output low time, its unit is 0.125s, it should be >0. - - - Output high time, its unit is 0.125s, it should be >0. - - - - - Power down signal 0:bltc_pd depend on SW_PD 1:bltc_pd depend on bltc output - - - Power down signal : 0: Power on the reference current source 1: Power down the reference current source - - - - - BLTC_VERSION information Default value is 16h0100 (r1p0) - - - - - - - - - Write this bit 1 will start calibration process, write 0 has no effect Read this this will get the current calibration status. If 1, means the calibration is on progress. If 0, means calibration is finished, current is idle. - - - - - Calibration cycle control, this is the low part of calibration cycle. Coupled with CAL_CYCLE_P1[7:0], the whole calibration cycles is : Calibration cycle = {CAL_CYCLE_P1[7:0],CAL_CYCLE_P0[15:0]}; The calibration cycle means using how many self-oscillator clocks to do calibration, the more cycles used, the more accuracy will be achieved. To make calculation simple, calibration cycle should be multiple of 2, that means, Calibration cycle = 2^n - - - - - Calibration cycle control, this is the high part of calibration cycle. - - - - - Calibration result, part 0. Coupled with CAL_RESULT_P1, the total calibration result is : Cal result = {CAL_RESULT_P1[15:0],CAL_RESULT_P0[15:0]} - - - - - Calibration result, part 1. - - - - - Write this bit 1 will start 32k sigma-delta divider factor update process. write 0 has no effect Read this this will get the current update process status. If 1, means the update process is not finished. If 0, means this process is finished,current is idle. - - - - - 32k sigma-delta divider factor fraction part. This field is part of the fraction bits. - - - - - 32k sigma-delta divider integer. - - - - - Factor update done interrupt enable - - - Calibration done interrupt enable.. - - - - - Write 1 to this bit will clear OSC_FAC_UPD_DONE_INT_RAWWrite 0 has no effect - - - Write 1 to this bit will clear OSC_CAL_DONE_INT_RAWWrite 0 has no effect - - - - - Interrupt raw bits, 1 means factor update process has finished. - - - Interrupt raw bits, 1 means self-oscillator calibration process has finished. - - - - - - - - - 0: Function test mode -1: Analog test mode - - - 0: IOMODE -1-255: Analog Test Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EIC bits data input. -Note: EICDATA synchronizes the original data inputs with 2 cycles of Rtcdiv5_clk, so SW need delay 2ms to get the exact value of original data inputs when Rtcdiv5_clk is enabled. - - - - - bit type is changed from r/w to rw. - EICDATA register can be read if EICDMSK set 1 - - - - - - - - - - - EIC bits interrupt status register:1 high levels trigger interrupts, 0 low levels trigger interrupts. - - - - - EIC bits interrupt enable register:1 corresponding bit interrupt is enabled. 0 corresponding bit interrupt isnt enabled - - - - - EIC bits raw interrupt status register:1 interrupt condition met0 condition not met - - - - - EIC bits masked interrupt status register:1 Interrupt active 0 interrupt not active - - - - - EIC bits interrupt clear register:1 clears detected interrupt. 0 has no effect. - - - - - EIC bits trig control register:1: generate the trig_start pulse0: no effect It must set EICTRIG for using de-bounce function and getting active interrupt. - - - - - - - - - - - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - 1: clock of dbnc forced open; 0: no effect - - - de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) - - - de-bounce counter period value setting, the unit is millisecond - - - - - - - - - Reserved - - - Reserved - - - 0: Normal read mode, 1:Margin read1 mode - - - - - Efuse read data, -If SW use efuse controller to send a read command to efuse memory, the return value will store here. - - - - - Efuse data to be write. -If SW want to program the efuse memory, the data to be programmed will write to this register before SW issue a PGM command. - - - - - The efuse memory block index to be read or write. - - - - - Write 1 to this bit will clear normal read flag. This bit is self-clear, read this bit will always get 0 - - - Write 1 to this bit start READ mode(read mode). This bit is self-clear, read this bit will always get 0 - - - Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0 - - - - - 1 indicate EFUSE normal read has been done - - - If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1. - - - 1 indicate efuse memory in standby mode - - - 1 indicate efuse memory in read mode - - - 1 indicate efuse memory in programming mode - - - - - Magic number, only when this field is 0x2720, the Efuse programming command can be handle. -So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : -a) PGM_EN =1; -b) EFUSE_MAGIC_NUMBER = 0x2720 - - - - - Magic number, only when this field is 0x6868, the margin read is usable. - - - - - Config this register to control the timing of writing operation related signals. -300us voltage rise,20usx16 program,300us voltage fall - - - - - Config this register to control the timing of writing operation related signals -2.348us Read Time - - - - - - - - - - - - - Qmax Update enables. Write 1 to this bit will do a Qmax update processing. It is auto cleared to 0, after write 1. To check the updating status, please read QMAX_UPD_STS. - - - FGU Reset signal. Write this bit to reset the module, it is auto cleared to 0 after reset. - - - When write CLBCNT_SETH & CLBCNT_SETL, software should write this bit after write all of the two register to sync. It to CLK32KHz domain. - - - - - bit type is changed from r/w to rw. - Software force qmax low voltage area to be locked, (Need to check WRITE_ACTIVE_STS) - - - bit type is changed from r/w to rw. - Software force qmax high voltage area to be locked - - - bit type is changed from r/w to rw. - When set to 1, qmax counter will be forced to intergrate current, regardless of qmax lock conditions. - - - bit type is changed from r/w to rw. - Voltage high bit valid 0: voltage is 12 bits valid (high bit is omitted) 1: voltage is 13 bits valid - - - bit type is changed from r/w to rw. - FGU Disable signal. It indicates if the FGU is worked or not. 0: FGU is not disable and worked 1: FGU is disable and not worked - - - bit type is changed from r/w to rw. - Coulomb Counter Delta Threshold Mode. This bit indicates if the coulomb counter is working when the battery is in low power condition. 0: work when in low power condition 1: no work when in low power condition It is working in default. - - - bit type is changed from r/w to rw. - Voltage duty ratio. 2h0: 1-7 2h1: 1-3 2h2: 1-1 2h3: 1-0 When ADC_SEL = 0, these bits are invalid. Refer to Timing Diagram for detail - - - bit type is changed from r/w to rw. - When just use voltage of this module, this bit can disable all the current calculation logic, which will save power. 0: not disable current 1: disable current logic - - - bit type is changed from r/w to rw. - When update the Qmax, if the battery is not in relax mode, then the voltage wont lock, write this bit will force the voltage lock to OCV either the battery is in relax mode or in active mode. 0: not force lock 1: force lock - - - bit type is changed from r/w to rw. - There are 2 methods to judge whether the battery is in low power mode. 0: use relax counter to judge 1: use deep_sleep signal to judge - - - bit type is changed from r/w to rw. - When the battery is in relax mode, the current can be set to sample at each 1 second instead of each 500ms, which will save power. If this bit is set 1, then the module will auto switch to low power mode. 0: not auto low, SW should control manually 1: auto low when the battery is in relax mode. -Note: when AD1_ENABLE = 0, the voltage and current is measured in ADC0 -Note: when AD1_ENABLE = 1, the current is measured in ADC0, and voltage is measured in ADC1. - - - - - bit type is changed from r/w to rw. - RG_SD_RSV[14] - - - bit type is changed from r/w to rw. - Enable Common voltage tied to ground - - - bit type is changed from r/w to rw. - Enable high current mode - - - bit type is changed from r/w to rw. - Enable reference band gap - - - bit type is changed from r/w to rw. - When ADC_EN_SEL is 0, ADC enable is always high When ADC_EN_SEL is 1, FGU takes the control of ADC enable - - - Ad0_in_data - - - Ad1_in_data - - - bit type is changed from r/w to rw. - Force ADC1_VIN_EN interface to set value. - - - bit type is changed from r/w to rw. - Force ADC0_VIN_EN interface to set value. - - - bit type is changed from r/w to rw. - Force ADC0_IIN_EN interface to set value. - - - bit type is changed from r/w to rw. - Force ADC0/ADC1 interface enable. - - - bit type is changed from r/w to rw. - ADC1 Voltage Reference. 0: 0.1V 1: 0.2V - - - bit type is changed from r/w to rw. - ADC0 Voltage Reference. 0: 0.1V 1: 0.2V - - - bit type is changed from r/w to rw. - ADC0 / ADC1 Reset - - - bit type is changed from r/w to rw. - ADC0 / ADC1 Power Down - - - - - This flag indicates whether the battery is plugged in during power on sequence. - - - This flag indicates the power on open circuit voltage measurement is invalid. - - - Select current and voltage enable signal between fgu_top and fgu_ana 0: select fgu_ana current and voltage enable signal 1: select fgu_top current and voltage enable signal - - - Indicate the power is lower 0: not lower 1: lower Note: Case LOW_POWER_MODE = 0 when CURT_LOW is 1 and the relax counter is bigger than threshold, then the power is low. Case LOW_POWER_MODE = 1; The power mode select the deepsleep, then it is equal to deepsleep signal. - - - Indicate the current is lower then threshold 0: not lower 1: lower Note: when CURT_LOW is occur, the POWER_LOW may not occur other than the relax count is bigger than threshold. - - - To update the Qmax, there should be two OCV lock. 2b00: OCV0 not locked OCV1 not locked. 2b01: OCV0 locked first OCV1 locked second. 2b10: OCV0 locked first OCV1 locked second 2b11: Invalid When both of them are locked, the Qmax is locked. - - - Qmax updating status 0: not in updating process. 1: in updating process. - - - When write following register, software should check this register to know whether it has been sync. to clk32KHz domain. FGU_CONFIG, ADC_CONFIG, FGU_INT_EN, FGU_HIGH_OVER, FGU_LOW_OVER, FGU_CLBCNT_SETH, FGU_CLBCNT_SETL - - - - - bit type is changed from r/w to rw. - When the CLBCNT is lower than wet clbcnt low threshold , then interrupt - - - bit type is changed from r/w to rw. - When the OCV is lower than set ocv low threshold, then interrupt - - - bit type is changed from r/w to rw. - When Current data is ready, an interrupt is generated. It is used when calibration. - - - bit type is changed from r/w to rw. - When Voltage data is ready, an interrupt is generated. - - - bit type is changed from r/w to rw. - Qmax update timeout interrupt Enable - - - bit type is changed from r/w to rw. - Qmax update done interrupt Enable - - - bit type is changed from r/w to rw. - Relax Counter interrupt Enable. When the relax counter reached its set threshold, an interrupt is generated. - - - bit type is changed from r/w to rw. - Coulomb counter threshold interrupt Enable When the Coulomb counter reached the multiply of the threshold, then an interrupt is generated. E.g. If set CLBCNT_DELTA = 5mAh, then when the Coulomb counter is 5mAh, 10mAh, 15mAh will generate interrupt. - - - bit type is changed from r/w to rw. - Voltage High overload interrupts Enable. When the voltage is higher than the threshold, then an interrupt is generated. - - - bit type is changed from r/w to rw. - Voltage Low overload interrupt Enable. When the voltage is lower than the threshold, then an interrupt is generated. - - - - - CLBCNT lower interrupt clear - - - OCV lower interrupt clear - - - Current ready interrupt clear - - - Voltage ready interrupt clear - - - Qmax update timeout interrupt clear - - - Qmax update done interrupt clear - - - Relax counter interrupt clear - - - Coulomb counter delta interrupt clear - - - Voltage High overload interrupts clear. - - - Voltage Low overload interrupts clear. - - - - - CLBCNT lower interrupt raw status - - - OCV lower interrupt raw status - - - Current ready interrupt raw status - - - Voltage ready interrupt raw status - - - Qmax update timeout interrupt raw status - - - Qmax update done interrupt raw status - - - Relax counter interrupt raw status - - - Coulomb counter delta interrupt raw status - - - Voltage High overload interrupts raw status. - - - Voltage Low overload interrupts raw status. - - - - - CLBCNT lower interrupt status - - - OCV lower interrupt status - - - Current ready interrupt status - - - Voltage ready interrupt status - - - Qmax update timeout interrupt status - - - Qmax update done interrupt status - - - Relax counter interrupt status - - - Coulomb counter delta interrupt status - - - Voltage High overload interrupts status. - - - Voltage Low overload interrupts status. - - - - - Voltage now It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - Open Circuit Voltage. It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - Open Circuit Value read at the very beginning of 250ms - - - - - Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - bit type is changed from r/w to rw. - Voltage High overload threshold. It is forbidden that the battery voltage is higher than the voltage max threshold. If it violates that, the battery may be destroyed. Once it reaches this value, an interrupt is generated to notify the software to do something to deal with it. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Voltage low overload threshold. Once the battery voltage is lower than the set threshold, the device will not Work at any moment. To avoid the lost of data, the software should save the data and shut down the device when a lower threshold interrupt is generated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Voltage High-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshod of the locked high OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Voltage High-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked high OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Voltage Low-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshold of the locked low OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Voltage Low-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked low OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid - - - - - Qmax OCV record Low point The Low OCV record of Qmax updated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13] is omitted, and just 12 bit is valid - - - - - Qmax OCV record High Point The High OCV record of Qmax updated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13] is omitted, and just 12 bit is valid - - - - - bit type is changed from r/w to rw. - Set Coulomb Counter Value register, bit[29:16] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_SET_IND = 2h0, then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point -Note: the Coulomb Counter is 28 bits, and it is distributed in two register, after both of them are set, then it can be valid. When first write CLBCNT_SETH, then CLBCNT_SET_IND[1] is high to indicate it; second write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable.When first write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it; second write CLBCNT_SETH then CLBCNT_SET_IND[1] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable. - - - - - bit type is changed from r/w to rw. - Set Coulomb Counter Set Value register. bit[15:0]] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_H_IND =0 & CLBCNT_L_IND = 0), then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point - - - - - bit type is changed from r/w to rw. - Coulomb Counter Delta register, bit[29:16] Once the coulomb is changed multiply of the Coulomb counter threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point - - - - - bit type is changed from r/w to rw. - Coulomb Counter Delta register, bit[:15:0] Once the coulomb is changed multiply of the Coulomb counter delta threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point - - - - - Coulomb Counter Last OCV register, bit[31:16] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point 32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value point - - - - - Coulomb Counter Last OCV register, bit[15:0] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value - - - - - Coulomb Counter Value register, bit[31:16] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: maxpositive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value - - - - - Coulomb Counter Value register, bit[15:0] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value - - - - - Coulomb Counter Qmax Value, bit[31:16] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value - - - - - Coulomb Counter Qmax Value, bit[15:0] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Note: after Power On, it saved the first sampled Curt data, unsigned, and just 250ms data.14bits. or said POCI. - - - - - bit type is changed from r/w to rw. - FGU Qmax timeout set counter. When the Qmax update exceed the timeout set counter, then the Qmax quit and it is failed to update. The unit of the counter is 4 seconds, so the max value is 72.8 hours. Note: when the QMAX_TIMEOUT_CNT is 0, it means it is never timeout. - - - - - FGU Qmax timer counter. Once the Qmax is updating, the timer is counted from 0. After the Qmax is updated, the timer is stay on the last value until the next update process start. The unit of the counter is 4 seconds, so the max value is 72.8 hours. - - - - - bit type is changed from r/w to rw. - Relax Current threshold. It is unsigned value, It is a tiny value which will add or subtract the zero value (14h1FFF) of the CURT_VALUE, to indicate a low current threshold. And it will define the conception of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state. And then the relax counter will work to count, else it clear to 0. - - - - - bit type is changed from r/w to rw. - Relax counter threshold. When the counter reaches to this value, it stops at this value. The unit is 1 second. 13h1 means 1 second - - - - - Relax counter value. The relax counter register is 13 bit read-only register clocked every 1s and can go up to about 2hs. The counter is auto clearer to 0 when the current is out of the relax state. Definition of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state. - - - - - OCV Last count. After the OCV is locked, this counter will count how many times it keeps The unit is 1 second, and the max count is about 9 hours, if the count is bigger than 18hrs, than the count is keep its max value 16hFFFF. - - - - - Current offset value, It is signed value, and 2s complement value. Used to adjust the calibration current value. - - - - - - - - - - - bit type is changed from r/w to rw. - For software to set this area, where the data will be kept in USER_AREA_STS0 if the RTC clock is working. - - - - - bit type is changed from r/w to rw. - For software to clear this area, Set 1, the data kept in USER_AREA_STS0 will be cleared. Set 0, after clearing the status, the register value will be set back to 0 - - - - - The data will be kept in if RTC clock is working - - - - - - - Open Circuit Current. Refer to the Current Value. - - - - - bit type is changed from r/w to rw. - The OCV low threshold. When the real OCV lower than this register, then an interrupt is occurred. - - - - - bit type is changed from r/w to rw. - The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred. Its higer part. - - - - - bit type is changed from r/w to rw. - The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred. - - - - - bit type is changed from r/w to rw. - For software to set this area, where the data will be kept in USER_AREA_STS1 if the RTC clock is working. - - - - - bit type is changed from r/w to rw. - For software to clear this area, Set 1, the data kept in USER_AREA_STS1 will be cleared. Set 0, after clearing the status, the register value will be set back to 0 - - - - - The data will be kept in if RTC clock is working - - - - - Power On Open Circuit Voltage. If is just valid when the very time of power on . It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - Qmax Lock Low Point current value It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - Qmax Lock High Point current value It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000:represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - Legacy Open Circuit Voltage Value for Debug It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. - - - - - bit type is changed from r/w to rw. - Select which type of data being shit out to pad 0: current value 1: voltage value - - - bit type is changed from r/w to rw. - ATE test voltage time mode 3b000: 15.6ms 3b001: 31.25ms 3b010: 62.5ms 3b011: 125ms 3b100: 250ms 3b101: 500ms - - - bit type is changed from r/w to rw. - ATE test current time mode 3b000: 15.6ms 3b001: 31.25ms 3b010: 62.5ms 3b011: 125ms 3b100: 250ms 3b101: 500ms - - - - - ATE test current value saved register It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value - - - - - ATE test voltage value saved register It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. - - - - - - - - - CHIP ID low 16 bits - - - - - CHIP ID high 16 bits - - - - - TMR module enable 0: Disable the PCLK of timer 1: Enable the PCLK of timer - - - PSM module enable 0: Disable the PCLK of PSM 1: Enable the PCLK of PSM - - - BLTC module enable 0: Disable the PCLK of BLTC 1: Enable the PCLK of BLTC - - - PINREG module enable 0: Disable the PCLK of pin registers 1: Enable the PCLK of pin registers - - - FGU module enable 0: Disable the PCLK of FGU 1: Enable the PCLK of FGU - - - Efuse module enable 0: Disable the PCLK of efuse ctrl 1: Enable the PCLK of efuse ctrl - - - AUXADC module enable 0: Disable the PCLK of AUXADC 1: Enable the PCLK of AUXADC - - - Audio module enable 0: Disable the PCLK of Audio 1: Enable the PCLK of Audio - - - EIC module enable 0: Disable the PCLK of EIC 1: Enable the PCLK of EIC - - - WDG module enable 0: Disable the PCLK of watchdog 1: Enable the PCLK of watchdog - - - RTC module enable 0: Disable the PCLK of RTC 1: Enable the PCLK of RTC - - - CAL module enable 0: Disable the PCLK of CAL 1: Enable the PCLK of CAL - - - - - AUXAD clock enable, the clock is connected to AUXADC converter 0: disable AUXAD_CLK 1: enable AUXAD_CLK - - - AUXADC module work clock enable 0: disable clk_adc 1: enable clk_adc - - - Calibration module clock source select 2'b00: 32K-less 1MHZ clock 2'b01: DCDC_CLK2M_OUT 2'b10: DCDC_CLK3M_OUT 2'b11: N/A - - - CLK_CAL eanble 0: disable clk_cal 1: enable clk_cal - - - Audio 6.5M clock enable 0: disable clk_aud_6p5m_rx and clk_aud_6p5m_tx 1: enable clk_aud_6p5m_rx and clk_aud_6p5m_tx - - - Audio IF clock enable 0: disable CLK_AUDIF 1: enable CLK_AUDIF - - - - - TIMER RTC clock soft enable 0: Disable the RTC clock of timer 1: Enable RTC clock of timer - - - FLASH controller RTC clock enable 0: Disable the RTC clock of FLASH controller 1: Enable RTC clock of FLASH controller - - - EFS RTC clock soft enable 0: Disable the RTC clock of EFS 1: Enable RTC clock of EFS - - - BLTC RTC clock soft enable 0: Disable the RTC clock of BLTC 1: Enable RTC clock of BLTC - - - FGU RTC clock soft enable 0: Disable the RTC clock of FGU 1: Enable RTC clock of FGU - - - EIC RTC clock soft enable 0: Disable the RTC clock of EIC 1: Enable RTC clock of EIC - - - Watchdog RTC clock soft enable 0: Disable the RTC clock of Watchdog 1: Enable RTC clock of Watchdo - - - RTC RTC clock soft enable 0: Disable the RTC clock of RTC 1: Enable RTC clock of RTC - - - ARCH RTC clock soft enable 0: Disable the RTC clock of ARCH 1: Enable RTC clock of ARCH - - - - - AUD RX soft reset - - - AUD TX soft reset - - - BLTC soft reset - - - Audio IF soft reset - - - Efuse soft reset - - - Auxadc soft reset - - - PSM apb soft reset - - - FGU soft reset - - - EIC soft reset - - - Watchdog soft reset - - - RTC soft reset - - - CAL soft reset - - - - - TMR soft reset - - - - - LDO_DCXO power down 1: power down 0: power on - - - EMM domain power down 1: power down 0: power on - - - LDO of charge pump power down 1: power down 0: power on - - - DCDC_GEN power down 1: power down 0: power on - - - DCDC_CORE power down 1: power down 0: power on - - - internal oscillator enable 1'b0: oscillator off 1'b1: oscillator on - - - LDO_MEM power down 1: power down 0: power on - - - LDO_ANA power down 1: power down 0: power on - - - LDO_VDD28 power down 1: power down 0: power on - - - Bandgap power down 1: power down 0: power on - - - - - Power off_sequence enable - - - - - register soft reset,write 1 can: 1 reset total system 2 power down and up - - - - - - - - - - - clock output enable - - - phase shift option 1'b0: default, w/i 1/5 phase shift at internal mode 1'b1: uni-phase mode, all ouputs = channel 0 - - - clock selection for each channel RG_CLKOUT_SEL<0>: VCORE clk selection RG_CLKOUT_SEL<1>: VGEN clk selection RG_CLKOUT_SEL<2>: VPA clk selection 0: internal mode, default 1: external mode - - - soft reset of all dcdc generated clk - - - oscillator frequency tuing, (1/16)/step 4'b0000: default 3MHz 4'b0001: -1 step 4'b0111: -7 step 4'b1000: +8 step 4'b1111: +1 step - - - - - current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% - - - current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% - - - PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V - - - compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k - - - slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x - - - high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset - - - - - reference voltage trimming (base on 1.2V) 3'b000: default 3'b001: +12.5mV 3'b010: +25mV 3'b011: +37.5mV 3'b100: -50mV 3'b101: -37.5mV 3'b110: -25mV 3'b111: -12.5mV - - - force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off - - - force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode - - - anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on - - - - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCCORE, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 - - - - - output voltage selection, 3.125mV/step 9'b111100000: 1.5V 9'b111000000: 1.4V 9'b110100000: 1.3V 9'b110000000: 1.2V 9'b101100000: 1.1V 9'b101000000: 1.0V 9'b100100000: 0.9V 9'b100000000: 0.8V 9'b011100000: 0.7V 9'b011000000: 0.6V - - - - - current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% - - - current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% - - - PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V - - - compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k - - - slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x - - - high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset - - - - - force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off - - - reserved - - - force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode - - - anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on - - - - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCGEN, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 - - - - - output voltage selection, 12.5mV/step. 8'b00000000= 1.3V 8'b00001000= 1.4V 8'b00010000= 1.5V 8'b00011000= 1.6V 8'b00100000= 1.7V 8'b00101000= 1.8V 8'b00110000= 1.9V 8'b00111000= 2.0V 8'b01000000= 2.1V 8'b01001000= 2.2V 8'b01010000= 2.3V 8'b01011000= 2.4V 8'b01100000= 2.5V 8'b01101000= 2.6V 8'b01110000= 2.7V 8'b01111000= 2.8V - - - - - current limit threshold tuning 2'b00: default 2'b01: -0.5pF 2'b10: +1pF 2'b11: +0.5pF - - - current sense multiplier tuning 2'b00: default, x1 2'b01: x0.5 2'b10: x2 2'b11: x1.5 - - - compensation C3 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% - - - PFM mode threshold for upper limit 2'b00: default 2'b01: -50mV 2'b10: +50mV 2'b11: +100mV - - - compensation R2 select 2'b00: default, 960k 2'b01: 880k 2'b10: 1040k 2'b11: 1120k - - - compensation R3 select 2'b00: default, 5k 2'b01: 2.5k 2'b10: 10k 2'b11: 7.5k - - - sawtooth tuning manully 2'b00: default 2'b01: +15% 2'b10: -30% 2'b11: -15% - - - high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - - - low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x - - - - - zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset - - - anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on - - - APC mode enable 1'b0: default, RG control mode 1'b1: APC mode - - - APC ramp selection 1'b0: default, 2.0x ramp 1'b1: 2.5x ramp - - - bypass mode disable 1'b0: default, auto bypass 1'b1: bypass off - - - bypass force on 1'b0: default, auto bypass 1'b1: force bypass mode on - - - bypass mode threshold 2'b00: default, ~200mV - - - DVS control 1'b0: default, off 1'b0: on, for DCM down discharge - - - 100% duty selection 1'b0: default, max duty=100% 1'b1: max duty ~95% - - - - - clock gating enable - - - the phase difference, 26M per step - - - the division factor from 26M for DCDCWPA, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 - - - force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off - - - sawtooth calibration 1'b0: default, auto calibration before power-on 1'b1: calibration manully - - - DCDC power down 1'b0: DCDC on 1'b1: DCDC power down - - - - - output voltage selection, 25mV/step. 7'b1111100= 3.5V 7'b1110000= 3.2V 7'b1100000= 2.8V 7'b1010000= 2.4V 7'b1000000= 2.0V 7'b0110000= 1.6V 7'b0100000= 1.2V 7'b0010000= 0.8V 7'b0000000= 0.4V - - - - - force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode - - - - - DCDC to AUXADC trim channel selection 3'b001: select VCORE 3'b010: select VGEN (VGEN*18/37) 3'b011: select VPA (VPA*18/68) RG_DCDC_AUXTRIM_SEL<2>, internal test mode select: 0: default, internal test mode disable 1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path 3'b100: enpwm_vgen 3'b101: zx_vgen 3'b110: enpwm_vcore 3'b111: zx_vcore - - - - - - - - - - - - - - - LDO short protection power down - - - ANA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - ANA LDO bypass application: default 1'b0, no bypass default 1'b1, bypass - - - ANA LDO stability compensation: default 2'b00 - - - ANA LDO foldback current threshold adjust: default 1'b0 - - - ANA LDO current limit threshold adjust: default 1'b0 - - - - - ANA LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.8V, 6'b100000 - - - - - - - - - RF15 LDO short protection - - - RF15 LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - RF15 LDO bypass application: default 1'b0, no bypass default 1'b1, bypass - - - RF15 LDO stability compensation: default 2'b00 - - - RF15 LDO foldback current threshold adjust: default 1'b0 - - - RF15 LDO current limit threshold adjust: default 1'b0 - - - LDO_RF15 power down 1: power down 0: power on - - - - - RF15 LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.5V, 6'b1000 - - - - - - - - - CAMD LDO short protection - - - CAMD LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - CAMD LDO bypass application: default 1'b0, no bypass default 1'b1, bypass - - - CAMD LDO stability compensation: default 2'b00 - - - CAMD LDO foldback current threshold adjust: default 1'b0 - - - CAMD LDO current limit threshold adjust: default 1'b0 - - - LDO_CAMD power down 1: power down 0: power on - - - - - CAMD LDO program bits:12.5mV/step, 1.4V~2.1875V; default 1.8V, 6'b100000 - - - - - CON LDO short protection - - - CON LDO bypass application: default 1'b0, no bypass default 1'b1, bypass - - - CON LDO stability compensation: default 2'b00 - - - CON LDO foldback current threshold adjust: default 1'b0 - - - CON LDO current limit threshold adjust: default 1'b0 - - - LDO_CON power down 1: power down 0: power on - - - - - CON LDO program bits: 12.5mV/step, 1.1V~1.8875V; default 1.5V, 6'b100000 - - - - - MEM LDO short protection - - - MEM LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - MEM LDO bypass application: default 1'b0, no bypass default 1'b1, bypass - - - MEM LDO stability compensation: default 2'b00 - - - MEM LDO foldback current threshold adjust: default 1'b0 - - - MEM LDO current limit threshold adjust: default 1'b0 - - - - - MEM LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 6'h100000, 1.8V - - - - - SIM0 LDO short protection - - - SIM0 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - SIM0 LDO stability compensation: default 2'b10 - - - SIM0 LDO foldback current threshold adjust: default 1'b1 - - - SIM0 LDO current limit threshold adjust: default 1'b1 - - - - - LDO_SIM0 power down 1: power down 0: power on - - - - - SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 - - - - - SIM1 LDO short protection - - - SIM1 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - SIM1 LDO stability compensation: default 2'b10 - - - SIM1 LDO foldback current threshold adjust: default 1'b1 - - - SIM1 LDO current limit threshold adjust: default 1'b1 - - - - - LDO_SIM1 power down 1: power down 0: power on - - - - - SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 - - - - - - - - - - - CAMA LDO short protection - - - CAMA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - CAMA LDO stability compensation: default 2'b10 - - - CAMA LDO foldback current threshold adjust: default 1'b1 - - - CAMA LDO current limit threshold adjust: default 1'b1 - - - LDO_CAMA power down 1: power down 0: power on - - - - - CAMA LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111 - - - - - LCD LDO short protection - - - LCD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - LCD LDO stability compensation: default 2'b10 - - - LCD LDO foldback current threshold adjust: default 1'b1 - - - LCD LDO current limit threshold adjust: default 1'b1 - - - LDO_LCD power down 1: power down 0: power on - - - - - LCD LDO program bits: 12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 - - - - - MMC LDO short protection - - - MMC LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - MMC LDO stability compensation: default 2'b10 - - - MMC LDO foldback current threshold adjust: default 1'b1 - - - MMC LDO current limit threshold adjust: default 1'b1 - - - - - LDO_MMC power down 1: power down 0: power on - - - - - MMC LDO program bits: 12.5mV/step, 2V~3.5875V; default 3.0V, 7'b1010000 - - - - - SD LDO short protection - - - SD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - SD LDO stability compensation: default 2'b10 - - - SD LDO foldback current threshold adjust: default 1'b1 - - - SD LDO current limit threshold adjust: default 1'b1 - - - - - LDO_SD power down 1: power down 0: power on - - - - - SD LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.8V, 7'b100000 - - - - - DDR12 LDO short protection - - - DDR12 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - DDR12 LDO stability compensation: default 2'b10 - - - DDR12 LDO foldback current threshold adjust: default 1'b1 - - - DDR12 LDO current limit threshold adjust: default 1'b1 - - - - - LDO_DDR12 power down 1: power down 0: power on - - - - - DDR12 LDO program bits: 12.5mV/step, 0.8V~1.5875V ; default 1.25V, 7'b100100 - - - - - VDD28 LDO short protection - - - VDD28 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - VDD28 LDO stability compensation: default 2'b10 - - - VDD28 LDO foldback current threshold adjust: default 1'b1 - - - VDD28 LDO current limit threshold adjust: default 1'b1 - - - - - VDD28 LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111 - - - - - SPIMEM LDO short protection - - - SPIMEM LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - SPIMEM LDO stability compensation: default 2'b10 - - - SPIMEM LDO foldback current threshold adjust: default 1'b1 - - - SPIMEM LDO current limit threshold adjust: default 1'b1 - - - LDO_SPIMEM power down 1: power down 0: power on - - - - - SPIMEM LDO program bits:12.5mV/step, 1.75V~3.3375V; default is select by V_SPIMEM pad, when V_SPIMEM ==0, spimem voltage is 1.8V, register default is 7'b100 -when V_SPIMEM ==1, spimem voltage is 3.3V, register default is 7b1111100 - - - - - LDO DCXO trim bits: 5mV/step, 0.72V~0.875V; default 1.2V, 5'b10000 - - - DCXO LDO short protection - - - DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - DCXO LDO stability compensation: default 2'b10 - - - DCXO LDO foldback current threshold adjust: default 1'b1 - - - DCXO LDO current limit threshold adjust: default 1'b1 - - - - - DCXO LDO program bits: 12.5mV/step, 1.5V~3.0875V ; default 1.8V, 7'b0011000 - - - - - USB33 LDO short protection - - - USB33 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - USB33 LDO stability compensation: default 2'b10 - - - USB33 LDO foldback current threshold adjust: default 1'b1 - - - USB33 LDO current limit threshold adjust: default 1'b1 - - - - - LDO_USB33 power down 1: power down 0: power on - - - - - USB33 LDO program bits: 12.5mV/step, 2.1V~3.6875V; default 3.3V, 7'b1100000 - - - - - - - - - - - - - LDO trim bits: 5mV/step, 0.72V~0.875V; default 0.8V, 5'b10000 - - - LDO trim bits: 5mV/step, 0.72V~0.875V; default 0.8V, 5'b10000 - - - - - LDO VDDRTC output calibretion bit cover +/-10% step 0.625% acc +/- 0.3125% - - - LDO RTC output program bits, 00:1.8, 01:1.8, 10:1.85(default),11:1.9 - - - Backup battery output program bits;00:2.6, 01:2.8, 10:3.0(default),11:3.2 - - - - - VBAT2 LDO TRIM CONTROL BITS: -000: cal disable (default) -001: LDO VDDSIM0 cal enable; -010: LDO VDDSIM1 cal enable; -011: LDO VDDDCXOcal enable; -100: LDO VDDUSB cal enable; -101: LDO VDDCAMA cal enable; -110: LDO VDDVIB cal enable; - - - VBAT1 LDO TRIM CONTROL BITS: -000: cal disable (default) -001: LDO VDDMMC cal enable; -010: LDO VDD28 cal enable; -011: LDO VDDSPIMEM cal enable; -100: LDO VDDLCD cal enable; -101: LDO VDDPLLED cal enable; - - - DCDC supplied LDO TRIM CONTROL BITS: -000: cal disable (default) -001: LDO VDDCAMD cal enable; -010: LDO VDDCON cal enable; -011: LDO VDDANA cal enable; -100: LDO VDDVIO18 cal enable; -101: LDO VDDDDR12 cal enable; -110: LDO VDDMEM cal enable; -111: LDO VDDRF15 cal enable; - - - - - - - - - - - - - - - LDO and DCDC can be controlled by external device if this bit is set - - - IO PAD sleep enable in deep sleep mode - - - ALL LDO and DCDC power down enable in deep sleep mode - - - - - DCDC CORE power down reset valid threshold @32K clock - - - DCDC CORE power down reset release threshold @32K clock - - - DCDC CORE power down enable in deep sleep mode - - - DCDC CORE power drop enable in deep sleep mode - - - DCDC WPA power down enable in deep sleep mode - - - VIO1V8 power down enable in deep sleep mode - - - - - LDO RFA power down enable in deep sleep mode - - - LDO MMC power down enable in deep sleep mode - - - LDO DCXO power down enable in deep sleep mode - - - LDO SPIMEM power down enable in deep sleep mode - - - LDO VDD28 power down enable in deep sleep mode - - - LDO VIO18 power down enable in deep sleep mode - - - LDO DDR12 power down enable in deep sleep mode - - - LDO USB33 power down enable in deep sleep mode - - - LDO LCD power down enable in deep sleep mode - - - LDO CAMIO power down enable in deep sleep mode - - - LDO CAMD power down enable in deep sleep mode - - - LDO CAMA power down enable in deep sleep mode - - - LDO SIM1 power down enable in deep sleep mode - - - - - LDO CP power down enable in deep sleep mode - - - LDO CON power down enable in deep sleep mode - - - LDO SIM0 power down enable in deep sleep mode - - - LDO ANA power down enable in deep sleep mode - - - LDO MEM power down enable in deep sleep mode - - - - - DCDC CORE low power mode enable in deep sleep mode - - - DCDC GEN low power mode enable in deep sleep mode - - - DCDC WPA low power mode enable in deep sleep mode - - - - - LDO RFA low power mode enable in deep sleep mode - - - LDO MMC low power mode enable in deep sleep mode - - - LDO DCXO low power mode enable in deep sleep mode - - - LDO SPIMEM low power mode enable in deep sleep mode - - - LDO VDD28 low power mode enable in deep sleep mode - - - LDO VIO18 low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO DDR12 low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO USB low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO LCD low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO CAMIO low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO CAMD low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO CAMA low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO SIM1 low power mode enable in deep sleep mode 0: Disable 1: Enable - - - - - LDO CON low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO SIM0 low power mode enable in deep sleep mode 0: Disable 1: Enable - - - LDO ANA low power mode enable in deep sleep mode - - - LDO MEM low power mode enable in deep sleep mode 0: Disable 1: Enable - - - - - delay between two steps 00:1*32k clock 01:2*32k clock 10:3*32k clock 11:4*32k clock - - - step number - - - voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv - - - DCDCCORE step tune enable in deep sleep 0: disable 1: enable - - - - - DCDC CORE control bits in deep sleep mode - - - - - DCDC CORE can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - DCDC CORE can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - DCDC CORE can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - DCDC CORE can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - DCDC GEN can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - DCDC GEN can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set - - - DCDC GEN can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - DCDC GEN can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - DCDC WPA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - DCDC WPA can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set - - - DCDC WPA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - DCDC WPA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - - - LDO DCXO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO DCXO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO DCXO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO DCXO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO VDD28 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO VDD28 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO VDD28 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO VDD28 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO RFA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO RFA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO RFA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO RFA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO SIM0 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO SIM0 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO SIM0 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO SIM0 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO SIM1 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO SIM1 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO SIM1 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO SIM1 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO MEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO MEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO MEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO MEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO LCD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO LCD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO LCD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO LCD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO CAMIO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO CAMIO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO CAMIO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO CAMIO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO CAMA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO CAMA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO CAMA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO CAMA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO CAMD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO CAMD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO CAMD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO CAMD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO DDR12 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO DDR12 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO DDR12 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO DDR12 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO VIO18 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO VIO18 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO VIO18 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO VIO18 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO MMC can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO MMC can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO MMC can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO MMC can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO USB33 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO USB33 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO USB33 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO USB33 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO KPLED can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO KPLED can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO KPLED can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO KPLED can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO VIBR can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO VIBR can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO VIBR can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO VIBR can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO CON can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO CON can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO CON can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO ANA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO ANA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO ANA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO ANA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - LDO CP can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO CP can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO CP can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - LDO SPIMEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set - - - LDO SPIMEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set - - - LDO SPIMEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set - - - LDO SPIMEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set - - - - - - - - - - - - - - - Band-gap chopping enable: "0":chopping disable (default) "1": chopping enable - - - - - DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended - - - DCDC Voltage calibration disable 0: enable calibration 1: disable calibration - - - DCDC Voltage calibration disable 0: enable calibration 1: disable calibration - - - DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended - - - DCDC sleep voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1 - - - DCDC normal voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1 - - - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended - - - - - RC_MODE write ack flag - - - bit type is changed from wc to rc. - RC_MODE write ack flag clear, high effective - - - Low power LDO_DCXO power down set in RTC - - - Low power LDO_DCXO power down clear in RTC - - - 0: there isnt 32k crystal in PMIC - - - 32K clock select in 32K crystal removal option 0: From XO 1: From RC - - - RC 32K oscillator enable - - - - - RC 32K mode in battery drop case: - - - - - 26M wake up enable by ext_xtl3_en - - - 26M wake up enable by ext_xtl2_en - - - 26M wake up enable by ext_xtl1_en - - - 26M wake up enable by ext_xtl0_en - - - 26MHz crystal oscillator power down enable in deep sleep mode - - - 26MHz crystal oscillator output enable - - - 26MHz crystal oscillator wait cycles - - - - - RGB driver power down enable in chip deep sleep mode - - - RGB driver hardware power down enable - - - RGB driver soft power down - - - - - current mode enable "0" disable (default) "1" enable (default) - - - set current level in current mode 000:1.25uA;001:2.5uA;010:5uA;011:10uA;100:20uA;101:40uA;110:80uA;111:160uA; 8step - - - Internal resistor for sink current calibration bit. - - - Internal resistor for sink current calibration bit selection 0: From Software Register 1: From Ememory - - - External resisitor for sink current adjustment for test - - - - - Flash power on 1: power on 0: power down - - - FLASH_V hardware control enable - - - FLASH_V hardware control step 00: 1 cycle of clock 32k 01: 2 cycle of clock 32k 10: 3 cycle of clock 32k 11: 4 cycle of clock 32k - - - Current control bit. 16 steps. Min current: 15mA ("0000") One step is 15mA (default 4'b0) - - - - - Current control bit. 16 steps (default 4'b0) (0000:0.9mA 0001:1.8mA 0010:2.7mA 0011:3.6mA 0100:4.5mA 0101:5.4mA 0110:6.3mA 0111:7.2mA 1000:16.2mA 1001:22.5mA 1010:29.7mA 1011:37.8mA 1100:46.8mA 1101:56.7mA 1110:67.5mA 1111:79.2mA) - - - Key PAD LED driver power down "1" power down (default) "0" enable - - - Keypad LED pull down enable signale, high effective - - - KPLED LDO sleep power down enable - - - KPLED LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - KPLED LDO stability compensation: default 2'b10 - - - KPLED LDO foldback current threshold adjust: default 1'b1 - - - VIBR LDO current limit threshold adjust: default 1'b1 - - - - - KPLED LDO power down signal - - - KPLED LDO program bits: 100mV/step, 2.8V~3.5V; default 3.3V, 3'b101 - - - KPLED LDO TRIM program bits: 8mV/step 1.2V default - - - LDO short protection power down - - - - - VIBR LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - KPLED LDO stability compensation: default 2'b10 - - - VIBR LDO foldback current threshold adjust: default 1'b1 - - - VIBR LDO current limit threshold adjust: default 1'b1 - - - LDO short protection power down - - - Vibrator LDO sleep power down enable - - - VIBR LDO power down signal - - - VIBR LDO program bits: 100mV/step, 2.8V~3.5V; default 3.0V, 3'b010 - - - - - VIBR LDO TRIM program bits: 8mV/step 1.2V default - - - LDO EA load compensation EN ,effective(1'b1) - - - - - Whether Adie use inverse of clk_audif to sample Ddie tx data 0: No 1: Yes - - - Whether Adie use inverse of clk_aud6m5 to send rx data to Ddie 0: No 1: Yes - - - Whether Adie audio controller use inverse of clk_aud6m5 in tx path 0: No 1: Yes - - - Whether Adie audio controller use inverse of clk_aud6m5 in rx path 0: No 1: Yes - - - - - VCHG tracking voltage level for automatic input control loop(AICL) 00: 3.8V 01: 3.95V 10: 4.3V 11: 4.5V Default value is 11 - - - Charger CC mode enable, high effective - - - Charger battery sense DAC (CC-CV trans-point control) - - - Charger battery charging end voltage 00: Vend=4.2V 01: Vend=4.3V 10: Vend=4.4V 11: Vend=4.5V - - - Termination charger current programmable bits 00:cc*0.9 01:cc*0.4 10:cc*0.2 11:cc*0.1 - - - Charger power down - - - - - Choice of charger external power device 0:PNP+NMOS 1:PMOS+DIODE Default value is 0 - - - CC mode charging current 0000:300mA 0001 : 350 0010: 400mA 0011 : 450 0100: 500mA 0101 :550 0110: 600mA 0111: 650 1000: 700mA 1001: 750 1010: 800mA 1011: 900 1100: 1000mA 1101: 1100 1110: 1200mA 1111: 1300 Default4'b0 - - - control bits of over voltage protection for VCHG. When VCHG is above some level set by these 2 bits, charger power down and CHGR_OVI becomes high. 00: 6.0V 01: 6.5V 10: 7.0V 11: 9.7V Default 2'b01 - - - - - Chgr_int enable after CHG_DET_DONE - - - Charging port of NON-DCP status "1" Charging port is NON-DCP "0" Charging port is not NON-DCP - - - Charging detect done after charger insert once - - - The output of the comparator of DCD detection or SDP/NON-DCP detection "1" means DCD pass when doing DCD, or SDP if CHG_DET=0 "0" means DCD fail when doing DCD, or NON-DCP if CHG_DET=0 - - - The output of the comparator of DCP_DET loop "1" means DCP if CHG_DET is "1" "0" means CDP if CHG_DET is "1" - - - The output of the comparator of CHG_DET loop "1" DCP or CDP "0" SDP or NON-DCP - - - Charging port of SDP status "1" Charging port is SDP "0" Charging port is not SDP - - - Charging port of DCP status "1" Charging port is DCP "0" Charging port is not DCP - - - Charging port of CDP status "1" Charging port is CDP "0" Charging port is not CDP - - - Flag when charging current below some level(0.5*full current) in CV mode High effective - - - Charger voltage ready indicator, high effective When VCHG<4.1V: "0" When VCHG>4.3V: "1" - - - Charger present indicator, high effective When VCHG<3.1V: "0" When VCHG>3.3V: "1" - - - 0: switch DPDM to USB phy when DCP 1: keep to connect charger detector when DCP - - - VCHG over voltage(programmable) flag When VCHG higher than some voltage set by VCHG_OVP_V<5:0> and lasts 2mS, CHGR_OVI="1" The hysteresis voltage is 600mV. - - - - - FGU ANA soft reset - - - LDO FGU power down control 0: Normal Mode 1: Power Down Mode - - - charger int delay time: 000:0ms 001:64ms 010:264ms.. 111:764ms - - - ADC chop enable - - - ADC clock programming bits - - - input RC for ADC0 input filtering select signal: 0: ADC0 input with RC filtering 1: ADC0 input without RC filtering - - - 0: ADC0 input with RC filtering - - - 1: ADC0 input without RC filtering - - - SD ADC_A will be dc offset calibration Code mode 0(default) off 1 on - - - DP DM to auxADC select signal: "0": switch off, no DP/DM to auxADC "1": switch on, DP/DM to auxADC - - - The DP DM path switch enable "1" switch on, BC1P2 disable "0" invalid - - - - - Battery crash voltage setting: 00: 2.1V (default) 01: 2.2V 10: 2.3V 11: 2.5V - - - Over voltage locked-out enable (high effective) Default "1" - - - Over voltage locked-out detecting time 00 : 5.0V (default) 01 : 5.2V 10 : 4.8V 11 : 4.2V - - - Over voltage locked-out detecting time 00 : 1ms (default) 01 : 0.5ms 10 : 0.25ms 11 : 2ms - - - - - Schmitt Trigger 0: no Schmitt trigger 1: Schmitt trigger(default) - - - Control bit of de-glitch time for battery remove "00" 32us "01" 64us "10" 128us "11" no de-glitch default"00" - - - when VPP tie to 5V should shet VPP_5V_SEL=1 - - - Battery presence flag to SW and POCV, so need RTC domain "0" no battery "1" battery presence - - - VBAT detect. Active "0" is reset, no need 32K osc. - - - ALL GPI source debug - - - GPI debug enable - - - ALL_INT debug, if 1, interrupt will be sent - - - Interupt debug enable - - - - - When POR reset active, this register is reset to 0 - - - - - When WDG reset active, this register is reset to 0 - - - - - When POR_EXT_RST active, this register is reset to 0 - - - - - Setting this bit could disable the 1S debouncing time of power key after boot. - - - bit type is changed from wc to rc. - register reset flag clear - - - Power on source flag: -[0]: Debounced PBINT signal, set when PBINT=0 >50ms, clear when PBINT=1>50ms. -[1]: PBINT initiating power-up hardware flag, set when PBINT=0>1s, clear after power down. -[2]: Debounced PBINT2 signal, set when PBINT2=0 >50ms, clear when PBINT2=1>50ms. -[3]: PBINT2 initiating power-up hardware flag, set when PBINT2=0>1s, clear after power down. -[4]: Debounced CHGR_INT signal, set when VCHG=1 >50ms, clear when VCHG=0>50ms. -[5]: Charger plug-in initiating power-up hardware flag, set when VCHG=1>1s, clear after power down. -[6]: RTC alarm initiating power-up hardware flag -[7]: Long pressing power key reboot hardware flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear after power down. -[8]: PBINT initiating power-up software flag, set when PBINT=0>1s, clear by pbint_flag_clr. -[9]: PBINT2 initiating power-up software flag, set when PBINT2=0>1s, clear by pbint2_flag_clr. -[10]: Charger plug-in initiating power-up software flag, set when VCHG=1>1s, clear by chgr_int_flag_clr. -[11: External pin reset reboot software flag, set when EXTRSTN=0>30ms, clear by ext_rstn_flag_clr. -[12]: Long pressing power key reboot software flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear by pbint_7s_flag. -[13]: flag when register reset happened - - - - - uvlo + ovlo chip power down flag - - - bit type is changed from wc to rc. - uvlo + ovlo chip power down flag clear - - - uvlo chip power down flag - - - bit type is changed from wc to rc. - uvlo chip power down flag clear - - - 7s hard chip power down flag - - - bit type is changed from wc to rc. - 7s hard chip power down flag clear - - - OTP chip power down flag - - - bit type is changed from wc to rc. - OTP chip power down flag clear - - - HW chip power down flag - - - bit type is changed from wc to rc. - HW chip power down flag clear - - - OTP chip power down flag - - - bit type is changed from wc to rc. - OTP chip power down flag clear - - - - - Write 1'b1 to this bit will clear pbint_7s_flag. - - - Write 1'b1 to this bit will clear ext_rstn_flag. - - - Write 1'b1 to this bit will clear chgr_int_flag. - - - Write 1'b1 to this bit will clear pbint2_flag. - - - Write 1'b1 to this bit will clear pbint_flag. - - - 1: One-key Reset Mode; - - - 0: long reset; - - - The power key long pressing time threshold: 0~1: 2S 2: 3S 3: 4S 4: 5S 5: 6S 6: 7S 7: 8S 8: 9S 9: 10S 10:11S 11:12S 12: 13S 13:14S 14:15S 15:16S - - - EXT_RSTN PIN function mode when 1key 7S reset 0: EXT_INT 1: RESET - - - RTC register PBINT_7S_AUTO_ON_EN - - - 0: enable 7s reset function; 1: disable 7s reset function; - - - 0: software reset; 1: hardware reset; - - - - - RTC status register, set by HWRST_RTC_SET. - - - Software set this register to test VBAT and RTC power status. - - - - - PCLK_arch enable - - - - - Arch_en write protect bit status. When mcu_wr_prot_value==16'h3c4d, the bit is "1",else "0" - - - Arch_en write protect value - - - - - All power which default on write protect bit status. When mcu_wr_prot_value==16'h6e7f, the bit is "1",else "0" - - - Arch_en write protect value - - - - - SMPL mode: [15:13]: SMPL timer threshold 0: 0.25s 1: 0.5s 2: 0.75s.. 7: 2s [12:0]: SMPL enable 13'h1935: enable Others: disable - - - - - Set once SMPL timer not expired. - - - Set once SMPL mode write finish - - - bit type is changed from wc to rc. - Clear SMPL_PWR_ON_FLAG - - - bit type is changed from wc to rc. - Clear SMPL_MODE_WR_ACK - - - Set once SMPL timer not expired, - - - SMPL enable indication - - - - - RTC register flag - - - - - RTC register flag - - - - - RTC register flag, reset by RTC_RST, default is 16'hA596 - - - - - rtc time over thresthold value - - - set reset rtc cnt time,default 16s - - - - - VBAT Drop Time Count - - - - - Software reset certain power enable when ext_rstn valid - - - Software reset certain power enable when pb_7s_rst valid - - - Software reset certain power enable when reg_rst valid - - - Software reset certain power enable when wdg_rst valid - - - register reset enable: - - - reset LDO to normal mode threshold time - - - - - Software reset DCDC_GEN_PD enable when global reset valid - - - Software reset DCDC_CORE_PD enable when global reset valid - - - Software reset LDO_MEM_PD enable when global reset valid - - - Software reset LDO_DCXO_PD enable when global reset valid - - - Software reset LDO_VDD28_PD enable when global reset valid - - - Software reset LDO_ANA_PD enable when global reset valid - - - Software reset LDO_RF18_PD enable when global reset valid - - - Software reset LDO_USB33_PD enable when global reset valid - - - Software reset LDO_MMC_PD enable when global reset valid - - - Software reset LDO_DDR12_PD enable when global reset valid - - - Software reset LDO_VIO18_PD enable when global reset valid - - - - - OTP threshold option, 00 135, 01 140, 10 145, 11 150; - - - OTP function enable control bit - - - - - low 16 bit value of free timer - - - - - high 16 bit value of free timer - - - - - clock source for CORE DVFS 0: clock 26M 1: clock 32K - - - delay between two steps 00:1*32k clock or 2us in 26M 01:2*32k clock or 4us in 26M 10:3*32k clock or 8us in 26M 11:4*32k clock or 16us in 26M - - - step number - - - DVFS voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv - - - bit type is changed from wc to rc. - voltage tune start bit - - - voltage tune flag 0:done 1:on going - - - voltage tune enable 0: disable 1: enable - - - - - - - - - This interrupt is masked from TYPEC_INT_RAW_STATUS by TYPEC_INT_EN - - - This interrupt is masked from CAL_INT_RAW_STATUS by CAL_INT_EN - - - This interrupt is masked from TMR_INT_RAW_STATUS by TMR_INT_EN - - - This interrupt is masked from AUD_PROTECT_INT_RAW_STATUS by AUD_PROTECT_INT_EN - - - This interrupt is masked from EIC_INT_RAW_STATUS by EIC_INT_EN - - - This interrupt is masked from FGU_INT_RAW_STATUS by FGU_INT_EN - - - This interrupt is masked from WDG_INT_RAW_STATUS by WDG_INT_EN - - - This interrupt is masked from RTC_INT_RAW_STATUS by RTC_INT_EN - - - This interrupt is masked from ADC_INT_RAW_STATUS by ADC_INT_EN - - - - - typeC raw interrupt flag - - - calibration raw interrupt flag - - - timer raw interrupt flag - - - Audio protect raw interrupt flag - - - EIC raw interrupt flag - - - FGU raw interrupt flag - - - WDG raw interrupt flag - - - RTC raw interrupt flag - - - auxADC raw interrupt flag - - - - - bit type is changed from r/w to rw. - Enable TYPEC_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable CAL_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable TMR_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable AUD_PROTECT_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable EIC_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable FGU_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable WDG_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable RTC_INT_RAW_STATUS to system - - - bit type is changed from r/w to rw. - Enable ADC_INT_RAW_STATUS to system - - - - - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: default normal function selection 2b01: GPO 0 function selection 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: default normal function selection 2b01: GPO 1 function selection 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: default normal function selection 2b01: GPO 2 function selection 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: default normal function selection 2b01: GPO 3 function selection 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: default normal functon sel 2b01: VAD ADCL data function sel 2b10: VAD ADCR data function sel 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA - - - Weakly pull up for function mode - - - Weakly pull down for function mode - - - Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 - - - Weak pull up for chip deep sleep mode - - - Weak pull down for chip deep sleep mode - - - Input enable for chip deep sleep mode - - - Output enable for chip deep sleep mode - - - - - - - - - if write 0x454e to enable write psm reg, readback only [15] is high - - - - - psm calibration pre time. The time is from pull DCXO high to OSC 26M stable. unit is (clk_cal_64k_div_th +1)ms - - - psm calibration time 1s/(2^(16-rc_32k_cal_cnt_n))/( rc_32k_cal_cnt_p+1) - - - - - psm 26m calibration value update down threshold. -Value = (1/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) - - - - - psm 26m calibration value update up threshold -Value = (3/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) - - - - - 1'b1: rtc use psm cal 32K clock in 32K less mode,1'b0:rtc use RC 32K clock in 32K less mode - - - enable psm cal - - - clear psm int status - - - enble psm timer cnt - - - posedge to update psm cnt value - - - software reset psm module, auto clear - - - enable psm timer to wake up sys - - - enable psm alarm function - - - enable charger to power on sys - - - enable pbint2 to power on sys - - - enable pbint1 to power on sys - - - enable ext int to power on sys - - - enable rtc power on time out detect - - - enable psm fsm - - - - - The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms - - - The time to disable rtc clk in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms - - - The time to reset rtc in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to power off rtc done in power off rtc state, unit is (clk_cal_64k_div_th +1)ms - - - - - The time to release reset in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to power on rtc , unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The time to clock enable in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to release hold ISO in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The time to mark power on timeout in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms - - - The time to power on rtc done , unit is 4*(clk_cal_64k_div_th +1)ms - - - - - The low 16 bits threshold of psm time , unit is 10*(clk_cal_64k_div_th +1)ms - - - - - The high 16 bits threshold of psm time , unit is 10ms - - - - - The low 16 bits threshold of psm alarm time , unit is 10*(clk_cal_64k_div_th +1)ms - - - - - The high 16 bits threshold of psm alarm time - - - - - The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms - - - - - The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms - - - - - DCXO LDO short protection - - - DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 - - - DCXO LDO stability compensation: default 2'b10 - - - DCXO LDO foldback current threshold adjust: default 1'b1 - - - DCXO LDO current limit threshold adjust: default 1'b1 - - - DCXO voltage setting, 1.5~3.0875V,12.5mv step - - - - - Psm calibration divider,it is calculated with rc_32k_cal_cnt_n C log2(clk_cal_64k_div_th+1) - - - Psm rc 64K divider, the input RC clock is divider to CLK_64K/( clk_cal_64k_div_th+1) - - - Enable watchdog power on chip by internal RC clock - - - - - - - - - - - - - - - Psm cnt updated low 16 bits value, the step of read this value is : -(1)enable psm_cnt_update, -(2)wait till psm_cnt_update_vld ==1.(psm_fsm_status[6]) - - - - - Psm cnt updated high 16 bits value - - - - - - - - - - - - - - - - - psm cnt updated valid - - - when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when psm_cnt_en==1, then if psm cnt get psm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, -When psm_status_clr is high, this bit is low - - - when pbint2_pwr_en==1, then if pbint2 is low, this bit is high, -When psm_status_clr is high, this bit is low - - - when pbint1_pwr_en==1, then if pbint1 is low, this bit is high, -When psm_status_clr is high, this bit is low - - - when ext_int_en==1, then if ext_int is high, this bit is high, -When psm_status_clr is high, this bit is low - - - - - Only debug use - - - - - We can use this value to calculate the RC 64K clock real frequency. Rc_64k=( clk_cal_64k_div_th+1)*(2^ rc_32k_cal_cnt_p)*26*10^6/ (psm_cal_cnt*2^9) - - - - - - - - - RTC second counter value - - - - - RTC minute counter value - - - - - RTC hour counter value - - - - - RTC day counter value - - - - - bit type is changed from r/w to rw. - RTC second counter update Write new counter value to this register to start a second counter updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC minute counter update Write new counter value to this register to start a minute counter updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC hour counter update Write new counter value to this register to start an hour counter updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC day counter update Write new counter value to this register to start a day counter updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC second alarm update Write new counter value to this register to start a second alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC minute alarm update Write new counter value to this register to start a minute alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC hour alarm update Write new counter value to this register to start an hour alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - bit type is changed from r/w to rw. - RTC day alarm update Write new counter value to this register to start a day alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - - - Day alarm updating complete interrupt enable - - - Hour alarm updating complete interrupt enable - - - Minute alarm updating complete interrupt enable - - - Second alarm updating complete interrupt enable - - - Day counter updating complete interrupt enable - - - Hour counter updating complete interrupt enable - - - Minute counter updating complete interrupt enable - - - Second counter updating complete interrupt enable - - - Spare register updating complete interrupt enable - - - auxiliary alarm interrupt enable - - - Hour format select - - - alarm interrupt enable - - - day interrupt enable - - - hour interrupt enable - - - minute interrupt enable - - - Second interrupt enable - - - - - Day alarm updating complete interrupt raw status - - - Hour alarm updating complete interrupt raw status - - - Minute alarm updating complete interrupt raw status - - - Second alarm updating complete interrupt raw status - - - Day counter updating complete interrupt raw status - - - Hour counter updating complete interrupt raw status - - - Minute counter updating complete interrupt raw status - - - Second counter updating complete interrupt raw status - - - Spare register updating complete interrupt raw status - - - auxiliary alarm interrupt raw status - - - Reserved for debug - - - alarm interrupt raw status - - - day interrupt raw status - - - hour interrupt raw status - - - minute interrupt raw status - - - Second interrupt raw status - - - - - Day alarm updating complete interrupt clear - - - Hour alarm updating complete interrupt clear - - - Minute alarm updating complete interrupt clear - - - Second alarm updating complete interrupt clear - - - Day counter updating complete interrupt clear - - - Hour counter updating complete interrupt clear - - - Minute counter updating complete interrupt clear - - - Second counter updating complete interrupt clear - - - Spare register updating complete interrupt clear - - - Auxiliary alarm interrupt clear - - - alarm interrupt clear - - - day interrupt clear - - - hour interrupt clear - - - minute interrupt clear - - - Second interrupt clear - - - - - Day alarm updating complete interrupt masked status - - - Hour alarm updating complete interrupt masked status - - - Minute alarm updating complete interrupt masked status - - - Second alarm updating complete interrupt masked status - - - Day counter updating complete interrupt masked status - - - Hour counter updating complete interrupt masked status - - - Minute counter updating complete interrupt masked status - - - Second counter updating complete interrupt masked status - - - Spare register updating complete interrupt masked status - - - auxiliary alarm interrupt masked status - - - alarm interrupt masked status - - - day interrupt masked status - - - hour interrupt masked status - - - minute interrupt masked status - - - Second interrupt masked status - - - - - RTC second alarm value - - - - - RTC minute alarm value - - - - - RTC hour alarm value - - - - - RTC day alarm value - - - - - RTC spare register value - - - RTC alarm lock register value - - - - - bit type is changed from r/w to rw. - RTC spare register update Write new counter value to this register to start a spare register updating operation in VDDRTC domain. Reading this register can get recent updating value. - - - bit type is changed from r/w to rw. - RTC alarm lock register update Write new counter value to this register to start a register updating operation in VDDRTC domain. Reading this register can get recent updating value. Write 8hA5 to this register to unlock alarm function, and write other data to lock alarm function. That means, software must 8hA5 to this register to enable alarm function before using this function. - - - - - bit type is changed from r/w to rw. - RTC power flag register set - - - bit type is changed from r/w to rw. - RTC power flag register clear - - - - - RTC power flag status register - - - - - bit type is changed from r/w to rw. - RTC second auxiliary alarm register - - - - - bit type is changed from r/w to rw. - RTC minute auxiliary alarm register - - - - - bit type is changed from r/w to rw. - RTC hour auxiliary alarm register - - - - - bit type is changed from r/w to rw. - RTC day auxiliary alarm register - - - - - RTC second counter raw value Only for debug - - - - - RTC minute counter raw value - - - - - RTC hour counter raw value Only for debug - - - - - RTC day counter raw value Only for debug - - - - - - - - - the IP version of this timer - - - the IP patch version of this timer - - - - - timer load value of lower 16 bit. Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. - - - - - timer load value of higher 16 bit Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. - - - - - timer open bit 0: timer stops 1: timer runs - - - timer mode select 0: one-time mode 1: period mode - - - - - timer Interrupt clear - - - timer interrupt masked status - - - timer interrupt raw status - - - timer interrupt enable - - - - - timer counter of lower 16bit shadow value for read. When the timer in 16 bit mode, it represent the shadow value of the timer This read-only register indicates current counter value. The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. - - - - - timer counter of 16bit higher shadow value for read. It will be valid only in 64 bit mode. This read-only register indicates current counter value.The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. - - - - - - - - - wdg_load_low: low 16 bit of watchdog timer load value. Wdg_load_high: high 16 bit of watchdog timer load value. wdg_load_low and wdg_load_high are used together. Software should write wdg_load_high firstly, and then write wdg_load_low, because writing wdg_load_low can trig loading both wdg_load_low and wdg_load_high to watchdog counter, and writing wdg_load_high cannot trig this event. So software must guarantee w In reset mode, software should load new value before timer decrease to 0. In interrupt mode, this value is counting start number. The default value is about 8 seconds. - - - - - See wdg_load_low description - - - - - Watchdog reset enable bit 0: reset is disabled 1: reset is enabled In reset mode and combined mode, this bit should be 1 - - - Watchdog version 0: watchdog use old behavior, this is for backward compatibility. 1: watchdog uses new behavior, such as multiple loads without checking busy bit, only need to read once to get timer counter value. - - - Watchdog counter open: 0: counter stops. 1: counter runs. - - - Watchdog interrupt enable bit 0: interrupt is disabled 1: interrupt is enabled In interrupt mode and combined mode, this bit should be 1 - - - - - Watchdog reset clear Write 1 to this bit to clear reset Read this bit always get 0. - - - Watchdog interrupt clear Write 1 to this bit to clear interrupt Read this bit always get 0. - - - - - Watchdog load busy status 0: Watchdog is ready for new loading 1: Last loading is not completed Software must not load new value when this bit is busy, that is, this bit should be checked before any new loading. This bit is set after a new loading, and lasts two or three RTC clock cycles, about 60us - 92us. - - - Watchdog reset raw status. Watch dog reset cannot clear this raw status, so it can be used to judge if or not system rebooting comes from watchdog reset. Write wdg_rst_clr can clear this raw status. - - - Watchdog interrupt raw status. Watch dog reset cannot clear this raw status. Write wdg_int_clr can clear this raw status. - - - - - Watchdog interrupt masked status - - - - - wdg_cnt_low: Low 16 bit of watchdog timer counter value. wdg_cnt_high: High 16 bit of watchdog timer counter value. wdg_cnt_low and wdg_cnt_high are used together. This read-only register indicates current counter value. Its not recommended to read this register in normal usage. Because the counter is in different clock domain with APB, software needs use double-reading method to read this value, like system timer. - - - - - See wdg_cnt_low description. - - - - - Watchdog lock control Write 16hE551 to this register to unlock watchdog. Write other value to this register to lock watchdog If reading this register, bit-0 is lock status, and other bits are reserved. If watchdog is locked, all control registers cannot be written by software. - - - - - wdg_cnt_rd_low: Low 16 bit of watchdog timer counter value for read. wdg_cnt_rd_high: High 16 bit of watchdog timer counter value for read. wdg_cnt_rd_low and wdg_cnt_rd_high are used together. This read-only register indicates current counter value. Read once can get watchdog counter value. No need to double read this reg. Refer to timers TIMER0_CNT_RD or TIMER1_CNT_RD - - - - - Refer to wdg_cnt_rd_low - - - - - wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high are used together. Its useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds, which means reset will occur after irq is 1 for 6 seconds. - - - - - wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high are used together, which means reset will occur after irq is 1 for 6 seconds. Its useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds. - - - - - - - - - Enable CP sleep -0: disable -1: enable - - - - - Enable AP sleep(Auto cleared to be 0 when the system is awaked) -0: disable -1: enable - - - - - Enable AP sleep -0: disable -1: enable - - - Enable CP sleep -0: disable -1: enable - - - - - System begin to wakeup when the current ref_32k counter reach this value, the difference between warp value and current ref_32k value larger than one gsm frame is best. - - - - - Default value when the enable bit was disabled. - - - Enable bit of wcn idle_cg -0: disable -1: enable - - - Enable bit of wcn pd_pll -0: disable -1: enable - - - Enable bit of wcn pd_xtal -0: disable -1: enable - - - Enable bit of wcn chip_pd -0: disable -1: enable - - - - - Enable Timer sleep(Auto clear to be 0 when timer is awaked) -0: disable -1: enable - - - - - Threshold register M1: -when the signal pow_on_ack is low, both gsm and lte timer are sleeped, and the difference between current ref_32k counter -and sleep wrap value is larger than this register, system sleep state machine can shift to SLP state. - - - Threshold register M2: -when idct_sys1 and idct_sys2 are set to be1, the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP_PRE state. - - - - - Enable mode(TCU suspend and this bits are clear to be 0 when take over is started) -00: disbale or already release TCU. -01: take over TCU immediately -10: take over at gsm frame interrupt. -11: no effect. - - - - - restart TCU when gsm counter reach this register - - - restart mode(this bits clear to be 0 when TCU restarts) -00: disable -01: restart TCU immediately -10: restart TCU when gsm frame interrupt occurred. -11: restart TCU when gsm framc equal to TC_END_FRAMC. - - - - - Timer wakeup enable(software accessed only) -0: disable -1: enable - - - - - TCU restart enable(software accessed only) -Output to the port gsm_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. - - - - - gsm_frame_irq enable -1: enable -0: disable - - - - - cleared by writing 1 to correspond bit - - - - - ltem1_frame3_irq enable -1: enable -0: disable - - - ltem1_frame2_irq enable -1: enable -0: disable - - - ltem1_frame1_irq enable -1: enable -0: disable - - - - - bit type is changed from rw1c to rc. - cleared by writing 1 to correspond bit - - - - - ltem2_frame3_irq enable -1: enable -0: disable - - - ltem2_frame2_irq enable -1: enable -0: disable - - - ltem2_frame1_irq enable -1: enable -0: disable - - - - - bit type is changed from rw1c to rc. - cleared by writing 1 to correspond bit - - - - - NB timer state -0: running at 61.44M -1: running at 32K - - - H circuit state -0: not work -1: at wok - - - ltem2 timer state -0: running at 122.88M -1: running at 32K - - - ltem1 timer state -0: running at 122.88M -1: running at 32K - - - GSM timer state -0: running at 26M -1: running at 32K - - - SYS state -0: normal working -1: low power mode - - - - - Runtime of H circuit, the length is 2^h_run_time(number of 32k clocks) - - - Automatic computing mode enable(loop computing until disabled) -0: disable -1: enable - - - Invocation pattern(compute only one time, automatic clear to be 0 when finished.) -0: disable -1: enable - - - - - The length of sys clock in 2^h_run_time 32k cycles - - - - - The cycles number of 26M in 2^h_run_time 32k cycles - - - - - The cycles number of 122.88M in of 2^h_run_time 32k cycles - - - - - signal nb_lp_pu_reach wakeup enable -0: disable -1: enable - - - signal gsm_lp_pu_reach wakeup enable -0: disable -1: enable - - - sofware wakeup enable -0: disable -1: enable - - - OSW2 wakeup enable -0: disable -1: enable - - - OSW1 wakeup enable -0: disable -1: enable - - - wcn_osc_en wakeup enable -0: disable -1: enable - - - wcn2sys wakeup enable -0: disable -1: enable - - - pad_uart1_rxd wakeup enable -0: disable -1: enable - - - Uart1_irq wakeup enable -0: disable -1: enable - - - Gpio1_irq wakeup enable -0: disable -1: enable - - - Keyboard wakeup enable -0: disable -1: enable - - - Vad_int wakeup enable -0: disable -1: enable - - - Pad_gpio6 wakeup enable -0: disable -1: enable - - - - - pow_dfe_ack state -0: pow_dfe_ack is 0 when system exit IDLE -1: pow_dfe_ack is 1 when system exit IDLE - - - bit type is changed from rw1c to rc. - Threshold M1 state -1: pow_ack not meet threshold M1 or pow_ack not feedback in sleep period -0: meet threshold M1 - - - bit type is changed from rw1c to rc. - pow_ack state -0: pow_ack is 0 when system exit IDLE -1: pow_ack is 1 when system exit IDLE - - - bit type is changed from rw1c to rc. - system exit idle state -0: sys not enter idle -1: sys enter idle state - - - bit type is changed from rw1c to rc. - IDLE sleep wakeup state -0: awaked before the sleep warp time -1: awaked at the sleep warp time - - - bit type is changed from rw1c to rc. - Signal nb_lp_pu_reach wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - Signal gsm_lp_pu_reach wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - software wakeup state -0: software wakeupup signal not generated -1: software wakeupup system. - - - bit type is changed from rw1c to rc. - OSW2 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - OSW1 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK7 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK6 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK5 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK4 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWk3 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWk2 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK1 wakeup state -0: this signal not generated -1: this signal generated - - - bit type is changed from rw1c to rc. - AWK0 wakeup state -0: this signal not generated -1: this signal generated - - - - - 0: not effect -1: wakeup system -(accessed by software only, this bit shold clear bu software when system is awaked.) - - - - - 1: enable -0: disable - - - osw1 wrap value - - - - - OSW1 Timer is based on a slow counter, which start counting from the wrap value and decreasing 1 at each 2 cycles(counter frequency is 16K), the counter suspend when disabled. - - - - - Number of frames gsm sleeped. - - - - - Number of frames ltem1 sleeped. - - - Number of sub-frames ltem1 sleeped. - - - - - Number of frames ltem2 sleeped - - - Number of sub-frames ltem2 sleeped. - - - - - LTE sleep frame length, suggest keep the default value. - - - - - LTE sleep sub-frame length, suggest keep -the default value. - - - - - Idle_cg_en enable -1: enable. -0: disable. - - - Pd_pll_en enable -1: enable -0: disable - - - pd_xtal_en enable -1: enable. -0: disable. - - - chip_pd_en enable -1: enable. -0: disable. - - - - - The time from enable clock to obtain clock - - - The time of PLL from power saving state to output normal clock. - - - The time of OSC circuit from power saving -state to normal state. - - - The time of PMIC boost stabilization. - - - - - Current 32K counter value - - - - - target_irq enable -1: enable -0: disable - - - nb_pu_reach_irq enable -1: enable -0: disable - - - nb_tc_end_irq enable -1: enable -0: disable - - - nb_tc_start_irq enable -1: enable -0: disable - - - sys_awk _irq enable -1: enable -0: disable - - - Timer_awk_irq_enable -1: enable -0: disable - - - gsm_pu_reach_irq enable -1: enable -0: disable - - - gsm_tc_end_irq enable -1: enable -0: disable - - - gsm_tc_start_irq enable -1: enable -0: disable - - - osw1_irq enable -1: enable -0: disable - - - tstamp_irq enable -1: enable -0: disable - - - idle_frame_irq enable -1: enable -0: disable - - - idle_h_irq enable -1: enable -0: disable - - - layout_irq enable -1: enable -0: disable - - - - - bit type is changed from w1s to rs. - set cp interrupt enable register when writing 1 to correspond bits. - - - - - bit type is changed from rw1c to rc. - clear cp interrupt enable register when writing 1 to correspond bits. - - - - - bit type is changed from rw1c to rc. - clear interrupt state register when writing 1 to correspond bits. - - - - - target_irq enable -1: enable -0: disable - - - nb_pu_reach_irq enable -1: enable -0: disable - - - sys_awk _irq enable -1: enable -0: disable - - - Timer_awk_irq_enable -1: enable -0: disable - - - gsm_pu_reach_irq enable -1: enable -0: disable - - - osw2_irq enable -1: enable -0: disable - - - - - bit type is changed from w1s to rs. - set ap interrupt enable register when writing 1 to correspond bits. - - - - - bit type is changed from rw1c to rc. - clear ap interrupt enable register when writing 1 to correspond bits. - - - - - bit type is changed from rw1c to rc. - clear ap interrupt state register when writing 1 to correspond bits. - - - - - Ltem1 high-level frame number value - - - - - LTE-M1 frame number - - - LTE-M1 sub-frame number - - - - - frame adjust time -0: adjust at next frame interrupt -1: adjust frame immetiately - - - frame adjust direction -0: postive -1: negative - - - LTE-M1 frame offest value -(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) - - - - - LTE-M1 high-level frame value - - - - - LTE-M1 radio frame value - - - LTE-M1 sub-frame value - - - - - LTE-M1 counter value - - - - - LTE-M1 frame length - - - - - adjust time -0: adjust immetiately -1: adjust at next ltem frame interrupt - - - LTE-M1 adjuste frame length. -current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. - - - - - LTE-M1 high-level frame value time stamp register - - - - - LTE-M1 frame stamp value - - - - - LTE-M1 stamp counter - - - - - LTE-M2 high-level frame value - - - - - LTE-M2 radio frame value - - - LTE-M2 sub-frame value - - - - - adjust time. -0: adjust at next frame interrupt -1: adjust frame immetiately - - - adjust direction -0: postive -1: negative - - - Frame offest value(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value at the time of frame interrupt genereted. otherwise write b-1 into this register then current frame minus this value at the time of frame interrupt generated.) - - - - - LTE-M2 super read frame value - - - - - LTE-M2 radio frame read value - - - LTE-M2 sub-frame read value - - - - - LTE-M counter - - - - - LTE-M2 frame length value - - - - - adjust time -0: adjust immetiately -1: adjust at next ltem frame interrupt - - - LTE-M2 adjuste frame length. -current Ltem frame length load the register when write happens,then backed the LFRAML at the time of lte frame interrupt occurred. - - - - - LTE-M2 high-level frame time stamp register - - - - - LTE-M2 frame stamp value - - - - - LTE-M2 stamp counter - - - - - GSM frame value - - - - - adjust direction -0: postive -1: negative - - - frame offest value -(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 into this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) - - - - - GSM frame overflow value - - - - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - - LTE-M couner locked value - - - - - LTE-M high-level frame locked value, -lock the register LTEM_CFSR_HFN. - - - - - LTE-M frame locked value, lock the register -LTEM_CFSR_FN - - - - - LTE-M counter locked value - - - - - GSM frame locked value - - - - - GSM counter locked value - - - - - lock signal -000: ltem1 frame interrupt. -001: ltem2 frame interrupt. -010: gsm frame interrupt. -011: negative of 32k clock. -100: nb frame interrput. -others: gsm frame interrupt. - - - lock way -00: disable lock -01: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. -10: time stamp when lock signal comes after that bit 5 and 4 clear to be 0. -11: time stamp loop - - - 1: time stamp immediately. -0: not effect - - - - - The initial value of task planning, the register value decrement after a certain number of TS when started task planning, you can get the remaining time by reading this register. - - - - - Layoutt register descending unit. -15h0000: 1 -15h0001: 2 -15h0002: 3 -15h7fff: 32768 - - - Layout count time selection -0: ltem1 timer -1: ltem2 timer - - - task planning -1: start task planing -0: end timing -(The control bit is clear automatically after the timer is finished, and the software can be clear to bestop counting.) - - - - - LTE-M1 frame interrupt delay, take ltem1_framc as a reference. - - - - - LTE-M1 frame interrupt delay, take ltem1_framc as a reference. - - - - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - - Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. - - - Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. - - - - - NB timer enable -0: disable -1: enable - - - LTE-M timer enable -0: disable -1: enable -(note: this timer is the reference lte timer.) - - - GSM timer enable -0: disable -1: enable - - - LTE-M2 timer enable -0: disable -1: enable - - - LTE-M1 timer enable -0: disable -1: enable - - - - - bit type is changed from rw1c to rc. - NB frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - bit type is changed from rw1c to rc. - reference lte frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - bit type is changed from rw1c to rc. - GSM frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - bit type is changed from rw1c to rc. - LTE-M2 frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - bit type is changed from rw1c to rc. - LTE-M1 frame interrupt state -0: No interrupt occurred -1: interrupt occurred - - - - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt frame number -interrupt occurred when current frame reach this register. - - - - - enable(this bit is cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register. - - - - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_GSM - - - - - interrupt occurred when current frame reach this register. - - - - - - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - - - reference lte frame - - - - - reference lte frame locked value - - - - - reference lte counter locked value - - - - - reference 32k counter locked value - - - - - reference lte counter - - - - - GSM frame length value - - - - - 1: enable OSW2 timer -0: disable - - - OSW2 Timing start value - - - - - OSW2 Timer is based on a slow counter, which start counting from the start value and decreasing 1 at each 2 cycles(counter frequency is 16K) - - - - - IDLE GSM frame interrupt generated when GSM frame counter reach GSM_FRAME_GSM and GSM counter equal to this register. - - - - - LTE-M1 frame interrupt delay, -take ltem1_framc as a reference. - - - - - LTE-M2 frame interrupt delay, take ltem2_framc as a reference. - - - - - 1: select pd_xtal, 0: select chip_pd - - - - - the length of pd_xtal(or chip_pd) set to be 1. - - - - - The cycles number of 26M in 2^h_run_time 32k cycles - - - - - The cycles number of 122.88M in of 2^h_run_time 32k cycles - - - - - Enable mode(NB TCU suspend and this bits are cleared by hardware when take over started) -00: disbale or already release TCU. -01: take over TCU immediately -10: take over at gsm frame interrupt. -11: no effect. - - - - - restart TCU when gsm counter reach this register - - - restart mode(this bits cleared when TCU restarts) -00: disable -01: restart TCU immediately -10: restart TCU when gsm frame interrupt occurred. -11: restart TCU when gsm framc equal to TC_END_FRAMC. - - - - - TCU restart enable(accessed by software only.) -Output to the port nb_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. - - - - - The cycles number of 61.44M in the length of 2^h_run_time 32k cycles - - - - - The cycles number of 61.44M in the length of 2^h_run_time 32k cycles - - - - - Number of frames nb timer sleeped. - - - - - nb_frame_irq enable -1: enable -0: disable - - - - - cleared by writing 1 to correspond bit - - - - - NB frame value - - - - - NB frame length value - - - - - adjust direction -0: postive -1: negative - - - frame offest value -(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b- 1 to this register then current frame minus this value when frame interrupt occurred.) - - - - - NB frame overflow value - - - - - NB frame locked value - - - - - NB counter locked value - - - - - enable(this bit cleared automatically after the frame interrupt generated) -0: disable -1: enable - - - interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_NB - - - - - IDLE NB frame interrupt generated when NB frame counter reach IDLE_FRAME_NB and NB counter equal to this register. - - - - - bit type is changed from w1s to rs. - set wakeup enable register by writing 1 to correspond bits. - - - - - bit type is changed from rw1c to rc. - clear wakeup enable register by writing 1 to correspond bits. - - - - - Read enable register. -This bit should be set first when read the value of GSM counter, then rd_enable bit cleared by hardware after locked the GSM counter. - - - GSM framc - - - - - Read enable register. -This bit should be set first when read the value of NB counter, then rd_enable bit cleared by hardware after locked the NB counter. - - - NB framc - - - - - Eliminate jitter delay register - - - Emilinate the jitter from awake signal when writing 1 to correspond bits. - - - - - GGE low power Scheme selection signal -0: use RDA8909 LP Scheme -1: use IDLE module of LP Scheme - - - - - NB low power Scheme selection signal -0: use RDA8909 LP Scheme -1: use IDLE module of LP Scheme - - - - - 1:disbale PLL -0:enable PLL - - - 1:disable PLL -0:enbale PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - 1:disable PLL -0:enable PLL - - - - - bit type is changed from w1s to rs. - set corresponding bits of PD_PLL_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of PD_PLL_SW -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit6 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit5 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit4 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit3 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit2 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit1 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - select hardware signal or software register to control the PLL switch -1:software register(bit0 of PD_PLL_SW) -0:hardware signal(IDLE module of pd_pll signal invert) - - - - - bit type is changed from w1s to rs. - set corresponding bits of PD_PLL_SEL -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of PD_PLL_SEL -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - 1:disable PLL output clk -0:enable PLL output clk - - - - - bit type is changed from w1s to rs. - set corresponding bits of IDLE_CG_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of IDLE_CG_SW -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit6 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit5 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit4 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit3 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit2 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit1 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - select hardware signal or software register to control the PLL output clk switch -1:software register(bit0 of IDLE_CG_SW) -0:hardware signal(IDLE module of idle_cg signal invert) - - - - - bit type is changed from w1s to rs. - set corresponding bits of IDLE_CG_SEL -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of IDLE_CG_SEL -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - 1:control the RF_DIG enter in IDLE -0:control the RF_DIG exit to the IDLE - - - - - select the hardware signal or software register to control the RF_DIG enter in or extit to IDLE model. -1:software register(RF_IDLE_ENABLE_SW) -0:hardware signal( pow_on signal invert of IDLE module) - - - - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - - - UART module reset control: -0: reset -1: reset release - - - UART module clock control: -0: disable -1: enable - - - - - PSRAM IO LATCH: -0: release PSRAM PAD -1: no release PSRAM PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after PSRAM initialization when AP wake-up from deep sleep. - - - LPDDR IO LATCH: -0: release LPDDR PAD -1: no release LPDDR PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after LPDDR initialization when AP wake-up from deep sleep. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - mon15_sel: -00: select nb_en. -01: select awk_sys_valid. -10: select awake[7]. -11: select target_timer_stat[1]. - - - mon14_sel: -00: select gsm_en. -01: select wcn_chip_pd. -10: select awake[6]. -11: select target_timer_stat[0]. - - - mon13_sel: -00: select wake_timer. -01: select wcn_pd_xtal. -10: select awake[5]. -11: select target_timer_enable. - - - mon12_sel: -00: select timer_en_nb. -01: select wcn_pd_pll. -10: select awake[4]. -11: select nb_frame_int. - - - mon11_sel: -00: select timer_en_gsm. -01: select wcn_idle_cg. -10: select awake[3]. -11: nb_lp_pu_done. - - - mon10_sel: -00: select timer_en_ltem2. -01: select nb_en_sel. -10: select awake[2]. -11: select nb_lp_sf_slowrunning. - - - mon9_sel: -00: select timer_en_ltem1. -01: select gsm_en_sel. -10: select awake[1]. -11: select nb_fint. - - - mon8_sel: -00: select idst_nb_timer. -01: select idle_chip_pd. -10: select awake[0]. -11: select gsm_frame_int. - - - mon7_sel: -00: select idst_gsm_timer -01: select idle_pd_xtal. -10: select awk_self. -11: gsm_lp_pu_done. - - - mon6_sel: -00: select idst_ltem2_timer. -01: select idle_pd_pll. -10: select idst_gsm_ltem_timer. -11: select gsm_lp_sf_slowrunning. - - - mon5_sel: -00: select idst_ltem1_timer. -01: select idle_idle_cg. -10: select awk_gsm_ltem_timner. -11: select gsm_fint. - - - mon4_sel: -00: select idct_nb_timer. -01: select pow_on. -10: select idst_sys. -11: select rstctrl_uart. - - - mon3_sel: -00: select idct_gsm_timer. -01: select idct_sys_valid. -10: select nb_lp_pu_reach. -11: select clken_uart. - - - mon2_sel: -00: select idct_ltem2_timer. -01: select idct_ap. -10: select gsm_lp_pu_reach. -11: select psram_latch_reg. - - - mon1_sel: -00: select idct_ltem1_timer -01: select idct_cp. -10: select osw2_awk -11: select lpddr_latch_reg - - - mon0_sel: -00: select idct_timer. -01: select ltem1_fint. -10: select osw1_awk. -11: select ltem2_fint - - - - - set corresponding bits of MON_SEL -0:Invariance of corresponding bits -1:set corresponding bits - - - - - clear corresponding bits of MON_SEL -0:Invariance of corresponding bits -1:clear corresponding bits - - - - - Interrupt generated when the reference 32K counter reach to this register value. - - - - - 1: disable target timer. -0: enable - - - - - The locked value of reference 32K when interrupt generated. - - - - - Indicat the state of target timer in 32K clock domain - - - Indicate the state of target timer in 122.88M clock domain - - - - - 0:SLOW_CLK and system clk selected by software bit conrtol -1:SLOW_CLK and system clk select by hareware signal control - - - - - 0:SLOW_CLK selected(between 26M and 32k) by software bit control -1:SLOW_CLK selected(between 26M and 32k) by hareware signal control - - - - - The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sysmail0 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail0 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail0 interrupt clean register - - - - - sysmail0 interrupt mask register - - - - - sysmail0 interrupt status register - - - - - sysmail0 interrupt mask status register - - - - - - sysmail1 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail1 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail1 interrupt clean register - - - - - sysmail1 interrupt mask register - - - - - sysmail1 interrupt status register - - - - - sysmail1 interrupt mask status register - - - - - - sysmail2 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail2 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail2 interrupt clean register - - - - - sysmail2 interrupt mask register - - - - - sysmail2 interrupt status register - - - - - sysmail2 interrupt mask status register - - - - - - sysmail3 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail3 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail3 interrupt clean register - - - - - sysmail3 interrupt mask register - - - - - sysmail3 interrupt status register - - - - - sysmail3 interrupt mask status register - - - - - - sysmail4 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail4 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail4 interrupt clean register - - - - - sysmail4 interrupt mask register - - - - - sysmail4 interrupt status register - - - - - sysmail4 interrupt mask status register - - - - - - sysmail5 Interrupt generate register - - - - - bit type is changed from ws to rs. - sysmail5 interrupt bit set register - - - - - bit type is changed from w1c to rc. - sysmail5 interrupt clean register - - - - - sysmail5 interrupt mask register - - - - - sysmail5 interrupt status register - - - - - sysmail5 interrupt mask status register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clock select for module of IDLE_H: -00: 122.88M clock -01: 26M clock -10: 61.44M clock -11: 122.88M clock - - - clock select for module of ZSP_WD: -0: 32K clock -1: 26M clock - - - clock select for module of BB_SYSCTRL_WD: -0: 32K clock -1: 26M clock - - - clock select of 480M and SLOW: -0: SLOW clock -1: 480M clock - - - clock select of 122M and SLOW: -0: SLOW clock -1: 122.88M clock - - - - - bit type is changed from w1s to rs. - set corresponding bits of CLKSEL register: -0: Invariance of corresponding bits -1: set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of CLKSEL register: -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - ZSP and bus clock division: -0: no clock division -1: 1/16 clock division -2: 2/16 clock division -F: 15/16 clock division - - - - - LTE accelerator function clock division: -0: no clock division -1: 1/16 clock division -2: 2/16 clock division -F: 15/16 clock division - - - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - - - bit type is changed from w1s to rs. - set corresponding bits of CLKEN_BB_SYSCTRL regsiter: -0: Invariance of corresponding bits -1: set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of CLKSEL register -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - 0: close -1: open - - - - - bit type is changed from w1s to rs. - set corresponding bits of CLKEN_ZSP regsiter: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of CLKEN_ZSP register: -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - - bit type is changed from w1s to rs. - set corresponding bits of CLKEN_LTE register -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of CLKEN_LTE: -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - 0: ZSPCORE clock switch controlled by hardware -1: ZSPCORE clock switch controlled by register - - - - - 0: ZSP_AXIDMA clock switch controlled by hardware -1: ZSP_AXIDMA clock switch controlled by register - - - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - - - bit type is changed from w1s to rs. - set corresponding bits of RSTCTRL_BB_SYSCTRL register: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of RSTCTRL_BB_SYSCTRL: -0: Invariance of corresponding bits -1: set 1 of corresponding bits - - - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - - - bit type is changed from w1s to rs. - set corresponding bits of RSTCTRL_ZSP register: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of RSTCTRL_ZSP: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset) -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - 0: reset -1: no reset - - - - - bit type is changed from w1s to rs. - set corresponding bits of RSTCTRL_LTE register: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of RSTCTRL_LTE: -0: Invariance of corresponding bits -1: clean corresponding bits - - - - - 0: reset -1: no reset - - - - - 0: reset -1: no reset - - - - - waiting time of bus entered low power model,calculated by bus clock - - - - - Control bit of ZSP_CORE DOMAIN low power model -0: enable -1: disable - - - Control bit of PHY DOMAIN low power model -0: enable -1: disable - - - control bit of SWITCH2 DOMAIN low power model -0: enable -1: disable - - - control bit of SWITCH1 DOMAIN low power model: -0: enable -1: disable - - - - - bit type is changed from w1s to rs. - set corresponding bits of ZSP_BUSLPMC register -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of ZSP_BUSLPMC -0: Invariance of corresponding bits -1: clean corresponding bits - - - - - control bit of ZSPCORE force entering in low power model: -0: disable -1: enable - - - control bit of PHY DOMAIN force entering in low power model: -0: disable -1: enable - - - control bit of SWITCH2 DOMAIN force entering in low power model: -0: disable -1: enable - - - control bit of SWITCH1 DOMAIN force entering in low power model: -0: disable -1: enable - - - - - bit type is changed from w1s to rs. - set corresponding bits of ZSP_BUSFORCELPMC: -0: Invariance of corresponding bits -1: clean corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of ZSP_BUSFORCELPMC: -0: Invariance of corresponding bits -1: clean corresponding bits - - - - - 0: MAILBOX clock switch controlled by hardware -1: MAILBOX clock switch controlled by register - - - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - - bit type is changed from w1s to rs. - set corresponding bits of CLKEN_LTE_INTF register -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of CLKEN_LTE_INTF register -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - 0: LTE module clock auto gating individual -1: LTE modules invide into two parties : "uplink" and "downlink", and auto gating individual - - - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - - bit type is changed from w1s to rs. - set corresponding bits of LTE_AUTOGATE_EN register -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of LTE_AUTOGATE_EN register -0: Invariance of corresponding bits -1: clean of corresponding bits - - - - - When LTE autogating function enable, After module "running" signal was pull down, a counter begin to count from zero.LTE modules clock will be gated when the counter counts to this number value. - - - - - - - - - AON_LP hardware power domain switch: -1:AON_LP power domain switch controlled by hardware signal. -0:AON_LP power domain switch controlled by regiser. - - - BTFM hardware power domain switch: -1:BTFM power domain switch controlled by hardware signal. -0:BTFM power domain switch controlled by regiser. - - - RF hardware power domain switch: -1:RF power domain switch controlled by hardware signal. -0:RF power domain switch controlled by register. - - - GGE hardware power domian switch: -1:GGE power domain switch controlled by hardware signal. -0:GGEpower domain switch controlled by register. - - - LTE hardware power domain switch: -1:LTE power domain switch controlled by hardware signal. -0:LTE power domain switch controlled by register. - - - ZSP hardware power domain switch: -1:ZSP power domain switch controlled by hardware signal . -0:ZSP power domain switch controlled by register. - - - AP hardware power domain switch: -1:AP power domain switch controlled by hardware signal. -0:AP power domain switch controlled by register. - - - - - AP power domain on: -1:AP power domain on. -0:after AP power domain on,hardware cleared. - - - AP power domain off: -1:AP power domian off. -0:after AP power domain off,hareware cleared. - - - - - ZSP power domain on: -1:ZSP power domain on. -0:after ZSP power domain on,hardware cleared. - - - ZSP power domain off: -1:ZSP power domain off. -0:after ZSP power domain off,hardware cleared. - - - - - LTE power domain on: -1:LTE power domain on. -0:after LTE power domain on,hardware cleared. - - - LTE power domain off: -1:LTE power domain off. -0:after LTE power domain off,hardware cleared. - - - - - GGE power domain on: -1:GGE power domain on. -0:after GGE power domain on,hardware cleared. - - - GGE power domain off: -1:GGE power domain off. -0:after GGE power domain off,hardware cleared. - - - - - RF power domain on: -1:RF power domain on. -0:after RF power domain on,hardware cleared. - - - RF power domain off: -1:RF power domain off. -0:after RF power domain off,hardware cleared. - - - - - BTFM power domain on: -1:BTFM power domain on. -0:after BTFM power domain on,hardware cleared. - - - BTFM power domain off: -1:BTFM power domain off. -0:after BTFM power domain off,hardware cleared. - - - - - AON_LP power domain on: -1:AON_LP power domain on. -0:after AON_LP power domain on,hardware cleared. - - - AON_LP power domain off: -1:AON_LP power domain off. -0:after AON_LP power domain off,hardware cleared. - - - - - AP power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off of the middle state. - - - AP power domain current state: -1:on -0:off - - - - - ZSP power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off of the middle state. - - - ZSP power domain current state: -1:on -0:off - - - - - LTE power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off of the middle state. - - - LTE power domain current state: -1:on -0:off - - - - - GGE power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off the middle state. - - - GGE power domain current state: -1:on -0:off - - - - - RF power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off the middle state. - - - RF power domain current state: -1:on -0:off - - - - - BTFM power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off the middle state. - - - BTFM power domain current state: -1:on -0:off - - - - - AON_LP power domain stable state: -1:power domain stable. -0:power domain unstable,in the power on/off the middle state. - - - AON_LP power domain current state: -1:on -0:off - - - - - power control state machine for Intermediate state delay value,use function clk count - - - - - power gating cell domain power-on of waiting time value,use function clk count. - - - - - All of power gating cell power-on of waiting time value,use function clk count. - - - - - 0:release DDR port signals -1:no release DDR port signals.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after ddr initialization when AP wake-up from deep sleep. - - - - - 1:vote for off ZSP power domain -0:vote for on ZSP power domain - - - 1:vote for off ZSP power domain -0:vote for on ZSP power domain - - - 1:vote for off ZSP power domain -0:vote for on ZSP power domain - - - - - bit type is changed from w1s to rs. - set corresponding bits of ZSP_PD_POLL -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of ZSP_PD_POLL -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - - wcn2sys_sleep signal state - - - wcn2sys_osc_en signal state - - - wcn2sys_wakeup signal state - - - control WCN sub_system of awake siganl:sys2wcn_awake - - - - - when this bit set "1",the hardware signal arm_slp_req will enter in ARM sub_system ,force ARM's AXI bus enter LP model. -0:normal work -1:SLEEP request - - - - - the work status of AXI bus in ARM sub_system . -0:normal work -1:low_power state - - - - - 0:the hardware signal arm_slp_req controlled by ARM_SLP_REQ_SW register,and pwrctrl status is bypass. -1:pwrctrl status controlled by the hardware signal of arm_slp_req. - - - - - when this bit set "1",zsp_slp_req signal will enter in ZSP sub_system ,force ZSP's AXI bus enter in LP model. Before ZSP sub_system software reset,need this bit set "1",and wait ZSP_SLP_ACK register to be "1".after ZSP sub_system reset,should set this bit "0",so that ZSP bus can normal work. -0:normal work -1:SLEEP request - - - - - the status of AXI bus in ZSP sub_system. -0:normal work -1:low_power state - - - - - 0:zsp_slp_req signal controlled by ZSP_SLP_REQ_SW register,and pwrctrl status is bypass. -1: pwrctrl status controlled by the hareware signal of zsp_slp_req - - - - - when this bit set "1",ddr_slp_req hardware signal will enter in ARM sub_system,force DDR enter in self refresh. -0:normal work -1:SLEEP request - - - - - DDR work status -0:normal work status -1:low_power(self_refresh)state - - - - - 0:ddr_slp_req is the hardware signal controlled by DDR_SLP_REQ_SW register,and pwrctrl corresponding status is bypass. -1:pwrctrl status controlled by the hareware signal of ddr_slp_req - - - - - 0:normal work -1:DDR sleep request time out - - - 0:normal work -1:ZSP bus sleep request time out - - - 0:normal work -1:ARM bus sleep request time out - - - - - power domain auto control state machine status - - - AON_LP power domain state of machine status - - - BTFM power domain state of machine status - - - RF power domain state of machine status - - - GGE power domain state of machine status - - - LTE power domain state of machine status - - - ZSP power domain state of machine status - - - ARM power domain state of machine status - - - - - 0:power domain control siganl conrtolled by related bit of PWRCTRL_SW register -1:power domain conrtol signal conrtolled by hardware signal of PWRCTRL - - - - - btfm_pwr_ctrl - - - btfm_pwr_ctrl_pre - - - btfm_hold - - - btfm_rst_ctrl - - - btfm_clk_ctrl - - - rf_pwr_ctrl - - - rf_pwr_ctrl_pre - - - rf_hold - - - rf_rst_ctrl - - - rf_clk_ctrl - - - gge_pwr_ctrl - - - gge_pwr_ctrl_pre - - - gge_hold - - - gge_rst_ctrl - - - gge_clk_ctrl - - - lte_pwr_ctrl - - - lte_pwr_ctrl_pre - - - lte_hold - - - lte_rst_ctrl - - - lte_clk_ctrl - - - zsp_pwr_ctrl - - - zsp_pwr_ctrl_pre - - - zsp_hold - - - zsp_rst_ctrl - - - zsp_clk_ctrl - - - ap_pwr_ctrl - - - ap_pwr_ctrl_pre - - - ap_hold - - - ap_rst_ctrl - - - ap_clk_ctrl - - - - - bit type is changed from w1s to rs. - set corresponding bits of PWRCTRL_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of PWRCTRL_SW -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - aon_lp_pwr_ctrl - - - aon_lp_pwr_ctrl_pre - - - aon_lp_hold - - - aon_lp_rst_ctrl - - - aon_lp_clk_ctrl - - - - - bit type is changed from w1s to rs. - set corresponding bits of PWRCTRL_SW -0:Invariance of corresponding bits -1:set 1 of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of PWRCTRL_SW1 -0:Invariance of corresponding bits -1:clean corresponding bits - - - - - - - - - Interrupt vector entry address - - - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RASPD type EMA signal - - - RASPD type EMA signal - - - RASPU type EMA signal - - - RASPU type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RASPD type EMA signal - - - RASPD type EMA signal - - - RASPU type EMA signal - - - RASPU type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - - - ROM type EMA signal - - - ROM type EMA signal - - - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RFTPD type EMA signal - - - RASPD type EMA signal - - - RASPD type EMA signal - - - RASPU type EMA signal - - - RASPU type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - RADPD type EMA signal - - - - - awqos_zsp_axidma - - - arqos_zsp_axidma - - - awqos_zsp_ibus - - - arqos_zsp_ibus - - - awqos_zsp_dbus - - - arqos_zsp_dbus - - - - - - Used to store and determine whether the pow on and Other relevant information is in a calibrated version - - - - - RF scheme selection signal -0: use SOC RF scheme signal -1: use chip RF scheme - - - - - AD/DA data path select signal -1: LTE -0: NBIOT - - - - - AD/DA data path select signal -0: NBIOT -1: GGE - - - - - WCN 26M clock control: -0: disable -1: enable - - - ADI module 26M clock control: -0: disable -1: enable - - - VAD module 26M clock control: -0: disable -1: enable - - - AUD2AD module of 26M clock select: -0: AP_26M -1: after 17/16 clock operation - - - AUD2AD module of 26M clock switch: -0: disable -1: enable - - - audio pll input Reference clock select: -0: AP_26M -1: after 17/16 clock operation - - - 0: disable -1: enable - - - 0: disable -1: enable - - - 0: disable -1: enable - - - - - bit type is changed from w1s to rs. - set corresponding bits of RF_ANA_26M_CTRL register: -0: Invariance of corresponding bits -1: set "1" of corresponding bits - - - - - bit type is changed from w1c to rc. - clean corresponding bits of RF_ANA_26M_CTRL register: -0: Invariance of corresponding bits -1: clean corresponding bits - - - - - 0: DISABLE -1: ENABLE -When AP power domain shut-down, this bit will be clear to "0". Need software re-enable. - - - - - 0: do not force ddr_slp_ctrl wakeup -1: force ddr_slp_ctrl wakeup - - - - - force ddr_slp_ctrl wakeup done when "1" - - - - - after count N cycles,ddr_slp_ctrl begin sleep sequence when sleep condition meet. - - - - - LVDS_SPI_SEL - - - - - 0: select idle_test[16] (LTE frame irq signal.) -1: select lte_rbdp_tx[11]; - - - - - bit type is changed from rw1c to rc. - Indicate RFSPI_CONFILICT_IRQ happened when "1". Can be cleared by software writing "1". - - - bit type is changed from rw1c to rc. - Indicate TXFIFO_FULL_IRQ happened when "1". Can be cleared by software writing "1". - - - - - 0: select lte_up_rfctrl; -1: select rf_gpio_o[9]; - - - - - 0: 3-wire mode; -1: 4-wire mode; - - - - - - General ctrl signal for GGENB. - - - - - 1:enable -0:disable - - - 1:enable -0:disable - - - - - - - - - 0 - - - - - 1 - - - - - 2 - - - - - 3 - - - - - 4 - - - - - 5 - - - - - 6 - - - - - 7 - - - - - monitor_o[0] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[1] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[2] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[3] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[4] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[5] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[6] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - monitor_o[7] -3'h0: 0 -3'h1: 1 -3'h2: 2 -3'h3: 3 -3'h4: 4 -3'h5: 5 -3'h6: 6 -3'h7: 7 - - - - - 1 -0 - - - - - monitor output signal value. - - - - - - - - - WD_PROT function enable -0: WD_PROT register function invalid -1: WD_PROT register function valid - - - 0: timer mode -1: watchdog mode - - - 0000: no pre-div -0001: 1/2 pre-div -0010: 1/4 pre-div -0011: 1/8 pre-div -0100: 1/16 pre-div -0101: 1/32 pre-div -0110: 1/64 pre-div -0111: 1/128 pre-div -1000: 1/256 pre-div -others: no pre-div - - - 0: no influence to current timer value -1: clear current timer value to zero - - - 0: interrupt disable -1: interrupt enable - - - 0: keep the timer value when it reach the loaded value -1: clear the timer value to zero when it reach the loaded value - - - 0: stop -1: run -Note: WD_LOAD1/2 register can not be writen when this bit is '1'. -This bit will be clear by hardware when reset signal generated in watchdog mode; and in timer mode, this bit will be clear by hardware when timer value reach the loaded value and 'AR' is set to '0'. - - - - - WD_CONF and WD_LOAD1/2 register can be writen when this register value is 0xCCCC. - - - - - The low 32-bits of the load value. - - - - - The high 32-bits of the load value. - - - - - The low 32-bits of the timer value. - - - - - The high 32-bits of the timer value. - - - - - Write orderly 0xAAAA and 0x5555 to convert to timer mode from watchdog mode. -Write orderly 0xAAAA and 0x4444 to convert to watchdog mode from timer mode. -Write 0xBBBB to "feed dog" in watchdog mode. - - - - - 0: disable timer divider -1: enable timer divider - - - f= FuncClk/(DIV+1) - - - - - bit type is changed from w1c to rc. - The counter value of timer divider. - - - - - - - - - bit type is changed from w1c to rc. - Interrupt source flag(0-31) -0: no interrupt -1: capture interrupt - - - - - bit type is changed from w1c to rc. - Interrupt source flag(32-63) -0: no interrupt -1: capture interrupt - - - - - Interrupt mask bit (0-30) -0: open interrupt -1: mask interrupt - - - - - Interrupt mask bit (32-63) -0: open interrupt -1: mask interrupt - - - - - bit type is changed from w1s to rs. - sets the corresponding bit in the mask register (0-31) -0: the corresponding bit in the mask register do not change. -1: sets the corresponding bit in the mask register to '1'. - - - - - bit type is changed from w1s to rs. - sets the corresponding bit in the mask register(32-64) -0: the corresponding bit in the mask register do not change. -1: sets the corresponding bit in the mask register to '1'. - - - - - bit type is changed from w1c to rc. - clears the corresponding bit in the mask register(0-31) -0: the corresponding bit in the mask register do not change -1: Writing '1' clears the corresponding bit in the mask register to '0'. - - - - - bit type is changed from w1c to rc. - clears the corresponding bit in the mask register(32-64) -0: the corresponding bit in the mask register do not change -1: Writing '1' clears the corresponding bit in the mask register to '0'. - - - - - Global interrupt enable BIT -0: Interrupt is decided by corresponding mask bit -1: Maks all Interrupt - - - - - FIQ OR IRQ Select (0-31) -0: corresponding interrupt send to arm through IRQ -1: corresponding interrupt send to arm through FIR - - - - - FIQ OR IRQ Select (32-63) -0: corresponding interrupt send to arm through IRQ -1: corresponding interrupt send to arm through FIR - - - - - - IRQ status bit(0-31) -0: corresponding interrupt source no interrupt -1: corresponding interrupt source no interrupt send interrupt to arm through IRQ - - - - - IRQ status bit(32-63) -0: corresponding interrupt source no interrupt -1: corresponding interrupt source no interrupt send interrupt to arm through IRQ - - - - - IRQ interrupt source code -0000000: IRQ0 -0000001: IRQ1 -0000010: IRQ2 -...... -0111111: IRQ63 - - - - - Clear interrupt status bit -0: no operation -1: clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low - - - - - FIQ status bit(0-31) -0: corresponding interrupt source no interrupt -1: corresponding interrupt source no interrupt send interrupt to arm through Fiq - - - - - FIQ status bit(32-63) -0: corresponding interrupt source no interrupt -1: corresponding interrupt source no interrupt send interrupt to arm through Fiq - - - - - fiq interrupt source code -0000000: FIQ0 -0000001: FIQ1 -0000010: FIQ2 -...... -0111111: FIQ63 - - - - - Clear interrupt status bit -0: no operation -1: clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - Interrupt prio -0: Interrupt prio 0 -1: Interrupt prio 1 -...... -7: Interrupt prio 7 -Prio 0 is corrosponed to the highist prio - - - - - - - - - general used register security visit enable -0security -1unsecurity - - - response error stop function enable -0enable -1disable - - - the number of outstanding that can be send out -0: 2 -1: 3 -2: 4 - - - multe-channel transport priority mode control -0: there is no priority in the channels, using polling to DMA data -1: smaller channel number has high-priority.high-priority move data before low-priority channels - - - interrupt control bit -0: no interruption occurs when all logical channels finish -1: interruption occurs when all logical channels finish - - - the control bit of logical channel transport finish -0: don't stop all the channel,or automatically clear after setting -1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared - - - - - in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. - - - - - stop status -0: not finish -1: finish - - - the channel number of the final transmission -0000: channel 0 just finished the transmission -0001: channel 1 just finished the transmission -0010: channel 2 just finished the transmission -1011: channel 11 just finished the transmission -others: nonentity - - - - - 0 -1 - - - channel 11 interrupts state -0: the channel 11 has not been interrupted, or the interrupt bit has been cleared -1: channel 11 is interrupted - - - channel 10 interrupts state -0: the channel 10 has not been interrupted, or the interrupt bit has been cleared -1: channel 10 is interrupted - - - channel 9 interrupts state -0: the channel 9 has not been interrupted, or the interrupt bit has been cleared -1: channel 9 is interrupted - - - channel 8 interrupts state -0: the channel 8 has not been interrupted, or the interrupt bit has been cleared -1: channel 8 is interrupted - - - channel 7 interrupts state -0: the channel 7 has not been interrupted, or the interrupt bit has been cleared -1: channel 7 is interrupted - - - channel 6 interrupts state -0: the channel 6 has not been interrupted, or the interrupt bit has been cleared -1: channel 6 is interrupted - - - channel 5 interrupts state -0: the channel 5 has not been interrupted, or the interrupt bit has been cleared -1: channel 5 is interrupted - - - channel 4 interrupts state -0: the channel 4 has not been interrupted, or the interrupt bit has been cleared -1: channel 4 is interrupted - - - channel 3 interrupts state -0: the channel 3 has not been interrupted, or the interrupt bit has been cleared -1: channel 3 is interrupted - - - channel 2 interrupts state -0: the channel 2 has not been interrupted, or the interrupt bit has been cleared -1: channel 2 is interrupted - - - channel 1 interrupts state -0: the channel 1 has not been interrupted, or the interrupt bit has been cleared -1: channel 1 is interrupted - - - channel 0 interrupts state -0: the channel 0 has not been interrupted, or the interrupt bit has been cleared -1: channel 0 is interrupted - - - - - state of IRQ 23 generate requests of moving data -0: IRQ 23 does not generate requests of moving data -1: IRQ 23 generate requests of moving data - - - state of IRQ 22 generate requests of moving data -0: IRQ 22 does not generate requests of moving data -1: IRQ 22 generate requests of moving data - - - state of IRQ 21 generate requests of moving data -0: IRQ 21 does not generate requests of moving data -1: IRQ 21 generate requests of moving data - - - state of IRQ 20 generate requests of moving data -0: IRQ 20 does not generate requests of moving data -1: IRQ 20 generate requests of moving data - - - state of IRQ 19 generate requests of moving data -0: IRQ 19 does not generate requests of moving data -1: IRQ 19 generate requests of moving data - - - state of IRQ 18 generate requests of moving data -0: IRQ 18 does not generate requests of moving data -1: IRQ 18 generate requests of moving data - - - state of IRQ 17 generate requests of moving data -0: IRQ 17 does not generate requests of moving data -1: IRQ 17 generate requests of moving data - - - state of IRQ 16 generate requests of moving data -0: IRQ 16 does not generate requests of moving data -1: IRQ 16 generate requests of moving data - - - state of IRQ 15 generate requests of moving data -0: IRQ 15 does not generate requests of moving data -1: IRQ 15 generate requests of moving data - - - state of IRQ 14 generate requests of moving data -0: IRQ 14 does not generate requests of moving data -1: IRQ 14 generate requests of moving data - - - state of IRQ 13 generate requests of moving data -0: IRQ 13 does not generate requests of moving data -1: IRQ 13 generate requests of moving data - - - state of IRQ 12 generate requests of moving data -0: IRQ 12 does not generate requests of moving data -1: IRQ 12 generate requests of moving data - - - state of IRQ 11 generate requests of moving data -0: IRQ 11 does not generate requests of moving data -1: IRQ 11 generate requests of moving data - - - state of IRQ 10 generate requests of moving data -0: IRQ 10 does not generate requests of moving data -1: IRQ 10 generate requests of moving data - - - state of IRQ 9 generate requests of moving data -0: IRQ 9 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 8 generate requests of moving data -0: IRQ 8 does not generate requests of moving data -1: IRQ 8 generate requests of moving data - - - state of IRQ 7 generate requests of moving data -0: IRQ 7 does not generate requests of moving data -1: IRQ 7 generate requests of moving data - - - state of IRQ 6 generate requests of moving data -0: IRQ 6 does not generate requests of moving data -1: IRQ 6 generate requests of moving data - - - state of IRQ 5 generate requests of moving data -0: IRQ 5 does not generate requests of moving data -1: IRQ 5 generate requests of moving data - - - state of IRQ 4 generate requests of moving data -0: IRQ 4 does not generate requests of moving data -1: IRQ 4 generate requests of moving data - - - state of IRQ 3 generate requests of moving data -0: IRQ 3 does not generate requests of moving data -1: IRQ 3 generate requests of moving data - - - state of IRQ 2 generate requests of moving data -0: IRQ 2 does not generate requests of moving data -1: IRQ 2 generate requests of moving data - - - state of IRQ 1 generate requests of moving data -0: IRQ 1 does not generate requests of moving data -1: IRQ 1 generate requests of moving data - - - state of IRQ 0 generate requests of moving data -0: IRQ 0 does not generate requests of moving data -1: IRQ 0 generate requests of moving data - - - - - state of ACK 23 generate requests of moving data -0: ACK 23 does not generate requests of moving data -1: ACK 23 generate requests of moving data - - - state of ACK 22 generate requests of moving data -0: ACK 22 does not generate requests of moving data -1: ACK 22 generate requests of moving data - - - state of ACK 21 generate requests of moving data -0: ACK 21 does not generate requests of moving data -1: ACK 21 generate requests of moving data - - - state of ACK 20 generate requests of moving data -0: ACK 20 does not generate requests of moving data -1: ACK 20 generate requests of moving data - - - state of ACK 19 generate requests of moving data -0: ACK 19 does not generate requests of moving data -1: ACK 19 generate requests of moving data - - - state of ACK 18 generate requests of moving data -0: ACK 18 does not generate requests of moving data -1: ACK 18 generate requests of moving data - - - state of ACK 17 generate requests of moving data -0: ACK 17 does not generate requests of moving data -1: ACK 17 generate requests of moving data - - - state of ACK 16 generate requests of moving data -0: ACK 16 does not generate requests of moving data -1: ACK 16 generate requests of moving data - - - state of ACK 15 generate requests of moving data -0: ACK 15 does not generate requests of moving data -1: ACK 15 generate requests of moving data - - - state of ACK 14 generate requests of moving data -0: ACK 14 does not generate requests of moving data -1: ACK 14 generate requests of moving data - - - state of ACK 13 generate requests of moving data -0: ACK 13 does not generate requests of moving data -1: ACK 13 generate requests of moving data - - - state of ACK 12 generate requests of moving data -0: ACK 12 does not generate requests of moving data -1: ACK 12 generate requests of moving data - - - state of ACK 11 generate requests of moving data -0: ACK 11 does not generate requests of moving data -1: ACK 11 generate requests of moving data - - - state of ACK 10 generate requests of moving data -0: ACK 10 does not generate requests of moving data -1: ACK 10 generate requests of moving data - - - state of ACK 9 generate requests of moving data -0: ACK 9 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 8 generate requests of moving data -0: ACK 8 does not generate requests of moving data -1: ACK 8 generate requests of moving data - - - state of ACK 7 generate requests of moving data -0: ACK 7 does not generate requests of moving data -1: ACK 7 generate requests of moving data - - - state of ACK 6 generate requests of moving data -0: ACK 6 does not generate requests of moving data -1: ACK 6 generate requests of moving data - - - state of ACK 5 generate requests of moving data -0: ACK 5 does not generate requests of moving data -1: ACK 5 generate requests of moving data - - - state of ACK 4 generate requests of moving data -0: ACK 4 does not generate requests of moving data -1: ACK 4 generate requests of moving data - - - state of ACK 3 generate requests of moving data -0: ACK 3 does not generate requests of moving data -1: ACK 3 generate requests of moving data - - - state of ACK 2 generate requests of moving data -0: ACK 2 does not generate requests of moving data -1: ACK 2 generate requests of moving data - - - state of ACK 1 generate requests of moving data -0: ACK 1 does not generate requests of moving data -1: ACK 1 generate requests of moving data - - - state of ACK 0 generate requests of moving data -0: ACK 0 does not generate requests of moving data -1: ACK 0 generate requests of moving data - - - - - - channel 11 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 10 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 9 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 8 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 7 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 6 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 5 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 4 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 3 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 2 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 1 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - channel 0 interrupt allocation bit -0: the interrupt of the channel is output to the dma_irq interruption -1: the interrupt of the channel is output to the dma_irq1 interruption - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - response error interrupt enable -0disable -1enable - - - security visit -0security -1unsecurity - - - after moving a COUNTP,the DADDR is automatically returned to the original destination addr -0: the destination addr does not automatically ring back -1: the destination addr automatically ring back - - - after moving a COUNTP,the SADDR is automatically returned to initial source addr -0: the source addr does not automatically ring back -1: the source addr automatically ring back - - - the length of moving data in one interrupt in interrupted mode -0: move a countp -1: move all count - - - mandatory transmission control bit -0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. -1: force a transmission without interruption in interrupted mode. - - - fixed destination addr control bit -0: destination addr can be incremented by different data types during transmission -1: the destination addr is fixed during transmission - - - fixed source addr control bit -0: source addr can be incremented by different data types during transmission -1: the source add is fixed during transmission - - - control bit of each transmission interruption -0: each transmission does not produce an interrupt signal -1: each transmission prodece an interrupt signal - - - control bit of whole transmission interruption -0: whole transmission does not produce an interrupt signal -1: whole transmission prodece an interrupt signal - - - control bit of synchronous interrupt trigger mode -0: this channel is in normal transmission mode -1: this channel is in sync interrupt trigger mode - - - data types -00: Byte (8 bits) -01: Half Word (16 bits) -10: Word (32 bits) -11: DWord (64 bits) - - - start control bit -0: stop the transmission of this channel -1: start the transmission of this channel - - - - - this channel corresponds to the ACK signal that is triggered -00000: ACK0 -00001: ACK1 -00010: ACK2 -10111: ACK23 - - - the source of interrupt trigger for this channel -00000: IRQ0 trigger transmission -00001: IRQ1 trigger transmission -00010: IRQ2 trigger transmission -01111: IRQ15 trigger transmission -10111: IRQ23trigger transmission - - - - - the source addr of this channel - - - - - the destination addr of this channel - - - - - The total length of the transmitted data is measured in byte - - - - - the data length per transmission is measured in byte - - - - - bit type is changed from w1c to rc. - response error interrupt flag -0unset -1set - - - bit type is changed from w1c to rc. - response error status -0unset -1set - - - bit type is changed from w1c to rc. - data linked list is paused -0: not paused -1: paused - - - bit type is changed from w1c to rc. - the linked list is completed -0: not completed -1: completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - COUNT transmission completion indication -0: COUNT is not completed -1: COUNT is completed - - - bit type is changed from w1c to rc. - scatter-gather pause - - - bit type is changed from w1c to rc. - the number of scatter-gather transfers completed -0x0000: 0 -0xFFFF: 65535 times - - - bit type is changed from w1c to rc. - scatter-gather transmission completion -0: scatter-gather is not completed -1: scatter-gather is completed - - - bit type is changed from w1c to rc. - COUNTP transmission completion indication -0: COUNTP is not completed -1: COUNTP is completed - - - bit type is changed from w1c to rc. - the whole transmission completion indication -0: the whole transmission is not completed -1: the whole transmission is completed - - - bit type is changed from w1c to rc. - the channel runs state -0: IDLE -1: TRANS - - - - - first addr of the structural body - - - - - scatter-gather transmission frequency -0x0: unlimited limit -0xFFFF: 65535 times - - - linked table read control -0: after the data is moved,the linked list isread and no descriptor_req are required -1: descriptor_req is needed to read the linked list - - - scatter-gather pause interrupt enable -0: disable -1: enable - - - scatter-gather complete interrupt enable -0: disable -1: enable - - - bit type is changed from w1c to rc. - scatter-gather function enable -0: disable -1: enable - - - - - channel runs position -0: the running bit of the channel does not change -1: set the running bit of the channel - - - - - clear the running bit of channel -0: the running bit of the channel does not change -1: clear the running bit of the channel - - - - - - - - - reserved fields of DFT - - - 1: HW insert zeros for imag part, 0: SW provide zeros - - - 1: mask DMA out intr; 0:not mask DMA out intr - - - 1: mask Calc intr; 0:not mask Calc intr - - - 1: mask DMA in intr; 0:not mask DMA in intr - - - 1:iq swap; 0:iq not swap - - - 1:fft; 0:ifft - - - force clock gating enable - - - base address of ram in dft - - - index of DFT N length - - - - - bit type is changed from w1s to rs. - write clear pulse for DFT error status, read in err status - - - bit type is changed from w1s to rs. - write clear pulse for DFT dma out interrupts, read in dma out interrupt source before mask - - - bit type is changed from w1s to rs. - write clear pulse for DFT calc interrupts, read in calc interrupt source before mask - - - bit type is changed from w1s to rs. - write clear pulse for DFT dma in interrupts, read in dma in interrupt source before mask - - - bit type is changed from w1s to rs. - write start trigger pulse of DFT, which will do dma rx, and read in dma rx request status - - - - - 1: interrupt source in dma out; 0 : no interrupt, read interrupt after mask - - - 1: interrupt source in calc; 0 : no interrupt, read interrupt after mask - - - 1: interrupt source in dma in; 0 : no interrupt, read interrupt after mask - - - DFT error status report upon interrupt gen, cleared via DFT_err_stat_clr set - - - DFT state machine status report - - - - - - - - - Monitor -0 -1 -:BUS Monitor - - - - - 0 -1 - - - BUSY -1 -0 - - - RBUSY -1 -0 - - - WBUSY -1 -0 - - - 1 -0 - - - 1 -0 - - - 1 -0 - - - 1 -0 - - - 1 -0 - - - 0 -1 -MON_M0_ADDR_WIDIDDDR0x0-0x1fff_ffffDDR - - - - - , -PCLK - - - - - MON_NUM_EN,MASTER - - - - - MASTER0 -0 -1 - - - 0 -1 - - - 0 -1 - - - LOCK -0 -1 - - - - - bit type is changed from w1c to rc. -0 -1 - - - bit type is changed from w1c to rc. - MASTER0 -0 -1 - - - bit type is changed from w1c to rc. - MASTER4 -0 -1 - - - bit type is changed from w1c to rc. - MASTER4 -0 -1 - - - bit type is changed from w1c to rc. - MASTER3 -0 -1 - - - bit type is changed from w1c to rc. - MASTER3 -0 -1 - - - bit type is changed from w1c to rc. - MASTER2 -0 -1 - - - bit type is changed from w1c to rc. - MASTER2 -0 -1 - - - bit type is changed from w1c to rc. - MASTER1 -0 -1 - - - bit type is changed from w1c to rc. - MASTER1 -0 -1 - - - bit type is changed from w1c to rc. - MASTER0 -0 -1 - - - bit type is changed from w1c to rc. - MASTER0 -0 -1 - - - bit type is changed from w1c to rc. -0 -1 - - - bit type is changed from w1c to rc. - MASTER4 -0 -1 - - - bit type is changed from w1c to rc. - MASTER3 -0 -1 - - - bit type is changed from w1c to rc. - MASTER2 -0 -1 - - - bit type is changed from w1c to rc. - MASTER1 -0 -1 - - - bit type is changed from w1c to rc. - MASTER0 -0 -1 - - - - - - - - - - - - - - - ID -: MON_START_ADDR, MON_END_ADDRMASTER0;MASTER0,ADDR_INT, - - - - - - - - - - - 0 --10xFF0x100 - - - - - 0 --10xFF0x100 - - - - - 0 - - - - - 0 --10xFF0x100 - - - - - 1 --10xFF0x100 - - - - - 1 --10xFF0x100 - - - - - 1 - - - - - 1 --10xFF0x100 - - - - - 2 --10xFF0x100 - - - - - 2 --10xFF0x100 - - - - - 2 - - - - - 2 --10xFF0x100 - - - - - 3 --10xFF0x100 - - - - - 3 --10xFF0x100 - - - - - 3 - - - - - 3 --10xFF0x100 - - - - - 4 --10xFF0x100 - - - - - 4 --10xFF0x100 - - - - - 4 - - - - - 4 --10xFF0x100 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 -1 - - - 0 -1 - - - 0000 -00011/2 -00101/4 -00111/8 -01001/16 -01011/32 -01101/64 -01111/128 -10001/256 - - - 0 -00 -10 - - - 0 -1Load - - - 0Load -1Load0 - - - 0 -1 -1STARTTR0 -20xCCCCSTARTPROT_EN -3STARTARSTART - - - - - 0xCCCCWD_CONFWD_LOAD12 -WD_CONF[9]1 - - - - - 32bit -1 - - - - - 32bit -1 - - - - - 32bit - - - - - 32bit - - - - - 0xAAAA0x5555 -0xAAAA0x4444 -0xBBBB - - - - - 0 -1 - - - f= FuncClk/(DIV+1) -WATCHDOG26MhzDIVWD_DIV_COUNT - - - - - bit type is changed from w1c to rc. - - - - - - - - - ACK - - - - - RIMCS - - - - - CQIMCS - - - - - PUSCHPUSCHCRCbit - - - - - PUSCHPUSCHCRCbit - - - - - 00BPSK -01QPSK -1016QAM -1164QAM - - - - - - - - - - PUSCH - - - PUSCH - - - - - RU - - - PUSCHCAT1/CATM -1PUSCH DATA -CAT-NB1RU - - - PUSCHCAT1/CATM1 -PUSCH DATACAT-NB -1RU - - - - - CQI31~0 - - - - - CQI31~0 - - - - - CQI - - - CQI65 - - - CQI64 - - - - - RI - - - RI - - - - - ACK4 - - - ACK - - - - - 0FDDTDDHARQ-ACK -1TDDHARQ-ACK - - - TDD HARQ-ACK - - - - - PUCCH -000~010RESERVED -0112 -1002a -1012b -110~111RESERVED - - - - - U - - - U - - - - - CV - - - - - GOLD - - - - - 1PUSCHULDFT -0PUSCHULDFT - - - 00PUSCH -01PUCCH UCI -10PRACH -11NPUSCH1NPUSCH2PUSCH IP - - - FUNC_SELPUSCH UCIPUCCH UCIFUNC_SEL00PUSCH UCIFUNC_SEL01PUCCH UCI -0UCI -1UCI - - - PUSCH_BUFFERMEM -00PUSCH_BUF1 -01PUSCH_BUF2 -10PUSCH_BUF3 -11PRACH_BUF - - - 0PUSCH_BUFFER -1PUSCH_BUFFER - - - PRACHZC -0ZC139 -1ZC839 - - - 0PUSCHCRCByte -1PUSCHCRCByte - - - 0LTE -1LTE - - - 0PUSCH -1PUSCH - - - 0PUSCH -1PUSCH - - - 0PUSCHTurbo -1PUSCHTurbo - - - 0PUSCHCRC -1PUSCHCRC - - - 0LTE -1LTE - - - - - bit type is changed from rw1c to rc. -0 -1 - - - - - PUCCH format2/2a/2b UCI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Schedule SIB1 BR R13PBML - - - PHICH resourcePBML - - - PHICH durationPBML - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - Ng -01/6 -11/2 -21 -32 - - - 1~:9tm1,tm2,,tm9 - - - TDD0~9 -9 - - - 0~66 - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - 01 -12 -24 -32 - - - CP -0CP -1CP - - - FDDTDD -0TDD -1FDD - - - - - ID0~503 - - - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - Ng -01/6 -11/2 -21 -32 - - - 1~:9tm1,tm2,,tm9 - - - TDD0~99 - - - 0~66 - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - 01 -12 -24 -32 - - - CP -0CP -1CP - - - FDDTDD -0TDD -1FDD - - - - - MBSFN ID0~255 -ID0~503 - - - - - Temp-C-RNTI - - - RA_RNTI - - - - - SPS_RNTI - - - C_RNTI - - - - - TPC-PUCSH-RNTI - - - TPC-PUCCH-RNTI - - - - - G_RNTI - - - - - 2PRBCSI-RS -CSIRS_GROUP1 - - - 1PRBCSI-RS -011PRBRE#0 -RE#1101RE#0 -CSI-RS - - - - - CSI-RSOFDM1PDSCHNorm-CP2430OFDM#5689101213Ext-CP2429OFDM#45781011Norm-CP241OFDM#510OFDM#51CSI-RS - - - 4PRBCSI-RSCSIRS_GROUP1 - - - 3PRBCSI-RSCSIRS_GROUP1 - - - - - PMI (codebookSubsetRestriction) -0PMIbit -1PMIbit - - - - - BIT -Bit0:1OFDMCFI -Bit1:2OFDMCFI -Bit2:3OFDMCFI -Bit3:4OFDMCFI -0 -1 - - - - - HIOFDM0~3 - - - PHICH1 -0 -1 - - - PHICH10~7 - - - PHICH10~99 - - - PHICH0 -0 -1 - - - PHICH00~7 - - - PHICH00~99 - - - - - UEDCImax57 - - - UEDCImax57 - - - COMMDCImax57 - - - COMMDCImax57 - - - DCILEN -0 -1 - - - PUSCH -0DCI0 -1DCI0C - - - CSI -01 -12 - - - 0 -1 - - - SRS -0DCISRS_REQ -1DCISRS_REQ - - - PDCCH -0:1 -1:2 -2:3 -3:4 -78 - - - - - PMIDCIPMI -0DCIPMI -1PMI - - - HARQ:0~15 - - - tx2:0~3tx4:0~15 - - - 0 -1 -2 -3PORT7 -4PORT8 -5PORT5 - - - 0 -1 - - - Nscid(UE)0~1 - - - 0~3 - - - 0:QPSK -1:16QAM -2:64QAM - - - max10296 - - - - - 0 -1 - - - 0~3 - - - max2216 - - - - - 0 -1 - - - 0~3 - - - max2216 - - - - - 0~65535 - - - :0~1023 - - - :0~9 - - - - - 0~65535 - - - :0~1023 - - - :0~9 - - - - - SC-N-RNTI -0 -1 - - - SC-RNTI -0 -1 - - - G-RNTI -0 -1 - - - TPC-PUCCH-RNTI -0 -1 - - - TPC-PUSCH-RNTI -0 -1 - - - Temp-C-RNTI -0 -1 - - - SPS-C-RNTI -0 -1 - - - C-RNTI -0 -1 - - - RA-RNTI -0 -1 - - - P-RNTI -0 -1 - - - SI-RNTI -0 -1 - - - - - SC-RNTI -0 -1 - - - G-RNTI -0 -1 - - - Temp-C-RNTI -0 -1 - - - SPS-C-RNTI -0 -1 - - - C-RNTI -0 -1 - - - RA-RNTI -0 -1 - - - P-RNTI -0 -1 - - - SI-RNTI -0 -1 - - - - - SINR DMA -0 -1 - - - PMI DMA -0 -1 - - - SINR -0 -1 - - - PMI -0 -1 - - - PDCCH -0 -1 - - - PBCH -0 -1 - - - MBMS -0MBMS -1MBMS - - - CTRL QFQT -01 -12 -23 - - - PBCH -0 -1 - - - SINR -0 -1 - - - PMI -0 -1 - - - HI -0 -1 - - - PDCCH -0 -1 - - - PBCH -0 -1 - - - - - PDSCH DMA -0 -1 - - - PDSCH -0 -1 - - - DATA QFQT -01 -12 -23 - - - CSIRS -0 -1 - - - SIHQBUF -0HQBUF0 -1HQBUF1 - - - PDSCH -0 -1 - - - PDS -0 -1 - - - PDSCH -0 -1 - - - - - LDTC -0 -1 - - - - - LDTC -0 -1 - - - - - bit type is changed from rw1c to rc. - DCI -0DCI -1DCI - - - bit type is changed from rw1c to rc. - MIB -0MIB -1MIB - - - bit type is changed from rw1c to rc. - SINR -0 -1 - - - bit type is changed from rw1c to rc. - PMI -0 -1 - - - bit type is changed from rw1c to rc. - PDCCH -0 -1 - - - bit type is changed from rw1c to rc. - PBCH -0 -1 - - - - - bit type is changed from rw1c to rc. - PAGINGCRC -0 -1 - - - bit type is changed from rw1c to rc. - PAGINGCRC -0CRC -1CRC - - - bit type is changed from rw1c to rc. - SICRC -0 -1 - - - bit type is changed from rw1c to rc. - SICRC -0CRC -1CRC - - - bit type is changed from rw1c to rc. - PDSCH CRC -0 -1 - - - bit type is changed from rw1c to rc. - PDSCH CRC -0CRC -1CRC - - - bit type is changed from rw1c to rc. - PDSCH -0 -1 - - - - - FHdata -0FH0 -1FH1 - - - FHctrl -0FH0 -1FH1 - - - DSCHOUT -0DSCHOUT0 -1DSCHOUT1 - - - FFTBUF -0FFTBUF0 -1FFTBUF1 - - - - - PDCCH - - - GQ -0Q15 -1Q16 -7Q22 - - - HQ -0CC -1IR - - - HQ BUF -04bit -16bit - - - SDGnoise -0noise -1GM - - - PMI/PWR -0 -1 - - - CTCG -0OFDM4(OFDM4)CRS -1OFDM8(OFDM8)CRS - - - CRS G -01PRB -12PRB - - - CRS36 PRB -03PRB -16PRB - - - UE RSPRB1,3 -0 -1 - - - - - 16bit10bit -0 -1 - - - 16bit10bit -0x015~6 -0x114~5 -0x213~4 -0x312~3 -0x411~2 -0x510~1 -0x69~0 -reserved - - - 16bit -0x028~13 -0x127~12 -0x226~11 -0x325~10 -0x424~9 -0x523~8 -0x622~7 -0x721~6 -0x820~5 -0x919~4 -0xa18~3 -0xb17~2 -0xc16~1 -0xd15~0 -Reserved - - - - - 0x025~10 -0x124~9 -0x223~8 -0x322~7 -0x421~6 -0x520~5 -0x619~4 -0x718~3 -0x817~2 -0x916~1 -0xa15~0 - - - - - 0.5msbitmapbitprbbit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[99:96]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[31:0]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[99:96]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[31:0]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[64:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprbbit -0prb -1prb - - - - - 0.5msbitmapbit[31:0]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[99:96]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[31:0]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[99:96]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[31:0]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[95:64]prbbit -0prb -1prb - - - - - 0.5msbitmapbit[99:96]prbbit -0prb -1prb - - - - - 8 - - - 7 - - - 6 - - - 5 - - - 4 - - - 3 - - - 2 - - - 1 - - - - - 16 - - - 15 - - - 14 - - - 13 - - - 12 - - - 11 - - - 10 - - - 9 - - - - - 24 - - - 23 - - - 22 - - - 21 - - - 20 - - - 19 - - - 18 - - - 17 - - - - - 25 - - - - - 1CRS - - - - - 1CRS - - - - - 1CRSAGC - - - - - 1CRSAGC - - - - - PDCCH -0 -1 - - - PBCH -0 -1 - - - 1 - - - 0 - - - - - PDSCH -0 -1 - - - 0 - - - - - 2 - - - 1 - - - - - 4 - - - 3 - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - 32Q300~7fff_ffff - - - - - AGC - - - - - PDCCHPBCH - - - - - 32Q300~7fff_ffff - - - - - AGC - - - - - - - - - - - - - PDCCHINDX - - - PBCHINDX3 - - - PBCHINDX2 - - - PBCHINDX1 - - - PBCHINDX0 - - - - - INDX7 - - - INDX6 - - - INDX5 - - - INDX4 - - - INDX3 - - - INDX2 - - - INDX1 - - - INDX0 - - - - - INDX15 - - - INDX14 - - - INDX13 - - - INDX12 - - - INDX11 - - - INDX10 - - - INDX9 - - - INDX8 - - - - - INDX23 - - - INDX22 - - - INDX21 - - - INDX20 - - - INDX19 - - - INDX18 - - - INDX17 - - - INDX16 - - - - - INDX31 - - - INDX30 - - - INDX29 - - - INDX28 - - - INDX27 - - - INDX26 - - - INDX25 - - - INDX24 - - - - - INDX34 - - - INDX33 - - - INDX32 - - - - - bit type is changed from rw1c to rc. - 15HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 14HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 13HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 12HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 11HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 10HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 9HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 8HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 7HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 6HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 5HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 4HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 3HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 2HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 1HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 0HARQBUFFER -0: -1: - - - - - 7HARQBUFFER:0~15 - - - 6HARQBUFFER:0~15 - - - 5HARQBUFFER:0~15 - - - 4HARQBUFFER:0~15 - - - 3HARQBUFFER:0~15 - - - 2HARQBUFFER:0~15 - - - 1HARQBUFFER:0~15 - - - 0HARQBUFFER:0~15 - - - - - 15HARQBUFFER:0~15 - - - 14HARQBUFFER:0~15 - - - 13HARQBUFFER:0~15 - - - 12HARQBUFFER:0~15 - - - 11HARQBUFFER:0~15 - - - 10HARQBUFFER:0~15 - - - 9HARQBUFFER:0~15 - - - 8HARQBUFFER:0~15 - - - - - 64QAM -02 -1 - - - 16QAM -02 -1 - - - QPSK -02 -1 - - - 64QAM -0 -1 - - - 16QAM -0 -1 - - - QPSK -0 -1 - - - 2 - - - 1 - - - 1 -90~8 - - - - - PAG-1 - - - SI-1 - - - PDS-1 - - - PDS-1 - - - - - 0 -1 - - - CRC -0CRC16 -1CRC24A - - - DMA -0 -1 - - - 0 -1 - - - VIT -0:1 -1:2 -2:3 -3:4 - - - - - - - - PDCCHfalse alarm - - - PDCCHfalse alarm(U8Q7) - - - - - VIT - - - - - VIT -0 -1 - - - - - bit type is changed from rw1c to rc. - VIT CRCCRC -0 -1 - - - bit type is changed from rw1c to rc. - VIT CRC -0 -1 - - - bit type is changed from rw1c to rc. - PBCH -0 -1 - - - - - DCI false alarm0 - - - DCI false alarm - - - - - CFI -1~41.4M1 - - - - - HI1 - - - HI0 - - - - - - - - - - - - - - - - - - - - - - - - - PDSCH 15 - - - PDSCH 14 - - - PDSCH 13 - - - PDSCH 12 - - - PDSCH 11 - - - PDSCH 10 - - - PDSCH 9 - - - PDSCH 8 - - - PDSCH 7 - - - PDSCH 6 - - - PDSCH 5 - - - PDSCH 4 - - - PDSCH 3 - - - PDSCH 2 - - - PDSCH 1 - - - PDSCH 0 - - - - - SI1 - - - SI0 - - - - - PBCH - - - - - - - - - - 2 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 1 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - MultiCell -0SingalCell -1MultiCell - - - ABIS -0 -1DLFFT - - - ABIS -0 -1 - - - ABISSD PDSCH -0 -1 - - - ABISSD MPDCCH -0 -1 - - - ABISSD PBCH -0 -1 - - - - - 000 -011 -102 -0 - - - 2 -001port -012port -104port -1port - - - 1 -001port -012port -104port -1port - - - 2 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 1 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 2 CELL ID - - - 1 CELL ID - - - - - 1TS - - - - - 2TS - - - - - ABIS31+2 - - - ABIS22 - - - ABIS11 - - - - - 2 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 1 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - ABIS -0 -1DLFFT - - - ABIS -0 -1 - - - ABISSD PDSCH -0 -1 - - - ABISSD MPDCCH -0 -1 - - - ABISSD PBCH -0 -1 - - - - - 000 -011 -102 -0 - - - 2 -001port -012port -104port -1port - - - 2 -001port -012port -104port -1port - - - 2 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 1 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 2 CELL ID - - - 1 CELL ID - - - - - 1TS - - - - - 2TS - - - - - ABIS31+2 - - - ABIS22 - - - ABIS11 - - - - - REIS -0 -1 - - - REISNUM - - - - - REIS1 - - - REIS1RE20M1200RE - - - REIS0 - - - REIS0RE20M1200RE - - - - - REIS3 - - - REIS3RE20M1200RE - - - REIS2 - - - REIS2RE20M1200RE - - - - - REIS5 - - - REIS5RE20M1200RE - - - REIS4 - - - REIS4RE20M1200RE - - - - - REIS7 - - - REIS7RE20M1200RE - - - REIS6 - - - REIS6RE20M1200RE - - - - - 2ABISPORT -0port0 -1port1 - - - RBIS -0 -1 - - - RBISSD PDSCH -0 -1 - - - RBISSD MPDCCH -0 -1 - - - RBISSD PBCH -0 -1 - - - RBIS -0 -1 - - - RBIS -01 -12 -23 -34 -45 - - - RBIS - - - RBIS - - - - - RBIS0~99 - - - RBIS0~99 - - - RBIS0~99 - - - RBIS0~99 - - - - - RBIS0~99 - - - - - RBIS - - - - - RBIS - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DCI032 - - - - - DCI032 - - - - - DCI - - - - - DCI false alarm0 - - - DCI false alarm - - - - - 00 -11 - - - DCI1A -0ORDER -1ORDER - - - SPS-C-RNTI -0 -1 -2 -3 - - - DCI -0:DCI0 -1:DCI1 -2:DCI1A -3:DCI1B -4:DCI1C -5:DCI1D -6:DCI2 -7:DCI2A -8:DCI2B -9:DCI2C -10:DCI3/3A - - - DCI RNTI -0RNTI0SI-RNTI -1RNTI1P-RNTI -2RNTI2RA-RNTI -3RNTI3C-RNTI -4RNTI4SPS-RNTI -5RNTI5T-RNTI -6RNTI6TPCS-RNTI -7RNTI7TPCC-RNTI -8RNTI8G-RNTI -9RNTI9SC-RNTI -10RNTI10SC-N-RNTI - - - DCICOMMUE -0 -1UE - - - DCI(index:0~23) - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - PMIDCIPMI -0DCIPMI -1PMI - - - HARQ:0~15 - - - tx2:0~3tx4:0~15 - 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- - - - - - - - 0TYPE0 -1TYPE1 - - - Type0 - - - Type0/Type1RBA - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - DCI532 - - - - - DCI532 - - - - - DCI - - - - - DCI false alarm0 - - - DCI false alarm - - - - - 00 -11 - - - DCI5A -0ORDER -1ORDER - - - SPS-C-RNTI -0 -1 -2 -3 - - - DCI -0:DCI5 -1:DCI5 -2:DCI5A -3:DCI5B -4:DCI5C -5:DCI5D -6:DCI5 -7:DCI5A -8:DCI5B -9:DCI5C -10:DCI5/3A - - - DCI RNTI -0RNTI0SI-RNTI -1RNTI1P-RNTI -2RNTI2RA-RNTI -3RNTI3C-RNTI -4RNTI4SPS-RNTI -5RNTI5T-RNTI -6RNTI6TPCS-RNTI -7RNTI7TPCC-RNTI -8RNTI8G-RNTI -9RNTI9SC-RNTI -10RNTI10SC-N-RNTI - - - DCICOMMUE -0 -1UE - - - DCI(index:0~23) - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - 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- - SPS-C-RNTI -0 -1 -2 -3 - - - DCI -0:DCI6 -1:DCI6 -2:DCI6A -3:DCI6B -4:DCI6C -5:DCI6D -6:DCI6 -7:DCI6A -8:DCI6B -9:DCI6C -10:DCI6/3A - - - DCI RNTI -0RNTI0SI-RNTI -1RNTI1P-RNTI -2RNTI2RA-RNTI -3RNTI3C-RNTI -4RNTI4SPS-RNTI -5RNTI5T-RNTI -6RNTI6TPCS-RNTI -7RNTI7TPCC-RNTI -8RNTI8G-RNTI -9RNTI9SC-RNTI -10RNTI10SC-N-RNTI - - - DCICOMMUE -0 -1UE - - - DCI(index:0~23) - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - PMIDCIPMI -0DCIPMI -1PMI - - - HARQ:0~15 - - - tx2:0~3tx4:0~15 - - - 0 -1 -2 -3PORT7 -4PORT8 -5PORT5 - - - 0 -1 - - - Nscid(UE)0~1 - - - 0~3 - - - 0:QPSK -1:16QAM -2:64QAM - - - max10296 - - - - - DCI6C - - - - - - DCI6/DCI6A/DCI6B/DCI6C2 -01 -12 - - - DCI6 - - - DCI6CQI - - - DCI6/DCI6ATBCW -0 -1 - - - SRS -SRQDCI6DCI6ADCI6B TDDDCI6C TDD - - - - - - DCI6D POWER OFFSET - - - DAI - - - - - - - - - - - 0TYPE0 -1TYPE1 - - - Type0 - - - Type0/Type1RBA - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - DCI732 - - - - - DCI732 - - - - - DCI - - - - - DCI false alarm0 - - - DCI false alarm - - - - - 00 -11 - - - DCI7A -0ORDER -1ORDER - - - SPS-C-RNTI -0 -1 -2 -3 - - - DCI -0:DCI7 -1:DCI7 -2:DCI7A -3:DCI7B -4:DCI7C -5:DCI7D -6:DCI7 -7:DCI7A -8:DCI7B -9:DCI7C -10:DCI7/3A - - - DCI RNTI -0RNTI0SI-RNTI -1RNTI1P-RNTI -2RNTI2RA-RNTI -3RNTI3C-RNTI -4RNTI4SPS-RNTI -5RNTI5T-RNTI -6RNTI6TPCS-RNTI -7RNTI7TPCC-RNTI -8RNTI8G-RNTI -9RNTI9SC-RNTI -10RNTI10SC-N-RNTI - - - DCICOMMUE -0 -1UE - - - DCI(index:0~23) - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - PMIDCIPMI -0DCIPMI -1PMI - - - HARQ:0~15 - - - tx2:0~3tx4:0~15 - - - 0 -1 -2 -3PORT7 -4PORT8 -5PORT5 - - - 0 -1 - - - Nscid(UE)0~1 - - - 0~3 - - - 0:QPSK -1:16QAM -2:64QAM - - - max10296 - - - - - DCI7C - - - - - - DCI7/DCI7A/DCI7B/DCI7C2 -01 -12 - - - DCI7 - - - DCI7CQI - - - DCI7/DCI7ATBCW -0 -1 - - - SRS -SRQDCI7DCI7ADCI7B TDDDCI7C TDD - - - - - - DCI7D POWER OFFSET - - - DAI - - - - - - - - - - - 0TYPE0 -1TYPE1 - - - Type0 - - - Type0/Type1RBA - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - 0.5msbitmapbit[63:32]prbbit -0prb -1prb - - - - - 0.5msbitmapbitprb[63:32]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[95:64]bit -0prb -1prb - - - - - 0.5msbitmapbitprb[99:96]bit -0prb -1prb - - - - - - - - - - - - - - - - - - - - - - - - - MIB0 - - - - - MIB - - - - - MIB1 - - - - - MIB - - - - - MIB2 - - - - - MIB - - - - - MIB3 - - - - - MIB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Schedule SIB1 BR R13PBML - - - PHICH resourcePBML - - - PHICH durationPBML - - - PBCH -0PBCH -1PBCH - - - CATM1,2,6,9 - - - TDD -099 - - - 066 - - - 0: 1.4MHZ -1: 3MHZ -2: 5MHZ -310MHZ -4: 15MHZ -5: 20MHZ -6~75 - - - 0 1 -1 2 -2 4 -3 2 - - - CP -0 CP -1 CP - - - FDDTDD -0 TDD -1 FDD - - - - - ID0503 - - - - - G_RNTI - - - - - Temp-C-RNTI - - - RA-RNTI - - - - - SPS-C-RNTI - - - C-RNTI - - - - - TPC-PUCSH-RNTI - - - TPC-PUCCH-RNTI - - - - - MPDCCH1PRB -0 2 -1 4 -2 6 - - - MPDCCH1RBA - - - MPDCCH1ID -0503 - - - MPDCCH1 -0(LOC) -1(DIS) - - - - - 2PRBCSI-RSCSIRS_GROUP1 - - - 1PRBCSI-RS011PRBRE#0RE#1101RE#0CSI-RS - - - - - 4PRBCSI-RSCSIRS_GROUP1 - - - 3PRBCSI-RSCSIRS_GROUP1 - - - - - PMIcsi-NumrepetitionCE-R13: -0: 1 -1: 2 -2: 4 -3: 8 -4: 16 -5: 32 - - - PMI -0 PMIbit -1 PMIbit - - - - - PBCH -0 -1 - - - PBCH -0FDD90TDD05 -10PBCH - - - PBCH -0 1 -1 2 - - - PBCH2TDD03 -0 -1 -2 -3 - - - PBCH1(TDD,FDD)03 -0 -1 -2 -3 - - - PBCH(TDD/FDD)03 -0 -1 -2 -3 - - - - - MPDCCHFHBUNDbit3PRB3PRB -Bit2013PRBBUND03PRBBUND -Bit2113PRBBUND03PRBBUND - - - 0 -1 - - - UL TBSIZE -0max1000 -1max2984 - - - PDSCH_PUSCH -0 -1 - - - FDD HARQ -08 -110 - - - HARQ ACK -0 -1 - - - 0harq -1harq - - - MPDCCH DCI -0 -1 - - - MPDCCH SRSRREQ -0SRSRREQ -1SRSRREQ - - - MPDCCH COMM -0:1 -1:2 -2:3 -3:4 - - - MPDCCH SET -0:1 -1:2 -2:3 -3:4 - - - MPDCCH COMM(1256) -0:1 -1:2 -2:4 -3:8 -4:16 -8:256 - - - MPDCCH SET1(1~256) -0:1 -1:2 -2:4 -3:8 -4:16 -8:256 - - - - - MPDCCH COMM DCImax38 - - - MPDCCH SET1 COMM DCImax38 - - - MPDCCH SET1 UESPEC DCImax38 - - - - - MPDCCH SET10255 - - - - - tx2:03 -tx4:015 - - - 0 -1 -2 -3PORT7 -4PORT8 - - - HARQ015 - - - NscidUE01 - - - 03 - - - 0:QPSK -1:16QAM - - - max1000 - - - RB16 - - - RB05 - - - - - AGC - - - - - 065535 - - - 01023 - - - 09 - - - - - C-RNTI -0 -1 - - - SI-RNTISIB1SIB -0SIB1SIB -1SIB1 - - - PDSCHC-RNTSPS-C-RNTI -0C-RNTI -1SPS-RNTI - - - SI-RNTI -0 -1 - - - G-RNTI -0 -1 - - - SC-RNTI -0 -1 - - - Temp-C-RNTI -0 -1 - - - RA-RNTI -0 -1 - - - P-RNTI -0 -1 - - - TPC-PUSCH-RNTI -0 -1 - - - TPC-PUCCH-RNTI -0 -1 - - - SPS-C-RNTI -0 -1 - - - C-RNTI -0 -1 - - - - - PDSCH/PBCH -0 -1PDSCH /PBCH - - - MPDCCH -0 -1MPDCCH - - - PDSCH/PBCHPMI -0 -1 - - - MPDCCH(PMI) -0 -1 - - - CFI -0:1 -1:2 -2:3 -3:4 - - - MPDCCH/PDSCHSIB -0 -1 - - - PDSCH0 -000 -100 - - - CSI RS -0 -1 - - - 0 -1PDSCH/MPDCCH/PBCH - - - 0 -1 - - - QFQT -0Qtable0 -1Qtable1 -2Qtable2 - - - 0CEA -1CEB - - - :015 - - - MPDCCH SET1 -0 -1 - - - PDSCH URS -0 -1 - - - PDSCH CRS/PMI -0 -1 - - - 0 -1 - - - MPDCCH SET1 -0 -1 - - - PMI -0 -1 - - - PDSCH -0 -1 - - - MPDCCH SET1 -0 -1 - - - PBCH -0 -1 - - - PMI -0 -1 - - - PDSCH -0 -1 - - - MPDCCH -0 -1 - - - PBCH -0 -1 - - - - - LDTC -0 -1 - - - - - bit type is changed from rw1c to rc. -0LDTC -1LDTC - - - bit type is changed from rw1c to rc. - PMI -0PMI -1PMI - - - bit type is changed from rw1c to rc. - PDSCH -0PDSCH -1PDSCH - - - bit type is changed from rw1c to rc. - MPDCCH -0MPDCCH -1PBCH - - - bit type is changed from rw1c to rc. - PBCH -0PBCH -1PBCH - - - bit type is changed from rw1c to rc. -0 -1 - - - - - COEFF - - - DATMEM - - - RSMEM0~4 - - - DCI -0 -1 - - - DCI Ri -0DCI -1DCIRi - - - DCI2 -0DCI -1DCI2 - - - DCI -0DCI -1DCI - - - MIB -0MIB -1MIB - - - PDSCH CRC -0 -1 - - - PDSCH CRC -0CRC -1CRC - - - - - 065535 - - - 01023 - - - 09 - - - - - MPDCCH CNT - - - HARQ:0~15 - - - RNTI -0RNTI0C-RNTI -1RNTI1SPS-C-RNTI -2RNTI2TPC-PDCCH-RNTI -3RNTI3TPC-PDSCH-RNTI -4RNTI4P-RNTI -5RNTI5RA-RNTI -6RNTI6Temp-C-RNTI -7RNTI7SC-RNTI -8RNTI7G-RNTI -9RNTI7SI-RNTI - - - C-RNTI -0 -1 - - - SI-RNTISIB1SIB -0SIB1SIB -1SIB1 - - - MIB -0 -12 -24 - - - MPDCCH SET10255 - - - - - PDSCH UE -0 -1 - - - MPDCCH -0MPDCCHextendCPMPDCCH -1MPDCCHnormalCP - - - FIR/IIR -0FIR -1IIR - - - FIR -0:1 -1:2 -2:3 -3:4 - - - - - IIRHLS - - - FIRHLS - - - - - FIR1HLS - - - IIR/FIR0HLS - - - - - FIR2HLS - - - FIR1HLS - - - FIR0HLS - - - - - FIR3HLS - - - FIR2HLS - - - FIR1HLS - - - FIR0HLS - - - - - UE RSPRB1,3 -0:1 -1:3 - - - 16bit10bit -0 -1 - - - 16bit10bit -0x015~6 -0x114~5 -0x213~4 -0x312~3 -0x411~2 -0x510~1 -0x69~0 -RESERVED - - - 16bit -0x028~13 -0x127~12 -0x226~11 -0x325~10 -0x424~9 -0x523~8 -0x622~7 -0x721~6 -0x820~5 -0x919~4 -0xa18~3 -0xb17~2 -0xc16~1 -0xd15~0 -RESERVED - - - - - 0x02510 -0x1249 -0x2238 -0x3227 -0x4216 -0x5205 -0x6194 -0x7183 -0x8172 -0x9161 -0xa150 - - - - - PBCH -0 -1 - - - 2 - - - 1 - - - 0 - - - - - MPDCCH -0 -1 - - - 2 - - - 1 - - - 0 - - - - - PDSCH -0 -1 - - - 0 - - - - - 2 - - - 1 - - - - - 4 - - - 3 - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - OFDMCELL RSdata - - - OFDMCELL RSdata - - - - - 32Q3007fff_ffff - - - - - AGC - - - - - PDSCH(16~31bit) - - - MPDCCH/PBCH(16~31bit) - - - - - INDX3 - - - INDX2 - - - INDX1 - - - INDX0 - - - - - INDX11 - - - INDX10 - - - INDX9 - - - INDX8 - - - INDX7 - - - INDX6 - - - INDX5 - - - INDX4 - - - - - INDX19 - - - INDX18 - - - INDX17 - - - INDX16 - - - INDX15 - - - INDX14 - - - INDX13 - - - INDX12 - - - - - INDX9 - - - INDX8 - - - INDX7 - - - INDX6 - - - INDX5 - - - INDX4 - - - INDX3 - - - INDX2 - - - INDX1 - - - INDX0 - - - - - INDX19 - - - INDX18 - - - INDX17 - - - INDX16 - - - INDX15 - - - INDX14 - - - INDX13 - - - INDX12 - - - INDX11 - - - INDX10 - - - - - INDX32 - - - INDX31 - - - INDX30 - - - INDX29 - - - INDX28 - - - INDX27 - - - INDX26 - - - INDX25 - - - INDX24 - - - INDX23 - - - INDX22 - - - INDX21 - - - INDX20 - - - - - INDX7 - - - INDX6 - - - INDX5 - - - INDX4 - - - INDX3 - - - INDX2 - - - INDX1 - - - INDX0 - - - - - INDX15 - - - INDX14 - - - INDX13 - - - INDX12 - - - INDX11 - - - INDX10 - - - INDX9 - - - INDX8 - - - - - INDX16 - - - - - HARQ1280255 - - - HARQ320255 - - - - - HARQ6408191 - - - HARQ1608191 - - - - - MPDCCH m ECCEYpk4 - - - MPDCCH m ECCEYpk3 - - - MPDCCH m ECCEYpk2 - - - MPDCCH m ECCEYpk1 - - - MPDCCH m ECCEYpk0 - - - - - MPDCCH m ECCEYpk9 - - - MPDCCH m ECCEYpk8 - - - MPDCCH m ECCEYpk7 - - - MPDCCH m ECCEYpk6 - - - MPDCCH m ECCEYpk5 - - - - - bit type is changed from rw1c to rc. - 7HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 6HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 5HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 4HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 3HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 2HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 1HARQBUFFER -0: -1: - - - bit type is changed from rw1c to rc. - 0HARQBUFFER -0: -1: - - - - - 7HARQBUFFER:0~15 - - - 6HARQBUFFER:0~15 - - - 5HARQBUFFER:0~15 - - - 4HARQBUFFER:0~15 - - - 3HARQBUFFER:0~15 - - - 2HARQBUFFER:0~15 - - - 1HARQBUFFER:0~15 - - - 0HARQBUFFER:0~15 - - - - - max1000 - - - PDSCH - - - - - PDSCH - - - PDSCHmax4*2048-1 - - - - - - - - N -01 -11.5 -22 -3 2.5 - - - 2 - - - 1 - - - 1 -908 - - - - - -1 - - - - - VIT -0:1 -1:2 -2:3 -3:4 - - - - - DCI032 - - - - - DCI032 - - - - - 0 -1 -2 -3PORT7 -4PORT8 - - - 00 -11 - - - PRB2+4DCIPRB -0:2PRB -1:4PRB -2:6PRB - - - DCI -01 -12 - - - DCICOMMUE -0 -1UE - - - DCIRi -0R0 -1R1 -2R2 -3R3 - - - DCIPORTn0 -Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 -0PORT107 -1PORT108 -2PORT109 -3PORT110 -Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 -0:107 -1:109 -Extended cyclic prefix -0:107 -1:108 - - - DCI(index:023) - - - DCI RNTI -0RNTI0C-RNTI -1RNTI1SPS-C-RNTI -2RNTI2TPC-PDCCH-RNTI -3RNTI3TPC-PDSCH-RNTI -4RNTI4P-RNTI -5RNTI5RA-RNTI -6RNTI6Temp-C-RNTI -7RNTI7SC-RNTI -8RNTI8G-RNTI - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - tx2:03tx4:015 - - - HARQ:015 - - - Nscid(UE)01 - - - 03 - - - 0:QPSK -1:16QAM - - - max2984 - - - RB16 - - - RB05 - - - - - HARQ-ACK delay - - - HARQ-ACK bundling flag - - - SPS-C-RNTI -0 -1 -2 - - - DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification - - - DCI6-0A /DCI6-1ASRS - - - DCI6-0ACSI - - - DCI6-1A/DCI6-0A(TDD,uldl:16)DAI -DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX - - - DCI6-0A /DCI6-1A - - - - - - PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) - - - MPDCCH DCI (03),Transport blocks in a bundle - - - DCI2DI(direct indication) -0PAGING -1DI -DCI6-1ADCI1-BPDCCH ORDER -0ORDER -1ORDER - - - 0DCI -1 - - - 0 -1 - - - DCI -0:DCI6-1A -1:DCI6-1B -2:DCI6-0A -3:DCI6-0B -4:DCI3/3A -5:DCI2 - - - 015 - - - - - DCI6-1APDSCH1tbsize - - - - - DCIfalse alarm(vit) - - - DCIfalse alarm0 - - - DCI - - - - - DCI132 - - - - - DCI132 - - - - - 0 -1 -2 -3PORT7 -4PORT8 - - - 00 -11 - - - PRB2+4DCIPRB -0:2PRB -1:4PRB -2:6PRB - - - DCI -01 -12 - - - DCICOMMUE -0 -1UE - - - DCIRi -0R0 -1R1 -2R2 -3R3 - - - DCIPORTn0 -Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 -0PORT107 -1PORT108 -2PORT109 -3PORT110 -Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 -0:107 -1:109 -Extended cyclic prefix -0:107 -1:108 - - - DCI(index:023) - - - DCI RNTI -0RNTI0C-RNTI -1RNTI1SPS-C-RNTI -2RNTI2TPC-PDCCH-RNTI -3RNTI3TPC-PDSCH-RNTI -4RNTI4P-RNTI -5RNTI5RA-RNTI -6RNTI6Temp-C-RNTI -7RNTI7SC-RNTI -8RNTI8G-RNTI - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - tx2:03tx4:015 - - - HARQ:015 - - - Nscid(UE)01 - - - 03 - - - 0:QPSK -1:16QAM - - - max2984 - - - RB16 - - - RB05 - - - - - HARQ-ACK delay - - - HARQ-ACK bundling flag - - - SPS-C-RNTI -0 -1 -2 - - - DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification - - - DCI6-0A /DCI6-1ASRS - - - DCI6-0ACSI - - - DCI6-1A/DCI6-0A(TDD,uldl:16)DAI -DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX - - - DCI6-0A /DCI6-1A - - - - - - PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) - - - MPDCCH DCI (03),Transport blocks in a bundle - - - DCI2DI(direct indication) -0PAGING -1DI -DCI6-1ADCI1-BPDCCH ORDER -0ORDER -1ORDER - - - 0DCI -1 - - - 0 -1 - - - DCI -0:DCI6-1A -1:DCI6-1B -2:DCI6-0A -3:DCI6-0B -4:DCI3/3A -5:DCI2 - - - 015 - - - - - DCI6-1APDSCH1tbsize - - - - - DCIfalse alarm(vit) - - - DCIfalse alarm0 - - - DCI - - - - - DCI232 - - - - - DCI232 - - - - - 0 -1 -2 -3PORT7 -4PORT8 - - - 00 -11 - - - PRB2+4DCIPRB -0:2PRB -1:4PRB -2:6PRB - - - DCI -01 -12 - - - DCICOMMUE -0 -1UE - - - DCIRi -0R0 -1R1 -2R2 -3R3 - - - DCIPORTn0 -Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 -0PORT107 -1PORT108 -2PORT109 -3PORT110 -Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 -0:107 -1:109 -Extended cyclic prefix -0:107 -1:108 - - - DCI(index:023) - - - DCI RNTI -0RNTI0C-RNTI -1RNTI1SPS-C-RNTI -2RNTI2TPC-PDCCH-RNTI -3RNTI3TPC-PDSCH-RNTI -4RNTI4P-RNTI -5RNTI5RA-RNTI -6RNTI6Temp-C-RNTI -7RNTI7SC-RNTI -8RNTI8G-RNTI - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - tx2:03tx4:015 - - - HARQ:015 - - - Nscid(UE)01 - - - 03 - - - 0:QPSK -1:16QAM - - - max2984 - - - RB16 - - - RB05 - - - - - HARQ-ACK delay - - - HARQ-ACK bundling flag - - - SPS-C-RNTI -0 -1 -2 - - - DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification - - - DCI6-0A /DCI6-1ASRS - - - DCI6-0ACSI - - - DCI6-1A/DCI6-0A(TDD,uldl:16)DAI -DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX - - - DCI6-0A /DCI6-1A - - - - - - PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) - - - MPDCCH DCI (03),Transport blocks in a bundle - - - DCI2DI(direct indication) -0PAGING -1DI -DCI6-1ADCI1-BPDCCH ORDER -0ORDER -1ORDER - - - 0DCI -1 - - - 0 -1 - - - DCI -0:DCI6-1A -1:DCI6-1B -2:DCI6-0A -3:DCI6-0B -4:DCI3/3A -5:DCI2 - - - 015 - - - - - DCI6-1APDSCH1tbsize - - - - - DCIfalse alarm(vit) - - - DCIfalse alarm0 - - - DCI - - - - - DCI332 - - - - - DCI332 - - - - - 0 -1 -2 -3PORT7 -4PORT8 - - - 00 -11 - - - PRB2+4DCIPRB -0:2PRB -1:4PRB -2:6PRB - - - DCI -01 -12 - - - DCICOMMUE -0 -1UE - - - DCIRi -0R0 -1R1 -2R2 -3R3 - - - DCIPORTn0 -Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 -0PORT107 -1PORT108 -2PORT109 -3PORT110 -Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 -0:107 -1:109 -Extended cyclic prefix -0:107 -1:108 - - - DCI(index:023) - - - DCI RNTI -0RNTI0C-RNTI -1RNTI1SPS-C-RNTI -2RNTI2TPC-PDCCH-RNTI -3RNTI3TPC-PDSCH-RNTI -4RNTI4P-RNTI -5RNTI5RA-RNTI -6RNTI6Temp-C-RNTI -7RNTI7SC-RNTI -8RNTI8G-RNTI - - - DCIL -000L=1; -001L=2; -010L=4; -011L=8; -100L=12; -101L=16; -110L=24; - - - DCI (max38) - - - - - tx2:03tx4:015 - - - HARQ:015 - - - Nscid(UE)01 - - - 03 - - - 0:QPSK -1:16QAM - - - max2984 - - - RB16 - - - RB05 - - - - - HARQ-ACK delay - - - HARQ-ACK bundling flag - - - SPS-C-RNTI -0 -1 -2 - - - DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification - - - DCI6-0A /DCI6-1ASRS - - - DCI6-0ACSI - - - DCI6-1A/DCI6-0A(TDD,uldl:16)DAI -DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX - - - DCI6-0A /DCI6-1A - - - - - - PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) - - - MPDCCH DCI (03),Transport blocks in a bundle - - - DCI2DI(direct indication) -0PAGING -1DI -DCI6-1ADCI1-BPDCCH ORDER -0ORDER -1ORDER - - - 0DCI -1 - - - 0 -1 - - - DCI -0:DCI6-1A -1:DCI6-1B -2:DCI6-0A -3:DCI6-0B -4:DCI3/3A -5:DCI2 - - - 015 - - - - - DCI6-1APDSCH1tbsize - - - - - DCIfalse alarm(vit) - - - DCIfalse alarm0 - - - DCI - - - - - MIB - - - - - SIB1schedule0~31 - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - MIB -00 -11 -22 -33 - - - MIB -bit0 -bit11 alllegacyTDD0FDD90 -bit221 onlylegacyTDD0FDD90 -bit32 alllegacyTDD05FDD -bit42 onlylegacyTDD05FDD - - - - - MIB - - - - - SIB1schedule0~31 - - - 01.4Mhz -13Mhz -25Mhz -310Mhz -415Mhz -520Mhz -6~75 - - - MIB -00 -11 -22 -33 - - - MIB -bit0 -bit11 alllegacyTDD0FDD90 -bit221 onlylegacyTDD0FDD90 -bit32 alllegacyTDD05FDD -bit42 onlylegacyTDD05FDD - - - - - - - - - - 5 - - - 4 - - - 3 - - - 2 - - - 1 - - - 0 - - - - - 11 - - - 10 - - - 9 - - - 8 - - - 7 - - - 6 - - - - - 13 - - - 12 - - - - - LDTC CYCLE -LDTCCYCLE - - - - - REIS -0 -1 - - - REIS -0 -1REIS - - - REIS0 - - - REISNUM - - - - - REIS1 - - - REIS1RE20M1200RE - - - REIS0 - - - REIS0 RE20M1200RE - - - - - REIS3 - - - REIS3RE20M1200RE - - - REIS2 - - - REIS2 RE20M1200RE - - - - - REIS3 - - - REIS3RE20M1200RE - - - REIS2 - - - REIS2 RE20M1200RE - - - - - REIS3 - - - REIS3RE20M1200RE - - - REIS2 - - - REIS2 RE20M1200RE - - - - - 2ABISPORT -0port0 -1port1 - - - RBIS -0 -1 - - - RBISSD PDSCH -0 -1 - - - RBISSD MPDCCH -0 -1 - - - RBISSD PBCH -0 -1 - - - RBIS -0 -1 - - - RBIS -01 -12 -23 -34 -45 - - - RBIS - - - RBIS - - - - - RBIS0~5 - - - RBIS0~5 - - - RBIS0~5 - - - RBIS0~5 - - - RBIS0~5 - - - - - RBIS - - - - - RBIS - - - - - 2 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 1 -02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - 02port0port14port0port1port2port3 -12port04port0port2port3 -22port14port1port2port3 - - - MultiCell -0SingalCell -1:MultiCell - - - ABIS SD PDSCH -0 -1 - - - ABIS SD MPDCCH -0 -1 - - - ABIS SD PBCH -0 -1 - - - ABIS -0 -1 - - - - - 000 -011 -102 -0 - - - 2 -001port -012port -104port -1port - - - 1 -001port -012port -104port -1port - - - 2 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 1 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 2 CELL ID - - - 1 CELL ID - - - - - 1TS - - - - - 2TS - - - - - ABIS31+2 - - - ABIS22 - - - ABIS11 - - - - - PBML -0 -1 - - - LLR - - - LLR - - - LLR -0~255 - - - - - PDCCHfalse alarm - - - PDCCHfalse alarm(U8Q7) - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from rw1c to rc. - PMI -0 -1 - - - bit type is changed from rw1c to rc. - PBCH -0 -1 - - - bit type is changed from rw1c to rc. - PDSCH -0 -1 - - - bit type is changed from rw1c to rc. - MPDCCH -0 -1 - - - - - DCI -0 -1 - - - DCI Ri -0DCI -1DCIRi - - - DCI2 -0DCI -1DCI2 - - - DCI -0DCI -1DCI - - - - - MIB -0MIB -1MIB - - - PDSCH CRC -0 -1 - - - PDSCH CRC -0CRC -1CRC - - - - - LDTC - - - - - LDTC - - - - - 1TS - - - - - 2TS - - - - - TS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CATMCELL RSOFDM0 -0OFDM0 -1OFDM0 - - - FFT -0 -1 - - - 0FFTFFT -1FFTFFT - - - 0DLFFTLDTC1LDTC -1DLFFTLDTC1LDTC - - - 1DLFFTTXRXOFDM -0DLFFT - - - 0: -1: - - - 0~1023 - - - 0~9 - - - - - CELL RS&AGC -000 -001 -010 -011 -100 - - - CAT1CELL RSOFDM0 -0OFDM0 -1OFDM0 - - - MBMS -2b00MBMSCELLRS -2b01MBMS1CELLRS -2b10MBMS2CELLRS -2b1100 - - - 0MBMS -1MBMS - - - CELLID - - - CP -0NORM CP -1EX CP - - - CELLRS PORT -2b00port0 -2b01port0/1 -2b10port0/1/2/3 -2b11CELLPORT_SEL2b112b00prot0 - - - UERS PORT -0port5 -1port7/8 - - - 0CELLRS -1CELLRS - - - 0UERS -1UERS - - - - - RSCSIRSCSIRS BITMAP - - - CSIRSCSIRSOFDM - - - CSIRSCSIRSOFDM - - - - - MBMSCELLRSOFDMAGC - - - MBMSAGCMBMSCELLRSOFDMAGC - - - - - 0PBCH -1PBCH - - - 0CSIRS -1CSIRS - - - - - PRB -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -1116prb - - - 0~6 - - - 0TDD MODE -1FDD MODE - - - 0~9 - - - - - FFT0~4096 - - - - - NBIOTNBPRB0~5 - - - CP -0CP -1CP - - - 0~6 - - - 0TDD MODE -1FDD MODE - - - 0~9 - - - - - CELL RS&AGC -000 -001 -010 -011 -100 - - - 0NBNRS -1NBCRS - - - CELLRSNRSID - - - CELLRSNRS PORT -2b00port0 -2b01port0/1 -2b10port0/1/2/3 -2b112b10 - - - - - 0 -1 - - - - - CATMAGC - - - - - 0LDTC1LLR0 -1LDTC1LLR - - - CTCG -0OFDM4(OFDM4)CRS -1OFDM8(OFDM8)CRS - - - 000 -011 -102 -0 - - - 2 -001port -012port -104port -1port - - - 1 -001port -012port -104port -1port - - - 2 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 1 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 2 CELL ID - - - 1 CELL ID - - - - - 1TS - - - - - 2TS - - - - - - - ABISOFDM0~13 - - - CRSCRS - - - - - - - - - - AGC - - - - - 0DLFFT_INFO_OUT1 -1DLFFT_INFO_OUT2 - - - DLFFT INFO - - - 0CRS_POW_MAXPOWAGC -1CRS_POW_MAXPOWAGC - - - 0SOFT_IRT -1SOFT_IRT - - - 00CAT1 -01CATM -10NB-IOT -11CAT1 - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~18bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~19bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~20bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~21bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~22bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~23bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~24bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~25bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~26bit - - - - - ATMCELL RSOFDM0 -0OFDM0 -1OFDM0 - - - FFT -0 -1 - - - 0FFTFFT -1FFTFFT - - - 0DLFFTLDTC1LDTC -1DLFFTLDTC1LDTC - - - 1DLFFTTXRXOFDM -0DLFFT - - - 0: -1: - - - 0~1023 - - - 0~9 - - - - - CELL RS&AGC -000 -001 -010 -011 -100 - - - CELL RSOFDM0 -0OFDM0 -1OFDM0 - - - MBMS -2b00MBMSCELLRS -2b01MBMS1CELLRS -2b10MBMS2CELLRS -2b1100 - - - 0MBMS -1MBMS - - - CELLID - - - CP -0NORM CP -1EX CP - - - CELLRS PORT -2b00port0 -2b01port0/1 -2b10port0/1/2/3 -2b11CELLPORT_SEL2b112b00prot0 - - - UERS PORT -0port5 -1port7/8 - - - 0CELLRS -1CELLRS - - - 0UERS -1UERS - - - - - RSCSIRSCSIRS BITMAP - - - CSIRSCSIRSOFDM - - - CSIRSCSIRSOFDM - - - - - MBMSCELLRSOFDMAGC - - - MBMSAGCMBMSCELLRSOFDMAGC - - - - - 0PBCH -1PBCH - - - 0CSIRS -1CSIRS - - - - - PRB -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -1116prb - - - 0~6 - - - 0TDD MODE -1FDD MODE - - - 0~9 - - - - - FFT0~4096 - - - - - NBIOTNBPRB0~5 - - - CP -0CP -1CP - - - 0~6 - - - 0TDD MODE -1FDD MODE - - - 0~9 - - - - - CELL RS&AGC -000 -001 -010 -011 -100 - - - 0NBNRS -1NBCRS - - - CELLRSNRSID - - - CELLRSNRS PORT -2b00port0 -2b01port0/1 -2b10port0/1/2/3 -2b112b10 - - - - - 0 -1 - - - - - CATMAGC - - - - - 0LDTC1LLR0 -1LDTC1LLR - - - CTCG -0OFDM4(OFDM4)CRS -1OFDM8(OFDM8)CRS - - - 000 -011 -102 -0 - - - 2 -001port -012port -104port -1port - - - 1 -001port -012port -104port -1port - - - 2 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 1 -0006prb -00115prb -01025prb -01150prb -10075prb -101100prb -6prb - - - 2 CELL ID - - - 1 CELL ID - - - - - 1TS - - - - - 2TS - - - - - ABIS LLR-8~8 - - - ABISOFDM0~13 - - - CRSCRS - - - - - - - - - - AGC - - - - - 0DLFFT_INFO_OUT1 -1DLFFT_INFO_OUT2 - - - DLFFT INFO - - - 0CRS_POW_MAXPOWAGC -1CRS_POW_MAXPOWAGC - - - 0SOFT_IRT -1SOFT_IRT - - - 00CAT1 -01CATM -10NB-IOT -11CAT1 - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~18bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~19bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~20bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~21bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~22bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~23bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~24bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~25bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~26bit - - - - - 1RF -0RF - - - 1RF -0RF - - - 1RF -0RF - - - 1RF -0RF - - - 1RF -0RF - - - 1AXIDMA -AXIDMADLFFT -OFDM -0AXIDMA - - - 1DLFFTTXRX or LDTC or LDTC1ERROR -0DLFFTTXRX or LDTCor LDTC1ERROR - - - 1DLFFTOFDM -0DLFFT - - - 1DLFFTTXRXOFDM -0DLFFT - - - - - FFT0~4096 - - - - - 0: CATM/NB -1: CATM/NB - - - 0: CAT1 -1: CAT1 - - - - - bit type is changed from rw1c to rc. - 1MEASPWR -0 MEASPWR - - - bit type is changed from rw1c to rc. - 1RF -0RF - - - bit type is changed from rw1c to rc. - 1SDDLFFT -0SDDLFFT - - - bit type is changed from rw1c to rc. - 1COEFFLDTC -0COEFFLDTC - - - bit type is changed from rw1c to rc. - 1COEFFLDTC1 -0COEFFLDTC1 - - - bit type is changed from rw1c to rc. - 1RF -0RF - - - bit type is changed from rw1c to rc. - 1RF -0RF - - - bit type is changed from rw1c to rc. - 1RF -0RF - - - bit type is changed from rw1c to rc. - 1RF -0RF - - - bit type is changed from rw1c to rc. - 1AXIDMAAXIDMADLFFTOFDM -0AXIDMA - - - bit type is changed from rw1c to rc. - 1CSI -0CSI - - - bit type is changed from rw1c to rc. - 1MMSE -0MMSE - - - bit type is changed from rw1c to rc. - 1LDTC -0LDTC - - - bit type is changed from rw1c to rc. - 1TXRX -0TXRX - - - bit type is changed from rw1c to rc. - 1DLFFTOFDM -0DLFFT - - - bit type is changed from rw1c to rc. - 1DLFFTTXRXOFDM -0DLFFT - - - - - OFDM0~13 - - - - - DLFFT INFO 2 - - - DLFFT INFO 1 - - - 0 -1 - - - - - ABIS11 - - - - - ABIS22 - - - - - ABIS31+2 - - - - - CELLRS - - - - - CELLRSAGC - - - - - CELLRS - - - - - CELLRSAGC - - - - - CELLRS - - - - - CELLRSAGC - - - - - CELLRS - - - - - CELLRSAGC - - - - - CELLRS - - - - - CELLRSAGC - - - - - - - - - - OFDM 7TXRX - - - OFDM 6TXRX - - - OFDM 5TXRX - - - OFDM 4TXRX - - - OFDM 3TXRX - - - OFDM 2TXRX - - - OFDM 1TXRX - - - OFDM 0TXRX - - - - - OFDM 13TXRX - - - OFDM 12TXRX - - - OFDM 11TXRX - - - OFDM 10TXRX - - - OFDM 9TXRX - - - OFDM 8TXRX - - - - - TXRXSOFT IRT1 - - - TXRXSOFT IRT0 - - - - - ASSERTTXRX_ENABLE - - - ASSERTOFDM0~13 - - - - - ASSERT - - - - - 0ABISLLR_OUT3 -1ABISLLR_OUT3 - - - 0ABISLLR_OUT2 -1ABISLLR_OUT2 - - - 0ABISLLR_OUT1 -1ABISLLR_OUT1 - - - - - - - - - Coeffmeas -1 -0 - - - Coeffldtc\ldtc1 -1 -0 - - - Coeffldtc\ldtc1 buf -00ldtc buf1 -01ldtc buf2 -10ldtc buf3 -11 - - - CAT1CATM -0CATM -1CAT1 - - - 0 -1 - - - Port -0Port78 -1Port5 - - - 0QFQT -1QFQT - - - 0: NCP -1: ECP - - - 0: QFQT -1: QFQT - - - - - bit type is changed from rw1c to rc. - buf -00ldtc buf1 -01ldtc buf2 -10ldtc buf3 -11meas buf - - - bit type is changed from rw1c to rc. - - - bit type is changed from rw1c to rc. -0: -1: - - - - - 000: 6PRB -001: 15PRB -010: 25PRB -011: 50PRB -100: 75PRB -101: 100PRB -Others: RESERVED 6PRB - - - - - - 00: EPA -01: EVA -10: ETU -11: RESERVED EPA - - - - - 005 -0170 -10300 -11: 850 - - - TDDFDD -0TDD -1FDD - - - - - - 0000SS0 -0001SS1 -0010SS2 -0011SS3 -0100SS4 -0101SS5 -0110SS6 -0111SS7 -1000SS8 -1001SS9 - - - - - - - - - - - - - - - - - - - 1 -0 - - - 1 -0 - - - - - RAM3RAM -RAM3256+ - - - RAM2SPI RAM - - - RAM3RAM -RAM3256+ - - - RAM2SPI RAM - - - - - 1 -0 - - - SPI -1SPI -0GPO - - - SPI -1SPI -0SPI - - - - - - - - SPI - - - - - SPISENSCLK - - - SPI -0004 -0016default -0108 -01110 -10012 -10114 -11016 -11118 - - - SPI -0004 -0016default -0108 -01110 -10012 -10114 -11016 -11118 - - - 4-W3-W -0 -1 - - - 17bit4 -0 -1 - - - SPI -03 -14 - - - SPISPI -00:0 -01:1 -10:2 -11:3 - - - 00 -1 - - - 0Normal SPI -1DigRF SPI - - - SPI -0: -1; -1: -; - - - SPI -0: SPIIDLE -1: SPIIDLE - - - SPI -0: SPI -1: SPI - - - SPI -00000: 1-bits -00001: 2-bits -........... -11111: 32-bits - - - SPI -00000: 1-bits -00001: 2-bits -........... -11111: 32-bits - - - - - RFSPI - - - - - 1 -0 - - - 1 -0 - - - 0RAM -1RAM - - - 0 -1 -0xf0xA - - - RAM - - - 1 -0 - - - 1 -0 - - - 0RAM -1RAM - - - 0 -1 -0xf0xA - - - RAM - - - - - RF GPO control register - - - - - 1 -0 - - - - - - - - - RFAD - - - - - 1 -0 - - - FRAMC - - - - - - - - - - - - - 1 -0 - - - FRAMC - - - - - - - - - - - - - FRAML - - - FRAML - - - - - - - - FRAMC - - - - - - - - FRAMC - - - - - - - - - - - - - - - - - - - bit type is changed from r/w to rw. - DFT/IDFTindex0~4344index - - - bit type is changed from r/w to rw. - 00: BPSK -01: QPSK -10: 16QAM -11: 64QAM - - - bit type is changed from r/w to rw. - 0DFT/IDFT -1DFT/IDFT - - - bit type is changed from r/w to rw. - 0PUSCH -1PUSCH - - - bit type is changed from r/w to rw. - 0: DFT -1: IDFT - - - - - bit type is changed from r/w to rw. - PUCCHd(n) - - - - - SRS -021 -143 - - - bit type is changed from r/w to rw. -000 -011 -102 -113 - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - - - 0SRS1 -1SRS2 - - - SRSOFDM - - - SRSOFDM - - - SRSOFDM - - - bit type is changed from r/w to rw. - SRSZC - - - - - 0TX -1TX - - - 2 - - - 1 - - - PUCCH - - - PUCCH - - - - - PUSCH -00.5ms -11ms - - - PUSCH - - - PUSCH - - - PUSCH - - - PUSCH - - - - - PUSCH DMRS -1 -0 - - - PUSCH/PUCCH -0000normal -0001type0_shortend -0010type1_shortend -0011type2_shortend -0100type3_shortend -0101type4_shortend -0110type5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1u -0u - - - 1v -0v - - - TA0~32 - - - dmrsValue0~7 - - - - - SRSAPC - - - PUSCH/PUCCH/PRACHAPC - - - - - PUCCH1/1a/1b0~4095 - - - SRS - - - CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 - - - 0~1023 - - - - - OFDMoffset - - - OFDMoffset - - - - - 0ULDFTTXRXPUSCHERROR -1ULDFTTXRXPUSCHERROR - - - 1AXIDMA -0AXIDMA - - - 1OFDM13 -0OFDM13 - - - 1OFDM12 -0OFDM12 - - - 1OFDM11 -0OFDM11 - - - 1OFDM10 -0OFDM10 - - - 1OFDM9 -0OFDM9 - - - 1OFDM8 -0OFDM8 - - - 1OFDM7 -0OFDM7 - - - 1OFDM6 -0OFDM6 - - - 1OFDM5 -0OFDM5 - - - 1OFDM4 -0OFDM4 - - - 1OFDM3 -0OFDM3 - - - 1OFDM2 -0OFDM2 - - - 1OFDM1 -0OFDM1 - - - 1OFDM0 -0OFDM0 - - - - - bit type is changed from rw1c to rc. - 1OFDM13 -0OFDM13 - - - bit type is changed from rw1c to rc. - 1OFDM12 -0OFDM12 - - - bit type is changed from rw1c to rc. - 1OFDM11 -0OFDM11 - - - bit type is changed from rw1c to rc. - 1OFDM10 -0OFDM10 - - - bit type is changed from rw1c to rc. - 1OFDM9 -0OFDM9 - - - bit type is changed from rw1c to rc. - 1OFDM8 -0OFDM8 - - - bit type is changed from rw1c to rc. - 1OFDM7 -0OFDM7 - - - bit type is changed from rw1c to rc. - 1OFDM6 -0OFDM6 - - - bit type is changed from rw1c to rc. - 1OFDM5 -0OFDM5 - - - bit type is changed from rw1c to rc. - 1OFDM4 -0OFDM4 - - - bit type is changed from rw1c to rc. - 1OFDM3 -0OFDM3 - - - bit type is changed from rw1c to rc. - 1OFDM2 -0OFDM2 - - - bit type is changed from rw1c to rc. - 1OFDM1 -0OFDM1 - - - bit type is changed from rw1c to rc. - 1OFDM0 -0OFDM0 - - - bit type is changed from rw1c to rc. - 1pusch -0pusch - - - bit type is changed from rw1c to rc. - 1txrx -0txrx - - - - - OFDM -14b0 -14b10 -14b1101 -14b111012 - - - - - 0ULDFT -1ULDFT - - - 0ULDFT -1ULDFTPUSCH - - - 0 -1 - - - 0SRS -1SRS - - - 0FFTMEM -1FFTMEM - - - 1IFFT -0FFT - - - 1FFT/IFFT -0FFT/IFFT - - - 0 -1 - - - PRACH -000PRACH0 -001PRACH1 -010PRACH2 -011PRACH3 -100PRACH4 - - - PUCCH -000PUCCH1 -001PUCCH1a -010PUCCH1b -011PUCCH2 -100PUCCH2a -101PUCCH2b - - - 0NPUSCH format 1 -1NPUSCH format2 - - - OFDM - - - 0DATADRIVE -1DATADRIVE - - - UL_DFTPUSCH BUFFER -00PUSCH BUFFER1 -01PUSCH BUFFER2 -10PUSCH BUFFER3 -11PUSCH PRA_BUF - - - 000PUSCH -001PUCCH -010PRACH -011SRS -100NPUSCH -101NPRACH - - - FFT/IFFT -111 -110 -101 -1002048 -0111024 -010512 -001256 -000128 - - - 0: -1: - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - NPUSCH0~127 - - - 001 -013 -106 -1112 - - - NPUSCH 0~47 - - - Nslots1~160 - - - 0: 3.75KHz -1: 15KHz - - - - - RU0~19 - - - 1DMRS0~20480 - - - BASE_SEQ_NEXT0~30 - - - CYCLIC_SHIFT0~3 - - - - - t0~128 - - - frequency location of the first sub-carrier allocated to NPRACH -000frequency location0 -001frequency location2 -010frequency location12 -011frequency location18 -100frequency location24 -101frequency location34 -110frequency location36 -1110 - - - being the subcarrier selected by the MAC layer from 0-47 - - - - - - - - 0~29 - - - PUCCH2/2a/2b0~1184 - - - 0~7 - - - CP -0CP -1CP - - - 0TDD mode -1FDD mode - - - 1: -0: - - - - - NCSUGOLDC_INI -1if no value for or is configured by higher layers or the PUSCH transmission corresponds to a Random Access Response Grant or a retransmission of the same transport block as part of the contention based random access procedure -0otherwise - - - NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509 - - - NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509 - - - ID0~503 - - - - - RSID - - - - - nCsAn1/1a/1b0~7 - - - CE_mode -0CE_modeA -1CE_modeB - - - 00 1 -01 2 -10 3 -1100 1 - - - cqiNrb PUCCH2/2a/2b0~98 - - - - - ULDFT -00CAT1 -01CATM -10NB-IOT -11CAT1 - - - CAT1 -0006PRB -00115PRB -01025PRB -01150PRB -10075PRB -101100PRB -6PRB - - - - - 0DMA -1DMA - - - 0: -1: - - - - - SW_PAUSE_EN=1OFDM -14`b0 -14`b1OFDM0 -14`b11OFDM01 -14`b111OFDM012 - - - SW_PAUSE_EN=1 -0SW_PAUSE_OFDMOFDM -1SW_PAUSE_OFDMOFDM - - - 0 -1 - - - 0 -1 - - - 0 -1OFDM - - - - - bit type is changed from rw1c to rc. -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - - - bit type is changed from r/w to rw. - DFT/IDFTindex0~4344index - - - bit type is changed from r/w to rw. - 00: BPSK -01: QPSK -10: 16QAM -11: 64QAM - - - bit type is changed from r/w to rw. - 0DFT/IDFT -1DFT/IDFT - - - bit type is changed from r/w to rw. - 0PUSCH -1PUSCH - - - bit type is changed from r/w to rw. - 0: DFT -1: IDFT - - - - - bit type is changed from r/w to rw. - PUCCHd(n) - - - - - SRS -021 -143 - - - bit type is changed from r/w to rw. -000 -011 -102 -113 - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - - - 0SRS1 -1SRS2 - - - SRSOFDM - - - SRSOFDM - - - SRSOFDM - - - bit type is changed from r/w to rw. - SRSZC - - - - - 0TX -1TX - - - 2 - - - 1 - - - PUCCH - - - PUCCH - - - - - PUSCH -00.5ms -11ms - - - PUSCH - - - PUSCH - - - PUSCH - - - PUSCH - - - - - PUSCH/PUCCH -0000normal -0001type0_shortend -0010type1_shortend -0011type2_shortend -0100type3_shortend -0101type4_shortend -0110type5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1u -0u - - - 1v -0v - - - TA0~32 - - - dmrsValue0~7 - - - - - SRSAPC - - - PUSCH/PUCCH/PRACHAPC - - - - - PUCCH1/1a/1b0~4095 - - - SRS - - - CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 - - - 0~1023 - - - - - OFDMoffset - - - OFDMoffset - - - - - 0ULDFTTXRXPUSCHERROR -1ULDFTTXRXPUSCHERROR - - - 1AXIDMA -0AXIDMA - - - 1OFDM13 -0OFDM13 - - - 1OFDM12 -0OFDM12 - - - 1OFDM11 -0OFDM11 - - - 1OFDM10 -0OFDM10 - - - 1OFDM9 -0OFDM9 - - - 1OFDM8 -0OFDM8 - - - 1OFDM7 -0OFDM7 - - - 1OFDM6 -0OFDM6 - - - 1OFDM5 -0OFDM5 - - - 1OFDM4 -0OFDM4 - - - 1OFDM3 -0OFDM3 - - - 1OFDM2 -0OFDM2 - - - 1OFDM1 -0OFDM1 - - - 1OFDM0 -0OFDM0 - - - - - OFDM -14b0 -14b10 -14b1101 -14b111012 - - - - - 0ULDFT -1ULDFT - - - 0ULDFT -1ULDFTPUSCH - - - 0 -1 - - - 0SRS -1SRS - - - 0FFTMEM -1FFTMEM - - - 1IFFT -0FFT - - - 1FFT/IFFT -0FFT/IFFT - - - 0 -1 - - - PRACH -000PRACH0 -001PRACH1 -010PRACH2 -011PRACH3 -100PRACH4 - - - PUCCH -000PUCCH1 -001PUCCH1a -010PUCCH1b -011PUCCH2 -100PUCCH2a -101PUCCH2b - - - 0NPUSCH format 1 -1NPUSCH format2 - - - OFDM - - - 0DATADRIVE -1DATADRIVE - - - UL_DFTPUSCH BUFFER -00PUSCH BUFFER1 -01PUSCH BUFFER2 -10PUSCH BUFFER3 -11PUSCH PRA_BUF - - - 000PUSCH -001PUCCH -010PRACH -011SRS -100NPUSCH -101NPRACH - - - FFT/IFFT -111 -110 -101 -1002048 -0111024 -010512 -001256 -000128 - - - 0: -1: - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - NPUSCH0~127 - - - 001 -013 -106 -1112 - - - NPUSCH 0~47 - - - Nslots1~160 - - - 0: 3.75KHz -1: 15KHz - - - - - RU0~19 - - - 1DMRS0~20480 - - - BASE_SEQ_CURR0~30 - - - CYCLIC_SHIFT0~3 - - - - - t0~128 - - - frequency location of the first sub-carrier allocated to NPRACH -000frequency location0 -001frequency location2 -010frequency location12 -011frequency location18 -100frequency location24 -101frequency location34 -110frequency location36 -1110 - - - being the subcarrier selected by the MAC layer from 0-47 - - - - - bit type is changed from r/w to rw. - DFT/IDFTindex0~4344index - - - bit type is changed from r/w to rw. - 00: BPSK -01: QPSK -10: 16QAM -11: 64QAM - - - bit type is changed from r/w to rw. - 0DFT/IDFT -1DFT/IDFT - - - bit type is changed from r/w to rw. - 0PUSCH -1PUSCH - - - bit type is changed from r/w to rw. - 0: DFT -1: IDFT - - - - - bit type is changed from r/w to rw. - PUCCHd(n) - - - - - SRS -021 -143 - - - bit type is changed from r/w to rw. -000 -011 -102 -113 - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - bit type is changed from r/w to rw. - SRS - - - - - 0SRS1 -1SRS2 - - - SRSOFDM - - - SRSOFDM - - - SRSOFDM - - - bit type is changed from r/w to rw. - SRSZC - - - - - 0TX -1TX - - - 2 - - - 1 - - - PUCCH - - - PUCCH - - - - - PUSCH -00.5ms -11ms - - - PUSCH - - - PUSCH - - - PUSCH - - - PUSCH - - - - - PUSCH/PUCCH -0000normal -0001type0_shortend -0010type1_shortend -0011type2_shortend -0100type3_shortend -0101type4_shortend -0110type5_shortend -0111: type6_shortend -1000: type7_shortend -1001: other - - - 1u -0u - - - 1v -0v - - - TA0~32 - - - dmrsValue0~7 - - - - - SRSAPC - - - PUSCH/PUCCH/PRACHAPC - - - - - PUCCH1/1a/1b0~4095 - - - SRS - - - CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 - - - 0~1023 - - - - - OFDMoffset - - - OFDMoffset - - - - - 0ULDFTTXRXPUSCHERROR -1ULDFTTXRXPUSCHERROR - - - 1AXIDMA -0AXIDMA - - - 1OFDM13 -0OFDM13 - - - 1OFDM12 -0OFDM12 - - - 1OFDM11 -0OFDM11 - - - 1OFDM10 -0OFDM10 - - - 1OFDM9 -0OFDM9 - - - 1OFDM8 -0OFDM8 - - - 1OFDM7 -0OFDM7 - - - 1OFDM6 -0OFDM6 - - - 1OFDM5 -0OFDM5 - - - 1OFDM4 -0OFDM4 - - - 1OFDM3 -0OFDM3 - - - 1OFDM2 -0OFDM2 - - - 1OFDM1 -0OFDM1 - - - 1OFDM0 -0OFDM0 - - - - - OFDM -14b0 -14b10 -14b1101 -14b111012 - - - - - 0ULDFT -1ULDFT - - - 0ULDFT -1ULDFTPUSCH - - - 0 -1 - - - 0SRS -1SRS - - - 0FFTMEM -1FFTMEM - - - 1IFFT -0FFT - - - 1FFT/IFFT -0FFT/IFFT - - - 0 -1 - - - PRACH -000PRACH0 -001PRACH1 -010PRACH2 -011PRACH3 -100PRACH4 - - - PUCCH -000PUCCH1 -001PUCCH1a -010PUCCH1b -011PUCCH2 -100PUCCH2a -101PUCCH2b - - - 0NPUSCH format 1 -1NPUSCH format2 - - - OFDM - - - 0DATADRIVE -1DATADRIVE - - - UL_DFTPUSCH BUFFER -00PUSCH BUFFER1 -01PUSCH BUFFER2 -10PUSCH BUFFER3 -11PUSCH PRA_BUF - - - 000PUSCH -001PUCCH -010PRACH -011SRS -100NPUSCH -101NPRACH - - - FFT/IFFT -111 -110 -101 -1002048 -0111024 -010512 -001256 -000128 - - - 0: -1: - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - FFT -2b0025~14bit -2b0126~15bit -2b1027~16bit -2b1128~17bit - - - - - NPUSCH0~127 - - - 001 -013 -106 -1112 - - - NPUSCH 0~47 - - - Nslots1~160 - - - 0: 3.75KHz -1: 15KHz - - - - - RU0~19 - - - 1DMRS0~20480 - - - BASE_SEQ_CURR0~30 - - - CYCLIC_SHIFT0~3 - - - - - t0~128 - - - frequency location of the first sub-carrier allocated to NPRACH -000frequency location0 -001frequency location2 -010frequency location12 -011frequency location18 -100frequency location24 -101frequency location34 -110frequency location36 -1110 - - - being the subcarrier selected by the MAC layer from 0-47 - - - - - TXRX PING -1 -0 - - - TXRX PANG -1 -0 - - - - - - - - - - - OFDM0~13 - - - - - ASSERT TXRX PING -1 -0 - - - ASSERT TXRX PANG -1 -0 - - - ASSERT - - - ASSERT - - - - - ASSERT OFDM0~13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bit type is changed from rw1c to rc. - TRACE -0 -1 - - - bit type is changed from rw1c to rc. - TRACE -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - - - TRACE -0 -1 - - - TRACE -0 -1 - - - 0 -1 - - - 0 -1 - - - 0 -1 - - - 0 -1 - - - - - bit type is changed from rw1c to rc. - 0OFDM14 -1OFDM14 - - - bit type is changed from rw1c to rc. - 0OFDM13 -1OFDM13 - - - bit type is changed from rw1c to rc. - 0OFDM12 -1OFDM12 - - - bit type is changed from rw1c to rc. - 0OFDM11 -1OFDM11 - - - bit type is changed from rw1c to rc. - 0OFDM10 -1OFDM10 - - - bit type is changed from rw1c to rc. - 0OFDM9 -1OFDM9 - - - bit type is changed from rw1c to rc. - 0OFDM8 -1OFDM8 - - - bit type is changed from rw1c to rc. - 0OFDM7 -1OFDM7 - - - bit type is changed from rw1c to rc. - 0OFDM6 -1OFDM6 - - - bit type is changed from rw1c to rc. - 0OFDM5 -1OFDM5 - - - bit type is changed from rw1c to rc. - 0OFDM4 -1OFDM4 - - - bit type is changed from rw1c to rc. - 0OFDM3 -1OFDM3 - - - bit type is changed from rw1c to rc. - 0OFDM2 -1OFDM2 - - - bit type is changed from rw1c to rc. - 0OFDM1 -1OFDM1 - - - bit type is changed from rw1c to rc. - 0OFDM0 -1OFDM0 - - - - - 1 -0 -1 - - - 0OFDM -1OFDM - - - 0OFDM14 -1OFDM14 - - - 0OFDM13 -1OFDM13 - - - 0OFDM12 -1OFDM12 - - - 0OFDM11 -1OFDM11 - - - 0OFDM10 -1OFDM10 - - - 0OFDM9 -1OFDM9 - - - 0OFDM8 -1OFDM8 - - - 0OFDM7 -1OFDM7 - - - 0OFDM6 -1OFDM6 - - - 0OFDM5 -1OFDM5 - - - 0OFDM4 -1OFDM4 - - - 0OFDM3 -1OFDM3 - - - 0OFDM2 -1OFDM2 - - - 0OFDM1 -1OFDM1 - - - 0OFDM0 -1OFDM0 - - - - - DCOC -1 -0 - - - 0 -1 - - - 0 -1 - - - DFE -0DFE -1DFE - - - 0 -1 - - - CAT1 -0CAT1 -1CAT1 - - - - - 0 -1 - - - 0 -1 - - - - - - SOFT AFC -0 -1 - - - RSSI -1data -0data - - - RSSI -0: RSSI_MAX1 -1: RSSI_MAX2 -2: RSSI_MAX3 -3: RSSI_MAX4 -4: RSSI_MAX5 -Other: - - - 1 -0 - - - OTDOA -1 -0 - - - offset -1RXoffsetcp -0offset - - - 1IDDET -0IDDET - - - DLFFT DATA_DRIVE -0 -1 - - - 00CP -01CP -10CPIDDET - - - FIR -4h033-22 -4h132-21 -4h231-20 -4h330-19 -4h429-18 -4h528-17 -4h627-16 -4h726-15 -4h825-14 -4h924-13 -4ha23-12 -4hb22-11 -4hc21-10 -4hd20-9 -4he19-8 -4hf18-7 - - - TRACE -1 -0 - - - 0measpwr/dlfft offset -10 -0offsetoffset_ctrl_flag - - - 0 -1 - - - 0 -1 - - - 0 -1 - - - 0 -1 - - - RSSI -1 -0 - - - 0 -1 - - - - - OFDM - - - - - AFC -1 -0 - - - AFC -10hz - - - - - 1 -0 -AD_ON0 - - - RSSI0 -1 -0 - - - RSSI - - - - - 1~5 - - - - - - - - - - - - - - - - 3h5: 20M (1/16) -3h4: 15M (1/16) -3h3: 10M (1/8) -3h2: 5M (1/4) -3h1: 3M (1/2) -3h0: 1.4M -Other: - - - 1 -0 - - - FIR -1 -0 - - - FIR -5b0000034-23 -5b0000133-22 -5b0001032-21 -5b0001131-20 -5b0010030-19 -5b0010129-18 -5b0011028-17 -5b0011127-16 -5b0100026-15 -5b0100125-14 -5b0101024-13 -5b0101123-12 -5b0110022-11 -5b0110121-10 -5b0111020-9 -5b0111119-8 -5b1000018-7 -5b1000117-6 -5b1001016-5 -Other - - - - - - - - - - - - - - - DCOC -0 -1 - - - I - - - Q - - - - - GAIN1 -0 -1 - - - GAIN1 - - - - - GAIN2 -0 -1 - - - GAIN2 - - - - - IDDET -2h0:bit7 -2'h1:bit8 -2h2:bit9 -2'h3:bit10 - - - IDDET -3h0:bit0 -3'h1:bit1 -3h2:bit2 -3'h3:bit3 -3h4:bit4 -other:reserved - - - OTDOA -2h0:bit7 -2'h1:bit8 -2h2:bit9 -2'h3:bit10 - - - OTDOA -3h0:bit0 -3'h1:bit1 -3h2:bit2 -3'h3:bit3 -3h4:bit4 -other:reserved - - - MEASPWR -2h0:bit7 -2'h1:bit8 -2h2:bit9 -2'h3:bit10 - - - MEASPWR -3h0:bit0 -3'h1:bit1 -3h2:bit2 -3'h3:bit3 -3h4:bit4 -other:reserved - - - - - - 0 -1 - - - DATA_DRIVE -0 -1 - - - 1CP -0CP - - - 0 -1 - - - - - OFDM(-32~31) - - - - - PINGCP0 - - - - - PANGCP0 - - - - - PRACH -1 -0 -DFT - - - PRACH -3hxxx0~4 -DFT - - - NB -DFT - - - 1 -0 -DFT - - - 3h5: 20M (16) -3h4: 15M (16) -3h3: 10M (8) -3h2: 5M (4) -3h1: 3M (2) -3h0: 1.4M -Other: - - - 1 -0 - - - FIR -5b0000034-23 -5b0000133-22 -5b0001032-21 -5b0001131-20 -5b0010030-19 -5b0010129-18 -5b0011028-17 -5b0011127-16 -5b0100026-15 -5b0100125-14 -5b0101024-13 -5b0101123-12 -5b0110022-11 -5b0110121-10 -5b0111020-9 -5b0111119-8 -5b1000018-7 -5b1000117-6 -5b1001016-5 -Other - - - - - 0 -8hff : 255 -8hfe: 254 -8h01: 1 -8h00: 0 - - - - - - - - - - - 32h0:0 -32h1:1 -????????? - - - - - - - - - - RSSI - - - - - RSSI - - - - - RSSI - - - - - RSSI - - - - - RSSI - - - - - I - - - Q - - - - - - RX_MEM - - - AD_ON - - - 0 -1 - - - DLFFT - - - OTDOA - - - IDDET - - - MEAS - - - CP -0 -1 - - - 0 -1 - - - PING_PANG - - - OFDM - - - - - TX_MEM - - - DA_ON - - - 0 -1 - - - FIFO -0ping -1pang - - - OFDM - - - - - - - - TS - - - - - - AD_ON - - - 01 - - - mem - - - - - - CP - - - - - - - - TS - - - - - - DA_ON - - - 0 -1 - - - PING RAM - - - DFTPING - - - DFTPANG - - - PING - - - PANG - - - - - ADONFRAMC - - - FRAMC - - - - - - - - FRAMC - - - - - AD_ON - - - AD_ON - - - AD_ON - - - AD_ON - - - - - DA_ON - - - DA_ON - - - DA_ON - - - DA_ON - - - - - 4FFTBUF1 - - - 3FFTBUF1 - - - 2FFTBUF1 - - - 1FFTBUF1 - - - - - 4FFTBUF2 - - - 3FFTBUF2 - - - 2FFTBUF2 - - - 1FFTBUF2 - - - - - 4FFT2LDTC - - - 3FFT2LDTC - - - 2FFT2LDTC - - - 1FFT2LDTC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FDD_TDD -0FDD -1TDD - - - TXRXAD_ON -0~30720*10-110ms(AD ON) - - - - - MEASPWR1~30720*6(6ms) - - - - - Offset2 -0offset2 -1offset2 - - - MEASPWR 0~30720*6-1 - - - - - ID1 (0~30720*10-1) - - - - - ID2 (0~30720*10-1) - - - - - s - - - - - ID4 (0~30720*10-1) - - - - - ID5 (0~30720*10-1) - - - - - ID6 (0~30720*10-1) - - - - - ID7 (0~30720*10-1) - - - - - ID8 (0~30720*10-1) - - - - - Nboffset4 - - - - - ID3~ID8 -01 -12 -23 -511:512 - - - ID1ID2 -01 -12 -23 -511:512 - - - - - IFFT - - - IFFT - - - IFFT - - - IFFT - - - IFFT - - - IFFT - - - IFFT -2b00:bit[25:14] -2b01:bit[26:15] -2b10:bit[27:16] -2b11:bit[28:17] - - - - - IFFT - - - - - ID8 10 -bit[28] -bit[29] -bit[30]AFC -bit[31]:agc_compare - - - ID7 10 -bit[24] -bit[25] -bit[26]AFC -bit[27]:agc_compare - - - ID6 10 -bit[20] -bit[21] -bit[22]AFC -bit[23]:agc_compare - - - ID5 10 -bit[16] -bit[17] -bit[18]AFC -bit[19]:agc_compare - - - ID4 10 -bit[12] -bit[13] -bit[14]AFC -bit[15]:agc_compare - - - ID3 10 -bit[8] -bit[9] -bit[10]AFC -bit[11]:agc_compare - - - ID2 10 -bit[4] -bit[5] -bit[6]AFC -bit[7]:agc_compare - - - ID1 10 -bit[0] -bit[1] -bit[2]AFC -bit[3]:agc_compare - - - - - bit type is changed from r1c to rc. - ID8 10 -bit[28] -bit[29] -bit[30]AFC -bit[31]:agc_compare - - - bit type is changed from r1c to rc. - ID7 10 -bit[24] -bit[25] -bit[26]AFC -bit[27]:agc_compare - - - bit type is changed from r1c to rc. - ID6 10 -bit[20] -bit[21] -bit[22]AFC -bit[23]:agc_compare - - - bit type is changed from r1c to rc. - ID5 10 -bit[16] -bit[17] -bit[18]AFC -bit[19]:agc_compare - - - bit type is changed from r1c to rc. - ID4 10 -bit[12] -bit[13] -bit[14]AFC -bit[15]:agc_compare - - - bit type is changed from r1c to rc. - ID3 10 -bit[8] -bit[9] -bit[10]AFC -bit[11]:agc_compare - - - bit type is changed from r1c to rc. - ID2 10 -bit[4] -bit[5] -bit[6]AFC -bit[7]:agc_compare - - - bit type is changed from r1c to rc. - ID1 10 -bit[0] -bit[1] -bit[2]AFC -bit[3]:agc_compare - - - - - TRMS - - - SIGMA - - - DOPPLER - - - SINR - - - AFC - - - AFC - - - TRMS - - - RSRP - - - IRT - - - - - TRMS - - - SIGMA - - - DOPPLER - - - SINR - - - AFC - - - AFC - - - TRMS - - - RSRP - - - IRT - - - - - agcagcagc - - - - - ID3-80-15CATM - - - ID20-15CATM - - - ID10-15CATM - - - - - ID3-8 -01.4m -13m -25m -310m -415m -520m - - - ID3-8 -01.4m -13m -25m -310m -415m -520m - - - ID1-2 -01.4m -13m -25m -310m -415m -520m - - - ID1-2 -01.4m -13m -25m -310m -415m -520m - - - - - - Afc_factor - - - AFC -0 -1 -4 - - - AFC -0001 -0012 -0103 -0114 -1006 -10112 -Other:1 - - - - - ID1 AFC - - - - - SIGPWR alpha - - - SIGPWR -001 -012 -114 -Other1 - - - ID1-2 SIGPWR( - - - - - SIGMA alpha - - - SIGMA1~80 - - - - - Id1-2 Doppler alpha - - - Doppler_scaleQ12 - - - DOPPLER1~80 - - - - - Trms8q0 - - - 0TRMSDis_Limit -1RSRPDis_Limit - - - ID3-8: -0:1L_U16ExtractStepTab_true1 -11L_U16ExtractStepTab_true - - - ID1-2: -0:1L_U16ExtractStepTab_true1 -11L_U16ExtractStepTab_true - - - (N2N+1) - - - - - ID1-216q15 - - - ID1-216q10 - - - - - ID3-8 - - - ID1-2 - - - ID1-2beta16Q10 - - - - - - - - ID3-8RSRP - - - ID1-2RSRP - - - L_S32RsrpdB_Temp = L_S32RsrpdB - AGC_Base*16 - RSRPAgcAdjust*16 + L_U16DownSamplingCompensate*16 - - - - - ID1-2 - - - RSSI Q() - - - - - FFTIFFTQ - - - FFTIFFT - - - - - IRT -08910 -1 - - - pow - - - Scale - - - - - - IRT -001 -012 -114 - - - - - ID1-2 - - - ID1-216q10 - - - - - 1ScaleTh - - - - - 2ScaleTh - - - - - 4ScaleTh - - - - - 8ScaleTh - - - - - 16ScaleTh - - - - - 32ScaleTh - - - - - 64ScaleTh - - - - - 128ScaleTh - - - - - 256ScaleTh - - - - - 512ScaleTh - - - - - ID3-8 Rssi - - - ID1-2 Rssi - - - IDRSSI -0MEASPWROFDMRSSI -1MEASPWR - - - - - AGC - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - AFC - - - Crs_rssi -00 -01 -10 -11reserved - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - AFC -0IRT -1bit[8:1] - - - 01 -12 - - - CP -0CP -1CP - - - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - Crs_rssi - - - bit[25:16]9-0 - - - OFFLINE0 - - - SINR -000NASINR -0011 -0102 -0113 -1004 -OtherNA - - - AFC -0 -1 - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - AFC - - - Crs_rssi -00 -01 -10 -11reserved - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - AFC -0IRT -1bit[8:1] - - - 01 -12 - - - CP -0CP -1CP - - - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - Crs_rssi - - - bit[25:16]9-0 - - - OFFLINE0 - - - - - AFC -0 -1 - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - FFT -4`b0000 -4`b0001 -4`b0010 -. - - - OFFLINE0 - - - 0 -1 - - - NID 0~503 - - - 2port -0port 0 and port 1 -1only port 1 - - - 01 -12 - - - CP -0CP -1CP - - - Crs_rssi - - - - - - 0 -1 - - - 0 -1 -1 - - - - - Offline -00 -11 - - - offline -0 -1 - - - NID1-2 - - - IRT -0 -1 - - - AFC -0 -1 - - - 0CATM -1CAT1 -2NB -NB_LTEFFT - - - - - bit type is changed from r1s to rs. - NID_MAP -0 -1 - - - bit type is changed from r1s to rs. - NID3-8 - - - bit type is changed from r1s to rs. - Offlineonline -0online -1offline - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - bit type is changed from r1s to rs. - ID1 -0 - - - - - bit type is changed from rw1s to rs. - NID8 - - - bit type is changed from rw1s to rs. - NID7 - - - bit type is changed from rw1s to rs. - NID6 - - - bit type is changed from rw1s to rs. - NID5 - - - bit type is changed from rw1s to rs. - NID4 - - - bit type is changed from rw1s to rs. - NID3 - - - bit type is changed from rw1s to rs. - NID2 - - - bit type is changed from rw1s to rs. - NID1 - - - - - AFC - - - - - AFC - - - - - AFC - - - - - AFC - - - - - AFC - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - 1SIGPWR - - - - - 2SIGPWR - - - - - 3SIGPWR - - - - - 4SIGPWR - - - - - 5SIGPWR - - - - - 6SIGPWR - - - - - ID2SIGPWR - - - - - ID3SIGPWR - - - - - ID4SIGPWR - - - - - ID5SIGPWR - - - - - 1SIGMA - - - - - 1SINR LOG - - - 1SIGMAAGC - - - - - 2SIGMA - - - - - 2SINR LOG - - - 2SIGMAAGC - - - - - 3SIGMA - - - - - 3SINR LOG - - - 3SIGMAAGC - - - - - 4SIGMA - - - - - 4SINR LOG - - - 4SIGMAAGC - - - - - SIGMA - - - - - 5SINR LOG - - - SIGMAAGC - - - - - ID1SIGMA - - - - - 6SINR LOG - - - ID1SIGMAAGC - - - - - ID2SIGMA - - - - - ID2SINR LOG - - - ID2SIGMAAGC - - - - - ID3SIGMA - - - - - ID3SINR LOG - - - ID3SIGMAAGC - - - - - ID4SIGMA - - - - - ID4SINR LOG - - - ID4SIGMAAGC - - - - - ID5SIGMA - - - - - ID5SINR LOG - - - ID5SIGMAAGC - - - - - 1SINR - - - - - 2SINR - - - - - 3SINR - - - - - 4SINR - - - - - SINR - - - - - ID1SINR - - - - - ID2SINR - - - - - ID3SINR - - - - - ID4SINR - - - - - ID5SINR - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - RSRP - - - - - RSRPdB - - - - - Scale - - - - - ScaledB - - - - - RSRQdBOFDM - - - - - RSSIRSSI AGC - - - - - RSSIdBOFDM - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - Irt_scale -1 -0 - - - IRTscale - - - - - IRT scale - - - - - - - - - - - - - - - ID2 - - - ID1 - - - - - ID1-2 RBIS CORRECT -0 -1 - - - ID1-2 RBIS JUDGE -0 -1 - - - ID1-2 RBIS -0 -1 - - - ID1-2 RBIS -0 -1 - - - ID1-2 RBIS -01 -12 -23 -34 -45 - - - ID1-2 RBIS - - - ID1-2 RBIS - - - - - ID14RBIPRB - - - ID13RBIPRB - - - ID12RBIPRB - - - ID11RBIPRB - - - - - ID1 RBIS JUDGE - - - ID15RBIPRB - - - - - ID1 RBIS - - - - - ID1 RBIS - - - - - ID2 offset4 - - - ID2 RX IRT - - - ID1 offset4 - - - ID1 RX IRT - - - - - debug_rev_flag - - - debug_update_flag - - - id_update - - - offset2_update - - - din_id_sel - - - datagen_state - - - datain_state - - - - - inmem_in_act - - - invalid_data_cont - - - inmem_cont - - - - - datain_state_cur - - - func_id_sel - - - pow_state - - - func_state - - - - - ID6SIGPWR - - - - - ID7SIGPWR - - - - - ID8SIGPWR - - - - - ID6SIGMA - - - - - ID6SINR LOG - - - ID6SIGMAAGC - - - - - ID7SIGMA - - - - - ID7SINR LOG - - - ID7SIGMAAGC - - - - - ID8SIGMA - - - - - ID8SINR LOG - - - ID8SIGMAAGC - - - - - ID6SINR - - - - - ID7SINR - - - - - ID8SINR - - - - - ID2 AFC - - - - - ID3 AFC - - - - - ID4 AFC - - - - - ID5 AFC - - - - - ID6 AFC - - - - - ID7 AFC - - - - - ID8 AFC - - - - - Id3-8 Doppler alpha - - - - - trmsf_scale(Q12 - - - TRMS - - - TRMS alpha - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - OFFLINE0 - - - Hmmse QF mem -0QF mem -1QF mem - - - IRT scale -0 -1 - - - AFC\POW -00hls -01hmmse -10freqfirst -11hls - - - bit[9:0]9-0 - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - AFC HST - - - - - ID1SIGPWR - - - - - ID2SIGPWR - - - - - ID3SIGPWR - - - - - ID4SIGPWR - - - - - ID5SIGPWR - - - - - ID6SIGPWR - - - - - ID7SIGPWR - - - - - ID8SIGPWR - - - - - ID1SIGMA - - - - - ID2SIGMA - - - - - ID3SIGMA - - - - - ID4SIGMA - - - - - ID5SIGMA - - - - - ID6SIGMA - - - - - ID7SIGMA - - - - - ID8SIGMA - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - hls_agc_base - - - DOPPLER - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - TRMS - - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - TRMSPART1 - - - - - TRMSPART2 - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - POWbit[23:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - REIS_DC - - - REIS -0 -1 - - - REISNUM - - - - - REIS1RE20M1200RE - - - REIS0RE20M1200RE - - - - - REIS3RE20M1200RE - - - REIS2RE20M1200RE - - - - - REIS5RE20M1200RE - - - REIS4RE20M1200RE - - - - - REIS7RE20M1200RE - - - REIS6RE20M1200RE - - - - - Pos\delay -0pos -1:delay - - - 00IRT_Scale -01RSRP_Scale -10SINR -11POWMAX_Scale - - - 00IRT_Scale -01Sigpwr -10SINR -11IRT_Scale - - - - - Offline -MEASPWR_OFFLINE_SEL[5:4] - - - - - Id8TBin - - - Id7TBin - - - Id6TBin - - - Id5TBin - - - Id4TBin - - - Id3TBin - - - Id2TBin - - - Id1TBin - - - - - TbinID1~ID8 -0 -1 - - - Offline -0xF - - - - - 00 -143 - - - Offline1 -000 -0105 -1050 -1190 - - - Offline1 -01 -12 - - - Offline1 - - - - - 3 AGC - - - 2 AGC - - - 1 AGC - - - - - 6 AGC - - - 5 AGC - - - 4 AGC - - - - - 9 AGC - - - 8 AGC - - - 7 AGC - - - - - 12 AGC - - - 11 AGC - - - 10 AGC - - - - - 15 AGC - - - 14 AGC - - - 13 AGC - - - - - 18 AGC - - - 17 AGC - - - 16 AGC - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssi - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - Crs rssiagc - - - - - 03PRB -16PRB - - - - - 13bit -0x029~17 -0x128~16 -0x227~15 -0x326~14 -0x425~13 -0x524~12 -0x623~11 -0x722~10 -0x821~9 -0x920~8 -0xa19~7 -0xb18~6 -0xc17~5 -0xd16~4 -0xe15~3 -0xf14~2 - - - - - USED_WL_IND - - - QF MEM -00mem -01mem -Othermem - - - - - ID38 - - - - - INMEM -00 measpwr -01OTDOA -10 -11 - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - AFC HSTRSRP db - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - Pow_max_scale - - - - - AFC - - - - - AFC - - - - - AFC - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - AFCRSRP db - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - DOPPLER1 - - - - - DOPPLER2 - - - - - 20AGC - - - 19AGC - - - - - bit[7:0]id8-id1 -0: -1 - - - - - ID1 - - - ID1 - - - ID1 - - - ID1 - - - ID1 - - - ID1 - - - ID1 - - - ID110 -bit[0]\offine -bit[1] -bit[2]AFC -bit[3]Agc_compare - - - - - bit[7:0]id8-id1 -0 -1 - - - - - ID13 - - - ID12 - - - ID11 - - - - - ID23 - - - ID22 - - - ID21 - - - - - ID33 - - - ID32 - - - ID31 - - - - - ID43 - - - ID42 - - - ID41 - - - - - ID53 - - - ID52 - - - ID51 - - - - - ID63 - - - ID62 - - - ID61 - - - - - ID73 - - - ID72 - - - ID71 - - - - - ID83 - - - ID82 - - - ID81 - - - - - ID3-8 RBIS CORRECT -0 -1 - - - ID3-8 RBIS JUDGE -0 -1 - - - ID3-8 RBIS -0 -1 - - - ID3-8 RBIS -0 -1 - - - ID3-8 RBIS -01 -12 -23 -34 -45 - - - ID3-8 RBIS - - - ID3-8 RBIS - - - - - ID24RBIPRB - - - ID23RBIPRB - - - ID22RBIPRB - - - ID21RBIPRB - - - - - ID2 RBIS JUDGE - - - ID25RBIPRB - - - - - ID2 RBIS - - - - - ID2 RBIS - - - - - ID3-84RBIPRB - - - ID3-83RBIPRB - - - ID3-82RBIPRB - - - ID3-81RBIPRB - - - - - ID3-8 RBIS JUDGE - - - ID3-85RBIPRB - - - - - ID3-8 RBIS - - - - - ID3-8 RBIS - - - - - 1ScaleTh - - - - - 2ScaleTh - - - - - 4ScaleTh - - - - - 8ScaleTh - - - - - 16ScaleTh - - - - - 32ScaleTh - - - - - 64ScaleTh - - - - - 128ScaleTh - - - - - 256ScaleTh - - - - - 512ScaleTh - - - - - ID3-8 SIGPWR - - - - - ID3-8 - - - id3-816q10 - - - - - ID3-816q15 - - - ID3-816q10 - - - - - id3-8beta16Q10 - - - ID3-8 - - - - - ID14RBIPRB - - - ID13RBIPRB - - - - - ID12RBIPRB - - - ID11RBIPRB - - - - - ID1 RBIS JUDGE - - - ID15RBIPRB - - - - - ID24RBIPRB - - - ID23RBIPRB - - - - - ID22RBIPRB - - - ID21RBIPRB - - - - - ID2 RBIS JUDGE - - - ID25RBIPRB - - - - - ID3-84RBIPRB - - - ID3-83RBIPRB - - - - - ID3-82RBIPRB - - - ID3-81RBIPRB - - - - - ID3-8 RBIS JUDGE - - - ID3-85RBIPRB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DMAIDDET -0: -1: - - - DMAMEM -0: -1: - - - 5ms+2OFDM -1~9856 - - - 4b000: 5ms+2OFDM -4b0001: 1 -4b1111: 15 - - - 0: -1: - - - 3b001: PSS -3b010: PSS -3b011: SSS -3b100: -3b101: -3b110: - - - bit type is changed from r/w to rw. - TXRXOFFSET -1:OFFSET -0:OFFSET - - - 1: TXRXDMA; -0: TXRXDMA - - - 1: IDDET -0: IDDET - - - 1: IDDET -0: IDDET - - - - - bit type is changed from r/w to rw. - RSSI - - - PSS.1~12512 - - - ,1~5 - - - 0: ICS;1: IDDET - - - 0: 0: - - - 0: ID2 1: ID20 2: ID21 3: ID22 - - - 0: 1: 1 -2: 3 3: 5 - - - 0: AGC 1: AGC - - - 0: 1: - - - - - bit type is changed from r/w to rw. - RSSI - - - 1~12 - - - 1: -0: - - - 1: -0: - - - 1: AGC -0: AGC - - - 1: -0: - - - - - bit type is changed from r/w to rw. - RSSI - - - bit type is changed from r/w to rw. -0: -1:1 -2:2 -3:4 - - - bit type is changed from r/w to rw. - 0: -1: - - - 1~10 - - - NID1ID 0~168 - - - ICSIDDET1~12 - - - 1: -0: - - - 0:ICS -1: ID DETECT - - - 1: ID 0: ID - - - 1: FDD 0: TDD - - - 1: -0: - - - 1: -0: - - - 1: AGC -0: AGC - - - 1: -0: - - - - - RSSI - - - 0: -1:1 -2:2 -3:4 - - - 1~12 - - - PSSSSSM0~4 - - - 1: FDD -0: TDD - - - 1: -0: - - - 1: -0: - - - 1: -0: - - - 1: AGC -0: AGC - - - 1: -0: - - - - - RSSI - - - 0:1ms -1:2ms -2:3ms -3:4ms -4:5ms - - - 00: 01: 0 10: 5 - - - 1~5 - - - ID1 0~167 - - - ID2 0~2 - - - 0: AGC -1: AGC - - - 0: -1: - - - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - RSSI -8~7 - - - - - 1: -0: - - - 1: 1 -0: 1 - - - 1:RSSI -0: RSSI - - - 1: -0: - - - 1: AXIDMA -0: AXIDMA - - - 1:TXRX -0: TXRX - - - 1: -0: - - - 1: -0: - - - 1:SSS -0: SSS - - - 1:PSS -0: PSS - - - 1:PSS -0: PSS - - - - - RSSI - - - PSSTXRX0PSSSSSTXRX -00~19200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 0~200 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - 1 - - - 0 - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - PSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - PSSID-32768~32767 - - - PSSID-32~31 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS)15 00 - - - SSS - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - NID1 0-167 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - ID 0~9599 - - - - - SSSMAX 10 - - - 0:31 1:61 2:127 - - - IDDET PSSASSIST_WINMAX_NUMPOS_NUMPOS_NUM - - - 2b00:2 2b01:4 2b10:8 others:2 - - - 0-127 - - - - - - Q3 - - - - - PSS2 -1024~1023 - - - PSS1 -1024~1023 - - - PSS0 -1024~1023 - - - - - PSS4 -1024~1023 - - - PSS3 -1024~1023 - - - - - PSS -4096~4095 - - - - - PSS -4096~4095 - - - - - PSS -4096~4095 - - - - - PSS -4096~4095 - - - - - RSSI - - - - - PSS -32~31 - - - PSS -32~31 - - - - - PSS -32~31 - - - PSS -32~31 - - - - - PSS -32~31 - - - PSS -32~31 - - - - - PSS -32~31 - - - PSS -32~31 - - - - - PSS -32~31 - - - PSS -32~31 - - - - - -8~7 - - - -8~7 - - - -8~7 - - - -8~7 - - - - - FFT/IFFT () -4`b0000 -4`b0001 -4`b0010 - - - FFT/IFFT PSS/SSS -4`b0000 -4`b0001 -4`b0010 - - - - - 1 -0 - - - - - - IDCP -1EXTEND CP 0NORMAL CP - - - ID(SSS) -15 00 - - - SSS - - - SSS - - - - - - - - SSS 9600 - - - 0 -11 -22 --11 --22 - - - - - 0 - - - - - SSS -00 -11 -1212 - - - PSSPSSSSS -00 -11 -1212 - - - - - PSSPSSSSS -0~200 - - - - - PSSRSSIPSSSSS -RSSI - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - SSS IDDET -0~11 - - - 0-8 - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - PSSPSSSSS - - - PSSPSSSSS - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - PSSPSSSSSID - - - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - - - - NID1 -0-167 - - - IDCP -1EXTEND CP -0NORMAL CP - - - ID(SSS) -15 -00 - - - NID2 -0-2 - - - - - bit type is changed from rw1c to rc. - 1: -0: - - - bit type is changed from rw1c to rc. - 1: -0: - - - bit type is changed from rw1c to rc. - 1:1 -0: - - - bit type is changed from rw1c to rc. - 1:RSSI -0: RSSI - - - bit type is changed from rw1c to rc. - 1: -0: - - - bit type is changed from rw1c to rc. - 1:AXIDMA -0: - - - bit type is changed from rw1c to rc. - 1:TXRX -0: - - - bit type is changed from rw1c to rc. - 1: -0: - - - bit type is changed from rw1c to rc. - 1: -0: - - - bit type is changed from rw1c to rc. - 1:SSS -0: - - - bit type is changed from rw1c to rc. - 1:PSS -0: - - - bit type is changed from rw1c to rc. - 1:PSS -0: - - - - - 1 -0 - - - 1 -0 - - - 1 -0 - - - 1 -0 - - - PSS -1 -0 - - - PSS -1 -0 - - - - - - - - - - 0~1023 - - - - - 0: -1: - - - FFT -0: FFT -1: FFT(1024),FFT - - - : -0: -1: , - - - 1~999 - - - 0~999 - - - 0: 5M -1: 10M -2: 20M -: 5M - - - 0: 5ms -1: 5ms - - - 0: 5ms -1: 5ms - - - - - ; -0:[19:0],20bit -1:[20:1],20bit -12:[31:12],20bit -:12; - - - ,;I^2+Q^2=PWR(32bit) -0:[31:15],16bit -1:[31:14],16bit -15:[31:0],16bit - - - 0~49 - - - 0~50 - - - 20MHz -0: -1: - - - 15MHz -0: -1: - - - 10MHz -0: -1: - - - 5MHz -0: -1: - - - 3MHz -0: -1: - - - 1.4MHz -0: -1: - - - 200KHz -0: -1: - - - ,1~11 - - - - - Selectbinnum0~511 - - - selectbinnum0~511 - - - - - 0~99 - - - 0~99 - - - 0~99 - - - 0~99 - - - - - 0~99 - - - 0~99 - - - 0~99 - - - - - 0~15 - - - 0~15 - - - 0~15 - - - 0~15 - - - 0~15 - - - 0~15 - - - 0~15 - - - - - - - 0~127 - - - - - - - - - - AGC - - - - - 2 - - - 1 - - - - - bit type is changed from r/w to rw. - PSSRSSI0~47990~9599 - - - bit type is changed from r/w to rw. - PSSRSSI0~47990~9599 - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - PSSRSSI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1PWR1 - - - 1PWR0 - - - - - - 1 - - - 1AGC - - - - - - - - - data_drive -0data_drive -1data_drive - - - DMACSI -0 -1 - - - CSI -0 -1 - - - - - cp -0 -1 - - - FH -5d0fh[11:0] -5d1fh[12:1] -5d2fh[13:2] -5d16fh[27:16] -othersfh[28:17] - - - CSI-RSCRS -0CSI-RS -1CRS - - - LS/FH/ -0LS/FH/ -1 - - - RIri_sel=1PMI -0RI=1 -1RI=2 - - - PMIRI -0RI -1RI - - - PMI -0PMI -1PMI - - - RI -0RI -1RI - - - RIRI -0RI=1 -1RI - - - 6/15/25/50/75/100PRB - - - total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB - - - CSI-RS1248CRS24 -01RIPMI -12 -24 -38 - - - - - ((1-th2)/(1+th2))^2RI01Q15th240 - - - ((1-th1)/(1+th1))^2RI01Q15th160 - - - - - RI=2248i1bitmapbit0~bit150~151 - - - RI=1248i1bitmapbit0~bit150~151 - - - - - RI=28i2bitmapbit0~bit150~151 - - - RI=18i2bitmapbit0~bit150~151 - - - - - - - - 0 -1 - - - - - OFDM0CCSI-RS - - - - - OFDM1CCSI-RS - - - - - bit type is changed from rw1c to rc. - - - bit type is changed from rw1c to rc. -0 -1 - - - - - sw_pause_en=1 -0 -1 - - - 0 -10 - - - 0 -1 - - - - - bit type is changed from rw1c to rc. -0 -1 - - - bit type is changed from rw1c to rc. -0 -1 - - - - - RIPRBRI -0RI=1 -1RI=2 - - - - - PMIPRBPMI - - - - - 1 - - - - - 2 - - - - - 1 - - - - - 2 - - - - - cp -0 -1 - - - FH -5d0fh[11:0] -5d1fh[12:1] -5d2fh[13:2] -5d16fh[27:16] -othersfh[28:17] - - - CSI-RSCRS -0CSI-RS -1CRS - - - LS/FH/ -0LS/FH/ -1 - - - RIri_sel=1PMI -0RI=1 -1RI=2 - - - PMIRI -0RI -1RI - - - PMI -0PMI -1PMI - - - RI -0RI -1RI - - - RIRI -0RI=1 -1RI - - - 6/15/25/50/75/100PRB - - - total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB - - - CSI-RS1248CRS24 -01RIPMI -12 -24 -38 - - - - - ((1-th2)/(1+th2))^2RI01Q15th240 - - - ((1-th1)/(1+th1))^2RI01Q15th160 - - - - - RI=2248i1bitmapbit0~bit150~151 - - - RI=1248i1bitmapbit0~bit150~151 - - - - - RI=28i2bitmapbit0~bit150~151 - - - RI=18i2bitmapbit0~bit150~151 - - - - - 0 -1 - - - - - OFDM0CCSI-RS - - - - - OFDM1CCSI-RS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0PUSCH -1PUSCH - - - 0 -1 - - - 0PUSCH -1PUSCH - - - 0 -1 - - - - - bit type is changed from rw1c to rc. - DCI -0 -1 - - - bit type is changed from rw1c to rc. - ULPC -0 -1 - - - - - - - - - - - - - - ID - - - - - DCI Format 0 -6PRB5bit -15PRB7bit -25PRB9bit -50PRB11bit -75PRB12bit -100PRB13bit -DCI Format 4 -6PRB6bit -15PRB7bit -25PRB10bit -50PRB12bit -75PRB13bit -100PRB14bit - - - PUSCH - - - - - - 0 -1 - - - 0 -1 - - - 00 -11 - - - 0TDD -1FDD - - - - - type0PRBtype1PRB - - - type0type0Type20type1PRB - - - type0PRBLen1type1PRB - - - type0type0Type21type1PRB - - - - - PUSCHPRB -type0PRBLen = Len1 = Len2 -type1PRBLen = Len1+Len2 - - - - - -6363 - - - - - - UE-3033dBm - - - 0000 -0010.4 -0100.5 -0110.6 -1000.7 -1010.8 -1100.9 -1111 - - - UE -0Ks0 -1Ks1.25 - - - 000PRACH -001PUSCH -010PUCCH -011PUSCHPUCCH -100SRS -101PUSCHSRS -110PUCCHSRS -111PUSCHPUCCHSRS - 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- - - - 0 -1 - - - - - bit type is changed from rw1c to rc. -0 -1 - - - - - - - - - 0~30720TS - - - - - -30720x13.8 ~30720x13.8TS - - - - - 0:catm -1:cat1 - - - 0:1.4M -1:3M -2:5M -:5M - - - PRSPRB100PRB200PRB0~199 - - - 0 -1 - - - 0512 -1256 - - - - - 0occasion -1occasion -[0]ID1 -[23]ID24 - - - - - ID -0ID -1ID -[0]ID1 -[23]ID24 - - - - - ID -0ID -1ID -[0]ID1 -[23]ID24 - - - - - eg1IQ - - - - - occasionAGC - - - - - occasionID10~120ID1SF_ID1 - - - occasionID210~9 - - - PRSID2ID 0~4095 - - - ID1 -012 -14 - - - ID1CP -0CP -1CP - - - - - ID1certain-8192x3x2 TS ~8192x3x2TS1 - - - ID1uncertain0 TS ~1024x3x2TS2 - - - - - occasionID20~120ID2SF_ID2 - - - occasionID210~9 - - - PRSID2ID 0~4095 - - - ID2 -012 -14 - - - ID2CP -0CP -1CP - - - - - ID2certain-8192x3x2 TS ~8192x3x2TS1 - - - ID2uncertain0 TS ~1024x3x2TS2 - - - - - occasionID30~120ID3SF_ID3 - - - occasionID310~9 - - - PRSID3ID 0~4095 - - - ID3 -012 -14 - - - ID3CP -0CP -1CP - - - - - ID3certain-8192x3x2 TS ~8192x3x2TS1 - - - ID3uncertain0 TS ~1024x3x2TS2 - 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- - - - occasionID90~120ID9SF_ID9 - - - occasionID910~9 - - - PRSID9ID 0~4095 - - - ID9 -012 -14 - - - ID9CP -0CP -1CP - - - - - ID9certain-8192x3x2 TS ~8192x3x2TS1 - - - ID9uncertain0 TS ~1024x3x2TS2 - - - - - occasionID100~120ID10SF_ID10 - - - occasionID1010~9 - - - PRSID10ID 0~4095 - - - ID10 -012 -14 - - - ID10CP -0CP -1CP - - - - - ID10certain-8192x3x2 TS ~8192x3x2TS1 - - - ID10uncertain0 TS ~1024x3x2TS2 - - - - - occasionID110~120ID11SF_ID11 - - - occasionID1110~9 - - - PRSID11ID 0~4095 - - - ID11 -012 -14 - - - ID11CP -0CP -1CP - - - - - ID11certain-8192x3x2 TS ~8192x3x2TS1 - - - ID11uncertain0 TS ~1024x3x2TS2 - - - - - occasionID120~120ID12SF_ID12 - - - occasionID1210~9 - - - PRSID12ID 0~4095 - - - ID12 -012 -14 - - - ID12CP -0CP -1CP - - - - - ID12certain-8192x3x2 TS ~8192x3x2TS1 - - - ID12uncertain0 TS ~1024x3x2TS2 - - - - - occasionID130~120ID13SF_ID13 - - - occasionID1310~9 - - - PRSID13ID 0~4095 - - - ID13 -012 -14 - - - ID13CP -0CP -1CP - - - - - ID13certain-8192x3x2 TS ~8192x3x2TS1 - - - ID13uncertain0 TS ~1024x3x2TS2 - - - - - occasionID140~120ID14SF_ID14 - - - occasionID1410~9 - - - PRSID14ID 0~4095 - - - ID14 -012 -14 - - - ID14CP -0CP -1CP - - - - - ID14certain-8192x3x2 TS ~8192x3x2TS1 - - - ID14uncertain0 TS ~1024x3x2TS2 - - - - - occasionID150~120ID15SF_ID15 - - - occasionID1510~9 - - - PRSID15ID 0~4095 - - - ID15 -012 -14 - - - ID15CP -0CP -1CP - - - - - ID15certain-8192x3x2 TS ~8192x3x2TS1 - - - ID15uncertain0 TS ~1024x3x2TS2 - - - - - occasionID160~120ID16SF_ID16 - - - occasionID1610~9 - - - PRSID16ID 0~4095 - - - ID16 -012 -14 - - - ID16CP -0CP -1CP - - - - - ID16certain-8192x3x2 TS ~8192x3x2TS1 - - - ID16uncertain0 TS ~1024x3x2TS2 - - - - - occasionID170~120ID17SF_ID17 - - - occasionID1710~9 - - - PRSID17ID 0~4095 - - - ID17 -012 -14 - - - ID17CP -0CP -1CP - - - - - ID17certain-8192x3x2 TS ~8192x3x2TS1 - - - ID17uncertain0 TS ~1024x3x2TS2 - - - - - occasionID180~120ID18SF_ID18 - - - occasionID1810~9 - - - PRSID18ID 0~4095 - - - ID18 -012 -14 - - - ID18CP -0CP -1CP - - - - - ID18certain-8192x3x2 TS ~8192x3x2TS1 - - - ID18uncertain0 TS ~1024x3x2TS2 - - - - - occasionID190~120ID19SF_ID19 - - - occasionID1910~9 - - - PRSID19ID 0~4095 - - - ID19 -012 -14 - - - ID19CP -0CP -1CP - - - - - ID19certain-8192x3x2 TS ~8192x3x2TS1 - - - ID19uncertain0 TS ~1024x3x2TS2 - - - - - occasionID200~120ID20SF_ID20 - - - occasionID2010~9 - - - PRSID20ID 0~4095 - - - ID20 -012 -14 - - - ID20CP -0CP -1CP - - - - - ID20certain-8192x3x2 TS ~8192x3x2TS1 - - - ID20uncertain0 TS ~1024x3x2TS2 - - - - - occasionID210~120ID21SF_ID21 - - - occasionID2110~9 - - - PRSID21ID 0~4095 - - - ID21 -012 -14 - - - ID21CP -0CP -1CP - - - - - ID21certain-8192x3x2 TS ~8192x3x2TS1 - - - ID21uncertain0 TS ~1024x3x2TS2 - - - - - occasionID220~120ID22SF_ID22 - - - occasionID2210~9 - - - PRSID22ID 0~4095 - - - ID22 -012 -14 - - - ID22CP -0CP -1CP - - - - - ID22certain-8192x3x2 TS ~8192x3x2TS1 - - - ID22uncertain0 TS ~1024x3x2TS2 - - - - - occasionID230~120ID23SF_ID23 - - - occasionID2310~9 - - - PRSID23ID 0~4095 - - - ID23 -012 -14 - - - ID23CP -0CP -1CP - - - - - ID23certain-8192x3x2 TS ~8192x3x2TS1 - - - ID23uncertain0 TS ~1024x3x2TS2 - - - - - occasionID240~120ID24SF_ID24 - - - occasionID2410~9 - - - PRSID24ID 0~4095 - - - ID24 -012 -14 - - - ID24CP -0CP -1CP - - - - - ID24certain-8192x3x2 TS ~8192x3x2TS1 - - - ID24uncertain0 TS ~1024x3x2TS2 - - - - - FFT9 - - - FFT8 - - - FFT7 - - - FFT6 - - - FFT5 - - - FFT4 - - - FFT3 - - - FFT2 - - - FFT1 -2b00:bit[29:14] -2b01:bit[30:15] -2b10:bit[31:16] -2b11:bit[32:17] - - - - - IFFT8 - - - IFFT7 - - - IFFT6 - - - IFFT5 - - - IFFT4 - - - IFFT3 - - - IFFT2 - - - FFT -2b00:bit[29:14] -2b01:bit[30:15] -2b10:bit[31:16] -2b11:bit[32:17] - - - - - 0phasemax,2 -1phasephasemax,2 - - - 0~31,3 - - - IFFT7 - - - IFFT6 - - - IFFT5 - - - IFFT4 - - - IFFT3 - - - IFFT2 - - - FFT -2b00:bit[29:14] -2b01:bit[30:15] -2b10:bit[31:16] -2b11:bit[32:17] - - - - - 0~32x2,2/3 - - - 0~32x2,2/3 - - - 0~32x2,1 - - - 0~32x2,1 - - - - - 0: -1: - - - - - 0: OTDOA/ -1: OTDOA - - - - - bit type is changed from rw1c to rc. - 1: -0: - - - - - Bit[n]: -0: -1: -Bit01 -Bit78 - - - - - - - - - - axidma - - - OTDOA - - - - - - Ts - - - AD_ON16Ts - - - - - 16Ts - - - - - IRT/AFCPDPPWR/RSSI MAX:20 - - - IRT/AFC -20bitbit -0 -1 - - - - - IRTPHASE - - - IRTPHASE16Ts - - - IRT(-256~25516TsOFFSET) - - - - - AFC-4096~2095TsOFFSET - - - - - xAGC - - - - - 2AGC - - - 1AGC - - - 0AGC - - - - - 5AGC - - - 4AGC - - - 3AGC - - - - - 8AGC - - - 7AGC - - - 6AGC - - - - - 11AGC - - - 10AGC - - - 9AGC - - - - - 14AGC - - - 13AGC - - - 12AGC - - - - - 17AGC - - - 16AGC - - - 15AGC - - - - - 19AGC - - - 18AGC - - - - - 0: 0 -1FDD90TDD05 - - - 5 -05 -15 - - - 40MS - - - schedulingInfoSIB1-BR-r13 - - - phich-Config: PHICH resource - - - phich-Config: PHICH duration - - - dl-Bandwidth - - - - - PORT -0: 2PORT0PORT14PORT0PORT1PORT2PORT3 -1: PORT0 -2: PORT1 - - - 0:1 -1:2 -2:4 - - - ID0~504 - - - PBCH -0: -1: - - - CP -0: NORMAL CP -1: EXTEND CP - - - FDD/TDD -0: TDD -1: FDD - - - AFC -0: 1 -1: 2 -2: 4 - - - IRT -0: 1 -1: 2 -2: 4 - - - - - IRT -0 -1SCALE - - - IRT0~31 - - - IRTSCALE -0 -1 - - - IRT0~63 - - - AFCOFDM -0:1 -1:2 -2:3 -3:4 - - - AFC -0: 1RE -1: 1PRB -2: 2PRB -3: 3PRB -4: 6PRB - - - - - - - - - - - - - 0 -1 - - - - - AFC -0FIRST -1FIRST - - - IRT -0FIRST -1FIRST - - - AFC -0 -1 - - - IRT -0 -1 - - - 0 -1 - - - PBMEAS -0 -1 - - - - - IRT_OUTTs - - - - - SINR - - - - - SINRDB - - - - - POWER - - - - - POWER - - - - - AFC_OUTHz - - - - - SIGMA - - - - - POWER - - - - - SINR - - - - - SINRDB - - - - - RSSI(DBQ4) - - - - - RSSI(DBQ4) - - - - - RSSI(DBQ4) - - - - - AGC_OUT(DBQ0) - - - - - AFCAFC - - - - - AFCAFC - - - - - AFCAFC - - - - - AFCAFC - - - - - bit type is changed from rw1c to rc. - MEM - - - bit type is changed from rw1c to rc. - MEM - - - bit type is changed from rw1c to rc. - 1: AFC -0: - - - bit type is changed from rw1c to rc. - 1: IRT -0: - - - bit type is changed from rw1c to rc. - 1:REC -0: - - - - - AFC RSRP -16Q4 - - - IRT RSRP -16Q4 - - - - - AFC RSRQ -16Q4RSRPRSSI - - - AFC RSSI -16Q4 - - - - - PBMEAS - - - - - MEM - - - ADDR - - - - - - - - - - - - - - - IRT - - - - - IRT - - - - - IRTPHASE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 -1 - - - - - Dump -1 -0 - - - Tx Trace -1 -0 - - - IDDET offline -1 -0 - - - ODTOA -1 -0 - - - RX -1 -0 - - - - - - - - DL offline -1 -0 - - - 3h0:420M/15M -3h1:810M -3h2:165M -3h3:323M -3h4:641.4M -Others: 4 - - - - - - - - IDDET offline -1 -0 - - - 3h0:420M/15M -3h1:810M -3h2:165M -3h3:323M -3h4:641.4M -Others: 4 - - - - - DMA_req7 -1 -0 - - - DMA_req6 -1 -0 - - - DMA_req5 -1 -0 - - - DMA_req4 -1 -0 - - - DMA_req3 -1 -0 - - - DMA_req2 -1 -0 - - - DMA_req1 -1 -0 - - - DMA_req0 -1 -0 - - - - - Capt_err34 -1 -0 - - - Capt_err12 -1 -0 - - - Mem56 finish -1 -0 - - - Mem56 pang -1 -0 - - - Mem56 ping -1 -0 - - - Mem34 finish -1 -0 - - - Mem34 pang -1 -0 - - - Mem34 ping -1 -0 - - - Mem12 finish -1 -0 - - - Mem12 pang -1 -0 - - - Mem12 ping -1 -0 - - - - - bit type is changed from rw1s to rs. - Capt_err34 -1 -0 - - - bit type is changed from rw1s to rs. - Capt_err12 -1 -0 - - - bit type is changed from rw1s to rs. - Mem56 finish -1 -0 - - - bit type is changed from rw1s to rs. - Mem56 pang -1 -0 - - - bit type is changed from rw1s to rs. - Mem56 ping -1 -0 - - - bit type is changed from rw1s to rs. - Mem34 finish -1 -0 - - - bit type is changed from rw1s to rs. - Mem34 pang -1 -0 - - - bit type is changed from rw1s to rs. - Mem34 ping -1 -0 - - - bit type is changed from rw1s to rs. - Mem12 finish -1 -0 - - - bit type is changed from rw1s to rs. - Mem12 pang -1 -0 - - - bit type is changed from rw1s to rs. - Mem12 ping -1 -0 - - - - - bit type is changed from rw1c to rc. - Capt_err34 -1 -0 - - - bit type is changed from rw1c to rc. - Capt_err12 -1 -0 - - - bit type is changed from rw1c to rc. - Mem56 finish -1 -0 - - - bit type is changed from rw1c to rc. - Mem56 pang -1 -0 - - - bit type is changed from rw1c to rc. - Mem56 ping -1 -0 - - - bit type is changed from rw1c to rc. - Mem34 finish -1 -0 - - - bit type is changed from rw1c to rc. - Mem34 pang -1 -0 - - - bit type is changed from rw1c to rc. - Mem34 ping -1 -0 - - - bit type is changed from rw1c to rc. - Mem12 finish -1 -0 - - - bit type is changed from rw1c to rc. - Mem12 pang -1 -0 - - - bit type is changed from rw1c to rc. - Mem12 ping -1 -0 - - - - - bit type is changed from rw1c to rc. - Capt_err34 - - - bit type is changed from rw1c to rc. - Capt_err12 - - - bit type is changed from rw1c to rc. - Mem56 finish - - - bit type is changed from rw1c to rc. - Mem56 pang - - - bit type is changed from rw1c to rc. - Mem56 ping - - - bit type is changed from rw1c to rc. - Mem34 finish - - - bit type is changed from rw1c to rc. - Mem34 pang - - - bit type is changed from rw1c to rc. - Mem34 ping - - - bit type is changed from rw1c to rc. - Mem12 finish - - - bit type is changed from rw1c to rc. - Mem12 pang - - - bit type is changed from rw1c to rc. - Mem12 ping - - - - - Mem12 - - - - - Mem34 - - - - - Mem12 - - - - - Mem56 - - - - - - - - - - Mem12 pang -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem12 pang - - - Mem12 ping -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem12 ping - - - - - Mem34 pang -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem34 pang - - - Mem34 ping -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem34 ping - - - - - Mem56 pang -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem56 pang - - - Mem56 ping -000IDLE -001MEM -010MEM -011DMA -100MEM -Others: IDLE - - - Mem56 ping - - - - - Err -0MEM12 Ping -1MEM12 Pang - - - Error(ERR - - - - - Err -0MEM34 Ping -1MEM34 Pang - - - Error(ERR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BB2G Ram Space -
- This RAM is used in 2G mode as ACC buffer and code space. -
- In NB mode, it can also be used as TCM memory space. - - - - - - - - - - This field is used for setting the first polynomial to encode - or the CRC computation -
- First polynomial to encode : -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) -
- Cyclic code : -
- 000 = D8 + D4 + D3 + D2 + 1 -
- 001 = D3 + D + 1 -
- 010 = D14 + D13 + D5 + D3 + D2 +1 -
- 011 = D6 + D5 + D3 + D2 + D1 + 1 -
- 100 = D10 + D8 + D6 + D5 + D4 + D2 + 1 -
- 101 = D16 + D12 + D5 + 1 -
- 110 = (D23 + 1)*(D17 + D3 + 1) -
- 111 = reserved - - - - - Second polynomial to encode : -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) - - - - - Third polynomial to encode: -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) - - - - - Fourth polynomial to encode: -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) - - - - - Fith polynomial to encode: -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) - - - - - Sixth polynomial to encode: -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No polynomial code used (input connected to output) - - - - - RSC (Recursive Systematic Convolutional) polynomial code: -
- 000 = G0 -
- 001 = G1 -
- 010 = G2 -
- 011 = G3 -
- 100 = G4 -
- 101 = G5 -
- 110 = G6 -
- 111 = No RSC - - - - - Number of polynomial code to process: -
- 0x0 = 0 -
- 0x1 = 1 (First Poly) -
- 0x2 = 2 (First poly and second Poly) -
- 0x3 = 3 (First poly, second poly, third Poly) -
- 0x6 = 6 (first Poly to sixth Poly) -
- 0x7 = reserved - - - - - Enable Puncturing -
- 0 = No puncturing (puncturing disabled) -
- 1 = Enable puncturing - - - - - - - Number of inputs bits to process -
- 0x01 = 1 -
- 0x02 = 2 -
- 0x03 = 3 -
- ... -
- 0xFD = 253 -
- 0xFE = 254 -
- 0xFF = 255 -
- 0x100 = 256 -
- ... -
- 0x1BF = 447 -
- 0x1C0 = 448 - - - - - - When 1 the bb_cp2 is running - - - - - - LRAM address for the next access -
- Automatically incremented after each access - - - - - Select LRAM for the next access -
- 0 = Puncturing LRAM -
- 1 = Data LRAM - - - - - - CRC code LSB bits - - - - - CRC code MSB bits - - - - - - - CP2 register access selection bit -
- 0= All registers are only accessible through the APB bus -
- 1= All registers are only accessible by the BCPU through the CP2 bus - - - - - - - LRAM Data. This register is used for access to the - puncturing LRAM or to the Data LRAM. -
- All access into this register, increment the LRAM_ADDR register. - - - - - -// changing xml generated defines -#undef BB_CP2_ENABLE_PUNCTURING -#undef BB_CP2_LRAM_DATA -#undef BB_CP2_BIT_NUMBER -#define BB_CP2_ENABLE_PUNCTURING(n) (((n)&1)<<24) -/// BB_CP2 address mapping -#define BB_CP2_CTRL 0 -#define BB_CP2_BIT_NUMBER 1 -#define BB_CP2_STATUS 2 -#define BB_CP2_LRAM_ADDR 3 -#define BB_CP2_CRC_CODE_LSB 4 -#define BB_CP2_CRC_CODE_MSB 5 -#define BB_CP2_LRAM_DATA 0 -#define BB_CP2_LRAM_PUNC (0<<5) -#define BB_CP2_DATA_LRAM (1<<5) -/* BB_CP2 ACCESSES */ -// macro for converting a constant to a string -#define CT_CONVERT_TO_STRING(x) #x -// control register -> GPR -#define CT_BB_CP2_RD_CTRL_REG(regaddr, n) asm volatile("cfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n))) -// GPR -> control register -#define CT_BB_CP2_WR_CTRL_REG(regaddr, n) asm volatile("ctc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n))) -// general register -> GPR -#define CT_BB_CP2_RD_GNRL_REG_GPR(regaddr, n) asm volatile("mfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n))) -// GPR -> general register -#define CT_BB_CP2_WR_GNRL_REG_GPR(regaddr, n) asm volatile("mtc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n))) -// general register -> memory -#define CT_BB_CP2_RD_GNRL_REG_MEM(regaddr, out) asm volatile("swc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((out))) -// memory -> general register -#define CT_BB_CP2_WR_GNRL_REG_MEM(regaddr, in) asm volatile("lwc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((in))) - - - - - - - - BCPU Irq Lines - - - - - - - - If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU. -
- The cause for the Irq sources, one bit for each module's irq source. -
- The cause is the actual Irq source masked by the mask register. - - - - - - The status for the level Irq sources, one bit for each module's irq source. -
- The status reflect the actual Irq source. - - - - - - Writing '1' sets the corresponding bit in the mask register to '1'. -
- Reading gives the value of the mask register. - - - - - - Writing '1' clears the corresponding bit in the mask register to '0'. -
- Reading gives the value of the mask register. - - - - - - - This is the Main Irq source it drive the system CPU interrupt line 0. -
- This bit comes from the modules irq and is masked by the Mask and SC registers. - - - - - This is the WDT Irq source it drive the system CPU interrupt line 1. -
- This bit comes from watchdog module. - - - - This is the debug Irq source, the value written here drives the system CPU interrupt line 4. - - - - This is the Host Irq source it drive the system CPU interrupt line 5. -
- This bit is controlled by the host internal register. - - - - Status of the Interrupt enable semaphore bit. - - - - - - Interrupt enable semaphore, used for critical section. -
- Read returns its value and then clears it to '0' disabling interrupts. -
- Write the read value to restore the previous state, this will exit the critical section. - - - - - Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section) - - - - - Writing '1' to this bit will put the BCPU to sleep (i.e.: Disable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section) - - - - - Writing '1' sets the corresponding bit in the mask register to '1'. -
- Reading gives the value of the mask register. - - - - - - Writing '1' clears the corresponding bit in the mask register to '0'. -
- Reading gives the value of the mask register. - - - - - - Writing '1' clears the corresponding Pulse IRQ. -
- Pulse IRQ are set by the modules and cleared here. - - - - - - The status for the Pulse Irq sources, one bit for each module's irq source. -
- The status reflect the actual Irq source. - - - - - - - - - - - - - BB Rom Space -
- This rom is used for BCPU. - - - - - - - Base address of block in int_Rom patched (corresponding data are read from int_SRam) - - - - - - - - - - - - - - - BB Rom patch Ram Space -
- Used for store the patch instead of rom, when patch is valid - - - - - - - - - write 1 will enable CHOLK module - - - 1:level INT will be masked, 0:level INT will not be masked - - - 1: Complex mode ; 0: Real mode - - - - - RESI GAIN - - - RESI2 GAIN - - - OGRS_GAIN - - - OLES1_GAIN - - - OLES2_GAIN - - - COEF_GAIN - - - GRAD_GAIN - - - GOPS_GAIN - - - OLES3_GAIN - - - - - ITER_THRE1 - - - - - Matrix COVA base addr in BBSRAM - - - - - CE base addr in BBSRAM - - - - - COEF base addr in BBSRAM - - - - - Matrix Row Number, maximal is 24 for Real, and 16 for Complex - - - Matrix COVA effective element number - 1 to read - - - MAXIMAL iteration number - 1 for CHOLK - - - - - CHOLK Done status, ACC enable and SW write this bit will clear this Done status, hardware will set this bit when done. - - - - - write 0 to this bit will clear CHOLK level RAW interrupt source bit, write 1 will not. read this bit will get raw cholk INT source bit - - - read this bit will get cholk INT status after masking. INT_out = INT_RAW and ~MASK - - - - - - - - - Writing a '1' in this register triggers an A5 process. Ignored if the module is - already processing. Auto-reset bit - - - Selects the appropriate algorithm - - - - - - - 1 when running, 0 in other case. - - - 1 when data block ready (Ciphering processed), reseted when the data register is read. - - - - - Cipher key Kc, LSB bit [31:0]. - - - - - Cipher key Kc, MSB bit [31:0]. - - - - - Count register, this field represent the TDMA frame number. - - - - - Data block2 bit[31:0] - - - - - Data block2 bit[63:32] - - - - - Data block2 bit[95:64] - - - - - Data block2 bit[113:96] - - - - - - - - - - - - - - - - - - - - - - - - - - - Select Between A5/1-A5/2 and A5/3 Ciphering Block - - - Initialize A5/3 Ciphering - - - Select Ciphering Blcok Size - - - Switch Between A5/1 and A5/2 Algorithm if A5/1-A5/2 Block is Selected - - - Status and Activation of Ciphering Block - - - - - Cipher Key0 - - - - - Cipher Key1 - - - - - Cipher Key2 - - - - - Cipher Key3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Cipher Key4 - - - - - Cipher Key5 - - - - - Cipher Key6 - - - - - Cipher Key7 - - - - - GSM mode:00001111 - EDGE mode:11110000 - - - CB=0000 - - - CD=0 - - - - - - - - CE=0000000000000000 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cipher_a53 internal Spram space - - - - - - - - Control setting. y, i.e. numerator of atan computation. - - - - - Control setting. x, i.e. denominator of atan computation. - - - - - The start signal. Use the posedge of this signal. - - - - - - - Status is set to 1 when an operation is finished. - - - - - - - . angle. The actual value is angle*pi/4 - - - amplitude. - - - - - amplitude only. - - - - - - - - - - - - - - - - - - - - - - - - - - - Control setting. comand type. - - - Control setting. Number of internal loop iteration. - - - Control setting. Number of nb_symbol. - - - Control setting. Number of shift bits. - - - - - address register 0. - - - - - address register 1. - - - - - address register 2. - - - - - address register 3. - - - - - address register 4. - - - - - address register 5. - - - - - data register 0. - - - - - data register 1. - - - - - data register 2. - - - - - data register 3. - - - - - for ircombine idx0 - - - for ircombine idx1 - - - for ircombine idx2 - - - - - data register 5. - - - - - Status is set to 1 when an operation is finished. - - - - - Control setting. Number of A row. - - - Control setting. Number of B column. - - - Control setting. Number of A column and B row. - - - Control setting. Number of shift bit after multiply. - - - - - - - - - - Number of bits to be (De)Interleaved. - - - This value gives the write offset (in number of bursts) to be - added to a Burst Base address (ignored for Type 1b). For normal - operation, this offset should be even (lsb will be ignored). - - - Selects (de-)interleaving type. - - - - - - - - - - - - - - Sets the interrupt mask ('1': interruption enabled) - - - Starts the de-interleaving process. - - - Starts the interleaving process. - - - - - This bit is high when a (de-)interleaving process is ongoing. It - stays high if the module is stalled during operation. - - - - - This is the start address of the burst buffer in SRAM - - - - - This is the start address of the frame buffer in - SRAM. - - - - - This bit is the unmasked version of the IT_CAUSE bit. - - - This bit is set when the ITLV module finishes an ongoing - operation. It can be masked by setting ITLV_CMD(IT_MASK) to '1'. - Resetting this bit is done by writing in IT_CLEAR register. IT_CAUSE is - the image of the ITLV_DONE_H interrupt line to the CPU. - - - - - Setting this bit to '1' resets the Interleaver's - interrupt. - - - - - - - - - - In read mode this register contains the sample received on the Rx chain. I component is located on bit[15:0] and Q component is located on bit[31:16]. -
- This register accesses to the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data sample arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. -
- The data written[29:0] into this register is the data transmitted. Any attempt to write data when the FIFO is full results in the write data being lost. - - - - - - - - Turn on/off the rf_if interface - - - - - - - Turn on/off the DigRF mode - - - - - - - Rx Fifo Overflow interrupt Enable - - - - - Calibration bypass - - - - - - - Rx swap I/Q - - - - - - - Force Rx On. This bit is used only with the analog option. - - - - - - - Force Decimator On - - - - Force start of calibation in receive mode -
- Writing a 1 to this bit launch the calibration phase. Write only bit, this bit doesn't need to be cleared. - - - - - Writing a 1 to this bit resets and flush the receive Fifo. -
- Write only bit, this bit doesn't need to be cleared. - - - - - - - - Tx Fifo Overflow interrupt Enable - - - - - - - Tx Fifo Underflow interrupt Enable: - - - - - - - Force DAC On. This bit is used only with the analog option. - - - - - - - Force DAC Off. This bit is used only with the analog option. - - - - - - - Force Tx Oen. This bit is used only with the analog option. - - - - - - - Force GMSK On. - - - - - - - Tx swap I/Q. This bit is used only with the analog option. - - - - Writing a 1 to this bit resets and flush the transmit Fifo. -
- Write only bit, this bit doesn.t need to be cleared. - - - - - - - - Rx rate for DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) - - - - Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled) -
- 0 = No inversion -
- 1 = Invert clock polarity - - - - - - Tx mode for the DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) - - - - Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled) -
- 0 = No inversion -
- 1 = Invert clock polarity - - - - - Shift input sample in DigRF mode only. -
- The Rx sample are on 16-bit, this field select a variable of bit among 16. -
- 000 = 16-bit selected -
- 001 = 15-bit selected -
- 010 = 14-bit selected -
- 011 = 13-bit selected -
- 100 = 12-bit selected - - - - - Select the sample alignement in DigRF mode only.. -
- 0 = MSB aligned sample -
- 1 = LSB aligned sample - - - - - - Those bits indicate the number of data available in the Rx Fifo. - - - Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. - - - - Rx overflow cause register -
- This bit indicates that an interruption was generated when the Rx fifo is overflow. -
- This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. - - - - - Tx overflow cause register -
- This bit indicates that an interruption was generated when the Tx fifo is overflow. -
- This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. - - - - - Tx underflow cause register -
- This bit indicates that an interruption was generated when the Tx fifo is underflow. -
- This bit is cleared when the Tx_underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. - - - - - This bit indicates that the receiver received a new sample when the FIFO was already full. -
- The new sample is discarded. This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written - - - - - This bit indicates that the user tried to write on the FIFO while it was already full. -
- This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written - - - - - This bit indicates that the modulator tried to read on the FIFO while it was empty. -
- This bit is cleared when the Tx_Underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written - - - - - - Clear Rx Interrupt Overflow interrupt. - - - Clear Tx Interrupt Overflow interrupt. - - - Clear Tx Interrupt Underflow interrupt. - - - - - Number of symbol to transmit - - - 0 for GMSK, 1 for 8PSK - - - Indicate an end of the transmit for this current burst - - - - - Rx offset measured after calibration for I channel - - - Rx offset measured after calibratio for Q channel - - - - - Rx Gain digital - - - Rx Gain analog - - - Rx Gain enable - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and current - APB transfer (if one in progress) is completed and the channel is then - disabled. - - - - - Burst size on AHB bus -
- 0 = Single access -
- 1 = burst Access (4 words). - - - - - Set FIFO mode . -
- 0 = no fifo mode, transfer stop when the - current transfer counter reaches zero. Channel must be re-enabled for - future transfer. -
- 1 = Fifo mode, when the current AHB address - counter reaches the end address of the FIFO. AHB address counter is - reloaded with the initial value. In FIFO mode channel is not disabled at - the end of the transfer. - - - - - - - - In no fifo mode the channel is automatically disabled at the - end of the transfer. In fifo mode the channel is disabled only when - disabled write is performed in the control register. - - - When 1 the fifo is empty - - - Cause interrupt half tc when fifo mode is enable. - - - Half of TC interrupt when fifo mode is enable status bit. - - - Cause interrupt End of TC. - - - Cause interrupt End of FIFO. - - - Cause interrupt Half Transfer Count (This interruption is - generated when the IFC has transferred 96 word). - - - End of TC interrupt status bit. - - - End of FIFO interrupt status bit. - - - Half TC interrupt status bit. - - - Current value of transfer counter. - - - - - AHB Start Address. - - - - - The last page address of the FIFO, it is the first address not - used for the FIFO. The start address of the FIFO is specified by the - register AHB_ADDR and the last page address of the FIFO is specified by - this field. The size of the fifo (END_ADDR - START_ADDR) must be a - multiple of burst of 4x32-bits. - - - - - - Transfer Count -
- In no FIFO mode, this bit indicated - the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per - transfer. -
- In FIFO mode this field define, after how many - transfer an interrupt in generated. - - - - - - End TC Mask interrupt. When one this interrupt is - enabled. - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - Half TC Mask interrupt. When one this interrupt is - enabled - - - NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is - enabled - - - - - Write one to clear end of TC interrupt. - - - Write one to clear end of FIFO interrupt. - - - Write one to clear end of Half TC interrupt. - - - Write one to clear end of Half TC (the real one) interrupt. - - - - - Current AHB address value. - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and current - APB transfer (if one in progress) is completed and the channel is then - disabled. - - - - - Burst size on AHB bus -
- 0 = Single access -
- 1 = burst Access (4 words). - - - - - Set FIFO mode . -
- 0 = no fifo mode, transfer stop when the - current transfer counter reaches zero. Channel must be re-enabled for - future transfer. -
- 1 = Fifo mode, when the current AHB address - counter reaches the end address of the FIFO. AHB address counter is - reloaded with the initial value. In FIFO mode channel is not disabled at - the end of the transfer. - - - - - - - - In no fifo mode the channel is automatically disabled at the - end of the transfer. In fifo mode the channel is disabled only when - disabled write is performed in the control register. - - - When 1 the fifo is empty - - - Cause interrupt half tc when fifo mode is enable. - - - Half of TC interrupt when fifo mode is enable status bit. - - - Cause interrupt End of TC. - - - Cause interrupt End of FIFO. - - - Cause interrupt Half Transfer Count (This interruption is - generated when the IFC has transferred 96 word). - - - End of TC interrupt status bit. - - - End of FIFO interrupt status bit. - - - Half TC interrupt status bit. - - - Current value of transfer counter. - - - - - AHB Start Address. - - - - - The last page address of the FIFO, it is the first address not - used for the FIFO. The start address of the FIFO is specified by the - register AHB_ADDR and the last page address of the FIFO is specified by - this field. The size of the fifo (END_ADDR - START_ADDR) must be a - multiple of burst of 4x32-bits. - - - - - - Transfer Count -
- In no FIFO mode, this bit indicated - the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per - transfer. -
- In FIFO mode this field define, after how many - transfer an interrupt in generated. - - - - - - End TC Mask interrupt. When one this interrupt is - enabled. - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - Half TC Mask interrupt. When one this interrupt is - enabled - - - NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is - enabled - - - - - Write one to clear end of TC interrupt. - - - Write one to clear end of FIFO interrupt. - - - Write one to clear end of Half TC interrupt. - - - Write one to clear end of Half TC (the real one) interrupt. - - - - - Current AHB address value. - - - - - dump the 'data from dfe to nb core' to mem - - - when the bit is 1, dump only when nb-core comes an pulse ,capture the set data numbers ,then stop - when the bit is 0, dump all bit normal dump mode - - - when the bit is 1, downsample enable - when the bit is 0, disable - - - get data from mem, simu the data format from dfe to nb core - - - get data from mem, simu the data format from nbcore to dfe - - - feed data rate 1.92MHz=0x20 192KHz=0x140, 96KHz=0x280, 38.4KHz=0x640, 32KHz=0x780 - - - fifo empty siganl - - - fifo empty signal - - - clr feed fifo point - - - clr dump fifo point - - - when the bit is 1, nb use the rf_dma - when the bit is 0, 2g use the rf_dma - - - - - the bandwidth select signal - - - bypass the filter function to the data - - - combine a unused data with I0 used as I0Q0, combine Q0I1 , used as I1Q1. - next goes on. the last Qn will be discarded. - - - set the delay of fclk_fordata to delay the rbdp_tx data - - - set the delay of fclk external, only for the clk_phy gen fclk - - - 1'b0 the source is fclk gen by clk_phy, 1'b1 the source is mclk - - - - - - dump_ovfl irq - - - dump_udfl irq - - - feed_ovfl irq - - - feed_udfl irq - - - dump_ovfl when ifc is still working irq - - - dump_udfl when ifc is still working irq - - - - - dump_ovfl mask - - - dump_udfl mask - - - feed_ovfl mask - - - feed_udfl mask - - - dump_ovfl when ifc is still working mask - - - dump_udfl when ifc is still working mask - - - - - dump_ovfl before mask irq source - - - dump_udfl before mask irq source - - - feed_ovfl before mask irq source - - - feed_udfl before mask irq source - - - dump_ovfl when ifc is still working irq source - - - dump_udfl when ifc is still working irq source - - - - - dump_ovfl clr irq - - - dump_udfl clr irq - - - feed_ovfl clr irq - - - feed_udfl clr irq - - - dump_ovfl when ifc is still working clr irq - - - dump_udfl when ifc is still working clr irq - - - - - - - - - - - - - - - - - - - - Enable the rf spi -
- 1 = Enable -
- 0 = Disable (will finish current command anyway) - - - - - Chip select polarity -
- 1 = the chip select is active low -
- 0 = the chip select is active high - - - - - DigRF Read style mode -
- 1 = DigRF Read style mode (read after CS disabled) -
- 0 = SPI Read mode (read during write) - - - - - DigRF style clocked back to back mode -
- 1 = clocked back to back transfers using turnarround timing only when more data are present in the FIFO. -
- 0 = stop the clock between each access according to CS_End_Hold and CS_Pulse_Min timings - - - - - Input mode -
- 1 = Record input data to input FIFO -
- 0 = No input data - - - - - SPI Clock polarity -
- 1 = the clock disabled level is high, and the first edge is a falling edge. -
- 0 = the clock disabled level is low, and the first edge is a rising edge. - - - - - Transfer start to first edge delay -
- value from 0 to 2 is the number of spi clock half period between the Transfer start and the first clock edge. - - - - - Transfer start to first data out delay -
- value from 0 to 2 is the number of spi clock half period between the Transfer start and the first data out. - - - - - Transfer start to first data in sampled delay -
- value from 0 to 3 is the number of spi clock half period between the Transfer start and the first data sampled in. -
- The DI_Delay only specify the sampling time, for frame size, the counter is based on the DO_Delay even in DigRF read mode. - - - - - Transfer start to CS activation delay -
- value from 0 to 3 is the number of spi clock half period between the Transfer start and the CS activation edge. - - - - - Transfer end to chip select deactivation delay -
- value from 0 to 3 is the number of spi clock half period between the end of transfer (DO) and the CS deactivation edge. -
- Not used for Clocked_Back2Back mode - - - - - Number of data in the frame, or number of out data in DigRF read mode. -
- The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits) -
- The frame size is given for the number of data, the actual number of clock pulses might be greater. First if Clock_Delay < DO_Delay an extra clock pulse is generated, second in case of DigRF read or back2back, some more clock pulses will be generated. - - - - - - - - - - Chip select deactivation to new start of transfer minimum delay -
- value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new transfer start (transfer will start only if more data are available in the transmit FIFO) -
- Not used for Clocked_Back2Back mode - - - - - Frame Size For Input in DigRF input mode -
- The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits) - - - - - - - - - - TurnAround time: end of write frame to start of read frame delay (in cycles) -
- value from 0 to 3 is the number of spi clock period between the end of the output frame (without the DO_Delay) and the Input Frame start. -
- Also used for Clocked_Back2Back mode, when Clocked_Back2Back=1 and there is more data available in the transmit FIFO: -
- value from 0 to 3 is the number of spi clock period between the end of the frame (without the DO_Delay) and the start of the new frame. - (It can also be seen as the number of spi clock period between the end of the last data bit and the start of the new data bit.) - - - - - - - The SPI activity status -
- 1 = A transfer is in progress -
- 0 = The transfer is done - - - - - Error status -
- 1 = a new command (or gain) has been requested while a command was in progress. -
- 0 = No error -
- Write 1 to clear. - - - - - The Gain Table overflow status. -
- 1 = Too many data has been written in the table -
- Writing a 1 clear the overflow status. - - - - - The Gain Table underflow status. -
- 1 = a next gain request has been received while the read pointer was already at the top of the table. -
- Writing a '1' clear the underflow status. - - - - - - - - Command FIFO level, number of command in the FIFO - - - - The command FIFO overflow status. -
- 1 = Too many data has been written in the FIFO -
- Writing a 1 clear the overflow status. - - - - - The command FIFO underflow status. -
- 1 = Data has been requested to read while the FIFO was empty -
- Writing a 1 clear the underflow status. - - - - - - - - Command FIFO level, number of bytes in the FIFO - - - - The command data FIFO overflow status. -
- 1 = Too many data has been written in the FIFO -
- Writing a 1 clear the overflow status. - - - - - The command data FIFO underflow status. -
- 1 = Data has been requested to read while the FIFO was empty -
- Writing a 1 clear the underflow status. - - - - - - - - Receive FIFO level, number of bytes in the FIFO - - - - The receive FIFO overflow status. -
- 1 = Too many data has been written in the FIFO -
- Writing a 1 clear the overflow status. - - - - - The receive FIFO underflow status. -
- 1 = Data has been requested to read while the FIFO was empty -
- Writing a 1 clear the underflow status. - - - - - - - Read in the receive FIFO -
- Writing this register will write to Cmd_Data fifo (same as Cmd_Data register). This is because this address is used by the IFC channels to access the fifos. - - - - - - Writing 1 send the next command in the Cmd FIFO (This replace the TCU next cmd signal) - - - - Writing 1 flush both Cmd, and cmd_data FIFO, - don't do it when SPI is active (transfer in progress) - - - - - Writing 1 flush the receive data FIFO, - don't do it when SPI is active (transfer in progress) - - - - - Writing 1 place the read pointer at the beginning of the gain table. - don't do it when SPI is active (transfer in progress) - - - - Writing 1 place the write pointer at the beginning of the gain table allowing to fill the table. - - - Writing 1 change all the ouputs of the SPI interface to drive a logical '0'. This mode stops when a new command is requested to be send (by TCU) or when writting 0 to this register. This mode is useful when powering off the tranciever chip connected to the RF_SPI. - - - - - Write the size in bytes of the next command in the FIFO - - - - Write 1 to mark the command. -
- Marked commands are discarded if Enable_Rf_Spi_Marked_Cmd is low in the tcu register. - - - - - - Write in the Command data FIFO - - - - - Size of a Gain command in bytes. - - - - - Write in the Gain Table (the pointer auto increments) - - - - - - Cmd_Data_DMA_Done IRQ Cause bit -
- 1 = the IRQ was triggered by the end of the DMA transfer to the cmd FIFO. -
- To clear it write 1 in this bit or Cmd_Data_DMA_Done_Status bit. - - - - - Cmd_FIFO_empty IRQ Cause bit -
- 1 = the IRQ was triggered because the Cmd_FIFO is empty. -
- To clear it, fill the FIFO. - - - - - Cmd_Threshold IRQ Cause bit -
- 1 = the IRQ was triggered because the Cmd_FIFO level is below the Cmd_Threshold. -
- To clear it, fill the FIFO. - - - - - Rx_FIFO_full IRQ Cause bit -
- 1 = the IRQ was triggered because the Rx_Data_FIFO is full. -
- To clear it, read from the FIFO. - - - - - Rx_Threshold IRQ Cause bit -
- 1 = the IRQ was triggered because the Rx_Data_FIFO level is over the Rx_Threshold. -
- To clear it, read from the FIFO. - - - - - Error IRQ Cause bit -
- 1 = the IRQ was triggered because an error occured. Read the Status register to check the kind of error. -
- To clear it, clear it in the Status register. - - - - - - - - - - - - - Cmd_Data_DMA_Done IRQ Status bit -
- 1 = the end of the DMA transfer to the cmd FIFO occured. -
- To clear it write 1 in this bit or Cmd_Data_DMA_Done_Cause bit. - - - - - Cmd_FIFO_empty IRQ Status bit -
- 1 = the Cmd_FIFO is empty. - - - - - Cmd_Threshold IRQ Status bit -
- 1 = the Cmd_FIFO level is bellow the Cmd_Threshold. - - - - - Rx_FIFO_full IRQ Status bit -
- 1 = the Rx_Data_FIFO is full. - - - - - Rx_Threshold IRQ Status bit -
- 1 = the Rx_Data_FIFO level is over the Rx_Threshold. - - - - - Error IRQ Status bit -
- 1 = an error occured. Read the Status register to check the kind of error. - - - - - - - - - - - - - - - Cmd_Data_DMA_Done IRQ Mask bit -
- 1 = the Cmd_Data_DMA_Done IRQ is enabled -
- 0 = the Cmd_Data_DMA_Done IRQ is disabled - - - - - Cmd_FIFO_empty IRQ Mask bit -
- 1 = the Cmd_FIFO_empty IRQ is enabled -
- 0 = the Cmd_FIFO_empty IRQ is disabled - - - - - Cmd_Threshold IRQ Mask bit -
- 1 = the Cmd_Threshold IRQ is enabled -
- 0 = the Cmd_Threshold IRQ is disabled - - - - - Rx_FIFO_full IRQ Mask bit -
- 1 = the Rx_FIFO_full IRQ is enabled -
- 0 = the Rx_FIFO_full IRQ is disabled - - - - - Rx_Threshold IRQ Mask bit -
- 1 = the Rx_Threshold IRQ is enabled -
- 0 = the Rx_Threshold IRQ is disabled - - - - - Error IRQ Mask bit -
- 1 = the Error IRQ is enabled -
- 0 = the Error IRQ is disabled - - - - - - - - - - - - - - Command FIFO Threshold, number of command in the FIFO bellow which the Cmd_Threshold_IRQ is triggered. - - - Receive FIFO Threshold, number of bytes in the FIFO above which the Rx_Threshold_IRQ is triggered. - - - - - - Clock Divider -
- The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2 - - - - - - - - - When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz. -
- for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. - - - - - - - - - - - - - - - - - - - - - - This field indicates which standard channel to use. -
- Before using a channel, the CPU read this register to know which channel must be used. - After reading this registers, the channel is to be regarded as - busy. -
- After reading this register, if the CPU doesn't want to use - the specified channel, the CPU must write a disable in the control - register of the channel to release the channel. -
- 0000 = use Channel0 -
- 0001 = use Channel1 -
- 0010 = use Channel2 -
- ... -
- 0111 = use Channel7 -
- 1111 = all channels are busy - - - - - - - - - - - - This register indicates which channel is enabled. It is a copy - of the enable bit of the control register of each channel. One bit per - channel, for example: -
- 0000_0000 = All channels disabled -
- 0000_0001 = Ch0 enabled -
- 0000_0010 = Ch1 enabled -
- 0000_0100 = Ch2 enabled -
- 0000_0101 = Ch0 and Ch2 enabled -
- 0000_0111 = Ch0, Ch1 and Ch2 enabled -
- 1111_1111 = all channels enabled - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - - - - Debug Channel Status . -
- 0= The debug channel is running - (not idle) -
- 1= The debug channel is in idle mode - - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- When the channel is enabled, for a peripheral to memory transfer - the DMA wait request from peripheral to start transfer. - - - - - Channel Disable, write one in this bit disable the channel. -
- When writing one in this bit, the current AHB transfer and - current APB transfer (if one in progress) is completed and the channel - is then disabled. - - - - - Exchange the read data from fifo halfword MSB or LSB -
- - - - - Exchange the write data to fifo halfword MSB or LSB -
- - - - - Set Auto-disable mode -
- 0 = when TC reach zero the - channel is not automatically released. -
- 1 = At the end of the - transfer when TC reach zero the channel is automatically disabled. the - current channel is released. - - - - - Peripheral Size -
- 0= 8-bit peripheral -
- 1= 32-bit peripheral - - - - - - - - - Select DMA Request source - - - - When one, flush the internal FIFO channel. -
- This bit must be used only in case of Rx transfer. Until this bit is 1, the APB - request is masked. The flush doesn't release the channel. -
- Before writting back this bit to zero the internal fifo must empty. - - - - - Set the MAX burst length for channel 0,1. - This bit field is only used in channel 0~1, for channel 2~6, it is reserved. -
- The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. -
- . - - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - - - - AHB Address. This field represent the start address of the - transfer. -
- For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - - - Transfer Count, this field indicated the transfer size in bytes to perform. -
- During a transfer a write in this register add the new value to the current TC. -
- A read of this register return the current current transfer count. - - - - - - - - - - Channel Enable, write one in this bit enable the channel. -
- This channel works only in fifo mode. - - - - Channel Disable, write one in this bit to disable the channel. - - - - - Enable bit, when '1' the channel is running - - - The internal channel fifo is empty - - - Internal fifo level - - - - - - AHB Start Address. -
- This field represent the start address of the fifo. - The start address must 32-bit aligned. - - - - - - - AHB End Address. -
- This field represent the last address of the fifo (it is the first address not used in the fifo). -
- The end address must 32-bit aligned. - - - - - - - Transfer Count, transfer size in bytes. -
- This bit - indicated the transfer size in bytes to perform. Up to 16kbytes per - transfer. -
- During a transfer a write in this register add the new - value to the current TC. A read of this register return the current - current transfer count. - - - - - - - - - - - - 0: sel 26MHz clock. -
- 1: sel 32KHz clock. - - - - - 0: sel 61.44MHz clock. -
- 1: sel 32KHz clock. - - - - Number of snapshot. - - - Number of snapshot. - - - Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. - - - - - - - Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. - - - - - - - - - 0: low active, assert reset. -
- 1: high inactive, deassert reset. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0: not disable ip_* clock. -
- 1: disable ip_* clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0: enable hclk_* auto clock gating. -
- 1: disable hclk_* auto clock gating. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0: enable pclk_* auto clock gating. -
- 1: disable pclk_* auto clock gating. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0: enable pclk_* and clk_* auto clock gating. -
- 1: disable pclk_* and clk_* auto clock gating. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cfg ram. - - - - - - select debug signal. -
- 0: nbiot_dbgout -
- 1: irq_dbg0 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53, gsm_fint_h_bb, gsm_tcu_bcpu_irq_h}; -
- 2: irq_dbg1 = {5'h0, irq_aif_apb_h, nb_acc_int_dsp, nb_tx_int_dsp, nb_rx_int_dsp, nb_tcu_sync_irq_h, irq_mailbox_gge_h, nb_rf_spi_irq, gsm_rf_spi_irq}; -
- 3: irq_dbg2 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53, nb_fint_h_bb, nb_tcu_bcpu_irq_h}; -
- 4: tcu_dbg0 = {gsm_tcu_lps_fint, gsm_lps_tcu_fint_masked, gsm_lps_tcu_stop_counters, gsm_lp_pu_ready, gsm_lp_pu_done, tcu_nb_fint, gsm_fint_h_sys, gsm_fint_h_bb, gsm_toggle_fint_x, gsm_toggle_fint_b, -
- gsm_snap_config, gsm_send_spi_cmd_h, nb_o_tcu_trig, gsm_enable_rf_spi_marked_cmd_h}; -
- 5: tcu_dbg1 = {5'h0, gsm_send_spi_cmd_h, gsm_next_gain_h, gsm_first_gain_h, rx_soc_h, digrf_strobe_h, gsm_tcu_bcpu_irq_h, gsm_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h}; -
- 6: tcu_dbg2 = {4'h0, gsm_tco}; -
- 7: tcu_dbg3 = {nb_tcu_lps_fint, nb_lps_tcu_fint_masked, nb_lps_tcu_stop_counters, nb_lp_pu_ready, nb_lp_pu_done, tcu_nb_fint, nb_fint_h_sys, nb_fint_h_bb, nb_toggle_fint_x, nb_toggle_fint_b, -
- nb_snap_config, nb_send_spi_cmd_h, nb_o_tcu_trig, nb_enable_rf_spi_marked_cmd_h}; -
- 8: tcu_dbg4 = {5'h0, nb_send_spi_cmd_h, nb_next_gain_h, nb_first_gain_h, rx_soc_h, digrf_strobe_h, nb_tcu_bcpu_irq_h, nb_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h}; -
- 9: tcu_dbg5 = {4'h0, nb_tco}; -
- deault: 16'hDABC; - - - - - select rfif dump signal. -
- 0: dfe_dump_data -
- 1: dfe_rx_data -
- 2: dfe_tx_data -
- deault: dfe_dump_data - - - - - - when bcpu is sleep, can disable bcpu cache mem. - - - when bcpu not use cache, can disable bcpu cache mem. - - - - - - - - - - - Internal TCO mapping - - - - - - - - - - - Clear TCO 0 : set the TCO 0 to the inactive state -
- To clear TCO n, use event 2*n - - - - - Set TCO 0 : set the TCO 0 to the active state -
- To set TCO n, use event 2*n+1 - - - - ... - - - - - - - - - - - - stop modulation - - - starts modulation and output on IQ DAC - - - - - - - disable IQ ADC - - - enable IQ ADC - - - stop recording IQ samples - - - start recording IQ samples - - - Clear RF_PDN - - - Set RF_PDN - - - Send RF spi command - - - - - - Start Ramp 0 - - - Start Ramp 1 - - - Start Ramp 2 - - - Start Ramp 3 - - - Start Ramp 4 - - - - - Trigger BCPU TCU irq 0 - - - Trigger BCPU TCU irq 1 - - - Trigger XCPU TCU irq 0 - - - Trigger XCPU TCU irq 1 - - - End of the WakeUp Mode - - - Start of Rf_spi Transfer - - - End of Rf_spi Transfer - - - - - - Value loaded into the TCU counter when the Load bit is set to 1 - - - - - - - - Writing a 1 to this bit will load the TCU with the TCU loadval value -
- Writing a 0 has no effect - - - - - - - - - - - Writing a 1 to enable run tcu wakeup function in lowpower skip frame -
- Writing a 0 to disable - - - - - - - TCU counter wrap value. -
- The TCU counter returns to 0 when this value is reached - - - - - - TCU counter current value - - - - - Writing 1 transfer the programmed events to the active area. - - - Writing 1 to this bit with one of the ForceLatch bit will force the corresponding Active Area to receive no events (i.e. clear it) instead of transfering the programmed area. - - - Writing 1 clears the Program Area - - - - - Configure the TCO polarity - - - - - - Error Status: become 1 when writing to Program Area while the TCU is coping the Program Area to the Active Area. In this case the write is ignored. -
- Write 1 to clear it. - - - - This bit allows to access directly the active area for debug purposes - - - - - - - - - Writing 1 disable the events that affect corresponding TCO. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events that affect corresponding TCO. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events SEND_SPI_CMD. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events NEXT_GAIN. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events FIRST_GAIN. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events NEXT_FC. -
- Reading return the actual enable state. - - - - - Writing 1 disable the corresponding Ramp event. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events RX_SOC. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events DIGRF_STB. -
- Reading return the actual enable state. - - - - - Writing 1 disable the corresponding BCPU TCU irq event. -
- Reading return the actual enable state. - - - - - Writing 1 disable the corresponding XCPU TCU irq event. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events RFSPI_START. -
- Reading return the actual enable state. - - - - - Writing 1 disable the events RFSPI_END. -
- Reading return the actual enable state. - - - - - Writing 1 disable the marked rf spi commands (cf RF SPI). -
- Reading return the actual enable state. - - - - - - - Writing 1 enable the events that affect corresponding TCO. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events that affect corresponding TCO. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events SEND_SPI_CMD. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events NEXT_GAIN. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events FIRST_GAIN. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events NEXT_FC. -
- Reading return the actual enable state. - - - - - Writing 1 enable the corresponding Ramp event. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events RX_SOC. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events DIGRF_STB. -
- Reading return the actual enable state. - - - - - Writing 1 enable the corresponding BCPU TCU irq event. -
- Reading return the actual enable state. - - - - - Writing 1 enable the corresponding XCPU TCU irq event. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events RFSPI_START. -
- Reading return the actual enable state. - - - - - Writing 1 enable the events RFSPI_END. -
- Reading return the actual enable state. - - - - - Writing 1 enable the marked rf spi commands (cf RF SPI). -
- Reading return the actual enable state. - - - - - - - Writing 1 set corresponding TCO to the active state (The actual line state also depends on TCO_Polarity). -
- Reading returns the actual state of all TCOs. - - - - - - - Writing 1 set corresponding TCO to the inactive state (The actual line state also depends on TCO_Polarity). -
- Reading returns the actual state of all TCOs. - - - - - - Enable Clk_TCU same with Clk_Sys. - - - - - Enable the 208kHz pulse generation for DAI Simple. (!) When enabling the clock field Enable_Qbit should also be enabled. - - - - - Enable the Quarter bit generation (required for normal TCU operation) - - - - - - - - 1 when the IRQ was triggered because the tcu counter synchronization is done. -
- Write 1 in cause or status bit to clear. - - - - - - - - 1 when the tcu counter synchronization is done. -
- Write 1 in cause or status bit to clear. - - - - - - - - - when 1 the LPS_IRQ_TCU_Sync_Done is enabled. - - - - - - - - enable sync tcu counter to global counter function. - - - tcu counter load value when synchronized. - - - - - - - - - - - TCU counter value when rfspi conflict happen - - - - - - The event Id will be executed when the TCU counter reaches the value programmed in Event time field of this register. - - - - Event to be executed when the TCU counter reaches the programmed event time. -
- - - - - - - - - - - - - - Writing a '1' in this register triggers a Viterbi Equalization - process. Ignored if any Viterbi process is already ongoing. Auto-reset. - - - Writing a '1' in this register triggers a Viterbi Decoding - process. Ignored if any Viterbi process is already ongoing. Auto-reset. - - - Writing a '1' in this register triggers the TraceBack process. - Ignored if any Viterbi process is already ongoing. Auto-reset. - - - When this bit is set, it enables the generation of the - VITAC_DONE_H interrupt. - - - Indicates whether a puncturing scheme has to be used during - decoding. If this bit is set to '0', the code is assumed unpunctured and - no puncturing matrix is needed. - - - - This field sets the number of states of the Trellis: -
- "00": 16 states -
- "01": 32 states -
- "10": 64 states -
- "11": reserved - - - - When this bit is set, the channel symbols are treated in the - reverse order, i.e. CH_SYMB_ADDR represents the end of the buffer and - the symbols are read out backward. - - - - This field sets the convolutional code rate for decoding: -
- "010": 1/2 rate -
- "011": 1/3 rate -
- "100": 1/4 rate -
- "101": 1/5 rate -
- "110": 1/6 rate -
- others: reserved - - - - - This field sets the amount of shift right applied at the output - of the equalizer BM calculation: -
- "0000": BM = OUT[30:19] -
- "0001": BM = OUT[29:18] -
- ... -
- "1111": BM = OUT[15:4] - - - - - This field sets the amount of shift right applied to the - difference of the two metrics arriving at a node to create a Softvalue: -
- "0000": SoftVal = DELTA[15:9] -
- "0001": SoftVal = - DELTA[14:8] -
- ... -
- "1101": SoftVal = DELTA[2:0]&"0000" -
- others: - reserved - - - - Number of symbols to be Equalized / Decoded. Auto decrement. - - - - - This bit is high when an equalization process is ongoing. It - stays high when the module is stalled during operation. - - - This bit is high when an decoding process is ongoing. It stays - high when the module is stalled during operation. - - - This bit is high when an traceback process is ongoing. It stays - high when the module is stalled during operation. - - - - After a Viterbi process, this field reports the number of - rescaling operations that have been performed along the trellis. -
- This field is reset at every new Viterbi process. - - - - - - - This is the start address of the channel symbols buffer in - SRAM. For Equalization channel symbols are the sampled RF samples - (2x12-bits packed complex values), and for Decoding channel symbols are - a frame of softvalues (4x8-bits packed). -
- This address must be - 4-bytes aligned, bits[1:0] will be ignored. - - - - - - - For Equalization, this is the base address of the partial sum - terms buffer in SRAM. (2x12-bits packed complex values) -
- For - Decoding, this is the base address of the puncturing matrix. -
- This - address must be 4-bytes aligned, bits[1:0] will be ignored. - - - - - - - This is the base address in SRAM of the Path Metrics buffer. - The VITAC will read and update PMs according to the scheme given in - 1.2.1.2. (2x16-bits packed values). -
- This address must be 4-bytes - aligned, bits[1:0] will be ignored. - - - - - - - This is the start address of the output buffer in SRAM. When in - Equalizer mode, the VITAC will output the calculated Softvalues - according to the scheme given in 1.2.1.7. When in Decoder mode, the - VITAC will output the trace words according to the scheme given in - 1.2.2.4. -
- This address must be 4-bytes aligned, bits[1:0] will be - ignored. - - - - - - Real part of the h0 parameter of the estimated channel - response. - - - Imaginary part of the h0 parameter of the estimated channel - response. - - - - - Real part of the hL parameter of the estimated channel - response. - - - Imaginary part of the hL parameter of the estimated channel - response. - - - - - This field indicates the threshold value to be reach by every - PMs for triggering a rescale operation. The rescale operation consist in - subtracting the threshold value to every PMs to avoid overflow during PM - update. - - - - This register bank stores the less significant bit of the output - from the coder for a particular code (see 1.2.2.1). The kth butterfly uses - the bit k of this register. - - This register stores the less significant bit of the output - from the coder for a particular code (see 1.2.2.1). The kth butterfly - uses the bit k of this register. - - - - - - This bit is set when the VITAC module finishes an ongoing - operation. It can be masked by setting VITAC_CMD(IT_MASK) to '1'. -
- Resetting this bit is done by writing in IT_CLEAR register. -
- IT_CAUSE is the image of the VITAC_DONE_H interrupt line to the - CPU. - - - - This bit is the unmasked version of the IT_CAUSE bit. - - - - - Setting this bit to '1' resets the VITAC interrupt. - - - - - - - - - Count Value for 1st TimeOut - - - - - Count Value for 2nd TimeOut - - - - - - Watchdog response mode. -
- 0 = Generate a system reset. -
- 1 = First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset. - - - - - Reset pulse length in number of wdt clock cycles. The range of values available is 1 to 8 clk cycles. -
- 3'b000 - 1 clk cycle -
- 3'b001 - 2 clk cycles -
- 3'b010 - 3 clk cycles -
- ... -
- 3'b111 - 8 clk cycles - - - - - - - This register is used to restart/stop the WDT counter. As a safety feature to prevent accidental restarts/stops, write 8'h76 to restart and 8'h34 to stop. -
- When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. - - - - - - - A pulse to clear interrupt. -
- When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. - - - - - - - This register shows the word status of the WDT. -
- 0 = The watchdog counter is idle/stopped. -
- 1 = The watchdog counter runs. - - - - - This register shows the interrupt status of the WDT. -
- 0 = Interrupt is inactive. -
- 1 = Interrupt asserts. - - - - - - - - - - - - - Enables the Biterror calculation mode. Auto-reset. - - - Enables the DC Offset Correction (1st pass) mode. Auto-reset. - - - Enables the DC Offset Correction (2nd pass) mode. Auto-reset. - - - Enables the DC Offset Correction (3rd pass) mode. Auto-reset. - - - Enables the Training Sequence Cross-Correlation mode. - Auto-reset. - - - Enables the Symbol Re-Construction mode. Auto-reset. - - - Enables the Bit Extraction mode. Auto-reset. - - - Enables the Sum Of PROduCt mode. Auto-reset. - - - Enables the Channel Estimation mode. Auto-reset. - - - Enables the FCH Xcorrelation mode. Auto-reset. - - - Enables the Sliding window mode. Auto-reset. - - - Mask of the end of processing interrupt. - - - Data path setting. Pack I and Q on a single 32-bits word. - - - Data path setting. Enables derotation for DCOC 3pass. - - - Control setting. Number of internal loop iteration. - - - Control setting. Number of symbols to process. - - - - - This bit is high when an operation is ongoing. - - - Masked version of it_status that goes to Interrupt controller. - - - This bit is set high when an operation is finished. It must be reset before lauching a new operation if Xcor interrupt is enabled. - - - - - Multipurpose Data Register. -
- Store Training Sequence in - TSXC mode. -
- Store SUM in DCOC 3rd pass mode. -
- Store bit - sequence in SREC mode. -
- Store SUM in SPROC mode. -
- Store I SUM - in CHEST mode. -
- Store R(k-1) in FCHXC mode. - - - Multipurpose. - - - - - Multipurpose Data Register. -
- Store Training Sequence in - TSXC mode. -
- Store bit sequence in SREC mode. -
- Store Q SUM in - CHEST mode. - - - Multipurpose. - - - - - Multipurpose Data Registers. -
- D0 stores - symbols/softvalues/channel taps depending on mode. Not readable. -
- D1 - stores decoded bits/IQ threshols/IQ Offsets/A terms depending on mode. Not - readable. -
- D2 (aka A1) serves as Rd address (decoded bits, A or B - terms) / Wr address register (I or packed IQ results, Symbols) / event - counter depending on mode. -
- D3 (aka A2) serves as Wr address (Q - results) / event counter depending on mode. -
- D4 stores results from - VITAC / extracted HardValues depending on mode. Not readable. -
- D5 (aka - A3) serves as Wr address (CQ results) Not readable. - - - Multipurpose. - - - - - I part accumulator register. - - - - - I part accumulator register. - - - - - Address 0 Register. -
- Stores Rd address for symbols / - SoftValues / A terms depending on mode. -
- Auto - increment/decrement/reset. - - - 32-bit word address (bits 0 and 1 disregarded). - - - - Multipurpose Data Edge Registers. - - Multipurpose. - - - - - - - - - - program counter for the RF stage. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Theses interrupt lines are software interrupts (the cpu can write in the CP0 bits to trigger and clear them). - - - - - - - - Theses interrupt lines maps to the hardware interrupt lines from the corresponding irq module. - - - - - - - - - - - - The Coprocessor Error (CE) field indicate the coprocessor unit number referenced when a Coprocessor Unusable exception is taken. - - - - - - - - The Branch Delay (BD) bit indicate whether the last exception was taken while executing in a branch delay slot. - - - - - - - Current Interrupt Enable - - - - - Current Kernel/User mode - - - - - Previous Interrupt Enable - - - - - Previous Kernel/User mode - - - - - Old Interrupt Enable - - - - - Old Kernel/User mode - - - - - - - Interrupt Mask control the enabling of each of the external and software interrupts. (See Cause for more information on interruptions). - - - This bit control handling of non-cached instruction fetch requests. By default, the system block reads multiple words of data from the AMBA bus in burst transactions and saves them in the Streaming Buffer. Non cached instruction fetch requests get their data directly from the Streaming Buffer. - When "1" the cpu does not use the streaming buffer and does not ask for burst requests on the AMBA bus for non-cache instruction fetch requests. - - - - Cache Miss -
- Signals that the most recent access to the cachable space resulted in cache miss. - - - - Signals that 2 entries in the TLB matched the virtual address. This is an error condition but the processor takes no action other than signalling it via this bit in the Status Register. - - - Select the location of the exception vectors in ROM or in DRAM. - - - - Reverse Endian in User mode. - (probably unused in xcpu) - - - - Control the Usability of the corresponding Coprocessor Unit. (CP0 is always usable when in Kernel mode, regardless of the setting of the CU_0 bit. - - - Control the Usability of the corresponding Coprocessor Unit. - - - - - - - - - Exception Program Counter. Saves the value of the program counter for the instruction - that caused the exception. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bad virtual address. Saves the address that caused the address exception. - - - - - Exception Program Counter. Saves the value of the program counter for the instruction - that caused the exception by break point instruction. - - - - - - - - - - - - - - - assembler temporary register; - their values are not preserved across procedure calls. - - - - - - Used for expression evaluations and for hold integer function results. -
- Also used to pass the statuc link when calling nested procedure. - - - - - - - Used for expression evaluations and for hold integer function results. -
- Also used to pass the statuc link when calling nested procedure. - - - - - - register A0 to A3 is used to pass the first 4 words of integer type actual arguments; - their values are not preserved across procedure calls. - - - - - register A0 to A3 is used to pass the first 4 words of integer type actual arguments; - their values are not preserved across procedure calls. - - - - - register A0 to A3 is used to pass the first 4 words of integer type actual arguments; - their values are not preserved across procedure calls. - - - - - register A0 to A3 is used to pass the first 4 words of integer type actual arguments; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - saved register; - their values must preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - temporary register, used for expression evaluations; - their values are not preserved across procedure calls. - - - - - reserved for the operating system kernal. - - - - - reserved for the operating system kernal. - - - - - contains the global pointer. - - - - - contains the stack pointer. - - - - - a saved register (like s0-s7). - - - - - contains the return address; used for expression evaluation. - - - - - - - Debug Page Address Register Is a 4 bit register used for extending the address of -the debug to enable full access to the cache RAMs. -
- bit 3 is used when accessing the TAGs to select between Instruction TAG (0) or Data TAG (1). - - - - - - - - when "ON" all accesses for data are treated as non cache. Data is fetched directly from main memory. The content of the Data Cache is not altered. - - - when "ON" all accesses for instructions are treated as non cache. Data is fetched directly from main memory. The content of the cache is not altered. - - - when "ON" all accesses to either Instruction or data caches result in a cache miss and a cache refill. This is a quick way to initialize the caches. - - - - - - - - - - - logic analyzer control register - - - run control. -
- 0 ela-500 disabled. register programming permitted. -
- 1 ela-500 enabled. - - - - - timestamp control register - - timestamp enable. - - - - timestamp interval. -
- when timestamps are enabled, tsint specifies the bit number of the 16-bit trace counter that causes a timestamp - packet to be requested. the trace counter runs from elaclk. when the specified bit changes, a timestamp - packet is requested to be inserted into the trace sram when there is an elaclk cycle during which trace data is - not being captured. the ela-500 does not insert back-to-back timestamps in the sram, even when tsint - causes multiple requests to be made. -
- when tsint = 0, a timestamp is written when action.trace disables trace. looping trigger states enable - and then disable trace, causing timestamp writes. a timestamp is always written when ctrl.run is cleared and - the previous trace write contained a data payload. - - - - - trace counter 1 select. -
- selects the bit number of the 16-bit trace counter that is presented as trace counter[1] in the sram header byte. - - - - - trace counter 0 select. -
- selects the bit number of the 16-bit trace counter that is presented as trace counter[0] in the sram header byte. - - - - - trigger state select register - - - each bit identifies the trigger state that enables independent trace. only trigger state 4 supports independent trace. -
- altts[4]=0 trigger state 4 independent trace disabled. -
- altts[4]=1 trigger state 4 independent trace enabled. -
- all other bits read zero. - - - - - - pre-trigger action register - - sets the value to drive on elaoutput[3:0]. - - - enables trace. - - - sets the level to drive on stopclock. - - - sets the value to drive on cttrigout[1:0]. - - - - - current trigger state register - - - 0 ela-500 is still tracing. -
- 1 indicates that the ela-500 has stopped advancing trigger states and stopped trace. -
- finalstate can be set by trigctrl.countbrk reaching the final loop count, - or by programming nextstate or altnextstate to zero. - - - - - reads current trigger state. this is a one-hot encoded field. -
- when ctrl.run: -
- 0 raz -
- 1 returns current trigger state. -
- if finalstate is 1, then the ctsr field gives the trigger state when finalstate - became 1. - - - - - current counter value register - - returns the counter value when the ctsr was last read. if the ctsr has never been read, then the value in the ccvr - is undefined. - - - - current action value register - - value driven on elaoutput[3:0]. - - - - trace active. -
- 0b0 trace is not active. -
- 0b1 trace is active. - - - - - level driven on stopclock. -
- 0b0 0 driven on stopclock. -
- 0b1 1 driven on stopclock. - - - - value driven on cttrigout[1:0]. - - - - read captured transaction id register - - returns the captured transaction id. - - - - - ram read address register - - - ram read address. -
- writes to the rra cause the trace sram data at that address to be transferred into the holding - register. -
- after the sram read data is transferred to the holding register, rra increments by one. this - prepares the rra address for sequential rrdr reads. -
- the rra automatically increments after apb reads from the rrdr have read the contents of the - holding register. an rrdr read of the last data in the holding register initiates a read to sram at - the address pointed to by the rra. the holding register is filled with the data at this address, then - the rra increments. - - - - - ram read data register - - - reads sram data from the holding register. -
- reads from the rrd return the sram data from the holding register. the first read of the rrd after an rrar update - returns the trace data header byte value, zero-extended to 32 bits. subsequent reads of the rrd return 32-bit chunks of - the trace data payload, starting with the least significant word, until all the payload data has been read, that is, two - words if grp_width = 64, four words if grp_width = 128, and eight words if grp_width = 256. -
- when the final 32 bits of the payload have been read, the rra is incremented automatically, and the next word of - sram data is copied into the holding register. this enables the sram data content to be read out efficiently. -
- the rra wraps to address zero if it is incremented beyond the maximum depth of the sram. - - - - - ram write address register - - - the wrap bit is set when the ram write address is incremented beyond 2ram_addr_size while -
- the ela-500 is capturing trace data. the wrap bit is not set by writes to the rwdr that cause the -
- ram write address to roll over. software must clear the wrap bit when writing to the rwar. - - - - - ram write address. -
- writes to the rwa set the sram address for data that is then written through the rwdr. -
- reads from the rwa return the address of the sram location that is to be written next, either by - writes to the rwdr, or by the trace unit. -
- when trace is stopped, the rwa contains the address of the last sram location that was written - plus one. if the ram write address was incremented beyond the depth of the ram while the - ela-500 was capturing trace data, the wrap bit is set. -
- the rwar is automatically incremented by apb writes to the sram through the rwdr. - - - - - ram write data register - - - writes data to the write holding register and initiates an sram write when the write holding register is full. - writes to the rwd update the internal write holding register. -
- the first write to the rwd sets the header byte value from the least significant byte written. subsequent writes to the - rwd set 32-bit chunks of the payload, starting with the least significant chunk. when the final 32 bits of the payload - have been written, the content of the holding register is copied into the sram and the rwa is incremented - automatically. - - - - - - - signal select registers - - - selects signal group. -
- 0x1 selects signal group 0. -
- 0x2 selects signal group 1. -
- 0x4 selects signal group 2. -
- 0x8 selects signal group 3. -
- 0x10 selects signal group 4. -
- 0x20 selects signal group 5. -
- 0x40 selects signal group 6. -
- 0x80 selects signal group 7. -
- 0x100 selects signal group 8. -
- 0x200 selects signal group 9. -
- 0x400 selects signal group 10. -
- 0x800 selects signal group 11. - - - - - trigger control registers - - - selects the alternative comparison mode: -
- 0b0 trigger signal alternative comparisons selected. -
- 0b1 trigger counter alternative comparisons selected. - - - - - trigger signal alternative comparison type select: -
- 0b000 trigger signal alternative comparisons disabled. -
- 0b001 alternative compare type is equal (==). -
- 0b010 alternative compare type is greater than (>). -
- 0b011 alternative compare type is greater than or equal (>=). -
- 0b101 alternative compare type is not equal (!=). -
- 0b110 alternative compare type is less than (<). -
- 0b111 alternative compare type is less than or equal (<=). - - - - -
- 0b00 disable use of the captured id for signal comparisons. -
- 0b01 capture id when trigger signal condition matches. - the id is captured, from signalgrp[id_capture_size-1:0]. -
- 0b10 use the captured id instead of the target value in sigcomp[id_capture_size-1:0] for - comparison of signalgrp[id_capture_size-1:0]. -
- 0b11 use the captured id instead of the signalgrp[id_capture_size-1:0] for a comparison - against sigcomp[id_capture_size-1:0]. - - - - - loop counter break. -
- the loop counter break uses the trigger state counter to break loops between trigger states after a trigger - counter comparison. when the counter comparison matches, the trigger state goes to a final state, which - stops trace writes and leaves the output actions at the previous trigger state action value. -
- 0b0 normal operation. -
- 0b1 break trigger state loop: a counter comparison match causes a transition to the - final state, otherwise go to the nextstate trigger state as the counter - increments. - - - - - counter clear. -
- 0b0 do not clear the counter value when moving to a different nextstate. -
- 0b1 clear the counter value when moving to a different nextstate. -
- note: trigctrl.watchrst must be 0b0 when using this feature. - - - - - trace capture control. -
- 0b00 trace is captured when trigger signal comparison succeeds. -
- 0b01 trace is captured when trigger counter comparison succeeds. -
- 0b10 trace is captured every elaclk cycle. -
- 0b11 reserved. - - - - - counter source select. -
- 0b0 counter is incremented every elaclk cycle. -
- 0b1 counter is incremented when trigger signal comparison matches. - - - - - counter reset. -
- 0b0 do not reset the counter after a trigger signal comparison match. -
- 0b1 reset the counter after a trigger signal comparison match. -
- the counter acts like an activity watchdog timer, only allowing advancement to the - next trigger state when the trigger counter comparison is reached. the counter is - reset by a signal comparison. - - - - - comparison mode. acts as both a counter enable and a select for the comparison mode. -
- 0b0 disable counters and select trigger signal comparison mode. -
- 0b1 enable counters and select trigger counter comparison mode. - - - - - trigger signal comparison type select. -
- 0b000 trigger signal comparisons disabled. the enabled counters count clocks - immediately after the trigger state has been entered and generate a programmable - output action and transition to the next trigger state when the counter compare - register count is reached, that is when a trigger counter comparison match - occurs. -
- 0b001 compare type is equal (==). -
- 0b010 compare type is greater than (>). -
- 0b011 compare type is greater than or equal (>=). -
- 0b101 compare type is not equal (!=). -
- 0b110 compare type is less than (<). -
- 0b111 compare type is less than or equal (<=). - - - - - next state registers - - - selects the next state to move to after the trigger condition has been met in the current - state. -
- 0x0 do not change state. this is the final trigger state. -
- 0x1 selects trigger state 0. -
- 0x2 selects trigger state 1. -
- 0x4 selects trigger state 2. -
- 0x8 selects trigger state 3. -
- 0x10 selects trigger state 4, when num_trig_states=5. - - - - - action registers - - value to drive on elaoutput[3:0]. - - - - trace active. -
- 0b0 trace is not active. -
- 0b1 trace is active. - - - - - level to drive on stopclock. -
- 0b0 drive 0 on stopclock. -
- 0b1 drive 1 on stopclock. - - - - value to drive on cttrigout[1:0]. - - - - alt next state registers - - - selects the next state to move to after the conditional trigger condition has been - met in the current state. -
- 0x0 do not change state. this is the final trigger state. -
- 0x1 selects trigger state 0. -
- 0x2 selects trigger state 1. -
- 0x4 selects trigger state 2. -
- 0x8 selects trigger state 3. -
- 0x10 selects trigger state 4, when num_trig_states=5. - - - - - alt action registers - - value to drive on elaoutput[3:0]. - - - - trace active. -
- 0b0 trace is not active. -
- 0b1 trace is active. - - - - - level to drive on stopclock. -
- 0b0 drive 0 on stopclock. -
- 0b1 drive 1 on stopclock. - - - - value to drive on cttrigout[1:0]. - - - - - counter compare registers - - value that, when reached in the associated up-counter for this trigger state, causes a trigger counter - comparison match to occur. - - - - - external mask registers - - - mask exttrig[5:0] signals. each signal is masked by clearing the appropriate bit. -
- 0b0 external trigger input signal is masked and is not used in comparisons. -
- 0b1 external trigger input signal is not masked. - - - - - mask cttrigin[1:0] signals. each signal is masked by clearing the appropriate bit. -
- 0b0 external trigger input signal is masked and is not used in comparisons. -
- 0b1 external trigger input signal is not masked. - - - - - external compare registers - - compare value for exttrig[5:0] signals. - - - compare value for cttrigin[1:0] signals. - - - - - signal mask registers - - - mask bits from sigcomp[31:0]. -
- mask bits from sigcomp[63:32]. -
- mask bits from sigcomp[95:64]. these bits are only used if grp_width = 128 or 256. -
- mask bits from sigcomp[127:96]. these bits are only used if grp_width = 128 or 256. - - - - - - signal compare registers - - - compare value for signal group signals[31:0]. -
- compare value for signal group signals[63:32]. -
- compare value for signal group signals[95:64]. these bits are only used if grp_width = 128 or 256. -
- compare value for signal group signals[127:96]. these bits are only used if grp_width = 128 or 256. - - - - - - - - integration mode action trigger output register - - value to drive on elaoutput[3:0] when itctlr.ime = 1. - - - - level to drive on stopclock when itctlr.ime = 1. -
- 0b0 drive 0 on stopclock. -
- 0b1 drive 1 on stopclock. - - - - value to drive on cttrigout[1:0] when itctlr.ime = 1. - - - - - integration mode external trigger input register - - captures the value on exttrig[5:0] when itctlr.ime = 1. - - - captures the value on cttrigin[1:0] when itctlr.ime = 1. - - - - - integration mode control register - - - integration mode enable. -
- 0b0 integration mode disabled. the ela-500 operates normally. -
- 0b1 integration mode enabled when ctrl.run = 0. - - - - - - lock access register - - permits writes to the other ela-500 registers when the access code 0xc5acce55 is written. writing any other value - prevents access to the other ela-500 registers. - - - - lock status register - - - returns the status of the lock access control. -
- 0b001 write access permitted. -
- 0b011 write access not permitted. - - - - - authentication status register - - - secure, non-invasive debug. -
- 0b10 debug disabled. -
- 0b11 debug enabled. - - - - - secure, invasive debug. -
- 0b10 debug disabled. -
- 0b11 debug enabled. - - - - - non-secure, non-invasive debug. -
- 0b10 debug disabled. -
- 0b11 debug enabled. - - - - - non-secure, invasive debug. -
- 0b10 debug disabled. -
- 0b11 debug enabled. - - - - - device architecture register - - - the architect of the device. -
- 0x23b arm. - - - - - indicates that the register is present. -
- 1 register present. - - - - - architecture revision. -
- 0 first revision. - - - - - the architecture of the device. -
- 0x0a75 coresight ela. - - - - - device configuration register 2 - - - 0: level detect of cttrigin and exttrig. -
- 1: single edge detect of cttrigin and exttrig. - - - - - indicates the comparator width. - 0: comparator width = grp_width. -
- >0: comparator width = (comp_width + 1) x 8. -
- for example, if comp_width = 15, then comparator width = 256. - - - - - 0x00 num_trig_states=4. trigger state 4 is not implemented. -
- 0x10 num_trig_states=5. trigger state 4 is implemented and can be used for independent trace. -
- all other encodings are reserved and read as 0x00. - - - - - device configuration register 1 - - counter width in bits. fixed at 32. - - - number of trigger states. four or five. - - - - signal group width. the field value is (signal group width/8) - 1. -
- for example, 7 if grp_width = 64, 15 if grp_width = 128, and 31 if grp_width = 256. - - - - number of signal groups. fixed at 12. - - - - device configuration register - - - 0: trace read data scrambler not present. -
- 1: trace read data scrambler present. - - - - 2-30 bits when cond_trig = 1, or 0 otherwise. - - - - shows the value of the cond_trig parameter. -
- 1, when cond_trig = 1, or 0 otherwise. - - - - sram address width in bits. - - - - trace implementation: -
- 1 fixed at 1. indicates trace header format revision 1. - - - - - atb trace: -
- 0 atb trace not implemented. -
- 1 atb trace is implemented. - - - - - device type identifier register - - - 0x75. -
- sub type = 0x7. -
- major type = 0x5. - - - - - peripheral id4 register - - 0x0. one 4kb count. - - - 0x4. jep continuation code for arm. - - - - peripheral id5 register - - 0x00. reserved. - - - - peripheral id6 register - - 0x00. reserved. - - - - peripheral id7 register - - 0x00. reserved. - - - - peripheral id0 register - - 0xb8. bits[7:0] of part number 0x9b8. - - - - peripheral id1 register - - 0xb. bits[3:0] of jep106 identification code for arm 0x3b. - - - 0x9. bits[11:8] of part number 0x9b8. - - - - peripheral id2 register - - 0x2. revision number. indicates revision r2p0. - - - 0b1. fixed at 0b1. - - - 0b011. bits[6:4] of jep106 identification code for arm 0x3b. - - - - peripheral id3 register - - 0x0. revand. - - - 0x0. indicates whether the customer has modified the behavior of the component. in most cases, this field is - 0b0000. you can change this value when you make authorized modifications to this component. - - - - component id0 register - - 0x0d. preamble. - - - - component id1 register - - 0x9. indicates a coresight component. - - - 0x0. preamble. - - - - component id2 register - - 0x05. preamble. - - - - component id3 register - - 0xb1. preamble. - - - - - - - - - - Control setting. psample increment. - - - Control setting. Number of symbols. - - - Control setting. node metric history. - - - Control setting. Command. - - - - - pbmml address. - - - - - pzfm address. - - - - - psample address. - - - - - softbits output address. - - - - - Status is set to 1 when an operation is finished,It must be reset before lauching a new operation - - - sv shift bits. - - - bm shift bits. - - - - - zfhist history. - - - - - - - - - - - Returns 1 and locks the DMA channel for a transaction if it is - available. Else returns 0. -
- Clear the transfer done interrupt - status. - - - - - - Status of the DMA: 1 if enabled, 0 if disabled. - - - - Cause of the interrupt. This bit is set when the transfer is - done and the interrupt mask bit is set. -
- Write one in the Int Clear - or write 0 in Enable control bits to clear Int Done Cause bit. - - - - - Status of the interrupt. Status of the transfer: 1 if the - transfer is finished, 0 if it is not finished. -
- Write one in the - Int Clear or write 0 in Enable control bits to clear Int Done Status - bit. - - - - Actual status of channel lock. Channel is unlocked at the end - of transaction or when the DMA is disabled. - - - - - Controls the DMA. Write 1 to enable the DMA, write 0 to disable - it. When 0 is written in this register, the Int Done Status and Cause - bits are reset. - - - End of transfer interrupt generation. When 1, the DMA will send - an interrupt at transaction completion. - - - - - - - Clear the transfer done interruption (this will clear Int Done - Status and Int Done Cause). -
- This bit is auto-clear. You will - always read 0 here. - - - - If this bit is set, the source address will be ignored and the - memory will be fill with the value of the pattern register. - - - - Set the MAX burst length. -
- The 2'b10 mean burst max 16, 2'b01 mean burst max 8, 00 mean burst max 4. - - - - The DMA stop the current transfer and flush his FIFO (write - only bit). When the FIFO is empty and last write performed, the DMA is - disabled and available for a next transfer. The number of bytes copied - is readable on DMA_XFER_SIZE register. - - - - - Enable Gea process when 1. - - - - - This field sets the type of GEA algorithm to process. - - - - - - This field selects the Direction in the GEA algorithm. - - - - - Enable FCS process when 1. - - - - - - Destination address management. -
- 00 : Normal DMA operation, - DMA_DST_ADDR register define the destination address. -
- 01 : DMA - write address is constant (no incremented) and defined by the - DMA_DST_ADDR register. All data write are in 16-bit. -
- 10 : DMA - write address is alternatively defined by DMA_DST_ADDR and - DMA_SD_DST_ADDR registers. All data write are in 16-bit. -
- In this - configuration, DMA write operation is alternatively: -
- DMA_DST_ADDR - <= DMA_PATTERN register -
- DMA_SD_DST_ADDR <= - Data[DMA_SRC_ADDR] -
- 11 : reserved - - - - - - Source start read byte address. When a transfer is stalled by - the Stop_Transfer bit, this register give the next current source - address, which is directly the value to re-program to complete the - transfer stopped. - - - - - Destination start read byte address. When a transfer is stalled - by the Stop_Transfer bit, this register give the next current - destination address, which is directly the value to re-program to - complete the transfer stopped. - - - - - Second destination address. This register is only used when - Dst_Address_Mgt=10. - - - - - Transfer size in bytes. Maximum: 262144 bytes. When a transfer - is stopped by the Stop_Transfer bit, this register give the number of - remainder bytes to transfer. - - - - - Value taken to fill the memory when the configuration bit Use - Pattern is set. When the pattern mode is used the destination address - must be 32-bit aligned and the transfer size multiple of 4. when - Dst_Address_Mgt=10 Pattern is the data written at the address given by - the Dst_Address register. - - - - - GEA key Kc, LSB bit [31:0]. - - - - - GEA key Kc, MSB bit [31:0]. - - - - - MessKey (Input) register. - - - - - Frame Check Sequence. - - - The FCS is correct in reception when the final remainder is - equal to C(x)= x^22 + x^21 + x^19 + x^18 + x^16 + x^15 + x^11 + x^8 + - x^5 + x^4 - - - - - - - - - PSS Enable -1b0: Stop PSS calculation -1b1: Start PSS calculation - - - PSS hypothesis number - - - PSS output ping-pong buffer selection -1b1:Select the pong buffer as the first output buffer -1b0: Select the ping buffer as the first output buffer - - - - - PSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. - - - PSS start offset of subframe. Range is from 0 to 9. - - - - - PSS internal sub frame counter(from 0 to 9) - - - - - Indicate the buffer selection on current interrupt -1b0: buffer0 is selection -1b1: buffer1 is selection - - - PSS output buffer 0 status. Clear by DSP or MCU -1b1: buffer 0 is ready. -1b0:buffer0 is idle - - - PSS output buffer 0 status. -1b1: buffer 0 is over written. -1b0: buffer 0 is normal - - - PSS output buffer 1 status. Clear by DSP or MCU -1b1: buffer 1 is ready. -1b0:buffer 1 is idle - - - PSS output buffer 1 status. -1b1: buffer 1 is over written. -1b0: buffer 1 is normal - - - PSS calculation done status. Update very 1ms and clear by DSP or MCU. -1b1: PSS calculation done -1b0: PSS is idle or under calculating - - - PSS write memory arbitration error status. -1b1: the memory has conflict -1b0: the memory is normal - - - - - bit8: pss final output data non-zero status -bit7: pss 148x40 memory out data non-zero status -bit6: pss 148x40 memory in data non-zero status -bit5: pss power non-zero status -bit4: pss 1312x24 memory out data non-zero status -bit3: pss 1312x24 memory in data non-zero status -bit2: pss in local sequence non-zero status -bit1: pss_corr_calc in data non-zero status -bit0: pss_deci in data non-zero status - - - - - - PSS sample position for Pu of hypothesis 0 - - - PSS sample position for Pu of hypothesis 1 - - - PSS sample position for Pu of hypothesis 2 - - - PSS sample position for Pu of hypothesis 3 - - - - - PSS sample position for Pu of hypothesis 0 - - - PSS sample position for Pu of hypothesis 1 - - - PSS sample position for Pu of hypothesis 2 - - - - - PSS sample position for Pl of hypothesis 0 - - - PSS sample position for Pl of hypothesis 1 - - - PSS sample position for Pl of hypothesis 2 - - - PSS sample position for Pl of hypothesis 3 - - - - - PSS sample position for Pl of hypothesis 4 - - - PSS sample position for Pl of hypothesis 5 - - - PSS sample position for Pl of hypothesis 6 - - - - - PSS set 0 coefficient for hypothesis 0 - - - PSS set 0 coefficient for hypothesis 1 - - - PSS set 0 coefficient for hypothesis 2 - - - PSS set 0 coefficient for hypothesis 3 - - - - - PSS set 0 coefficient for hypothesis 4 - - - PSS set 0 coefficient for hypothesis 5 - - - PSS set 0 coefficient for hypothesis 7 - - - - - PSS set 1 coefficient for hypothesis 0 - - - PSS set 1 coefficient for hypothesis 1 - - - PSS set 0 coefficient for hypothesis 2 - - - PSS set 0 coefficient for hypothesis 3 - - - - - PSS set 1 coefficient for hypothesis 4 - - - PSS set 1 coefficient for hypothesis 5 - - - PSS set 0 coefficient for hypothesis 6 - - - - - - - Real part of the local sequence 0 - - - Imag part of the local sequence 0 - - - - - - - Real part of the local sequence 1 - - - Imag part of the local sequence 1 - - - - - - - Real part of the local sequence 2 - - - Imag part of the local sequence 2 - - - - - - - Real part of the local sequence 3 - - - Imag part of the local sequence 3 - - - - - - - Real part of the local sequence 4 - - - Imag part of the local sequence 4 - - - - - - - Real part of the local sequence 5 - - - Imag part of the local sequence 5 - - - - - - - Real part of the local sequence 6 - - - Imag part of the local sequence 6 - - - - - - - Start trigger of one CFO calculation process by writing 1 to this register - - - - - CFO data capture start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. - - - CFO data capture start offset of sub-frame. Range is from 0 to 13. - - - - - CFO calculation start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. - - - CFO calculation start offset of sub-frame. Range is from 0 to 13. - - - - - Rotated frequency bin number when rCFO_MODE=0. - - - 1: Normal mode. CFO module only deal with 1 frequency bin(f0) and 9 sampling positions(Tau). 147 correlation results are reported to corresponding ram at most. -0: Searching mode. CFO module deal with 1~7 frequency bins(f0~6) and 21 sampling positions(Tau). 9 correlation results are reported to corresponding registers. - - - Start write address of CFO correlation results reporting ram - - - Correlation results truncation (32bits to 16bits). -0:>>8 1:>>7 2:>>6 3:>>5 -4:>>4 5:>>3 6:>>2 7:>>1 - - - Tau number of CFO correlation when rCFO_MODE=0. - - - - - Sampling position start offset for bin f0 - - - Sampling position start offset for bin f1 - - - Sampling position start offset for bin f2 - - - Sampling position start offset for bin f3 - - - - - Sampling position start offset for bin f4 - - - Sampling position start offset for bin f5 - - - Sampling position start offset for bin f6 - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. -[31:16]:Imag part -[15:0]: Real part - - - - - - CFO calculation done status. Clear by DSP or MCU. -1b1: CFO calculation done -1b0: CFO is idle or under calculating - - - Memory request error for writing of CFO reporting ram when rCFO_MOED=0 -0: Normal -1: Error -Bit 2: DSP control bus error -Bit 1: accelerator memory access collusion - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -4 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -3 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -2 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -1 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = 0 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +1 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +2 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +3 is reported -[31:16]: imag part -[15:0]: real part - - - - - When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +4 is reported -[31:16]: imag part -[15:0]: real part - - - - - - SSS Enable -1b0:Stop SSS calculation -1b1: Start SSS calculation - - - - - SSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. - - - SSS start offset of subframe. Range is from 0 to 9. - - - - - SSS start calculation offset of sample within a subframe. Based on 1.92MHz. Range is from 0 to 1920. - - - SSS start calculation offset of subframe. Range is from 0 to 9. - - - - - Real part of SSS phase shift - - - Imag part of SSS phase shift - - - - - Real part of SSS phase shift 1 - - - Imag part of SSS phase shift 1 - - - - - Real part of SSS phase shift 2 - - - Imag part of SSS phase shift 2 - - - - - Real part of SSS phase shift 3 - - - Imag part of SSS phase shift 3 - - - - - Real part of SSS phase shift 4 - - - Imag part of SSS phase shift 4 - - - - - Real part of SSS phase shift 5 - - - Imag part of SSS phase shift 5 - - - - - Real part of SSS phase shift 6 - - - Imag part of SSS phase shift 6 - - - - - Real part of SSS phase shift 7 - - - Imag part of SSS phase shift 7 - - - - - Real part of SSS phase shift 8 - - - Imag part of SSS phase shift 8 - - - - - Real part of SSS phase shift 9 - - - Imag part of SSS phase shift 9 - - - - - Real part of SSS phase shift 10 - - - Imag part of SSS phase shift 10 - - - - - SSS internal sub frame counter(from 0 to 9) - - - - - global sample count value at SSS subframe start - - - global subframe count value at SSS subframe start - - - Global radio frame count value at SSS subframe start - - - - - Indicate the buffer selection on current interrupt -1b0: MEM0 is selection -1b1: MEM1 is selection - - - SSS output buffer 0 status. Clear by DSP or MCU -bit 2: 1b1: MEM2 or MEM0 is ready.1b0:buffer0 is idle - - - SSS output buffer 0 status. -bit 3: 1b1: MEM2 or MEM0 is over written. 1b0: buffer 0 is normal - - - SSS output buffer 1 status. Clear by DSP or MCU -bit 4: 1b1: MEM3 or MEM1 is ready.1b0:buffer1 is idle - - - SSS output buffer 1 status. -bit 5: 1b1: MEM3 or MEM1 is over written. 1b0: buffer 1 is normal - - - SSS calculation done status. Update very 1ms and clear by DSP or MCU. -1b1: SSS calculation done -1b0: SSS is idle or under calculating - - - SSS write memory arbitration error status. -0: Normal -1: Error -Bit 7: DSP control bus error -Bit 8: accelerator memory access collusion - - - - - OFDM symbol CP offset which use to locate the FFT windows start position for serving cell. -Value:[0:9] - - - FFT result scaling -3d0: 2^-3 -3d1: 2^-2 -3d2: 2^-1 -3d3: 2^0 -3d4: 2^1 -3d5: 2^2 - - - - - Correlation result sScaling for both power and correlation -3d0: 20 -3d1: 2-1 -3d2: 2-2 -3d3: 2-3 -3d4: 2-4 -3d5: 2-5(Default) -3d6: 2-6 -3d7: 2-7 - - - Cyclic shift value -It is used when rSSS_CYCLIC_SHIFT_FIX_EN = 1'b1.Rang is from 0 to 2. - - - Fix cyclic shift enable - - - PCI ID -It is used when rSSS_PCI_ID_FIX_RN = 1'b1 or rSSS_SIC_EN = 1'b1. Range is from 0 to 503. - - - Fix PCI ID Enable. - - - SIC Enable -Used for succesive interference cancellation. - - - SSS output ping-pong buffer selection -1b1:Select the pong buffer as the first output buffer -1b0: Select the ping buffer as the first output buffer - - - Scaling for correlation only -3d0: 2-4 -3d1: 2-3 -3d2: 2-2 -3d3: 2-1 -3d4: 20(Default) -3d5: 21 -3d6: 22 -3d7: 23 - - - - - SSS total power - - - - - - - - - RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. - - - - - RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. - - - - - RX interrupt output OS 0 127 - - - - - - RX adjustment subframe count from 0 9 (auto clear in next subframe) - - - RX adjustment symbol count from 0 13 (auto clear in next subframe) - - - RX adjustment symbol direction (auto clear in next subframe) -0: advance -1: postpone - - - RX coarse adjustment sample count from 0 138 in (chip unit) - (auto clear in next subframe) - - - RX coarse adjustment sample direction (auto clear in next subframe) -0: advance -1: postpone - - - - - RX fine adjustment sample count from 0 9 in (chip unit) - (auto clear in next subframe) - - - RX fine adjustment sample direction (auto clear in next subframe) -0: advance -1: postpone - - - - - RX interrupt symbol number 0-13 - - - RX interrupt symbol number 0-13 - - - RX interrupt buffer index -Mirror rRX_INT_BUF_IDX_MCU register - - - - - RX interrupt symbol number 0-13 - - - RX interrupt symbol number 0-13 - - - RX interrupt buffer index - - - - - RX SFN number 0-1023 - - - - - global sample count value at RX subframe start - - - global subframe count value at RX subframe start - - - global sample count value at RX subframe start - - - - - global sample count value at RX radio frame start - - - global subframe count value at RX radio frame start - - - global sample count value at RX radio frame start - - - - - global sample count value at TCU subframe start - - - global subframe count value at TCU subframe start - - - global sample count value at TCU subframe start - - - - - - TX coarse adjustment sample count from 0 1919 in (chip unit) - (auto clear in next subframe) - - - TX coarse adjustment sample direction - (auto clear in next subframe) -0: advance -1: postpone - - - - - 15KHz: TX fine adjustment sample count from 0 9 in (chip unit) -3.75Hz: TX fine adjustment sample count from (0 9) x 4 in (chip unit) -Remark: SW should configure the sample boundary which is aligned to 3.75Hz sample if the timing adjustment between TX transmission. -(auto clear in next subframe) - - - TX fine adjustment sample direction - (auto clear in next subframe) -0: advance -1: postpone - - - TX fine adjustment mode control: -0: adjust the boundary at the end of the current subframe -1: adjust the CP at the first symbol of the next TX - - - - - - global sample count value at TX subframe start - - - global subframe count value at TX subframe start - - - global radio frame count value at TX subframe start - - - - - TX subsample control -0: sync with global subsample counter -1: only sync with RX subsample counter when TX is not on transmission - - - - - Control RX coarse adjustment status - - - Control RX fine adjustment status - - - Control TX coarse adjustment status - - - Control TX fine adjustment status - - - - - Control adjustment enable -1: enable -0: disable - - - - - - Trigger to sample global counter position for DSP debegging - - - - - global counter sample position when CAPTURE1_GLB_CNT is accessed - - - global counter subframe position when CAPTURE1_GLB_CNT is accessed - - - global counter radio frame position when CAPTURE1_GLB_CNT is accessed - - - - - Trigger to sample global counter position for MCU debegging - - - - - global counter sample position when CAPTURE2_GLB_CNT is accessed - - - global counter subframe position when CAPTURE2_GLB_CNT is accessed - - - global counter radio frame position when CAPTURE2_GLB_CNT is accessed - - - - - For sleep operation -When SLEEP_W is accessed, the start values needed for wake-up are loaded. Then values have to be written before the SLEEP_W is accessed - - - - - Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for alignment of the DFE input valid. -0-31 - - - global counter sample position in sleep mode (in chip unit) - - - global counter subframe position - - - global counter radio frame position - - - - - Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for align the DFE input valid. -0-31 - - - RX sample count value - - - RX OFDM symbol count value - - - RX subframe count value - - - - - Sleep Elapsed Subsample counter -Range: 0-31 - - - Sleep Elapsed Subsample counter -Range: 0-1919 - - - - - Sleep Elapsed SF counter -Range: 0-2^32-1 - - - - - - TCU event subsample time - - - TCU event subframe time - - - - - RX synchronization method mode -0: normal mode -1: sync counter with input i_rx_sync_start pulse in DUMP mode only (For testing only) - - - - - RX subframe count sync initialization value - 1 - - - Global subframe count sync initialization value - 1 - - - Global radio frame count sync initialization value - 1 - - - - - RX Capture event sample time - - - RX Capture event subframe time - - - - - - DSP memory 0 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - DSP memory 1 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - DSP memory 2 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - DSP memory 3 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - DSP memory 4 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - DSP memory 5 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - - DSP memory 7 control -00: HW control with NB core clock -10: HW control with AHB clock -11: DSP control with AHB clock - - - - - - - - - RX FFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX Cell Search PSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX Cell Search SSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX CFO sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX Viterbi sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX AGC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - RX DS_BSEL sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - TX frontend sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - PUSCH encoder sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - TX CHSC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - FFT 512 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - NPRS acc1 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - FINE_IFFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - rNBIOT general part reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - NC_RSRP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - - - Enable/disable the clock for RX FFT/RSRP module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for RX Cell Search module PSS -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for RX Cell Search module SSS -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for RX CFO module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for RX Viterbi module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for RX AGC module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for DS_BSEL module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for TX Frontend module. -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for PUSCH encoder module. -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for TX TX channel-interleaver and scrambling module. -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for FFT 512 module. -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for NPRS ACC1 module. -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for FINE ifft module -0: clock disabled -1: clock enabled. - - - Enable/disable the clock for NBIOT module -0: clock disabled -1: clock enabled. - - - - - Debug signal selection - - - Debug signal output enable - - - - - RFIN reset by DSP, it is used to re-timing the global timer to balance the timing of IQ data input from DFE in sample boundary. Write 1 and auto-clear by HW. -0: default value -1: reset to re-timing the sample boundary in global timer. - - - - - Sample the glb_subsample_cnt with input rx_data_vld to check the phase change of the input - - - Keep track the RFIN data strobe in valid window. -0: Normal -1: Error - - - - - PSS Correlator coarse clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. - - - SSS Correlator coarse clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. - - - - - FFT_RSRP fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP. - - - PSS Correlator fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. - - - SSS Correlator fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. - - - CFO Correlator fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module CFO Correlator. - - - Viterbi fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module Viterbi. - - - AGC fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module AGC. - - - DS_BSEL fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module DS_BSEL. - - - TX_FRONTEND fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module TX_FRONTEND. - - - PUSCH_ENC fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module PUSCH_ENC. - - - TX_CHSC fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module TX_CHSC. - - - FFT 512 fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module FFT 512. - - - NPRS ACC1 fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module NPRS ACC1. - - - FIne IFFT fine clock gating, -0: free running -1: clock gated by the clock enabled signal which generated from sub-module FINE_IFFT. - - - - - NBIOT CORE APB domain reset by software, auto-clear to zero when write 1 to this register by DSP -0: default value; -1: Reset whole sub-module. - - - - - Debug General Purpose Output -Remark: need to set rNBIOT_MONITOR to 0x1a3 - - - - - - Minor Revision - - - MAJOR Revision - - - - - - - - - DS_BSEL accelerator start - - - - - Maximum time out value for TX bit level processing in 61.44Mhz unit - - - Number of Candidate -0: 1 candidate -1: 2 candidate -2: 3 candidate -3: 4 candidate - - - Bit de-selection and combining -0: Disable -1: enable -Remark: When this bit is disabled, the output data number is equal to rDESCR_SIZE0 and it only support 1 candidate. - - - Descramble enable -0: Disable -1: enable - - - NCB minus: NCB 3ND - - - - - Descramble X1 value for candidate 0 - - - - - Descramble X1 value for candidate 1 - - - - - Descramble X1 value for candidate 2 - - - - - Descramble X1 value for candidate 3 - - - - - Descramble X2 value for candidate 0 - - - - - Descramble X2 value for candidate 1 - - - - - Descramble X2 value for candidate 2 - - - - - Descramble X2 value for candidate 3 - - - - - Descramble size 0 - - - Descramble size 1 - - - - - Descramble size 3 - - - Descramble size 2 - - - - - Descramble input buffer start address 0 - - - Descramble input buffer start address 1 - - - - - Descramble input buffer start address 3 - - - Descramble input buffer start address 4 - - - - - DS_BSEL output memory start address - - - - - The last candidate Descramble X2 state value - - - - - The last candidate Descramble X2 state value - - - - - (This bit is write 1 clear) -0: No Done -1: Done - - - If Done bit would not clear before this engine re-engine would indicate overwritten output buffer -0: Normal -1: Error - - - 0: Normal -1: Error -Bit 0: DSP control bus error -Bit 1: accelerator memory access collusion - - - 0: Normal -1: Error - - - - - - - - - FFT calculation enable - - - the period of FFT done interrupt, 0: one time per-subframe; 1: twice per-subframe. - - - - - FFT/RSRP enable - - - FFT result scaling - - - 0: FFT disabled, 5 RSRP CELLs calculation mode; 1: FFT + 2 RSRP Cell calculation mode. - - - - - FFT OFDM symbol CP offset - - - - - RSRP Cell0 Enabled. - - - RSRP Cell1 Enabled. - - - RSRP Cell2 Enabled. - - - RSRP Cell3 Enabled. - - - RSRP Cell4 Enabled. - - - - - Frame start position of RSRP Cell0 based on global timer. - - - - - Frame start position of RSRP Cell1 based on global timer. - - - - - Frame start position of RSRP Cell2 based on global timer. - - - - - Frame start position of RSRP Cell3 based on global timer. - - - - - Frame start position of RSRP Cell4 based on global timer. - - - - - OFDM symbol CP offset for NCELL0. - - - - - OFDM symbol CP offset for NCELL1. - - - - - OFDM symbol CP offset for NCELL2. - - - - - OFDM symbol CP offset for NCELL3. - - - - - OFDM symbol CP offset for NCELL4. - - - - - vshift of NCELL0. - - - vshift of NCELL1. - - - vshift of NCELL2. - - - vshift of NCELL3. - - - vshift of NCELL4. - - - - - confiugred subframe idx when RSRX cell enabled. - - - confiugred subframe idx when RSRX cell enabled. - - - confiugred subframe idx when RSRX cell enabled. - - - confiugred subframe idx when RSRX cell enabled. - - - confiugred subframe idx when RSRX cell enabled. - - - - - Offset address for RSRP write memory buffer. - - - - - Indicated whether the data in ping-pong buffer is updated. - - - FFT buffer ping-pong flag - - - Indicated which triple buffer is UPDATED - - - Indicated which buffer is just updated when interrupt asserted. - - - Indicated which triple buffer is UPDATED - - - Indicated which buffer is just updated when interrupt asserted. - - - Indicated which triple buffer is UPDATED - - - Indicated which buffer is just updated when interrupt asserted. - - - Indicated which triple buffer is UPDATED - - - Indicated which buffer is just updated when interrupt asserted. - - - Indicated which triple buffer is UPDATED - - - Indicated which buffer is just updated when interrupt asserted. - - - - - subframe index of serving cell - - - - - subframe idx of NCELL0 - - - subframe idx of NCELL1 - - - subframe idx of NCELL2 - - - subframe idx of NCELL3 - - - subframe idx of NCELL4 - - - - - FFT pingpong buffer overwritten status - - - RSRP Cell0 triple buffer over-written status. - - - RSRP Cell1 triple buffer over-written status. - - - RSRP Cell2 triple buffer over-written status. - - - RSRP Cell3 triple buffer over-written status. - - - RSRP Cell4 triple buffer over-written status. - - - FFT write buffer bus error - - - RSRP CELL0 write buffer bus error - - - RSRP CELL1 write buffer bus error - - - RSRP CELL2 write buffer bus error - - - RSRP CELL3 write buffer bus error - - - RSRP CELL4 write buffer bus error - - - - - FFT pingpong buf idx - - - RSRP0 Triple buffer idx - - - RSRP1 Triple buffer idx - - - RSRP2 Triple buffer idx - - - RSRP3 Triple buffer idx - - - RSRP4 Triple buffer idx - - - - - FFT subframe idx - - - RSRP Cell0 subframe idx - - - RSRP Cell1 subframe idx - - - RSRP Cell2 subframe idx - - - RSRP Cell3 subframe idx - - - RSRP Cell4 subframe idx - - - - - - - - - Interrupt Masking bit for RX_INT_DSP - - - - - Interrupt Masking bit for RX_INT_MCU - - - - - Interrupt Masking bit for TX_INT_DSP - - - - - Interrupt masking bit from the interrupt of fft_done_int - - - Interrupt masking bit of NCELL0 decode done intterupt - - - Interrupt masking bit of NCELL1 decode done interrupt - - - Interrupt masking bit of NCELL2 decode done interrpt - - - Interrupt masking bit of NCELL3 decode done interrupt - - - Interrupt masking bit of NCELL4 decode done interrupt - - - Interrupt masking bit of PSS SF done interrupt - - - Interrupt masking bit of SSS SF done interrupt - - - Interrupt masking bit of CFO SF done interrupt - - - Interrupt masking bit of Viterbi decode done interrupt - - - Interrupt masking bit of AGC interrupt masking - - - Interrupt masking bit of DS_BSEL interrupt - - - Interrupt masking bit of PUSCH encoder interrupt - - - Interrupt masking bit of TX_CHSC interrupt - - - Interrupt masking bit of FFT_512 done interrupt - - - Interrupt masking bit of NPRS_ACC1 done interrupt - - - Interrupt masking bit of FINE_IFFT done interrupt - - - - - interrupt status of RX_INT_DSP, write 1 clear. - - - - - Interrupt status of RX_INT_MCU, write 1 clear. - - - - - Interrupt status of TX_INT_DSP, write 1 clear. - - - - - Interrupt status of fft_sf_done_int - - - Interrupt status of RSRP Cell0 decode done interrupt - - - Interrupt status of RSRP Cell1 decode done interrupt - - - Interrupt status of RSRP Cell20 decode done interrupt - - - Interrupt status of RSRP Cell3 decode done interrupt - - - Interrupt status of RSRP Cell4 decode done interrupt - - - Interrupt status of PSS SF done interrupt - - - Interrupt status of SSS SF done interrupt - - - Interrupt status of CFO SF done interrupt - - - Interrupt status of Viterbi decode done - - - Interrupt status of AGC interrupt - - - Interrupt status of DS_BSEL interrupt - - - Interrupt status of PUSCH Encoder interrupt - - - Interrupt status of TX_CHSC interrupt - - - Interrupt status of FFT_512 done interrupt - - - Interrupt status of NPRS_ACC1 done interrupt - - - Interrupt status of FINE IFFT done interrupt - - - - - - - - - Symbol power accumulation enable/disable signal and effective at subframe boundary. - 1 : enable - 0 : disable - - - - - Gain used in shift and saturation of accumulation power value. -Bit[3:0] Gain -0000 2^-24 (default) -0001 2^-23 -0010 2^-22 -0011 2^-21 - - - Accumulation length of samples in every symbol. - 0: 128 - 1: 64 - 2: 32 - 3: 16 - - - Offset of samples from symbols boundaries which is the start boundary of agc symbol power calculation. - - - - - Reading address for DSP to read asp response ram, and this register would auto-increment whenever access the rASP_RD_DATA register -PING buffer address: 0~20 -PONG buffer address: 21~41 - - - - - Bit[27:16]: Q DC offset configuration -Bit[11:0]: I DC offset configuration - - - - - - Report agc symbol power and DCC done status, write 1 to clear this status - - - Index bit to indicate which buffer is updated of PING-PONG -1: PONG buffer data is updated -0: PING buffer data is updated - - - - - Data = mem[rASP_RD_ADDR] which is the ASP response memory data content. The ASP_RD_ADDR would auto increase whenever access this register. -ASP response Memory address range is 0-41 -Address(0~6,21~27): symbol power, bit[15:0] for symbol 0,2,4,6,8,10,12 and bit[31:16] for symbol 1,3,5,7,9,11,13 -Address(7~20,28~41):dc_offset value, bit[15:0] for I and bit[31:16] for Q - - - - - - Forward/Inverse FFT transform computing selection - - - PING-PONG memory selection -1b0: Memory0; -1b1: Memory1. - - - FFT scaling, it can be implemented by bit shift, -3d0: 2^-3 -3d1: 2^-2 -3d2: 2^-1 -3d3: 2^0 (default) -3d4: 2^1 -3d5: 2^2 -3d6: 2^3 -3d7: 2^4 - - - FFT_amp_out scaling for amplitude square output, it can be implemented by bit shift, -3d0: 2^-3 -3d1: 2^-2 -3d2: 2^-1 -3d3: 2^0 (default) -3d4: 2^1 -3d5: 2^2 -3d6: 2^3 -3d7: 2^4 - - - IFFT Output amptitude data -1b0: IFFT output normal data(I+j*Q); -1b1: IFFT output amptitude data(I^2+Q^2). - - - - - FFT start indication, when write 1 to this register, a high active pulse will be generated and input to FFT engine to start FFT calculation. - - - - - FFT done status, write 1 clear. - - - An error grant is received when FFT request memory write bus to store FFT result. -Bit1: DSP control error; -Bit0: Accelerator memory access error. - - - This register is used to check the range of FFT/IFFT input, -1b1: absolute maximum FFT/IFFT input less than 32, in this case, the resolution of FFT/IFFT output will loss 1bit; -1b0: normally. - - - - - - NPRS accelerator 1 Start - - - - - Maximum time out value in 61.44Mhz unit - - - Mode selection: -2b00: copy + dot product -2b01: dot product -2b10: copy - - - Copy Source memory before sequence dot product -0: Memory 0 -1: Memory 1 - - - Copy memory with bit-reversed address write location enable -0: Disable -1: Enable - - - Destination memory after sequence dot product -0: Memory 0 -1: Memory 1 - - - Dot Product from memory 5 to memory 0/1 with bit-reversed address write location enable -0: Disable -1: Enable - - - Conjugate Sequence data Enable -0: Disable -1: Enable - - - - - Operation length -1 -Default : (511) - - - - - Sequence Memory Start Offset Address - - - - - (This bit is read write 1 clear) -0: No Done -1: Done - - - If Done bit would not clear before this engine re-engine would indicate overwritten output buffer -0: Normal -1: Error - - - Read/Write process in Memory 0/1 (FFT/IFFT input/output memory) -0: Normal -1: Error -Bit 0: DSP control bus error -Bit 1: accelerator memory access collusion - - - Read/Write process in Memory 5 (Copied FFT memory) - - - Read process in Memory 4 (Sequence memory) - - - 0: Normal -1: Error - - - - - - Fine IFFT START -A pulse to grigger the Fine IFFT - - - - - NPRS Coarse Timing Result -Range is from 0 to 272 - - - Fine IFFT calculation offset. Range is from 0 to 95. - - - Fine IFFT calculation length. Range is from 1 to 96. - - - - - Fine IFFT output a+bj scaling -3d0:x2^0(default) -3d1:x2^-1 -3d2:x2^-2 -3d3:x2^-3 -3d4:x2^-4 -3d5:x2^-5 -3d6:x2^-6 -3d7:x2^-7 - - - Fine IFFT output power scaling -3d0:x2^-3 -3d1:x2^-2 -3d2:x2^-1 -3d3:x2^0 (default) -3d4:x2^1 -3d5:x2^2 -3d6:x2^3 -3d7:x2^4 - - - Fine IFFT output selection -1b0: Output IFFT result: a+bj -1b1: Output power result: a^2+b^2 - - - Fine IFFT input data control -1b0: Input data in inverse order -1b1: Input data in inverse order and swap bit0~bit255 with bit256~bit511 - - - - - Fine IFFT input data start address - - - - - Fine IFFT output data start address - - - - - Fine IFFT calculation done status. -1b1: Fine IFFT calculation done -1b0: Fine IFFT is idle or under calculating - - - Fine IFFT output buffer status -1b1: Fine IFFT output buffer is over written -1b0: Fine IFFT output buffer is normal - - - Fine IFFT calculation done status. -1b1: Fine IFFT calculation done -1b0: Fine IFFT is idle or under calculating - - - - - - - - - Maximum time out value for TX channel-interleaver and scrambling in 61.44Mhz unit. - - - Start control: - 0: Trigger by SW start - 1: Trigger by HW start. - - - Channel interleaver enable - 0: Disable - 1: Enable. - - - Scramble enable - 0: Disable - 1: Enable. - - - - - TX channel-interleaver and scrambling accelerator 2 start. - - - - - Bit selection memory start address. - - - Scramble memory start output address. - - - - - Ncb minus NCB - 3ND. - - - K0 minus: K0 position without dummy bit.. - - - - - Row size for ch-interleaver. - - - Modulation type - 0: BPSK - 1: QPSK. - - - Column size in each resource unit: - (NUL_sym-1)* Nul_slot. - - - - - scrambling size in current subframe. - - - - - scrambling X1. - - - - - scrambling X2. - - - - - Last scrambling state in X1. - - - - - Last scrambling state in X2. - - - - - (This bit is read write 1 clear) - 0: No Done - 1: Done. - - - If Done bit would not clear before this engine re-engine would indicate overwritten output buffer - 0: Normal - 1: Error - - - 0: Normal - 1: Error - Bit 0: DSP control bus error - Bit 1: accelerator memory access collusion - - - 0: Normal - 1: Error - - - - - - - - - PUSCH offset1 for 3.75K process delay - - - PUSCH offset0 for 15K process delay - - - PRACH offset for process delay - - - - - TA Value - - - - - the advance time of PRACH start adjustment - - - - - RF delay from NBIOT_CORE to chip output - - - - - PUSCH Enable - - - PRACH Enable - - - - - Delta CP adjustment - - - - - TX frame mode for PUSCH - - - Module type - - - TX Buffer idx - - - CP length of PRACH0/1 - - - PUSCH Tone mode - - - Shorten PUSCH Enable - - - PUSCH Subcarrier POsition - - - - - TX Gain - - - - - thetal symbol incremental step value - - - symbol number modulo 2 - - - - - memory bus access error - - - TX Status, 2'b00: IDLE; 2'b01: PRACH; 2'b10: PUSCH 3.75K; 2'b11: PUSCH 15K - - - Subframe index of NPRACH or NPUSCH transmitted - - - - - - PRACH sub-carrier index 0~47 - - - Reserved - - - PRACH CFG Status - - - Next PRACH symbol group enabled - - - - - PRACH sub-carrier index 0~47 - - - Reserved - - - PRACH CFG Status - - - Next PRACH symbol group enabled - - - - - PRACH sub-carrier index 0~47 - - - Reserved - - - PRACH CFG Status - - - Next PRACH symbol group enabled - - - - - PRACH sub-carrier index 0~47 - - - Reserved - - - PRACH CFG Status - - - Next PRACH symbol group enabled - - - - - PRACH Nxt Command Read Pointer - - - Reserved - - - - - LPF1 coefficient0 - - - LPF1 coefficient1 - - - - - LPF1 coefficient2 - - - LPF1 coefficient3 - - - - - LPF2 coefficient0 - - - LPF2 coefficient1 - - - - - LPF2 coefficient2 - - - - - TX dout checksum - - - TX dout Checksum Enable - - - - - Configurable Number of zero data padded at the end of TX transmission - - - - - - - - - Maximum time out value for pusch encoder in 61.44Mhz unit. - - - Endian SWAP control for bit, byte and word. - - - - - Write this register will trigger pusch encoder start - - - - - TB Size for PUSCH. - - - - - Alpha init value for QPP interleaver. - - - - - Alpha Step value for QPP interleaver. - - - - - Rd address to DSP memory for pusch encoder. - - - - - WR address to DSP memory for pusch encoder. - - - - - (This bit is read write 1 clear) - 0: No Done - 1: Done. - - - Indicate overwritten happen for pusch encoder - 0: Normal - 1: Error - - - Bit 0: DSP control bus error, 0-Normal, 1-Error - Bit 1: accelerator memory access collusion, 0-Normal, 1-Error - - - 0: Normal - 1: Error - - - - - - - - - Start trigger of one sequential decoding of viterbi decoder which is generated by writing 1 to this register - - - - - Payload size of CBs to be decoded in one sequential decoding - - - Indicate the number(1~4) of coded blocks to be decoded in one sequential decoding process - - - Function of de-interleaving in hardware enable/disable - 1: Enable - 0: Disable - - - CRC mask checking enable/disable(for RNTI and antenna port number) - 1: Enable - 0: Disable - - - Indicate the CRC type of sequential decoding - 1:24 - 0:16 - - - List viterbi mode enable/disable - 1: Enable - 0: Disable - - - - - This register indicates the start address of viterbi output odd buffer for payload. - - - This register indicates the start address of viterbi output even buffer for payload. - - - This register indicates the start address of data in viterbi input ram. - - - - - Indicate CRC mask1(for RNTI and antenna port number) - - - Indicate CRC mask0(for RNTI and antenna port number) - - - - - Indicate CRC mask1(for RNTI and antenna port number) - - - Indicate CRC mask0(for RNTI and antenna port number) - - - - - Reorder the 32bit data written to viterbi output buffer - 2:Reverse the word sequence in the Dword(1Dword) - 1: Reverse the byte sequence in every word(2words). - 0: Reverse the bit sequence in every byte(4bytes). - - - In a sequential decoding process, if the corresponding time counter exceeds this set value of rVD_TIMECNT_LIMIT, bit4 of rVD_DEC_SATUS will be set to 1 and sent to high layer. - - - - - - Indicate even/odd viterbi output buffer to be written by decoder: -1: odd output buffer -0: even output buffer - - - - - Bit width of output scaling data's fractional part(S8.y) - - - Bit width of input scaling data's fractional part(S16.x) - - - This register(U8.7) is multiplied by scaling input data(S16.x) - - - Bitmap of CRC masks(0~3) used in blind decoding for the CB3 to be decoded - - - Bitmap of CRC masks(0~3) used in blind decoding for the CB2 to be decoded - - - Bitmap of CRC masks(0~3) used in blind decoding for the CB1 to be decoded - - - Bitmap of CRC masks(0~3) used in blind decoding for the CB0 to be decoded - - - - - Subframe index of current subframe on which DSP configure the decoding start siganl 'rVD_DEC_START' - - - 15: Antenna number for candidate CB3(0: 1 antenna 1: 2 antennas) -14:12: 80ms SFN for candidate CB3 - - - 15: Antenna number for candidate CB2(0: 1 antenna 1: 2 antennas) -14:12: 80ms SFN for candidate CB2 - - - 15: Antenna number for candidate CB1(0: 1 antenna 1: 2 antennas) -14:12: 80ms SFN for candidate CB1 - - - 15: Antenna number for candidate CB0(0: 1 antenna 1: 2 antennas) -14:12: 80ms SFN for candidate CB0 - - - - - - CRC checking result of the corresponding code block for output buffer odd, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. -1: good 0: fail -If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB - [31:28] for CB3(28:MASK0, 29:MASK1, 30:MASK2, 31:MASK3) - [27:24] for CB2(24:MASK0, 25: MASK1, 26: MASK2, 27: MASK3) - [23:20] for CB1(20: MASK0, 21: MASK1, 22: MASK2, 23: MASK3) - [19:16] for CB0(16: MASK0, 17: MASK1, 18: MASK2, 19: MASK3) -And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB - [28] for CB3 - [24] for CB2 - [20] for CB1 - [16] for CB0 - - - CRC check result of the corresponding code block for output buffer even, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. -1: good 0: fail -If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB - [15:12] for CB3(12: MASK0, 13: MASK1, 14: MASK2, 15: MASK3) - [11:8] for CB2(8: MASK0, 9: MASK1, 10: MASK2, 11: MASK3) - [7:4] for CB1(4: MASK0, 5: MASK1, 6: MASK2, 7: MASK3) - [3:0] for CB0(0: MASK0, 1: MASK1, 2: MASK2, 3: MASK3) -And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB - [12] for CB3 - [8] for CB2 - [4] for CB1 - [0] for CB0 - - - - - Symbol error number of the candidate CB1 - - - Symbol error number of the candidate CB0 - - - - - Symbol error number of the candidate CB1 - - - Symbol error number of the candidate CB0 - - - - - Symbol error number of the candidate CB1 - - - Symbol error number of the candidate CB0 - - - - - Symbol error number of the candidate CB1 - - - Symbol error number of the candidate CB0 - - - - - Report some configurations to MCU for output buffer even - [31:20] Report payload size - [19:0] Report configuration of register rVD_CANDI_CFG - - - - - Report some configurations to MCU for output buffer even - [31:20] Report payload size - [19:0] Report configuration of register rVD_CANDI_CFG - - - - - Viterbi-in ram reading error - - - Viterbi output buffer writing error - - - This bit indicate that the time counter is exceed the limit of set value - - - 3: This bit is to indicate that the odd memory is overwritten or not before UPDATED is cleared. -2: This bit is to indicate that the even memory is overwritten or not before UPDATED is cleared. - - - 1: This bit is to indicate that the odd memory is updated or not. -0: This bit is to indicate that the even memory is updated or not. - - - - - - - - - - int clear int[15:0] - - - - - int clear int[31:16] - - - - - read only irq[15:0] - - - - - read only irq[31:16] - - - - - - AFC PLL rxpll freq offset[15:0] - - - - - AFC PLL rxpll freq offset[23:16] - - - AFC PLL txpll freq offset[23:16] - - - - - AFC PLL txpll freq offset[15:0] - - - - - AFC PLL txpll1 freq offset[15:0] - - - - - AFC PLL bbpll1 freq offset[23:16] - - - AFC PLL bbpll2 freq offset[23:16] - - - - - AFC PLL bbpll2 freq offset[15:0] - - - - - AFC freq offset mode - - - AFC freq offset mode - - - AFC freq offset mode - - - AFC freq offset mode - - - - - - sdm rxpll - - - sdm rxpll - - - sdm rxpll - - - - - sdm rxpll freq_rxsdm[15:0] frequency dividing ratio for rxpll_div_bb[5:0] - - - - - sdm rxpll freq_rxsdm[31:16] frequency dividing ratio for rxpll_div_bb[5:0] - - - - - sdm rxpll - - - sdm rxpll - - - sdm rxpll 00: int divide; 01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm - - - sdm rxpll - - - sdm rxpll - - - - - sdm rxpll reserved_sdm_rxsdm - - - - - - sdm rxpll - - - - - sdm txpll - - - sdm rxpll - - - - - indication of dll_mode_txsdm being updated. write it to 1'b0 before assert it to 1'b1 - - - sdm txpll - - - sdm txpll - - - indication feedback clock frequency: - 2'b00: 182MHz, div 7 - 2'b01: 208MHz, div 8 - 2'b10: 234MHz, div 9 - 2'b11: 260MHz, div 10 - - - - - sdm txpll - - - sdm txpll - - - sdm txpll 00: int divide; 01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm - - - sdm txpll - - - sdm txpll - - - - - sdm txpll reserved_sdm_txsdm - - - - - - sdm txpll - - - - - bbpll1 - - - - - bbpll2 - - - bbpll1 - - - - - bbpll2 - - - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll1 pll_reserved_rx - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll1 pll_reserved_dig_1_rx regplls1_0_bit - - - - - bbpll1 pll_sdm_freq_rx[31:16] - - - - - bbpll1 pll_sdm_freq_rx[15:0] - - - - - bbpll1 reserved_sdm_rx - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll1 - - - bbpll1 - - - - - bbpll1 pll_reserved_dig_2_rx - - - - - bbpll1 - - - bbpll1 - - - - - - - - - bbpll1 plls1_clk_cp26m_en,plls1_clk_cp624m_en,plls1_clk_sdio156m_en,plls1_clk_sdio416m_en - - - bbpll1 - - - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - bbpll1 - - - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - bbpll2 pll_reserved_tx - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - bbpll2 pll_reserved_dig_1_tx regplls2_0_bit - - - - - bbpll2 pll_sdm_freq_tx[31:16] - - - - - bbpll2 pll_sdm_freq_tx[15:0] - - - - - bbpll2 reserved_sdm_tx - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - bbpll2 - - - bbpll2 - - - - - bbpll2 pll_reserved_dig_2_tx - - - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 [1] plls2_clk_cp307m_en - - - bbpll2 - - - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - bbpll2 - - - - - rxpll_cal target freq][15:8] - - - rxpll_cal target freq[7:0] - - - - - rxpll_cal [2:0]:rxpll_vco_bits[10:8] [6]:rxpll_cnt_enable [7]:rxpll_cal_enable - - - rxpll_cal reset - - - rxpll_cal [1]:rxpll_cal_opt [3:2]:rxpll_cnt_delay_sel [6:4]:rxpll_init_delay - - - - - rxpll_cal - - - rxpll_cal [7:0]:rxpll_vco_bits[7:0] - - - - - rxpll_cal - - - rxpll_cal - - - rxpll_cal - - - rxpll_cal rxvco_band_bit_bb - - - - - txpll_cal target freq][15:8] - - - txpll_cal target freq[7:0] - - - - - txpll_cal [2:0]:txpll_vco_bits[10:8] [6]:txpll_cnt_enable [7]:txpll_cal_enable - - - txpll_cal reset - - - txpll_cal [1]:txpll_cal_opt [3:2]:txpll_cnt_delay_sel [6:4]:txpll_init_delay - - - - - txpll_cal - - - txpll_cal [7:0]:txpll_vco_bits[7:0] - - - - - txpll_cal - - - txpll_cal - - - txpll_cal - - - txpll_cal txvco_band_bit_bb - - - - - gpio - - - - - - pa strobe - - - pa strobe - - - pa strobe - - - pa strobe - - - pa strobe - - - pa strobe - - - - - pa ctrl - - - pa ctrl - - - pa ctrl - - - pa ctrl - - - - - pa ctrl - - - pa ctrl - - - - - pa ctrl - - - pa ctrl - - - - - pa ctrl - - - pa ctrl - - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl ????? - - - - - ana ctrl ????? - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - ana ctrl - - - - - - controller rf - - - controller rf - - - controller rf - - - - - controller rf - - - controller rf - - - controller rf - - - controller rf - - - controller rf - - - controller rf - - - controller rf - - - - - controller rf - - - - - controller rf - - - - - controller rf - - - - - clk gen - - - clk gen - - - clk gen - - - clk gen - - - clk gen - - - - - clk gen - - - clk gen - - - clk gen - - - - - clk gen - - - clk gen - - - - - - chip id - - - - - chip id - - - - - revision_id - - - - - mean_dccal_i0 - - - - - mean_dccal_i1 - - - - - mean_dccal_q - - - - - bbpll2 - - - bbpll1 - - - - - - analogy - - - - - analogy - - - - - analogy - - - - - analogy - - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa ramp - - - pa ramp - - - - - pa_on_h direct value - - - pa_on_h direct control, assert high - - - threashold - - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - sys ctrl - - - - - DLPF vco band bit enable - 0: TXPLL vco band bit is from pll_cal - 1: TXPLL vco band bit is from DLPF - - - reset DLPF IIR3, active low - - - reset DLPF, active low - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cmd_mipi_sr[15:0] - - - - - cmd_mipi_sr[31:16] - - - - - data_mipi_sr[15:0] - - - - - data_mipi_sr[31:16] - - - - - data_out[15:0] - - - - - data_out[31:16] - - - - - REVERSED - - - data_valid_byte[3:0] - - - - - - - - - interrupt enable - - - - - interrupt pending - - - - - bit type is changed from w1s to rs. - set interrupt pending - - - - - bit type is changed from w1c to rc. - clear interrupt pending - - - - - - - - - Enable sleep - - - - - sleep stauts -0: not_sleep -1: sleep - - - - - - - - - when 1 written,core enters debug mode, when 0 written, core exits debug mode -when read, 1 means core is in debug mode - - - single step enable - - - - - set when the core is a sleeping state and wait for an event - - - single-step hit, sticky bit that must be cleared by external debugger - - - - - environment call for M-mode - - - store access fault (together with laf) - - - store address Misaligned (never traps) - - - load access fault (together with saf) - - - load access Misaligned (never traps) - - - ebreak instruction causes trap - - - illegal instruction - - - instruction access fault (not implemented) - - - instruction address misaligned (never traps) - - - - - interrupt caused us to enter debug mode - - - exception/interrupt number - - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - - Next PC to be executed - - - - - previous PC, already executed - - - - - - Statically 2'b11 and cannot be altered - - - Interrupt enable: -When an exception is encountered, Interrupt Enable will be set to 1'b0. -When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS. -If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code. - - - - - - When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. -When an eret instruction is executed, the value from MEPC replaces the current program counter. - - - - - this bit is set when the exception was triggerd by an interrupt - - - exception code - - - - - - hardware loop 0 start - - - - - hardware loop 0 end - - - - - hardware loop 0 counter - - - - - - hardware loop 1 start - - - - - hardware loop 1 end - - - - - hardware loop 1 counter - - - - - - Statically 2'b11 and cannot be altered - - - Interrupt enable: -When an exception is encountered, the current value of MSTATUS is saved in MESTATUS. -When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register. - - - - - - read as 0, which means RV32I - - - RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0. - - - - - - - - - - - - ID of the cluster - - - ID of the within the cluster - - - - - - - - - - [8]enable_clk_dac_afc; -[9]dac_afc_bit select dig_rtc reg; -[10]dig_afc_bit_dr; -[13]step_offset_update; - - - [0]vcore_vrtc_pwr_sel source select 0:vcore_vrtc_pwr_sel reg; 1:pu_xtal from IDLE_UART -[1]pu_xtal_ana source select 0: pu_xtal_rtc from IDLE_UART; 1:pu_xtal reg -[6]pu_xtal reg 0:pull down XTAL enter LP mode; 1:pull up XTAL enter normal mode -[7]vcore_vrtc_pwr_sel reg 0: Vrtc power 1: Vcore power - - - - - - RTC - - - [2]enable_clk26m_lp -[6]idle_uart sw resetn 0:reset 1:release reset - - - - - RTC - - - RTC - - - - - [9:8]lp_mode delay pu_xtal cycle select 2'b00: 4us; 2'b01:8us; 2'b10:12us; 2'b11:20us - - - RTC - - - - - - - 32k gen div step_offset LP mode - - - - - 32k gen div step_offset Normal mode - - - [5]lp_mode_en_dr; -[4]lp_mode_en_reg; -[7]change_reg_flag_dr; -[6]change_reg_flag_reg; -[3]lp_mode_h_dr; -[2]lp_mode_h_reg; - - - - - to XTAL for input clk_26m enable - - - CAFC - - - - - BBPLL2 ref clk 26m enable - - - BBPLL1 ref clk 26m enable - - - tsxadc clk 26m enable - - - XTAL parameter - - - pwdadc clk 26m enable - - - xtal_osc_ibit lp mode - - - xtal_osc_ibit normal mode - - - - - RFPLL refcal clk 26m - - - oscadc clk 26m enable - - - xtal_fixi_bit lp mode - - - xtal_fixi_bit normal mode - - - - - pmic clk 26m enable - - - clk_26m_interface enable - - - xdrv pmic parameter - - - xdrv aux2 parameter - - - xdrv aux1 parameter - - - xdrv parameter - - - - - xtal_hsel lp mode - - - CADC bit lp mode - - - xtal_hsel normal mode - - - CADC bit normal mode - - - - - RTC - - - - - RTC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - for TXDP modules after RC -0: use unmasked 61.44MHz clk when polarIQ disabled -1: use 26m_fbc clk when polarIQ enabled - - - 1: use external resetn, 0-use sw/enable generated internal resetn for rxdp - - - 0: clk_dac -1: clk_dac invert - - - 0: clk_adc -1: clk_adc invert - - - 0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT, 9:eMTC - - - 0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT - - - 0: SDM mode -1: SAR mode - - - 0:26M/30.72MHz -1:52M/61.44MHz -2:104M/122.88MHz - - - 0: ZF mode -1: IF mode - - - - - 0: registers module clk gating enabled; 1: registers module clk always on - - - 0: RX CIC1 doesn't work in loft mode; 1: RX CIC1 works in loft mode - - - reset for ET, active low - - - clock enable for ET - - - sw controlled resetn for rxdp -0: assert reset -1: not reset - - - DFE clock shift control. -0: clock shift disabled -1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency - - - clock enable for BB GGE @26MHz - - - clock enable for BB LTE @122.88MHz - - - clock enable for BB NB/WT @61.44MHz - - - clock enable for DFE NB/WT/LTE TX - - - clock enable for DFE GSM TX - - - clock enable for DFE RX - - - clock enable for DAC - - - clock eanble for ADC - - - - - Start to load DC value, active high. Before next load, set it low firstly - - - IQ swap in DC module -0: no swap -1. swap - - - Hold DC accumulator calculation in DC calibration mode - - - This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc - - - Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. - - - Load DC value in calibration mode to debug port, only used for debug purpose - - - DC module work mode. -0: DC calibration mode -1: DC cancel mode - - - - - DC real part value used in cancel mode - - - - - DC image part value used in cancel mode - - - - - Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register - - - - - Slow convergence control, work with conv_mode_ct_rg register - - - Fast convergence control, work with conv_mode_ct_rg register - - - Duration time of DC calibration, which is based on sample unit - - - DC convergence loop mode selection. -0: fast -1: slow -2: fast->slow -3: fast->hold - - - - - load rxdp_gain_ct to DFE. Write it to 1b'0 before assert it - - - bypass rxdp_gain_ct_load - - - Gain BB control. [-24db, 47.9375db], step=1/16db - - - - - - Bit [15:0] of RX group delay coefficient 0 - - - - - Bit [19:16] of RX group delay coefficient 0 - - - - - Bit [15:0] of RX group delay coefficient 1 - - - - - Bit [19:16] of RX group delay coefficient 1 - - - - - Bit [15:0] of RX group delay coefficient 2 - - - - - Bit [19:16] of RX group delay coefficient 2 - - - - - Bit [15:0] of RX group delay coefficient 3 - - - - - 1: LP -0: BP - - - Bit [19:16] of RX group delay coefficient 3 - - - - - Read rate of DFE ADC FIFO, which depends on RX mode. -5'h00: GGE -5'h01: NB/WT - - - Write enable of DFE ADC FIFO, active high - - - - - - Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high - - - - - Real part of DC value, it is stable when rxdp_dcc_val_reg is high - - - - - Image part of DC value, it is stable when rxdp_dcc_val_reg is high - - - - - Data enable of Notch DC -0: disable -1: enable - - - - - - - Coefficient a for real part of Notch DC - - - - - Coefficient a for image part of Notch DC - - - - - Coefficient k of Notch DC - - - - - mrrm bandwidth selection - - - - - Data enable of Notch H 1st core -0: disable -1: enable - - - Data enable of Notch H 2nd core -0: disable -1: enable - - - - - Coefficient a for real part of Notch H 1st core - - - - - Coefficient a for image part of Notch H 1st core - - - - - Coefficient a for real part of Notch H 2nd core - - - - - Coefficient a for image part of Notch H 2nd core - - - - - Coefficient k of Notch H 1st core - - - Coefficient k of Notch H 2nd core - - - - - Coefficient COEF0 of ACI filter - - - - - Coefficient COEF1 of ACI filter - - - - - Coefficient COEF2 of ACI filter - - - - - Coefficient COEF3 of ACI filter - - - - - Coefficient COEF4 of ACI filter - - - - - Coefficient COEF5 of ACI filter - - - - - Coefficient COEF6 of ACI filter - - - - - Coefficient COEF7 of ACI filter - - - - - Coefficient COEF8 of ACI filter - - - - - Coefficient COEF9 of ACI filter - - - - - Coefficient COEF10 of ACI filter - - - - - Coefficient COEF11 of ACI filter - - - - - Coefficient COEF12 of ACI filter - - - - - Coefficient COEF13 of ACI filter - - - - - Coefficient COEF14 of ACI filter - - - - - Coefficient COEF15 of ACI filter - - - - - Coefficient COEF16 of ACI filter - - - - - Coefficient COEF17 of ACI filter - - - - - Coefficient COEF18 of ACI filter - - - - - Coefficient COEF19 of ACI filter - - - - - Coefficient COEF20 of ACI filter - - - - - Coefficient COEF21 of ACI filter - - - - - Coefficient COEF22 of ACI filter - - - - - Coefficient COEF23 of ACI filter - - - - - Bit [15:0] of frequency offset for Mixer - - - - - Bit [23:16] of frequency offset for Mixer - - - - - Outband RSSI enable - - - Inband RSSI enable - - - Outband RSSI ushift value - - - Inband RSSI ushift value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - delay count to discard some initial samples - - - sample select in 12x data rate - - - sample number per symbol -0: 541K, 2x -1: 1.08M, 4x - - - - - sample select in 192K data rate - - - 0: 192K -1: 96K=192K/2 -2: 64K=192K/3 -.... -15: 12K=192K/16 - - - sel CIC2 mode -00: mode0, divided by 40, 96K -01: mode1, divided by 20, 192K -10/11: mode2, divided by 10, 384K - - - - - load rxdp_gain_ct_rf to DFE. Write it to 1b'0 before assert it - - - bypass rxdp_gain_ct_rf_load - - - Gain RF control. [-24db, 47.9375db], step=1/16db - - - - - start inband RSSI max and min measurement - - - - - timer count[15:0] for max and min measurement report after start - - - - - timer count[31:16] for max and min measurement report after start - - - - - start to load max and min measurement report. Before next load, set it low firstly - - - - - valid of max and min measurement report - - - inband RSSI min value - - - - - inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high - - - - - interrupt status to be able to start to load max and min measurement report - - - interrupt mask - - - interrupt clear - - - - - indication to read instant measurement report - - - - - valid of instant measurement report - - - - - inband RSSI instant value - - - - - start outband RSSI max and min measurement - - - - - timer count[15:0] for max and min measurement report after start - - - - - timer count[31:16] for max and min measurement report after start - - - - - indication to read max and min measurement report - - - - - valid of max and min measurement report - - - - - outband RSSI min value - - - - - outband RSSI max value - - - - - interrupt status to be able to start to load max and min measurement report - - - interrupt mask - - - interrupt clear - - - - - indication to read instant measurement report - - - - - valid of instant measurement report - - - - - outband RSSI instant value for WD - - - - - outband RSSI instant value for UP - - - - - outband RSSI instant value for DN - - - - - delay counter for rx_en - - - RX IQ swap - - - RX clock invert or not - - - enable digrf RX - - - - - delay counter for tx_data - - - TX clock invert or not - - - TX mode. -0: block mode -1: stream mode - - - - - Interp. HBF1 -0: SW bypass disable -1: SW bypass enable - - - Gain_BB - - - Notrch(H) 2nd core - - - Notrch(H) 1st core - - - Deci. HBF1 - - - ACI Filter - - - No use - - - Gain_RF - - - Group Delay Equ - - - No use - - - Notch(DC) - - - Mixer - - - RC - - - Deci.CIC2 - - - DC Calib.&Cancel - - - Deci.CIC1 - - - - - dnhb2 - - - imbc - - - mrrm - - - No use - - - deci_digrf - - - Interp. HBF3 - - - Interp. HBF2 - - - - - Interp. HBF1 -0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement -1: bypass controlled by SW. When it is set, rxdp_bypass_uphb1 will be used - - - Gain_BB - - - Notrch(H) 2nd core - - - Notrch(H) 1st core - - - Deci. HBF1 - - - ACI Filter - - - No use - - - Gain_RF - - - Group Delay Equ - - - No use - - - Notch(DC) - - - Mixer - - - RC - - - Deci.CIC2 - - - DC Calib.&Cancel - - - Deci.CIC1 - - - - - dnhb2 - - - imbc - - - mrrm - - - No use - - - deci_digrf - - - Interp. HBF3 - - - Interp. HBF2 - - - - - instant value of rxdp_dcc_re - - - - - instant value of rxdp_dcc_im - - - - - instant value of rssi_reg_ib_rssi - - - - - instant value of rssi_reg_wd_ob_rssi - - - - - instant value of rssi_reg_up_ob_rssi - - - - - instant value of rssi_reg_dn_ob_rssi - - - - - instant value of rxdp_imbc_wa_out - - - - - instant value of rxdp_imbc_wq_out - - - - - - Coefficient a1 for PLL Equ. - - - - - Coefficient a2 for PLL Equ. - - - - - Coefficient b1 for PLL Equ. - - - - - Coefficient b2 for PLL Equ. - - - - - Bit [27:12] of gain for PLL Equ. It is valid when AFC adjustment is being enabled - - - - - Bypass load_g: -0: disable bypass -1: enable bypass - - - Bypass PLL Equ: -0: disable bypass -1: enable bypass - - - - - No use - - - 4 LSB control - - - Former output shift control - - - - - No use - - - - - no use - - - - - Bit [34:32] for GSM TX frequency - - - use former output or not -0: RX don't use -1: TX use - - - - - Bit [15:0] for GSM TX frequency - - - - - Bit [31:16] for GSM TX frequency - - - - - Offset add to GSM TX frequency - - - - - - Output control for TX SDM frequency -0: freqency from register -1: freqency from psdm, used by GSM or polarIQ - - - No use - - - No use - - - No use - - - No use - - - GSM TX frequency control. -0: modulation signal act on GSM TX freqency -1: GSM TX freqency is fixed - - - - - GSM TX frequency load is at the same time of AFC adjustment or not -0: at the same time -1: not at the same time - - - Clear bit for read point of GSM TX FIFO - - - Clear bit for write point of GSM TX FIFO - - - PN test enable - - - - - The mode of pseudo random polynomial - - - - - The initial phase selection of differential encoding - - - The differential encoding enable for GSM TX data - - - - - Bit [11:0] of gain for PLL Equ. It works with register txdp_gsm_g_rg - - - - - txdp polar1 delay - - - txdp polar0 delay - - - - - gsm_grp_dly_coff1_rg[15:0] - - - - - gsm_grp_dly_coff1_rg[19:16] - - - - - gsm_grp_dly_coff2_rg[15:0] - - - - - gsm_grp_dly_coff2_rg[19:16] - - - - - gsm_grp_dly_coff3_rg[15:0] - - - - - gsm_grp_dly_coff3_rg[19:16] - - - - - gsm_grp_dly_coff4_rg[15:0] - - - - - gsm_grp_dly_coff4_rg[19:16] - - - - - register value from GSM upper and low branch - - - - - position of txdp_gdequ(2) in txdp_gsm -0: upper branch -1: low branch - - - MDLL mode: -0: 26MHz*7 -1: 26MHz*8 -2: 26MHz*9 -3: 26MHz*10 - - - upper branch enable in txdp_gsm for 2P modulation - - - bypass txdp_uplpf(2) in txdp_gsm - - - load gsm_grp_dly_in_rg to DFE, assert it to load. Before load, write it to low firstly - - - input mode for upper and low branch: -0: from DFE register, gsm_grp_dly_in_rg -1: from DFE function - - - bypass txdp_gdequ(2) in txdp_gsm - - - - - vco_gain for upper branch - - - - - register value for data_pm_dac[15:0] - - - - - bypass for data_pm_dac: -0: data_pm_dac from DFE function -1: data_pm_dac from DFE regsiter - - - register value for data_pm_dac[30:16] - - - - - - load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it - - - bypass txdp_wedge_gain_ct_load - - - Gain control of NB/WT TX. [-24db, 47.9375db], step=1/16db - - - - - - - - - - - - - - - - - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Amplitude compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - Phase compensation curve of DPD - - - - - - Coefficient 4 of ACLR filter - - - - - Coefficient 5 of ACLR filter - - - - - Coefficient 6 of ACLR filter - - - - - Coefficient 7 of ACLR filter - - - - - - divide resource of clk_dac when test mode. -0: divide by 1 -1: divide by 2 -2: divide by 4 -3: divide by 8 -4: divide by 16 -5: divide by 32 -6: divide by 64 -7: divide by 128 -8: divide by 256 -default: divide by 1 - - - resource of clk_dac when test mode. -00: clk_26m -01: clk_245p76m -10: clk_fbc -11: clk_adc_gge_nb - - - enable clk_dac when test mode - - - 0: clk_dac is from function mode -1: clk_dac is from test mode - - - - - txdp iq delay - - - - - Coefficient 0 of ACLR filter - - - - - Coefficient 1 of ACLR filter - - - - - Coefficient 2 of ACLR filter - - - - - Coefficient 3 of ACLR filter - - - - - Bit [15:0] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [19:16] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [15:0] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [19:16] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [15:0] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [19:16] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [15:0] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX - - - - - Bit [19:16] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX - - - - - value to be delayed for phase part - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - no use - - - no use - - - no use - - - - - no use - - - no use - - - - - - - - - - - - - - - - - - - - - - - BB TX data loopback to BB RX - - - BB RX IQ swap. 1: swap; 0: normal - - - BB TX IQ swap. 1: swap; 0: normal - - - ADC IQ swap. 1: swap; 0: normal - - - DAC IQ swap. 1: swap; 0: normal - - - BB RX. 0: two's complement 1: offset binary - - - BB TX. 0: two's complement 1: offset binary - - - RF ADC. 0: two's complement 1: offset binary - - - RF DAC. 0: two's complement 1: offset binary - - - - - instant value of txdp_loft_rssi_err - - - - - - valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high - - - start to load the result of temper_dout. Before next load, set it low firstly - - - - - bandwidth select - - - no use - - - - - - - - - temper_dout value - - - - - clock enable for temper - - - divide mode of clock from analog for Temcomp -0: not divide -1: 1/2 divide -2: 1/4 divide -3: 1/8 divide - - - clock invert for Temcomp -0: clock invert disable -1: clock invert enable - - - clock enable for temcomp - - - divide mode of clock from analog for Temcomp -0: not divide -1: 1/2 divide -2: 1/4 divide -3: 1/8 divide - - - clock invert for Temcomp -0: clock invert disable -1: clock invert enable - - - - - force bypass, high valid - - - bypass, high valid - - - no use - - - set sdm frequency value, high valid - - - sdm frequency value, high 8 bits - - - - - sdm frequency value, low 16 bits - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - Coefficient of filter - - - - - valid indication of temcom_pwd_dout after assert temcom_pout_load to avoid metastability. The temcom_pwd_dout is stable when this register is high - - - start to load the result of thermometer. Before next load, set it low firstly - - - temperature calibration LPF bypass, high valid - - - temperature calibration LPF shift value -0 : left shift by 7 bit -1 : left shift by 6 bit -2 : left shift by 5 bit -3 : left shift by 4 bit -4 : left shift by 3 bit -5 : left shift by 2 bit -6 : left shift by 1 bit -7 : left shift by 0 bit - - - select badwidth - - - no use - - - no use - - - - - temcom result - - - - - instant value of temper_dout - - - - - instant value of temcom_pwd_dout - - - - - - - - - swap of dfe_monitor[15:8] and dfe_monitor[7:0] - - - dfe_monitor select - - - - - The offset on DAC real part - - - - - The offset on DAC image part - - - - - The DAC real part on test mode - - - - - The DAC image part on test mode - - - - - Interp.CIC2 config mode for WT: -000: 60, 16K to 960K -001: 30, 32K to 960K -010: 25, 38.4K to 960K -011: 10, 96K to 960K -others: 5, 192K to 960K - - - - - select of function DAC data or test DAC data -00/01: select function DAC data including sine waveform -10: select test DAC data in txdp -11: select test DAC data in txdp - - - enable sine generation module - - - enable of test DAC data in rxdp - - - select of test DAC data in rxdp - - - enable of test DAC data in txdp - - - select of test DAC data in txdp - - - - - sine amp - - - - - sine frequency[15:0] - - - - - LOFT - - - LOFT - - - sine frequence[22:16] - - - - - UPLPF(1) - - - Interp. CIC1 -0: SW bypass disable -1: SW bypass enable - - - UPHBF(3) - - - UPHBF(2) - - - Group Delay Equ. - - - LPF of DPD only when PolarIQ - - - AMPM of DPD - - - Split of DPD - - - Whole DPD - - - RC - - - Gain - - - UPHBF(5) when PolarIQ - - - UPHBF(4) when PolarIQ - - - UPHBF(1) - - - ACLR LPF - - - ampequ - - - - - UPLPF(1) - - - Interp. CIC1 -0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement -1: bypass controlled by SW. When it is set, txdp_bypass_cic1 will be used - - - UPHBF(3) - - - UPHBF(2) - - - Group Delay Equ. - - - LPF of DPD only when PolarIQ - - - AMPM of DPD - - - Split of DPD - - - Whole DPD - - - RC - - - Gain - - - UPHBF(5) when PolarIQ - - - UPHBF(4) when PolarIQ - - - UPHBF(1) - - - ACLR LPF - - - ampequ - - - - - no use - - - clock enable for BB side when adc-dfe-lvds-bb, enable when lvds_rx_mode is 3 - - - no use - - - clock enable for ADC RX when adc-lvds-dfe-bb, enable when lvds_rx_mode is 1 - - - clock enable for DAC TX when bb-dfe-lvds-dac, enable when lvds_rx_mode is 0 - - - clock enable for lvds_tx, enable when lvds_tx_mode is 0/1/2/3 - - - no use - - - no use - - - no use - - - no use - - - 3: lvds_rx in adc-dfe-lvds-bb -2: lvds_rx in bb-lvds-dfe-dac -1: lvds_rx in adc-lvds-dfe-bb -0: lvds_rx in bb-dfe-lvds-dac - - - 3: lvds_tx in adc-dfe-lvds-bb -2: lvds_tx in bb-lvds-dfe-dac -1: lvds_tx in adc-lvds-dfe-bb -0: lvds_tx in bb-dfe-lvds-dac - - - LVDS enabled in DFE - - - - - frequency select of dfe2lvds_clk when bb-lvds-dfe-dac. -0: 7.68MHz -1: 15.36MHz -2: 30.72MHz -3: 61.44MHz - - - frequency select of dfe2lvds_clk when adc-dfe-lvds-bb. -0: 7.68MHz -1: 15.36MHz -2: 30.72MHz -3: 61.44MHz - - - clock select in BB side when adc-dfe-lvds-bb and bb-lvds-dfe-dac -0: use LVDS clock -1: use BBPLL clock - - - frequency indication of lvds2dfe_clk_dig_ref from LVDS -0: 122.88MHz -1: 61.44MHz - - - iq swap on lvds2dfe_data - - - iq swap on dfe2lvds_data - - - - - all zero bits, reserved for ECO - - - - - all one bits, reserved for ECO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1: clk always on, 0: clk gating by hardware - - - - - 1: clk always on, 0: clk gating by hardware - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1: clk always on, 0: clk gating by hardware - - - - - determine dac bits position when test mode. -0:[11:0], 1:[12:1], 2:[13:2], 3:[14:3], 4: [15:4] - - - - - Bit [11:0] of coefficient 0 of ampequ. for NB/LTE/eMTC TX - - - - - Bit [11:0] of coefficient 1 of ampequ. for NB/LTE/eMTC TX - - - - - Bit [11:0] of coefficient 2 of ampequ. for NB/LTE/eMTC TX - - - - - Bit [11:0] of coefficient 3 of ampequ. for NB/LTE/eMTC TX - - - - - Bit [27:12] of gain for ampequ. for NB/LTE/eMTC TX - - - - - Bit [11:0] of gain for ampequ. It works with register txdp_ampequ_g_rg - - - - - read interval for FIFO A - - - read interval for FIFO B - - - - - read interval for FIFO C - - - read interval for FIFO D - - - - - FIFO dump full - - - FIFO dump empty - - - FIFO txdp_rc full - - - FIFO txdp_rc empty - - - FIFO rxdp_rc full - - - FIFO rxdp_rc empty - - - FIFO ADC full - - - FIFO ADC empty, this FIFO used between ADC and DFE - - - FIFO D full - - - FIFO D empty, this FIFO used when LVDS RX for bb-lvds-dfe-dac - - - FIFO C full - - - FIFO C empty, this FIFO used when normal TX or LVDS TX for bb-lvds-dfe-dac - - - FIFO B full - - - FIFO B empty, this FIFO used when LVDS RX for adc-dfe-lvds-bb - - - FIFO A full - - - FIFO A empty, this FIFO used when normal RX or LVDS TX for adc-dfe-lvds-bb - - - - - - clock frequency select when dump FIFO write -00000000: clk_122p88m_m -00000001: clk_61p44m_m -0000001x: clk_rxdp -000001xx: clk_rxdp_m -00001xxx: clk_txdp -0001xxxx: clk_245p76m_m(i.e., clk_txdp_m) -001xxxxx: lvds2dfe_clk -01xxxxxx: lvds2dfe_clk_dig_ref -1xxxxxxx: clk_pwd - - - clock frequency select when dump FIFO read -0: 122.88Mhz -1: 61.44MHz - - - enable dump - - - dump node selection. It works with register sel_clk_dump_w for correct clock. -0: dump RX data from DFE, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref -1: dump TX data from BB, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref -2: dump RXDP data, sel_clk_dump_w can be clk_rxdp/clk_rxdp_m -3: dump TXDP data, sel_clk_dump_w can be clk_txdp/clk_245p76m_m(clk_txdp_m)/clk_pwd -others: dump data from LVDS, sel_clk_dump_w can be can be lvds2dfe_clk - - - - - - - - - DLPF output clk_rdac enable. -0: disable -1: enable - - - DLPF sdm bypass - - - 1'b0: digital DLPF -1'b1: analog DLPF - - - vco data add enable - - - read vco data from fifo enable - - - vco data write into fifo enable - - - no use - - - register to analog - - - DLPF MDLL mode -0: 26x7MHz -1: 26x8MHz -2: 26x9MHz -3: 26x10MHz - - - DLPF notch bypass - - - DLPF output clock inverse - - - DLPF input clock inverse - - - DLPF lock mode - - - enable DLPF - - - no use - - - - - DLPF output direct control - - - DLPF output direct value - - - - - DLPF afc phase offset - - - - - DLPF kdco phase offset - - - - - DLPF gain kp afc - - - - - DLPF gain ki afc - - - - - DLPF gain kp 2m - - - - - DLPF gain ki 2m - - - - - DLPF gain kp 200k - - - - - DLPF gain ki 200k - - - - - DLPF IIR0 gain0[15:0] - - - - - DLPF IIR0 gain1[15:0] - - - - - DLPF IIR1 gain0[15:0] - - - - - DLPF IIR1 gain1[15:0] - - - - - DLPF IIR1 gain1[16] - - - DLPF IIR1 gain0[16] - - - DLPF IIR0 gain1[16] - - - DLPF IIR0 gain0[16] - - - - - diff_sel[2:0] - - - - - afc_diff_thr[15:0] - - - - - afc_diff_thr[31:16] - - - - - afc_cnt_thr - - - - - lock_2m_diff_thr[15:0] - - - - - lock_2m_diff_thr[31:16] - - - - - lock_2m_cnt_thr - - - - - lock_200k_diff_thr[15:0] - - - - - lock_200k_diff_thr[31:16] - - - - - lock_200k_cnt_thr - - - - - timer0_cnt[15:0] - - - - - timer0_cnt[31:16] - - - - - timer1_cnt[15:0] - - - - - timer1_cnt[31:16] - - - - - timer2_cnt[15:0] - - - - - timer2_cnt[31:16] - - - - - DLPF capture enable to dump internal values - - - - - real time afc_code - - - DLPF detect status - - - - - read time kdco_code - - - - - captured afc_code - - - - - captured kdco_code - - - - - tdc_code - - - - - dlpf_add - - - - - dlpf_gain0[15:0] - - - - - dlpf_gain0[22:16] - - - - - dlpf_gain1[15:0] - - - - - dlpf_gain1[30:16] - - - - - dlpf_sum0[15:0] - - - - - dlpf_sum0[31:16] - - - - - dlpf_sum0[38:32] - - - - - iir0_sum0[15:0] - - - - - iir0_sum0[31:16] - - - - - iir0_sum0[43:32] - - - - - iir0_sum0_reg[15:0] - - - - - iir0_sum0_reg[31:16] - - - - - iir0_sum0_reg[43:32] - - - - - iir0_data[15:0] - - - - - iir0_data[31:0] - - - - - iir1_sum0[15:0] - - - - - iir1_sum0[31:16] - - - - - iir1_sum0[43:32] - - - - - iir1_sum0_reg[15:0] - - - - - iir1_sum0_reg[31:16] - - - - - iir1_sum0_reg[43:32] - - - - - iir1_data[15:0] - - - - - iir1_data[31:16] - - - - - lpf2_data[15:0] - - - - - lpf2_data[31:16] - - - - - DLPF reserved control bit. -[15:3] reserved -[1] IIR2 bypass -[0] IIR1 bypass - - - - - DLPF IIR3 output valid - - - input data select: 1'b0: gro output 1'b1: dlpf notch output - - - load DLPF IIR3 output - - - decimator start point in dnsc - - - bypass 256 dnsc - - - DLPF IIR3 input clock inverse - - - enable DLPF IIR3 - - - reset DLPF IIR3, active low - - - - - a11[15:0] - - - - - a12[15:0] - - - - - a21[15:0] - - - - - a21[19:16] - - - a12[19:16] - - - a11[19:16] - - - - - g1[15:0] - - - - - g2[15:0] - - - - - g2[19:16] - - - g1[19:16] - - - - - IIR3 output - - - - - - - - - input iq_in and clk_in rate ratio - 0: 1:1 - 1: 1:2 - 2: 1:3 - .... - - - input ET_CLK signal: - 0: wide half clk - 1: wide 1 clk - 2: wide 2 clk - ... - 127: wide 127 clk - - - 0: IQ sel IQ_IN[13:2] - 1: IQ sel IQ_IN[12:1] - 2: IQ sel IQ_IN[11:0] - - - - - data to ETAPC frac delay: 1/16 datarate step, 015 - - - data to ETAPC int delay: 2us, 063 - - - - - - - - - - - Q0 - - - - - Q15 - - - - - cic fir enable - - - cic fir enable - - - hb fir enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 : {iq_re , iq_im[11:0] } - 1 : {hb_re , hb_im[11:0] } - 2 : {env_dato , 16'h0 } - 3 : {dlyint_dato , 16'h0 } - 4 : {dlyfrac_dato, 16'h0 } - 5 : {dtr_dato , 16'h0 } - 6 : {iir_dato , 16'h0 } - 7 : {log_dato , 16'h0 } - 8 : {modif_dato , 16'h0 } - 9 : {tpc_dato , 16'h0 } - 10 : {p2v_dato , 16'h0 } - 11 : {volt_dato , 16'h0 } - 12 : {cic1_dato , 16'h0 } - 13 : {notch_dato , 16'h0 } - 14 : {cic2_dato , 16'h0 } - 15 : {clip_dato , 16'h0 } - - - - - 0: hardware auto open clock - 1: software force open clock - - - - - - - - - - - Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. - - - Channel Disable, write one in this bit disable the channel. -When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. - - - Channel Enable, write one in this bit enable the channel. -When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. - - - - - Three Quarter of FIFO interrupt status bit. - - - Quarter of FIFO interrupt status bit. - - - Half of FIFO interrupt status bit. - - - End of FIFO interrupt status bit. - - - Cause interrupt Three Quarter of FIFO. - - - Cause interrupt Quarter of FIFO. - - - Cause interrupt Half of FIFO. - - - Cause interrupt End of FIFO. - - - When 1 the fifo is empty - - - When 1 the channel is enabled - - - - - AHB Start Address. This field represent the start address of the FIFO located in RAM. - - - - - Fifo size in bytes, max 32kBytes. -The size of the fifo must be a multiple of 16 (The four LSB are always zero). - - - - - - - THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - HALF FIFO Mask interrupt. When one this interrupt is enabled. - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - - - bit type is changed from w1c to rc. - Write one to clear Three Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear half of fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear end of fifo interrupt. - - - - - Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. - - - - - Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. - - - Channel Disable, write one in this bit disable the channel. -When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. - - - Channel Enable, write one in this bit enable the channel. -When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. - - - - - Three Quarter of FIFO interrupt status bit. - - - Quarter of FIFO interrupt status bit. - - - Half of FIFO interrupt status bit. - - - End of FIFO interrupt status bit. - - - Cause interrupt Three Quarter of FIFO. - - - Cause interrupt Quarter of FIFO. - - - Cause interrupt Half of FIFO. - - - Cause interrupt End of FIFO. - - - When 1 the fifo is empty - - - When 1 the channel is enabled - - - - - AHB Start Address. This field represent the start address of the FIFO located in RAM. - - - - - Fifo size in bytes, max 32kBytes. -The size of the fifo must be a multiple of 16 (The four LSB are always zero). - - - - - - - THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - HALF FIFO Mask interrupt. When one this interrupt is enabled. - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - - - bit type is changed from w1c to rc. - Write one to clear Three Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear half of fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear end of fifo interrupt. - - - - - Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. - - - - - Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. - - - Channel Disable, write one in this bit disable the channel. -When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. - - - Channel Enable, write one in this bit enable the channel. -When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. - - - - - Three Quarter of FIFO interrupt status bit. - - - Quarter of FIFO interrupt status bit. - - - Half of FIFO interrupt status bit. - - - End of FIFO interrupt status bit. - - - Cause interrupt Three Quarter of FIFO. - - - Cause interrupt Quarter of FIFO. - - - Cause interrupt Half of FIFO. - - - Cause interrupt End of FIFO. - - - When 1 the fifo is empty - - - When 1 the channel is enabled - - - - - AHB Start Address. This field represent the start address of the FIFO located in RAM. - - - - - Fifo size in bytes, max 32kBytes. -The size of the fifo must be a multiple of 16 (The four LSB are always zero). - - - - - - - THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - QUARTER FIFO Mask interrupt. When one this interrupt is enabled. - - - HALF FIFO Mask interrupt. When one this interrupt is enabled. - - - END FIFO Mask interrupt. When one this interrupt is enabled. - - - - - bit type is changed from w1c to rc. - Write one to clear Three Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear Quarter fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear half of fifo interrupt. - - - bit type is changed from w1c to rc. - Write one to clear end of fifo interrupt. - - - - - Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. - - - - - - - - - Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. -In case of Dual Mode implementation, reset also common blocks. - - - Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. - - - Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. -Note that when RFTEST_ABORT is requested - 1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. - 2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. - - - Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. -No action happens if it is written with 0. - - - Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - 0: Normal operation of MD bits management -1: Allow a single Tx/Rx exchange whatever the MD bits are. -- value forced by SW from Tx Descriptor -- value just saved in Rx Descriptor during reception - - - 0: Normal operation of Sequence number -1: Sequence Number Management disabled: -- value forced by SW from Tx Descriptor -- value ignored in Rx -> No SN error reported. - - - 0: Normal operation of Acknowledge -1: Acknowledge scheme disabled: -- value forced by SW from Tx Descriptor -- value ignored in Rx -> No NESN error reported. - - - 0: Normal operation. Encryption / Decryption enabled. -1: Encryption / Decryption disabled. -Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data. - - - 0: Normal operation. Whitening enabled. -1: Whitening disabled. - - - 0: Normal operation. CRC removed from data stream. -1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. - - - 0: Normal operation. Frequency Hopping Remapping algorithm enabled. -1: Frequency Hopping Remapping algorithm disabled - - - Advertising Channels Error Filtering Enable control -0: RW-BLE Core reports all errors to RW-BLE Software -1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software - - - 0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. -1: Enable RW-BLE Core Exchange table pre-fetch mechanism. - - - Default Rx Window size in 2s. Used when device -- is master connected -- performs its second receipt. -0 is not a valid value. Recommended value is 10 (in decimal). - - - Indicates the maximum number of errors allowed to recognize the synchronization word. - - - - - RW-BLE Core Type C 0x8 means BLE v4.2 (i.e. correspond LL version assigned number). Correspond to FS v8.0.10) - - - RW-BLE Core version C Major release number. Correspond to FS v8.0.10 - - - RW-BLE Core upgrade C Upgrade number. Correspond to FS v8.0.10 - - - RW-BLE Core Build C Build number - - - - - 0: RW-BLE Core is used as a standalone BLE device -1: RW-BLE Core is used in a Dual Mode device - - - Number of supported Isochronous Channel (0 to 3) -00: No ISO/Audio Channel available -01: One ISO/Audio Channel available -10: Two ISO/Audio Channels available -11: Three ISO/Audio Channels available - - - 0: AES deciphering not present -1: AES deciphering present - - - 0: WLAN Coexistence mechanism not present -1: WLAN Coexistence mechanism present (Default Value) - - - RFIF[k]= 0: Control logic supporting radio k not present -RFIF[k]= 1: Control logic supporting radio k present -Index k values are: - 00001: Ripple RF. - 00010: External Radio Controller Support - 00100: IcyTRx Radio -xxx000: Reserved -Default value is 0000001 - - - 0: Diagnostic port not instantiated -1: Diagnostic port instantiated (Default Value) - - - 0: AES-CCM Encryption block not present -1: AES-CCM Encryption block present (Default Value) - - - Operating Frequency (in MHz) -Default value is 13MHz - - - 0: Interrupts are edge level generated, i.e. pulse. -1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement (Default Value) - - - Processor Bus Type -0: AHB Bus -1: X-Bar Bus - - - Processor bus width: -0: 16 bits (Default Value) -1: 32 bits - - - Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. -Default value is 13 (in decimal) - - - - - CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e. advertising, scanning, initiating, and connection) -0: CSCNT Interrupt not generated during events. -1: CSCNT Interrupt generated during events. - - - Audio channel 2 interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Audio channel 1 interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Audio channel 0 interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - SW triggered interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - End of event / anticipated pre-fetch abort interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Fine Target Timer Mask -0: Interrupt not generated -1: Interrupt generated - - - Gross Target Timer Mask -0: Interrupt not generated -1: Interrupt generated - - - Error Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Encryption engine Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - End of event Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Sleep Mode Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Rx Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - 625s Base Time Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - - - Audio channel 2 interrupt status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - Audio channel 1 interrupt status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - Audio channel 0 interrupt status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - SW triggered interrupt status -0: No SW triggered interrupt. -1: A SW triggered interrupt is pending. - - - End of event / Anticipated Pre-Fetch Abort interrupt status -0: No End of Event interrupt. -1: An End of Event interrupt is pending. - - - Masked Fine Target Timer Error interrupt status -0: No Fine Target Timer interrupt. -1: A Fine Target Timer interrupt is pending. - - - Masked Gross Target Timer interrupt status -0: No Gross Target Timer interrupt. -1: A Gross Target Timer interrupt is pending. - - - Masked Error interrupt status -0: No Error interrupt. -1: An Error interrupt is pending. - - - Masked Encryption engine interrupt status -0: No Encryption / Decryption interrupt. -1: An Encryption / Decryption interrupt is pending. - - - Masked End of Event interrupt status -0: No End of Advertising / Scanning / Connection interrupt. -1: An End of Advertising / Scanning / Connection interrupt is pending. - - - Masked Sleep interrupt status -0: No End of Sleep Mode interrupt. -1: An End of Sleep Mode interrupt is pending. - - - Masked Packet Reception interrupt status -0: No Rx interrupt. -1: An Rx interrupt is pending. - - - Masked 625s base time reference interrupt status - - - - - Audio channel 2 interrupt raw status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - Audio channel 1 interrupt raw status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - Audio channel 0 interrupt raw status -0: No Audio interrupt. -1: An Audio interrupt is pending. - - - SW triggered interrupt raw status -0: No SW triggered interrupt. -1: A SW triggered interrupt is pending. - - - End of event / Anticipated Pre-Fetch Abort interrupt raw status -0: No End of Event interrupt. -1: An End of Event interrupt is pending. - - - Fine Target Timer Error interrupt raw status -0: No Fine Target Timer interrupt. -1: A Fine Target Timer interrupt is pending. - - - Gross Target Timer interrupt raw status -0: No Gross Target Timer interrupt. -1: A Gross Target Timer interrupt is pending. - - - Error interrupt raw status -0: No Error interrupt. -1: An Error interrupt is pending. - - - Encryption engine interrupt raw status -0: No Encryption / Decryption interrupt. -1: An Encryption / Decryption interrupt is pending. - - - End of Event interrupt raw status -0: No End of Advertising / Scanning / Connection interrupt. -1: An End of Advertising / Scanning / Connection interrupt is pending. - - - Sleep interrupt raw status -0: No End of Sleep Mode interrupt. -1: An End of Sleep Mode interrupt is pending. - - - Packet Reception interrupt raw status -0: No Rx interrupt. -1: An Rx interrupt is pending. - - - 625s base time reference interrupt raw status -0: No 625s Base Time interrupt. -1: A 625s Base Time interrupt is pending. - - - - - bit type is changed from wos to s. - Audio channel 2 interrupt acknowledgement bit -Software writing 1 acknowledges the Audio channel 2 interrupt. This bit resets AUDIOINT2STAT and AUDIOINT2RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Audio channel 1 interrupt acknowledgement bit -Software writing 1 acknowledges the Audio channel 1 interrupt. This bit resets AUDIOINT1STAT and AUDIOINT1RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Audio channel 0 interrupt acknowledgement bit -Software writing 1 acknowledges the Audio channel 0 interrupt. This bit resets AUDIOINT0STAT and AUDIOINT0RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - SW triggered interrupt acknowledgement bit -Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit -Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Fine Target Timer interrupt acknowledgement bit -Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Gross Target Timer interrupt acknowledgement bit -Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Error interrupt acknowledgement bit -Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of Event interrupt acknowledgment bit -Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of Deep Sleep interrupt acknowledgment bit -Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Packet Reception interrupt acknowledgment bit -Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - 625s base time reference interrupt acknowledgment bit -Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. -Resets at 0 when action is performed - - - - - Writing a 1 samples the Base Time Counter value in BASETIMECNT register field. Resets at 0 when action is performed - - - Value of the 625s base time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW - - - - - Value of the current s fine time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration - - - - - Bluetooth Low Energy Device Address. LSB part. - - - - - Bluetooth Low Energy Device Address privacy indicator -0: Public Bluetooth Device Address -1: Private Bluetooth Device Address - - - Bluetooth Low Energy Device Address. MSB part. - - - - - Exchange Table Pointer that determines the starting point of the Exchange Table - - - Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List - - - - - - 0: Disable diagnostic port 3 output. All outputs are set to 0x0. -1: Enable diagnostic port 3 output. - - - Only relevant when DIAGEN3 = 1. -Selection of the outputs that must be driven to the diagnostic port 3. See section 2.16 for a detailed description. - - - 0: Disable diagnostic port 2 output. All outputs are set to 0x0. -1: Enable diagnostic port 2 output. - - - Only relevant when DIAGEN2 = 1. -Selection of the outputs that must be driven to the diagnostic port 2. See section 2.16 for a detailed description. - - - 0: Disable diagnostic port 1 output. All outputs are set to 0x0. -1: Enable diagnostic port 1 output. - - - Only relevant when DIAGEN1 = 1. -Selection of the outputs that must be driven to the diagnostic port 1. See section 2.16 for a detailed description. - - - 0: Disable diagnostic port 0 output. All outputs are set to 0x0. -1: Enable diagnostic port 0 output. - - - Only relevant when DIAGEN0 = 1. -Selection of the outputs that must be driven to the diagnostic port 0. See section 2.16 for a detailed description. - - - - - Directly connected to ble_dbg3[7:0] output. Debug use only. - - - Directly connected to ble_dbg2[7:0] output. Debug use only. - - - Directly connected to ble_dbg1[7:0] output. Debug use only. - - - Directly connected to ble_dbg0[7:0] output. Debug use only. - - - - - Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.16) - - - Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) - - - - - Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.16) - - - Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) - - - - - Indicates Resolving Address List engine Under run issue, happens when RAL List parsing not finished on time -0: No error -1: Error occurred - - - Indicates Resolving Address List engine faced a bad setting (e.g CS-RAL_EN = 1 and null RALPTR, or RALPTR > CS-PEER_RALPTR). -0: No error -1: Error occurred - - - Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software. -0: No error -1: Error occurred - - - Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. -0: No error -1: Error occurred - - - Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process -0: No error -1: Error occurred - - - Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than described in Table 3-11. -0: No error -1: Error occurred - - - Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time -0: No error -1: Error occurred - - - Indicates White List Timeout error, occurs if White List parsing is not finished on time -0: No error -1: Error occurred - - - Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. -0: No error -1: Error occured - - - Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. -0: No error -1: Error occured - - - Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) -0: No error -1: Error occurred - - - Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read -0: No error -1: Error occurred - - - Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. -0: No error -1: Error occurred - - - Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted -0: No error -1: Error occurred - - - Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller -0: No error -1: Error occurred - - - Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti -0: No error -1: Error occurred - - - - - Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port (Please refer to section 2.16 for details) - - - - - - Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet. -0: Access Code detection indicator provided as pulse -1: Access Code detection indicator provided as level - - - Enables the use of the delayed DC offset compensated data path in Radio Correlator block. -1: Enable -0: Disable - - - Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value -1: Enable -0: Disable - - - Control Ripple modulation mode in between FM and I&Q -1: I&Q modulation mode -0: FM modulation mode - - - Selects Jitter Elimination FIFO - - - Frequency of the SPI clock -00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz) -01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz) -10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz) -11: Do not use - - - This bit is READ ONLY. -0: Indicates that the SPI transfer is in progress. -1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer. - - - Software writing 1 triggers the SPI access. This bit is always read as 0. - - - - - Has no effect on Radio Controller - - - Extended radio selection field -5'b00000: No radio selected -5'b00001: RivieraWaves Ripple RF (BT4.0) -5'b00010: External Radio controller support -5'b00011-5'b11111: reserved - - - Pointer to the buffer containing data to be transferred to or received from the SPI port. - - - - - RF Rx Test Mode Delay Adjustment - - - Used to compensate Modem&RF Tx delay. When used, rtrip_delay should be set as Rx delay - - - Expected bit offset when rx symbol flag found. Used to compensate Modem&RF Rx delay. - - - Defines Rx window time threshold that forces Ripple AGC to max gain - - - - - BR/EDR Frequency Table pointer - - - - - Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s - - - This register holds the length in us of the RX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. - - - This register extends the length in us of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on the selected radio. - - - This register holds the length in us of the TX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. - - - - - Defines round trip delay value for 2M mode. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s - - - Expected bit offset when rx symbol flag found for 2M mode. Used to compensate Modem&RF Rx delay. - - - - - - Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: -0: Do not use data channel i+37. -1: Use data channel i+37. - - - - - - Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. -Value is in s. -Value to program depends on the used Advertising Packet type and the device filtering policy. -Please refer to Table 3-11 for details about ADVINT programming range. - - - - - Active scan mode back-off counter initialization value. - - - Active scan mode upper limit counter value. - - - - - - Start address pointer of the public devices white list. - - - - - Start address pointer of the private devices white list. - - - - - Number of private devices in the white list. - - - Number of public devices in the white list. - - - - - - 0: Cipher mode -1: Decipher mode - - - Writing a 1 starts AES-128 ciphering/deciphering process. -This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) - - - - - AES encryption 128-bit key. Bit 31 down to 0 - - - - - AES encryption 128-bit key. Bit 63 down to 32 - - - - - AES encryption 128-bit key. Bit 95 down to 64 - - - - - AES encryption 128-bit key. Bit 127 down to 96 - - - - - Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored. - - - - - AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) - - - - - AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. - - - - - Applicable to all event type -0: Normal mode of operation -1: Infinite Rx window - - - Applicable in RF Direct Rx Test mode only -0: Rx packet count disabled -1: Rx packet count enabled, and reported in CS-RXCCMPKTCNT and RFTESTRXSTAT-RXPKTCNT on RF abort command - - - Applicable to all event type -0: Normal mode of operation. -1: Infinite Tx packet / Normal start of a packet but endless payload - - - Applicable to all event type -0: Normal mode of operation: TxDESC-<TXADVLEN/TXLEN> controls the Tx packet payload size -1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit) - - - Defines the PRBS in use -0: Tx Packet Payload are PRBS9 type -1: Tx Packet Payload are PRBS15 type - - - Applicable to all event type -0: Tx Packet Payload source is the Control Structure -1: Tx Packet Payload are PRBS generator - - - Applicable in RF Direct Tx Test mode only -0: Tx packet count disabled -1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command - - - Applicable to all event type, valid when RFTESTCNTL-TXLENGTHSRC = 1 -Tx packet length in number of byte - - - - - Reports number of transmitted packet during Test Modes. -Value is valid if RFTESTCNTL-TXPKTCNTEN is set - - - - - Reports number of correctly received packet during Test Modes (no sync error, no CRC error). -Value is valid if RFTESTCNTL-RXPKTCNTEN is set - - - - - - Controls the Anticipated pre-Fetch Abort mechanism -0: Disabled -1: Enabled - - - Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort - - - Defines Exchange Table pre-fetch instant in s - - - - - Gross Timer Target value on which a ble_grosstgtim_irq must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[22:0] = BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. - - - - - Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625s: interrupt is generated only when FINETARGET = BASETIMECNT - - - - - - Start address pointer of the RAL structure - - - - - Number of devices in RAL Structure - - - - - Writing a 1 initializes of Local RPA random number generation LFSR -This bit is reset once the LFSR is loaded - - - Initialization value for Local RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value - - - - - Writing a 1 initializes of Peer RPA random number generation LFSR -This bit is reset once the LFSR is loaded - - - Initialization value for Peer RPA random generation when PRDN_INIT is set to 1, else reports the current Peer RPA random number LFSR value - - - - - - Determine BLE Priority Scheduling Arbitration Mode -0: BLE Decision instant not used -1: BLE Decision instant used - - - Determine the decision instant margin for Priority Scheduling Arbitration. -Decision instant is defined as per formula of section 3.6 - - - - - - - - - Version type of bt_core. 1 for BTDM old version. 2 for BTDM new version. 3 for BLE only. - - - Major release number of bt_core - - - Upgrade number of bt_core - - - Set to 1 when working as a plug-in RF&modem board. Set to 0 in all other modes - - - Set to 1 when using plug-in RF&modem board. Set to 0 in all other modes - - - - - select tport clock - - - select tport trigger - - - select tport data1 - - - select tport data0 - - - - - select pll frequency for rf/modem for channel 0~31 -1 for 214.5MHz and 0 for 208MHz - - - - - select pll frequency for rf/modem for channel 32~63 -1 for 214.5MHz and 0 for 208MHz - - - - - select pll frequency for rf/modem for channel 64~78 -1 for 214.5MHz and 0 for 208MHz - - - - - tx calibration enable - - - rx calibration enable - - - force txon for rf to txon_value when txon_force is 1 - - - - - force rxon for rf to rxon_value when rxon_force is 1 - - - - - - - delay time in us to enable modem tx after link layer txon enable - - - delay time in us to disable modem&rf tx after link layer txon disable - - - delay time in us to enable modem rx after link layer rxon enable - - - delay time in us to disable modem&rf rx after link layer rxon disable - - - - - number of rc clock cycles when doing rc calibration - - - enable automatic rc calibration when BT wakeup - - - bit type is changed from w1s to rs. - rc calibration start by software - - - - - indicate rc caliration done - - - number of reference clock cycles when doing rc calibration. -F(rc) = F(ref) * rccal_length / rccal_result - - - - - BT active indicater: -0: rf_txon -1: rf_rxon -2: rf_txon | rf_rxon -3: modem_txon | modem_rxon - - - 0: BT tx will not be masked -1: BT tx will be masked - - - BT tx will be masked when: -0: mws_tx -1: mws_rx -2: mws_tx | mws_rx -3: mws_tx & mws_rx - - - - - status of osc_en. 1 means BT is using clock derived from oscillator - - - when set to 1, mask bt2pmu_wakeup output to 0 to avoid unnecessary wakeup - - - - - - - - - Reset the complete RW-BT Core except timing generator and register blocks, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. In case of Dual Mode implementation, reset also common blocks. - - - Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - Reset the complete register block, when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Forces the generation of bt_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. - - - Abort the current Inquiry / Page / Broadcast scan window when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Abort the current RF Testing when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. -Note that when RFTEST_ABORT is requested -1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. -2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. - - - Abort the current Inquiry Mode or Page Mode when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Abort the current Sniff Mode when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - 0: FLOW verification on Rx packets is activated. -1: Packets are accepted regardless of FLOW value (test mode). - - - 0: When FLOW = 0, LMP messages can be sent. -1: When FLOW = 0, LMP messages are not sent. - - - 0: Normal operation. Encryption enabled when required. -1: Encryption disabled. -Note this works for both E0 and AES-CCM encryption mechanism - - - 0: Normal operation. Whitening enabled. -1: Whitening disabled. - - - 0: ARQN verification on Rx packets is activated. -1: Packets are accepted regardless of ARQN value (test mode). - - - 0: Normal operation. CRC removed from incoming data stream. -1: CRC stripping disabled on Rx packets. - - - 0: Normal operation. Hopping enabled. -1: Hopping disabled, the frequency is set either by CS-FREQ or by RFTESTFREQ register fields. - - - 0: SEQN verification on Rx packets is activated. -1: Packets are accepted regardless of SEQN value (test mode). - - - This field updates the CS-TXBSY_EN field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. - - - This field updates the CS-RXBSY_EN field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. - - - This field updates the CS-DNABORT field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. - - - 0: Disable RW-BT Core. -1: Enable RW-BT Core. - - - Indicate the maximum number of errors allowed to recognize the Access Code. - - - - - RW-BT Core Type C 0x8 means BT v4.2 (i.e. correspond LM version assigned number). Correspond to FS v8.0.11 - - - Version of the RW-BT Core C Major release number. Correspond to FS v8.0.11. - - - Version of the RW-BT Core C Upgrade number. Correspond to FS v8.0.11 - - - RW-BT Core Build number - - - - - 0: RW-BT Core is used as a standalone BR/EDR device -1: RW-BT Core is used in a Dual Mode device - - - 0: MWS Coexistence 2-Wire Interface not supported -1: MWS Coexistence 2-Wire Interface supported - - - 0: MWS Coexistence 1-Wire Interface not supported -1: MWS Coexistence 1-Wire Interface supported - - - Number of supported Audio Channel (0 to 3) -00: No Audio Channel / No PCM. -01: One Audio Channel -10: Two Audio Channels -11: Three Audio Channels. - - - 0: PCM Not Instantiated -1: PCM Instantiated - - - 0: MWS Coexistence mechanism not present -1: MWS Coexistence mechanism present - - - 0: WLAN Coexistence mechanism not present -1: WLAN Coexistence mechanism present - - - RFIF[k]= 0: Control logic supporting radio k not present -RFIF[k]= 1: Control logic supporting radio k present -Index k values are: -00001: RW-BT Ripple RF. -00010: External Radio Controller Support -xxxx00: Reserved - - - 0: Diagnostics port not present -1: Diagnostics port present - - - 0: AES-CCM Encryption block not present -1: AES-CCM Encryption block present - - - Operating Frequency (in MHz) -Default is 13 MHz - - - 0: Interrupts are edge level generated, i.e. pulse. -1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement - - - Processor Bus Type -0: AHB Bus -1: X-Bar Bus - - - Processor Data bus width: -0 16 bits -1: 32 bits - - - Value of the RW_BT_ADDRESS_WIDTH parameter converted into binary. - - - - - Skipped Exchange Table entry Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - SW triggered Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - End of Frame Interrupt / Anticipated Pre-Fetch Abort mask -0: Interrupt not generated -1: Interrupt generated - - - End of Frame Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - MWS Serial Interface Rx Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - MWS Serial Interface Tx Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Error Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Gross Target Timer Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Fine Target Timer Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Momentary Offset 1 event Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Momentary Offset 0 event Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Frame Synchronization Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Audio Channel 2 Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Audio Channel 1 Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - Audio Channel 0 Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - End of Sleep Interrupt Mask -0: Interrupt not generated -1: Interrupt generated - - - Packet Receipt Interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - CLKN / Slot interrupt mask -0: Interrupt not generated -1: Interrupt generated - - - - - Skipped Exchange Table entry Interrupt status -0: No Skipped Exchange Table entry Interrupt -1: Skipped Exchange Table entry Interrupt is pending - - - SW Triggered Interrupt status -0: No SW triggered Interrupt -1: SW Triggered Interrupt is pending - - - End of Frame / Anticipated Pre-Fetch Abort Interrupt status -0: No End of Frame Interrupt -1: End of Frame Interrupt is pending - - - End of Frame Interrupt status -0: No End of Frame Interrupt -1: End of Frame Interrupt is pending - - - MWS Serial Interface Rx Interrupt status -0: No MWS WCI Interrupt -1: MWS WCI Interrupt is pending - - - MWS Serial Interface Tx Interrupt status -0: No MWS WCI Interrupt -1: MWS WCI Interrupt is pending - - - Error Interrupt status. -0: No Error interrupt. -1: Error interrupt is pending. - - - Gross Timer Interrupt status. -0: No Gross Timer interrupt. -1: Gross Timer interrupt is pending. - - - Fine Timer Interrupt status. -0: No Fine Timer interrupt. -1: Fine Timer interrupt is pending. - - - Momentary Offset 1 Interrupt status. -0: No Momentary Offset interrupt. -1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step - - - Momentary Offset 0 Interrupt status. -0: No Momentary Offset interrupt. -1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step - - - MWS Frame Synchronization Interrupt status. -0: No frame_sync interrupt. -1: A frame_sync interrupt is pending. - - - Audio Channel 2 Interrupt status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - Audio Channel 1 Interrupt status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - Audio Channel 0 Interrupt status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - end of Sleep Interrupt Status. -0: No End of Sleep Mode interrupt. -1: An End of Sleep Mode interrupt is pending. - - - Packet Reception Interrupt status. -0: No Rx interrupt. -1: An Rx interrupt is pending. - - - Slot Interrupt status. -0: No CLKN interrupt. -1: A CLKN interrupt is pending. - - - - - Skipped Exchange Table entry Interrupt raw status -0: No Skipped Exchange Table entry Interrupt -1: Skipped Exchange Table entry Interrupt is pending - - - SW Triggered Interrupt raw status -0: No SW Triggered Interrupt -1: SW Triggered Interrupt is pending - - - End of Frame / Anticipated Pre-Fetch Abort Interrupt raw status -0: No End of Frame Interrupt -1: End of Frame Interrupt is pending - - - End of Frame Interrupt raw status -0: No End of Frame Interrupt -1: End of Frame Interrupt is pending - - - MWS Serial Interface Rx Interrupt raw status -0: No MWS WCI Interrupt -1: MWS WCI Interrupt is pending - - - MWS Serial Interface Tx Interrupt raw status -0: No MWS WCI Interrupt -1: MWS WCI Interrupt is pending - - - Error Interrupt raw status. -0: No Error interrupt. -1: Error interrupt is pending. - - - Gross Timer Interrupt raw status. -0: No Gross Timer interrupt. -1: Gross Timer interrupt is pending. - - - Fine Timer Interrupt raw status. -0: No Fine Timer interrupt. -1: Fine Timer interrupt is pending. - - - Momentary Offset 1 Interrupt raw status. -0: No Momentary Offset interrupt. -1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step - - - Momentary Offset 0 Interrupt raw status. -0: No Momentary Offset interrupt. -1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step - - - MWS Frame Synchronization Interrupt raw status. -0: No frame_sync interrupt. -1: A frame_sync interrupt is pending. - - - Audio Channel 2 Interrupt raw status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - Audio Channel 1 Interrupt raw status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - Audio Channel 0 Interrupt raw status. -0: No eSCO SW Transport interrupt. -1: An eSCO SW Transport interrupt is pending. - - - End of Sleep Interrupt raw Status. -0: No End of Sleep Mode interrupt. -1: An End of Sleep Mode interrupt is pending. - - - Packet Reception Interrupt raw status. -0: No Rx interrupt. -1: An Rx interrupt is pending. - - - Slot Interrupt raw status. -0: No CLKN interrupt. -1: A CLKN interrupt is pending. - - - - - bit type is changed from wos to s. - Skipped Exchange Table entry Interrupt acknowledgment. -Software writing 1 acknowledges the Skipped Exchange Table entry interrupt. This bit resets SKETINTSTAT and SKETINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - SW triggered Interrupt acknowledgment. -Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of Frame / Anticipated Pre-Fetch Abort Interrupt acknowledgment. -Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEAPFAINTSTAT and FRAMEAPFAINTRWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of Frame Interrupt acknowledgment. -Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEINTSTAT and FRAMEINTRWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - MWS Serial Interface Rx Interrupt acknowledgment. -Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - MWS Serial Interface Tx Interrupt acknowledgment. -Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Error Interrupt acknowledgment. -Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Gross Timer Interrupt acknowledgment. -Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTINTSTAT and GROSSTGTINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Fine Timer Interrupt acknowledgment. -Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTINTSTAT and FINETGTINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Momentary Offset 1 Interrupt acknowledgment. -Software writing 1 acknowledges the Momentary offset event interrupt. This bit resets MTOFFINT1STAT and MTOFFINT1RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Momentary Offset 0 Interrupt acknowledgment. -Software writing 1 acknowledges the Momentary offset event interrupt. This bit resets MTOFFINT0STAT and MTOFFINT0RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - MWS Frame Synchronization Interrupt acknowledgement. -Software writing 1 acknowledges the frame_sync event interrupt. This bit resets FRSYNCINTSTAT and FRSYNCINTRAWSTAT flag. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Audio Channel 2 Interrupt acknowledgement. -Software writing 1 acknowledges the Audio Channel 2 interrupt. This bit resets AUDIOINT2STAT and AUDIOINT2RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Audio Channel 1 Interrupt acknowledgement. -Software writing 1 acknowledges the Audio Channel 1 interrupt. This bit resets AUDIOINT1STAT and AUDIOINT1RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Audio Channel 0 Interrupt acknowledgement. -Software writing 1 acknowledges the Audio Channel 0 interrupt. This bit resets AUDIOINT0STAT and AUDIOINT0RAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - End of Sleep Interrupt acknowledgement. -Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Packet Reception Interrupt acknowledgement. -Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. -Resets at 0 when action is performed - - - bit type is changed from wos to s. - Slot Interrupt acknowledgement. -Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. -Resets at 0 when action is performed - - - - - Writing a 1 samples the CLKN[27:0] value in SLOTCLK-SCLK register field. -Resets at 0 when action is performed. No action happens if it is written with 0 - - - Update the Native Bluetooth counter CLKN[27:1] (CLKN[0] is not considered), when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Native Bluetooth counter CLKN sampled at the time the processor has written the SAMP bit (precsision of 312.5s). This value does not change until the next writing of SAMP bit, and can therefore be safely accessed with 8-, 16- or 32-bits accesses. - - - - - Value of the current s fine time reference counter sampled at the time the processor has written the SAMP bit. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration - - - - - Enable automatic A-train/B-train switch during Page procedure. -0: Page procedure A-train/B-train counter disabled -1: Page procedure A-train/B-train counter enabled - - - Starting train value of Page procedure -0:Start with A-train -1:Start with B-train - - - Load A-train/B-train Page procedure conter, when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Defines A-train/B-train duration time during Page procedure, counted by 16-slots. -Loaded when ABTPAGELOAD is set. Start when Page procedure starts and ABTPAGEEN is set. Stops when ABTPAGEEN is reset. Switch of train when wrapping. - - - Enable automatic A-train/B-train switch during Inquiry procedure. -0: Inquiry procedure A-train/B-train counter disabled -1: Inquiry procedure A-train/B-train counter enabled - - - Starting train value of Inquiry procedure -0:Start with A-train -1:Start with B-train - - - Load A-train/B-train Inquiry procedure conter, when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Defines A-train/B-train duration time during Inquiry procedure, counted by 16-slots. -Loaded when ABTINQLOAD is set. Start when Inquiry procedure starts and ABTINQEN is set. Stops when ABTINQEN is reset. Switch of train when wrapping. - - - - - Default value equals d26. Should not exceed 'h88. -Applies when ET-SNIFF = 1 on first access code detection, in order to process the new bit offset (See section 3.5.5) - - - 0: Broadcast @ 1Mbps / normal mode -1: Broadcast operation in EDR Mode (@ 2/3 Mbps) / special features -The EDRCNTL-EDRBCAST bit is used in reception (slave side) as following: -if RXLTADDR= 0 (i.e. broadcast packet is received) - if EDRCNTL-EDRBCAST=0 , we consider the currently received packet is not an EDR-packet. The 1Mbps modulation is used. - if EDRCNTL-EDRBCAST=1, then apply EDR modulation or not depending on the control structure bit " ACLEDR" set in MISCNTL field. - - - 0: normal operation, EDR Rx guard window detection activated -1: EDR Rx guard window detection disabled. - - - 0: Direct order EDR Payload data transmit -1: Reverse order EDR Payload data transmit - - - 0: Direct order EDR Payload data receive -1: Reverse order EDR Payload data receive - - - Time out value before EDR packet reception that allow ending the Rx transaction if an EDR packet is not correctly detected. -Default value is set to 212 clock cycles @ 13MHz <-> 16.3us. Timing between Packet Header and EDR packet is defined as 5us+-0.25us + 11 synchronization symbol = 16.25us in the worst case - - - - - Exchange Table pointer value - - - Rx Descriptor current pointer value - - - - - External Wake-Up disable -0: RW-BT Core can be woken by external wake-up -1: RW-BT Core cannot be woken up by external wake-up - - - Enable external pin high level wakeup - - - Enable external pin low level wakeup - - - Enable external pin activity wakeup - - - Indicator of current Deep Sleep clock mux status: -0: RW-BT Core is not yet in Deep Sleep Mode -1: RW-BT Core is in Deep Sleep Mode (only low_power_clk is running) - - - Wake Up Request from RW-BT Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BT Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - CLKN integer and fractional part correction (i.e. CLKN Counter and Fine Counter). Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. - - - RW-BT Core sleep mode request control -0: RW-BT Core in normal active mode -1: Request RW-BT Core to switch in deep sleep mode. -This bit is reset on DEEP_SLEEP_STAT falling edge. - - - Controls the Radio module -0: Radio stands in normal active mode -1: Allow to disable Radio - - - Controls the RF High frequency crystal oscillator -0: High frequency crystal oscillator stands in normal active mode -1: Allow to disable High frequency crystal oscillator - - - - - Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz - - - - - Actual duration of the last deep sleep phase measured in low power oscillator cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low power clock tick until the end of the deep sleep phase. - - - - - Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator following an external wake-up request (signal wakeup_req) [064ms for 32kHz) - - - Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator when the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP) [064ms for 32kHz) - - - Time in low power oscillator cycles allowed for the radio module to leave low-power mode [032ms for 32kHz) - - - - - Phase correction value for the CLKN counter in s. - - - - - Determines whether CLNCNTCORR is an absolute correction or a signed delta increment correction -0: Absolute correction -1: Signed delta increment correction - - - CLKN Counter correction value / signed delta increment - - - - - Token Tx delay time after Slave receive completed - - - Token Rx delay time after Slave receive completed - - - 0: Use normal sync pulse for token ID -1: Use quick sync pulse for token ID - - - Size of Token Rx Window - - - Slave arbiter receive token ID but bypass arbitration - - - Slave arbiter enable - - - Slave observer will respond to master - - - Slave observer enable - - - - - - 0: Disable diagnostic port 3 output. All outputs are set to 0. -1: Enable diagnostic port 3 output. - - - Only relevant when DIAGEN3 = 1. -Selection of the outputs that are driven to the diagnostic port 3. - - - 0: Disable diagnostic port 2 output. All outputs are set to 0. -1: Enable diagnostic port 2 output. - - - Only relevant when DIAGEN2 = 1. -Selection of the outputs that are driven to the diagnostic port 2. - - - 0: Disable diagnostic port 1 output. All outputs are set to 0. -1: Enable diagnostic port 1 output. - - - Only relevant when DIAGEN1 = 1. -Selection of the outputs that are driven to the diagnostic port 1. - - - 0: Disable diagnostic port 0 output. All outputs are set to 0. -1: Enable diagnostic port 0 output. - - - Only relevant when DIAGEN0 = 1. -Selection of the outputs that are driven to the diagnostic port 0. - - - - - Directly connected to bt_dbg0[7:0] output. Debug use only - - - Directly connected to bt_dbg1[7:0] output. Debug use only - - - Directly connected to bt_dbg2[7:0] output. Debug use only - - - Directly connected to bt_dbg3[7:0] output. Debug use only - - - - - Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.19). - - - Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19). - - - - - Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.19) - - - Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19) - - - - - Indicates whether the Rx eSCO (during Voice over HCI operations) or Rx LM buffer pointer value programmed is null: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether Tx eSCO (during Voice over HCI operations) or Tx LM buffer pointer value programmed is null, or if an ACL Tx packet is set with a non null length while no buffer is associated: this is a major programming failure. -0: No error -1: Error occurred - - - Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure / Valid for non-connected states and Broadcast Scan mode -0: No error -1: Error occurred - - - Indicates whether Tx Descriptor pointer value programmed in Control Structure is null: this is a major programming failure / Valid for non-connected states and Broadcast mode -0: No error -1: Error occurred - - - Indicates whether ATT_NB field in Control Structure is null, or when during eSCO that eSCOLTCNLT<0/1/2>-RETXNB<0/1/2> register field is null: this is a major programming failure -0: No error -1: Error occurred - - - Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. -0: No error -1: Error occurred - - - Channel Map error, happens when actual number of bits set to one in selected CS-CHMAP is different from corresponding CS-NBCHGOOD at the beginning of Frequency Hopping process. -Note this is valid only if CS-AFHENA=1 -0: No error -1: Error occurred - - - Calculation of the hopping frequency not done before Tx/Rx EN is asserted -0: No error -1: Error occurred - - - Indicates an Frame Controller internal timing error -0: No error -1: Error occurred - - - Indicate a Frame Controller Exchange Memory Access error. -0: No error -1: Error occurred - - - Indicates Anticipated Pre-Fetch Mechanism error in Frame Controller: happens when 2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. -0: No error -1: Error occured - - - Indicates Anticipated Pre-Fetch Mechanism error in Frame Scheduler: happens when 2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. -0: No error -1: Error occured - - - Indicates Frame Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) -0: No error -1: Error occurred - - - MWS WCI Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted -0: No error -1: Error occurred - - - Frame Scheduler Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted -0: No error -1: Error occurred - - - PCM Exchange Memory request access error, happens when Exchange Memory access requests are not served in time and PCM samples are corrupted -0: No error -1: Error occurred - - - Audio EM Access Manager Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted -0: No error -1: Error occurred - - - Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted. -0: No error -1: Error occurred - - - Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted -0: No error -1: Error occurred - - - Indicates when the Encryption mode is enabled with Connectionless Slave Broadcast (Master or Slave) -0: No error -1: Error occurred - - - Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller -0: No error -1: Error occurred - - - Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti -0: No error -1: Error occurred - - - - - Software Profiling register: used by RW-BT Software for profiling purpose: this value is copied on Diagnostic port - - - - - - Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet. -0: Access Code detection indicator provided as pulse -1: Access Code detection indicator provided as level - - - Enables the use of the delayed DC offset compensated data path in Radio Correlator block. -1: Enable -0: Disable - - - Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value -1: Enable -0: Disable - - - Frequency of the SPI clock -00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz) -01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz) -10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz) -11: Do not use - - - This bit is READ ONLY. -0: Indicates that the SPI transfer is in progress. -1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer. - - - Software writing 1 triggers the SPI access. This bit is always read as 0. - - - - - Extended radio selection field -5'h00000: No radio selected -5'h00001: RivieraWaves Ripple RF (BT4.0) -5'h00010: External Radio controller support -5'h00011-5'b11111: reserved - - - Pointer to the buffer containing data to be transferred to or received from the SPI port. - - - - - Used to compensate Modem&RF Tx delay. When used, rtrip_delay should be set as Rx delay - - - Defines sync_p instant when provided to the Modem. - - - Defines Rx window time threshold that forces Ripple AGC to max gain - - - - - BR/EDR Frequency Table pointer - - - - - Round Trip Delay. This correspond to the cumulated Tx plus Rx latency of the radio (in us) - - - This register holds the length in us of the RX power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends on supported radio. - - - This register extends the length in us of the TX power down phase for the current radio device. -Default value is 3us (reset value). Operating range depends on supported radio. - - - This register holds the length in us of the TX power up phase for the current radio device. Default value is 210 us (reset value). Operating range is depends on supported radio. - - - - - - AES-CCM plain MIC value. - - - - - AES-CCM plain MIC value. - - - - - E0 Address pointer - - - - - - Applicable in Slave eSCO reserved slot only -0: Normal mode of operation -1: Allow reply on Sync Error - - - Applicable in Slave eSCO reserved slot only -0: Normal mode of operation -1: Allow reply on HEC Error - - - Applicable for all frame format -0: Normal mode of operation -1: Infinite Rx window - - - Set to 1 to force status of exchange table entry to be ready. Used for repeated tx - - - Applicable for all frame format -0: Normal mode of operation -1: Infinite Tx window - - - Defines the PRBS type in use -0: Tx Packet Payload are PRBS9 type -1: Tx Packet Payload are PRBS15 type - - - Applicable for all frame format -0: Tx Packet Payload source is the Control Structure -1: Tx Packet Payload are PRBS generator - - - - - Direct Loopback Test Mode enable control -0: Normal mode of operation -1: Direct Loopback Mode enabled (Received Packet Header, Payload Header, and Payload data directly re-transmitted in the next slot) - - - Test Mode enable control, applicable if CS-FH_EN=0 -0: Normal mode of operation -1: Test Mode enable, use <TX/RX>FREQ during Tx/Rx operations. - - - Frequency Table index to be used during Rx operation - - - Frequency Table index to be used during Tx operation - - - - - - Controls the Anticipated pre-Fetch Abort mechanism -0: Disabled -1: Enabled - - - Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort - - - Defines Exchange Table pre-fetch instant in s - - - - - Gross Timer Target value on which an Interrupt must be generated. -This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET = CLKN[27:5] and CLKN[4:0] = 0. - - - - - Fine Timer Target value on which an interrupt must be generated. -This timer has a precision of 625s: interrupt is generated only when FINETARGET = CLKN[27:1] - - - - - Returns the CLKN[27:0] value on each bt_sket_irq generation. - - - - - Signed number, time offset to the current frame_sync position in s. Valid range is [-625, 625]s. When SYNC_SOURCE=1, the following formula must apply: -TARGET_OFFSET = 559 C RF round trip delay C desired CS-BITOFF - - - Applies only when SYNC_SOURCE equals 1. Defines which connection to align piconet clock on. -The connection is labelled using CS-LINKLBL the piconet clock is aligned when CS-LINKLBL = SLVLBL field -Note the RW-BT Software must ensure the labelled connection is a slave connection, else it cannot work properly - - - Maximum shift size during incremental phase shift. Must be programmed to 1s (0x1) -Note CORR_STEP is considered as a signed value when BLINDCORR_EN is set (allows to drift forward and backward) - - - 0: Align piconet clock on frame_sync rising edge (when CORR_INTERVAL is reached) -1: Align piconet clock when CORR_INTERVAL is reached, without frame_sync rising edge - - - Frame sync signal polarity. - 0 : rising edge events sensitive - 1 : falling edge events sensitive - - - Defines synchronization signal source -0: MWS frame synchronization -1: Scatternet network scheduling optimization (See section 2.17) - - - Enable incremental phase shift - - - - - Correction interval time in slot interval. -Default value is 40 (i.e. 40x625s = 25ms) - - - Performs immediate clock shift update using CLOCK_SHIFT[10:0], when written with a 1. -Resets at 0 when action is performed. No action happens if it is written with 0. - - - Signed value of the clock shift to apply when CLOCK_SHIFT_EN is written with a 1 in [-625, 625]s range - - - - - Indicate the value of the phase when an immediate shift has been programmed or when a frame_sync event occurs, [-625, 625]s - - - Momentary offset, signed number which indicate the time between target_offset and the nearest alignment point, in [-625, 625]s range - - - - - - Toggle command for Voice Channel 0. -Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor -Please refer to section 2.18.5 for details. - - - Enables eSCO Channel 0 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: -0: Disabled. -1: Enabled. - - - Enables eSCO Channel 0 (controls Audio Path EM Access controller voice channel 0): -0: Disabled. -1: Enabled. - - - 0: bt_audio0_irq is generated on TeSCO/TSCO instant -1: bt_audio0_irq is generated INTDELAY0[5:0] slots after TeSCO/TSCO instant - - - Valid if ITMODE0 = 1 -Determines the slot number to wait before generating bt_audio0_irq - - - eSCO interval (in slots). -Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) - - - - - HW mute control: -0: Do not mute on bad reception of an (e)SCO packet. -1: Mute after data or bad reception, with the pattern stored in MUTEPATT0 -Note: See Table 2-34 for mute pattern value to apply - - - HW mute control: -0: Provides Source buffer to the Packet Controller for Tx operations -1: Forces POLL/NULL to be sent as a replacement of Audio Packets - - - SW mute status for Audio buffer 1 (i.e updated when TOG0=1): -Mute if not null. Please refer to Table 2-35 for details - - - SW mute status for Audio buffer 0 (i.e updated when TOG0=0): -Mute if not null. Please refer to Table 2-35 for details - - - Value of the null pattern used when HW muting is enabled. - - - - - Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. -Used when eSCOCHANCNTL0-TOG0 = 1 - - - Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 0. -Used when eSCOCHANCNTL0-TOG0 = 0 - - - - - Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. -Used when eSCOCHANCNTL0-TOG0 = 1 - - - Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 0. -Used when eSCOCHANCNTL0-TOG0 = 0 - - - - - Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). -Default value is 1 - - - 1: eSCO EDR Mode (2/3 Mbps) in reception -0: eSCO 1Mbps in reception - - - 1: eSCO EDR Mode (2/3 Mbps) in transmission -0: eSCO 1Mbps in transmission - - - Synchronous packet type: -0: SCO packet -1: eSCO packet - - - LT_ADDR of the Synchronous link (eSCO), used for TX. - - - - - Value of the SEQN bit in eSCO TX packets. Used as follows: -- Initialized by SW during eSCO link establishment -- Toggled by HW on each TSCO/TeSCO, written back afterwards - - - Negotiated, maximum number of bytes for eSCO Tx payloads. - - - Negotiated Tx packet type, as defined in [1]. - - - Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. - - - Negotiated Rx packet type, as defined in [1]. - - - - - Day Counter for AES-CCM nonce. - - - - - - Toggle command for Voice Channel 1. -Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor. -Please refer to section 2.18.5 for details. - - - Enables eSCO Channel 1 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: -0: Disabled. -1: Enabled. - - - Enables eSCO Channel 1 (controls Audio Path EM Access controller voice channel 1): -0: Disabled. -1: Enabled. - - - 0: bt_audio1_irq is generated on TeSCO/TSCO instant -1: bt_audio1_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant - - - Valid if ITMODE1 = 1 -Determines the slot number to wait before generating bt_audio1_irq - - - eSCO interval (in slots). -Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) - - - - - HW mute control: -0: Do not mute on bad reception of an (e)SCO packet. -1: Mute after data or bad reception, with the pattern stored in MUTEPATT1 -Note: See Table 2-34 for mute pattern value to apply - - - HW mute control: -0: Provides Source buffer to the Packet Controller for Tx operations -1: Forces POLL/NULL to be sent as a replacement of Audio Packets - - - SW mute status for Audio buffer 1 (i.e updated when TOG1=1): -Mute if not null. Please refer to Table 2-35 for details - - - SW mute status for Audio buffer 0 (i.e updated when TOG1=0): -Mute if not null. Please refer to Table 2-35 for details - - - Value of the null pattern used when HW muting is enabled. - - - - - Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. -Used when eSCOCHANCNTL1-TOG1 = 1 - - - Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. -Used when eSCOCHANCNTL1-TOG1 = 0 - - - - - Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. -Used when eSCOCHANCNTL1-TOG1 = 1 - - - Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. -Used when eSCOCHANCNTL1-TOG1 = 0 - - - - - Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). -Default value is 1 - - - 1: eSCO EDR Mode (2/3 Mbps) in reception -0: eSCO 1Mbps in reception - - - 1: eSCO EDR Mode (2/3 Mbps) in transmission -0: eSCO 1Mbps in transmission - - - Synchronous packet type: -0: SCO packet -1: eSCO packet - - - LT_ADDR of the Synchronous link (eSCO), used for TX. - - - - - Value of the SEQN bit in eSCO TX packets. Used as follows: -- Initialized by SW during eSCO link establishment -- Toggled by HW each TSCO/TeSCO, written back afterwards - - - Negotiated, maximum number of bytes for eSCO Tx payloads. - - - Negotiated Tx packet type, as defined in [1]. - - - Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. - - - Negotiated Rx packet type, as defined in [1]. - - - - - Day Counter for AES-CCM nonce. - - - - - - Toggle command for Voice Channel 2. -Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor -Please refer to section 2.18.5 for details. - - - Enables eSCO Channel 2 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: -0: Disabled. -1: Enabled. - - - Enables eSCO Channel 2 (controls Audio Path EM Access controller voice channel 2): -0: Disabled. -1: Enabled. - - - 0: bt_audio2_irq is generated on TeSCO/TSCO instant -1: bt_audio2_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant - - - Valid if ITMODE2 = 1 -Determines the slot number to wait before generating bt_audio2_irq - - - eSCO interval (in slots). -Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) - - - - - HW mute control: -0: Do not mute on bad reception of an (e)SCO packet. -1: Mute after data or bad reception, with the pattern stored in MUTEPATT2 -Note: See Table 2-34 for mute pattern value to apply - - - HW mute control: -0: Provides Source buffer to the Packet Controller for Tx operations -1: Forces POLL/NULL to be sent as a replacement of Audio Packets - - - SW mute status for Audio buffer 1 (i.e updated when TOG2=1): -Mute if not null. Please refer to Table 2-35 for details - - - SW mute status for Audio buffer 0 (i.e updated when TOG2=0): -Mute if not null. Please refer to Table 2-35 for details - - - Value of the null pattern used when HW muting is enabled. - - - - - Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. -Used when eSCOCHANCNTL2-TOG2 = 1 - - - Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. -Used when eSCOCHANCNTL2-TOG2 = 0 - - - - - Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. -Used when eSCOCHANCNTL2-TOG2 = 1 - - - Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. -Used when eSCOCHANCNTL2-TOG2 = 0 - - - - - Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). -Default value is 1 - - - 1: eSCO EDR Mode (2/3 Mbps) in reception -0: eSCO 1Mbps in reception - - - 1: eSCO EDR Mode (2/3 Mbps) in transmission -0: eSCO 1Mbps in transmission - - - Synchronous packet type: -0: SCO packet -1: eSCO packet - - - LT_ADDR of the Synchronous link (eSCO), used for TX. - - - - - Value of the SEQN bit in eSCO TX packets. Used as follows: -- Initialized by SW during eSCO link establishment -- Toggled by HW each TSCO/TeSCO, written back afterwards - - - Negotiated, maximum number of bytes for eSCO Tx payloads. - - - Negotiated Tx packet type, as defined in [1]. - - - Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. - - - Negotiated Rx packet type, as defined in [1]. - - - - - Day Counter for AES-CCM nonce. - - - - - - Sample Linear format for voice channel 0 -00: 8-bit samples -01: 13-bit samples -10: 14-bit samples -11: 16-bit samples - - - PCM / VoHCI Sample Type on Audio Path Channel 0 -00: Signed 1s complement -01: Signed 2s complement -10: Signed magnitude -11: Unsigned - - - a/-Law control for voice channel 0 -1: Enables a/-Law transcoding -0: Disables a/-Law transcoding / bypass mode - - - a/-Law configuration code for voice channel 0. (See Table 2-40) - - - CVSD control for voice channel 0 -1: Enables CVSD transcoding -0: Disables CVSD transcoding / bypass mode - - - Bit ordering at Byte interface for voice channel 0 -0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. -1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). - - - - - Sample Linear format for voice channel 1 -00: 8-bit samples -01: 13-bit samples -10: 14-bit samples -11: 16-bit samples - - - PCM / VoHCI Sample Type on Audio Path Channel 1 -00: Signed 1s complement -01: Signed 2s complement -10: Signed magnitude -11: Unsigned - - - a/-Law control for voice channel 1 -1: Enables a/-Law transcoding -0: Disables a/-Law transcoding / bypass mode - - - a/-Law configuration code for voice channel 1. (See Table 2-40) - - - CVSD control for voice channel 1 -1: Enables CVSD transcoding -0: Disables CVSD transcoding / bypass mode - - - Bit ordering at Byte interface for voice channel 1 -0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. -1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). - - - - - Sample Linear format for voice channel 2 -00: 8-bit samples -01: 13-bit samples -10: 14-bit samples -11: 16-bit samples - - - PCM / VoHCI Sample Format on Audio Path Channel 2 -00: Signed 1s complement -01: Signed 2s complement -10: Signed magnitude -11: Unsigned - - - a/-Law control for voice channel 2 -1: Enables a/-Law transcoding -0: Disables a/-Law transcoding / bypass mode - - - a/-Law configuration code for voice channel 2. (See Table 2-40) - - - CVSD control for voice channel 2 -1: Enables CVSD transcoding -0: Disables CVSD transcoding / bypass mode - - - Bit ordering at Byte interface for voice channel 2 -0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. -1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). - - - - - - Voice channel Selection. Select the voice channel to be routed to the PCM -00: Voice Channel 0 routed to PCM -01: Voice Channel 1 routed to PCM -10: Voice Channel 2 routed to PCM -11: Reserved - - - Loopback Test mode control -1: Loopback Mode enabled -0: Loopback Mode disabled / Normal operations - - - Valid when SAMPTYPE is set to Stereo mode, else not applicable -0: Select Left channel audio samples for Mono operation -1: Select Right channel audio samples for Mono operation - - - Audio channel Mono/Stereo mode control -0: Audio channel carries Mono samples -1: Audio channel carries Stereo samples - - - Master/Slave mode control -0: PCM is master (i.e. PCM generates pcmclk_out and pcmfsync_out from PLL) -1: PCM is slave (i.e. PLL disabled and pcmclk_in and pcmfsync_in are used) - - - Byte swapping control, valid only SAMPSZ is set to 16-bits -0: Samples to be sent used as-is -1: MSB and LSB bytes are swapped within samples - - - Valid in Stereo mode only, defines the Left / Right channel order -0: Left channel then Right channel -1: Right channel then Left channel - - - PCM main control -0: PCM disabled (i.e. pcm_gclk clock not enabled) -1: PCM enabled (i.e. pcm_gclk clock enabled) - - - - - Configures the first active slot of the frame, in [0:3] range -00: first active slot is slot 0 -01: first active slot is slot 1 -10: first active slot is slot 2 -11: first active slot is slot 3 -The maximum value this field can be configured to is determined by the SLOTNB-1 parameters. - - - Number of slots within a PCM frame -Valid values are in [1:4] range. -Other values are meaningless - - - PCM Codec Sample type -0: PCM codec supports Mono operation -1: PCM codec supports Stereo operation - - - PCM codec Sample size -0: PCM Frame carries 8-bit samples -1: PCM Frame carries 16-bit samples - - - Bit ordering within a PCM Frame -0: Sample are sent/received MSB first -1: Samples are sent/received LSB first - - - PCM / IOM mode selection -0: PCM mode (single clocking) -1: IOM mode (double clocking) - - - Selection of the PCM Frame Synchronization polarity (Valid when SAMPTYPE is set to Stereo mode, else not applicable) -0: Right channel when = 0, Left channel when = 1 -1: Right channel when = 1, Left channel when = 0 - - - Physical configuration of the pcmd_out pad. -00: Open-drain, hi-Z outside transmission -01: Push-pull, hi-Z outside transmission -10: Push-pull, driven to 0 outside transmission -11: Reserved - - - Physical shape of the PCM Frame Synchronization signal. -000: LF enclosing the last falling PCM Interface Clock edge in frame (Mono only) -001: FR enclosing the first rising PCM Interface Clock edge in frame (Mono only) -010: FF enclosing the first falling PCM Interface Clock edge in frame (Mono only) -011: LONG enclosing the first slot (8 bits) of the frame (Mono / Stereo 8-bits only) -100: LONG_16 enclosing first two slots (16 bits) of the frame (Mono 16 bits / Stereo 16-bits only) -101: STEREO Left/Right Frame differentiating (Stereo only, covers left or right channel only, polarity is set according to LRCHPOL) - - - - - Selection of the PCM Interface Clock polarity -0: Data is clocked out with the rising edge (standard) -1: Data is clocked out with the falling edge - - - PCM Clock counter limit - - - PCM Clock Counter value. - - - - - Right channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first) - - - Left channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first) - - - - - PLL control word, see equation below. - - - - - Open Loop Correction value, see equation below. - - - PLL control word, see equation below. - - - - - PLL control word, see equation below. - - - - - PCM Source Pointer 1 / Air to PCM direction - - - PCM Source Pointer 0 / Air to PCM direction - - - - - PCM Sink Pointer 1 / PCM to Air direction - - - PCM Sink Pointer 0 / PCM to Air direction - - - - - - Determine BR/EDR Priority Scheduling Arbitration Mode -0: BR/EDR Decision instant not used -1: BR/EDR Decision instant used - - - Determine the decision instant margin for Priority Scheduling Arbitration. Decision instant is defined as per formula of section 3.6 - - - - - PLC Pool Base Addr - - - PLC Pool Base Addr - - - - - PLC Pool Base Addr - - - PLC Pool Base Addr - - - - - PLC Pool Base Addr - - - PLC Pool Base Addr - - - - - PLC Pool Base Addr - - - PLC Pool Base Addr - - - - - PLC Pool Base Addr - - - PLC Pool Base Addr - - - - - PLC Pool buf Addr - - - - - bit type is changed from wos to s. - plc interrput clear pulse - - - plc interrput - - - plc ctrl fsm state - - - bit type is changed from wos to s. - plc_start - - - 0: hardware auto 1: software ctrl - - - mask for plc interrupt - - - diag0 selection - - - plc scaling mode - - - frame_mode length_x000D_ -0: 120_x000D_ 1: 90 2:60_x000D_ 3:30 - - - indicate current farme bad or good - - - enable for PLC - - - plc exception - - - swap word order - - - threshold for finding pitch - - - - - - - - - Bypass DC Cancel -1'h0:: not_bypass: RX DC Cancel is not bypassed -1'h1:: bypass: RX DC Cancel is bypassed - - - RESERVED - - - Bypass Mixer -1'h0:: not_bypass: RX Mixer is not bypassed -1'h1:: bypass: RX Mixer is bypassed - - - Bypass Square-root-raised-cosine Filter -1'h0:: not_bypass: RX SRRC filter is not bypassed -1'h1:: bypass: RX SRRC filter is bypassed - - - Bypass GFSK Derr1 -1'h0:: not_bypass: RX GFSK Derr1 is not bypassed -1'h1:: bypass: RX GFSK Derr1 is bypassed - - - Bypass GFSK Derr2 -1'h0:: not_bypass: RX GFSK Derr2 is not bypassed -1'h1:: bypass: RX GFSK Derr2 is bypassed - - - Bypass GFSK Patch -1'h0:: not_bypass: GFSK Patch is not bypassed -1'h1:: bypass: GFSK Patch is bypassed - - - Bypass GFSK Sample Step -1'h0:: not_bypass: RX GFSK Sample Step is 1 -1'h1:: bypass: RX GFSK Sample Step is 0 - - - Bypass DPSK Derr1 -1'h0:: not_bypass: RX DPSK Derr1 is not bypassed -1'h1:: bypass: RX DPSK Derr1 is bypassed - - - Bypass DPSK Derr2 -1'h0:: not_bypass: RX DPSK Derr2 is not bypassed -1'h1:: bypass: RX DPSK Derr2 is bypassed - - - Bypass DPSK Patch -1'h0:: not_bypass: DPSK Patch is not bypassed -1'h1:: bypass: DPSK Patch is bypassed - - - Bypass DPSK Sample Step -1'h0:: not_bypass: RX DPSK Sample Step is 1 -1'h1:: bypass: RX DPSK Sample Step is 0 - - - - - Switch ADC Clock Edge -1'h0:: not_switch: ADC clock edge is not switched -1'h1:: switch: ADC clock edge is switched - - - Select New Packet -1'h0:: from_LL: newpacket_dsp is from baseband -1'h1:: from_reg: newpacket_dsp is from newpacket_reg - - - Switch DAC Clock Edge -1'h0:: not_switch: DAC clock edge is not switched -1'h1:: switch: DAC clock edge is switched - - - RESERVED - - - LPF Data Width Select -2'h0:: shift_9bits -2'h1:: shift_8bits -2'h2:: shift_7bits -2'h3:: shift_6bits - - - Switch TX DAC datai sign -1'h0:: unsigned: TX DAC datai is unsigned; analog common format -1'h1:: signed: TX DAC datai is signed - - - Switch TX DAC dataq sign -1'h0:: unsigned: TX DAC dataq is unsigned; analog common format -1'h1:: signed: TX DAC dataq is signed - - - Switch RX ADC IQ data sign -1'h0:: unsigned: RX ADC data is unsigned; analog common format -1'h1:: signed: RX ADC data is signed - - - SRRC IQ_SEL Polarity -1'h0:: iq_sel_inv -1'h1:: iq_sel_raw - - - Sum Error Range Control -3'h0 Left shift 3 bits of sum err and limit sumerr within [-2^-4, 2^-4] -3'h1 Left shift 2 bits of sum err and limit sumerr within [-2^-3, 2^-3] -3'h2 Left shift 1 bits of sum err and limit sumerr within [-2^-2, 2^-2] -3'h3 Hold the sum err -3'h4 Right shift 1 bits of sum err -3'h5 Right shift 2 bits of sum err -3'h6 Right shift 3 bits of sum err -3'h7 Right shift 4 bits of sum err; - - - - - Set the AFC frequency of dem750 of rx link -dec2hex(2^16-round(2*740/13e3*2^16)) - - - - - DPSK TX Gain in EDR - - - Set the delay of input gfsk symbol, delay unit is 13MHz clock cycle. - - - Set the delay of input dpsk symbol, delay unit is 13MHz clock cycle. - - - - - Control the guard time length of bt frame -Guard time = (55-cnt_guard_ini)*T13Mclk - - - LL tx_power and debug tx_apc selection. -1'h1:: selected LL tx_power -1'h0::selected debug tx_apc - - - according to tx_power mapping digital gain. -1'h1:: bypass auto gain mapping function -1'h0:: no bypass - - - GFSK TX Gain in BR - - - - - after SRRC RSSI Output - - - after mixer before SRRC RSSI Output. - - - - - after SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal - - - befor SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal - - - Swap I/Q -1'h0:: no_swap: I/Q is not swaped -1'h1:: swap: I/Q is swaped - - - Swap I/Q of ddcl input data -1'h0:: no_swap: I/Q of ddcl input data is not swaped -1'h1:: swap: I/Q of ddcl input data is swaped - - - RESERVED - - - Swap I/Q of Mixer output data -1'h0:: no_swap: I/Q of mixer output data is not swaped -1'h1:: swap: I/Q of mixer output data is swaped - - - Swap ddcl input I data polarity -1'h0:: no_swap: I data polarity of ddcl input is not swaped -1'h1:: swap: I data polarity of ddcl input is swaped - - - Swap ddcl input Q data polarity -1'h0:: no_swap: Q data polarity of ddcl input is not swaped -1'h1:: swap: Q data polarity of ddcl input is swaped - - - Disable the ramping for edr guard time in ramp_gain_tx - - - GFSK TX Gain in EDR - - - - - BB Newpacket flag enable -1'h0:: Disable: the BB Newpacket flag enable -1'h1:: Enable: the BB Newpacket flag enable - - - Packet select -1'h0:: packet72 -1'h1:: new_packet - - - gfsk u_err 10/32 - - - gfsk u_dc 4/512 - - - gfsk ct_u_sp for rx demod - - - - - Switch err_in_patch for bt_dsp rx demod - - - dpsk u_err 8/32 - - - dpsk u_dc 5/64 - - - Switch dpsk ct_u for bt_dsp rx demod - - - - - Set the minimum phase error for rx demod. - - - - - Select the GFSK AFC of demod - - - Select the DPSK AFC of demod - - - RESERVED - - - GFSK demod threshold - - - - - DPSK diff enable -1'h0:: Disable -1'h1:: Enable - - - GFSK diff enable -1'h0:: Disable -1'h1:: Enable - - - DPSK sample threshold for demod - - - GFSK sample threshold for demod - - - GFSK sample 2nd threshold for demod - - - - - gfsk sample reference a2 for demod - - - - - GFSK sample reference a1 for demod - - - GFSK sample reference a3 for demod - - - - - RESERVED - - - tx guard timing delay to switch amp in ramp_gain_tx; counter in 13M - - - RESERVED - - - - - DC Cancle ct code for demod - - - DAC Test Enable -1'h0 dac data is 52m_tx IQ -1'h1 dac data depends on dac_data_sel - - - DAC Data Mux Select -6'b000000:: tx_52m_i: tx_52m_q -6'b000001:: tx_26m_i: tx_26m_q -6'b000010:: iqim_cancel_i: iqim_cancel_q -6'b000011:: tx_13m_i: tx_13m_q -6'b000100:: mixer_tx_i: mixer_tx_q -6'b000101:: accu_tx: blend_tx -6'b000110:: gfilter_tx: diff_tx -6'b000111:: ampm_am: ampm_pm -6'b001000:: cordic_tx_amp: cordic_tx_ang -6'b001001:: symbol2iq_tx_i: symbol2iq_tx_q -6'b001010:: tx_test_data0: tx_test_data1 -6'b100000:: angle: angle_rc -6'b100001:: adc_data_i: adc_data_q -6'b100010:: adc_din_i: adc_din_q -6'b100011:: lpf_i: lpf_q -6'b100100:: rateconv_i: rateconv_q -6'b100101:: calib_i: calib_q -6'b100110:: dc_calib_i: dc_calib_q -6'b100111:: cancel_flt_i: cancel_flt_q -6'b101000:: notch_i: notch_q -6'b101001:: gain_i: gain_q -6'b101010:: ble_mux_i: ble_mux_q -6'b101011:: mixer_i: mixer_q -6'b101100:: srrc_i: srrc_q -6'b101101:: mixer_i_13_0: mixer_q[13:0] -6'b101110:: srrc_i_11_0: srrc_q[11:0] -6'b101111:: err_gfsk: err_dpsk -6'b110000:: afc_gfsk: afc_in -6'b110001:: angle_offset: angle_offset1 -6'b110010:: rssi_out: rssi_out -6'b110011:: rx_test_data0: rx_test_data1 -6'b110100:: rx_test_data2: rx_test_data3 - - - - - 1'b1::SRRC RSSI input data from mixer output data -1'b0::SRRC RSSI input data from SRRC output data - - - 1'b1::mixer RSSI input data from mixer output data -1'b0::mixer RSSI input data from SRRC output data - - - 2'h0::rssi_out = rssi_out_noise_pre -2'h1::rssi_out = rssi_out_noise_post -2'h2::rssi_out = rssi_out_pre -2'h3::rssi_out = rssi_out_post - - - after SRRC RSSI threshold - - - DC cancle1 edr dc hold enable - - - before SRRC RSSI threshold - - - - - Count sample threshold reset for demod. - - - GFSK iph th reference for demod. - - - Sample point initial value - - - - - Guard time length threshold for demod - - - DPSK Seek Start Count - - - Fix7 enable during demod -1'h0:: Disable -1'h1:: Enable - - - Fix7 mode select during bt dsp demod -1'h0:: threshold_2 -1'h1:: threshold_3 - - - Rounding enable after sinc. -1'h0:: Disable -1'h1:: Enable - - - Threshold of Rounding after sinc. - - - - - AGC maximum threshold for demod - - - AGC minimum threshold for demod - - - - - AGC maximum large threshold for demod - - - AGC minimum large threshold for demod - - - - - AGC minimum threshold for demod - - - AGC logarithmic step enable for demod -1'h0:: Disable -1'h1:: Enable - - - AGC step mode for demod -2'b00:: AGC_step_1 -2'b01:: AGC_step_2 -2'b10:: AGC_step_3 -2'b11:: AGC_step_4 - - - AGC step over - - - Delay timer count enable -3'b000:: Delay_0us -3'b001:: Delay_0p5us -3'b010:: Delay_1us -3'b011:: Delay_2us -3'b100:: Delay_3us -3'b101:: Delay_4us -3'b110:: Delay_6us -3'b111:: Delay_8us - - - AGC gain index initial value for bt dsp - - - Demod mode select - - - - - AGC minimum threshold gain select for demod -2'b00:: Gain_2 -2'b01:: Gain_4 -2'b10:: Gain_8 -2'b11:: Gain_16 - - - AGCtm_intv_int initial value for demod - - - AGC tm_intv_int logarithmic initial value for demod - - - - - AGC index select -1'h0:: dgc_index_dsp -1'h1:: dgc_index_mx - - - DGC gain index - - - Maximum agc gain index - - - Newpacket select for demod -1'h0 If newpacket from BB has one zero byte, select GID for demod, else select newpacket from BB -1'h1 Select newpacket from BB - - - Newpacket zero bytes number -2'b00 If the 1st byte of newpacket is zero, -newpacket_bb_sel is logic high, else low -2'b01 If the 1st & 2nd byte of newpacket is zero, -newpacket_bb_sel is logic high, else low -2'b10 If the 1st & 2nd & 3rd byte of newpacket is zero, -newpacket_bb_sel is logic high, else low -2'b11 If the 1st & 2nd & 3rd &4th byte of newpacket is zero, newpacket_bb_sel is logic high, else low - - - AGC mode for dsp -3'h0:: Normal -3'h1:: RESERVED -3'h2:: Hold_after_timer -3'h3:: fix_to_index_ini -3'h4:: Hold_by_FSM -3'h5:: Th_large_mode: select by FSM -others RESERVED - - - - - AGC hold waiting time length - - - AGC hold time length - - - RX DC Calibration Done - - - RX DC Calibration Delay for 1 loop -2'h0:: 0p6ms -2'h1:: 1p2ms -2'h2:: 2p4ms -2'h3:: 4p8ms - - - DC offset fix select for rx -1'h0:: by_calib: DC offset data set by calibration -1'h1:: by_reg: DC offset data set by register - - - - - RX DC fixed offset data for I path when if_fix_dcofst is 1; otherwise use the auto calc values. - - - RX DC fixed offset data for Q path when if_fix_dcofst is 1; otherwise use the auto calc values. - - - - - rx dc offset for dc calibration; selected from dc_cali_i_fix & dc_i2d_work_i - - - rx dc offset for dc calibration; selected from dc_cali_q_fix & dc_i2d_work_q - - - - - TX Calibration Done - - - tx calib out i - - - tx calib out q - - - Fix TX DC Offset - - - TX Calibration Step Counters for 25KHz -2'b00:: 0p125_range -2'b01:: 0p25_range -2'b10:: 0p5_range -2'b11:: full_range - - - TX Calibration Comparison Polarity - - - TX Calibration Offset Polarity -0:: no_switch: the polarity of TX calibration offset -1:: switch: the polarity of TX calibration offset - - - TX Calibration Selection -2'b00:: mean: (tx_cal1 + tx_cal2)/2 -2'b01:: tx_cal1 -2'b10:: tx_cal2 - - - TX Calibration Offset Shift -2'b00:: x4: left shift by 2 bits -2'b01:: x2: left shift by 1 bit -2'b10:: x1: no shift - - - TX Gain Table Pointer during work - - - Bypass TX Calibration Offset -1'b0:: not_bypass -1'b1:: bypass - - - - - Fixed TX I Signed Data for DC offset - - - - - TX Q Signed Data for DC offset - - - - - TX I Signed Data offset in use - - - - - TX Q Signed Data offset in use - - - - - RSSI gain 0000 - - - ARSSI gain 0001 - - - - - RSSI gain 0010 - - - ARSSI gain 0011 - - - - - RSSI gain 0100 - - - ARSSI gain 0101 - - - - - RSSI gain 0110 - - - ARSSI gain 0111 - - - - - RSSI gain 1000 - - - ARSSI gain 1001 - - - - - RSSI gain 1010 - - - ARSSI gain 1011 - - - - - RSSI gain 1100 - - - ARSSI gain 1101 - - - - - RSSI gain 1110 - - - ARSSI gain 1111 - - - - - DAC Clock Force Enable while rx data to dac - - - Test Ports Clock Select -0:: clk_rx -1:: clk_tx - - - Test Ports Data Select -4'h0:: dac_data_i -4'h1:: dac_data_q -4'h2:: dout_tx_i_sum -4'h3:: dout_tx_q_sum -4'h4:: dout_tx_dac_i: depends on dac_data_sel -4'h5:: dout_tx_dac_q -4'h6:: dout_rx_dac_i -4'h7:: dout_rx_dac_q -4'h8:: dout_tx_dac_i_13m: by en_tx_13m -4'h9:: dout_tx_dac_q_13m: by en_tx_13m -4'ha:: dout_rx_dac_i_13m: by en_rx_13m -4'hb:: dout_rx_dac_q_13m: by en_rx_13m -4'hc:: dout_rx_dac_i_14m: by en_rx_14m -4'hd:: dout_rx_dac_q_14m: by en_rx_14m -4'he:: dout_tx_dac_i_26m: by en_tx_26m -4'hf:: dout_tx_dac_q_26m: by en_tx_26m - - - Test Ports Trigger Select -4'h0:: dem_st_chg -4'h1:: agc_st_chg -4'h2:: agc_flg_dem -4'h3:: ble_access_rb -4'h4:: if_peak -4'h5:: if_seeked_all -4'h6:: seek_en -4'h7:: flg_getsymbol -4'h8:: tx_symbol_off_gfsk -4'h9:: tx_amp_sel -4'ha:: tx_flg_start - - - - - Demod sample threshold2 - - - Demod sample threshold1 - - - - - The 4th byte newpacket for demod when sel_sync(register_41[13]) is 1 - - - - - The 3rd byte newpacket for demod when sel_sync(register_41[13]) is 1 - - - - - The 2nd byte newpacket for demod when sel_sync(register_41[13]) is 1 - - - - - The 1st byte newpacket for demod when sel_sync(register_41[13]) is 1 - - - - - SRRC RSSI gain control - - - Bluetooth GFSK modulation filter select - - - MIXER RSSI gain control - - - GFSK demod a2 reference for rx demod - - - - - GFSK demod a1 reference for rx demod - - - GFSK demod a3 reference for rx demod - - - - - GFSK ramp speed select -1'h0:: Slow -1'h1:: Fast - - - GFSK symbol end flag delay, with 13MHz clk step - - - GFSK symbol end flag delay, with 1MHz clk step - - - DPSK symbol delay, with 1MHz clk step - - - GFSK symbol delay, with 1MHz clk step - - - - - after SRRC RSSI noise out - - - after mixer before SRRC RSSI noise out - - - - - Switch the clk edge to sample rf ADC data -1'h0:: negedge: to sample the RF ADC data -1'h1:: posedge: to sample the RF ADC data - - - TX/RX direction -1'h0:: by_hw: TX/RX flag setting by deleying resetn_dsp_tx -1'h1:: by_reg: TX/RX flag setting by register - - - TX/RX flag -1'h0:: RX -1'h1:: TX - - - RESERVED - - - - - TX link 52M clk edge switch -1'h0:: Not_Switch -1'h1:: Switch - - - Digital gain2 output I/Q swap -1'h0:: Not_Swap -1'h1:: Swap - - - Rate converter LPF filter output I/Q swap -1'h0:: Not_Swap -1'h1:: Swap - - - SRRC filter output I/Q swap -1'h0:: Not_Swap -1'h1:: Swap - - - Low Pass Filter Enable in Channel Group1 -1'h0:: bypass -1'h1:: enable - - - Rate Converter Enable in Channel Group1 -1'h0:: bypass -1'h1:: enable - - - Notch Filter Enable in Channel Group1 -1'h0:: bypass -1'h1:: enable - - - Low Pass Filter Enable in Channel Group0 -1'h0:: bypass -1'h1:: enable - - - Rate Converter Enable in Channel Group0 -1'h0:: bypass -1'h1:: enable - - - Notch Filter Enable in Channel Group0 -1'h0:: bypass -1'h1:: enable - - - - - Dynamic sync enable for demod of rx link -1'h0:: static -1'h1:: Dynamic - - - Dynamic sync threshold - - - - - The 2nd minimum sync phase error threshold - - - - - GFSK modulation index - - - - - Tx link IQ swap -1'h0:: Not_swap -1'h1:: Swap - - - GFSK delay after gfsk modulation - - - DPSK delay after dpsk modulation - - - DPSK amplitude delay after dpsk modulation - - - - - Debug Master Data Select -5'h0:: gfilter_tx_dout -5'h1:: symbol2iq_tx_dout_q: symbol2iq_tx_dout_i -5'h2:: cordic_tx_amp_dout: cordic_tx_angle_dout -5'h3:: ampm_tx_dout_am: ampm_tx_dout_pm -5'h4:: diff_tx_dout -5'h5:: freq_blend_tx_dout -5'h6:: intigrate_tx_dout -5'h7:: cordic_iq_tx_dout_q: cordic_iq_tx_dout_i -5'h8:: dout_tx_13m_q: dout_tx_13m_i -5'h9:: iqim_cancel_dout_q: iqim_cancel_dout_i -5'ha:: dout_tx_26m_q: dout_tx_26m_i -5'hb:: dout_tx_52m_q: dout_tx_52m_i -5'hc:: dac_grp_bit_q_outp: dac_grp_bit_i_outp -5'h10:: adc_data_q: adc_data_i -5'h11:: adc_din_q: adc_din_i -5'h12:: lpf_q: lpf_i -5'h13:: rateconv_q: rateconv_i -5'h14:: calib_q: calib_i -5'h15:: dc_calib_q: dc_calib_i -5'h16:: cancel_flt_i: cancel_flt_q -5'h17:: notch_q: notch_i -5'h18:: gain_q: gain_i -5'h19:: ble_mux_q: ble_mux_i -5'h1a:: mixer_q: mixer_i -5'h1b:: srrc_q: srrc_i -5'h1c:: rssi_out -5'h1d:: angle_rc: angle -5'h1e:: angle_offset1: angle_offset -5'h1f:: err_dpsk: err_gfsk - - - - - GFSK modulation index for BLE mode - - - - - newpacket byte 4 inuse; selected from newpacket_reg, GID & newpacket_bb - - - - - newpacket byte 3 inuse; selected from newpacket_reg, GID & newpacket_bb - - - - - newpacket byte 2 inuse; selected from newpacket_reg, GID & newpacket_bb - - - - - newpacket byte 1 inuse; selected from newpacket_reg, GID & newpacket_bb - - - - - ?? - - - ?? - - - - - ?? - - - ?? - - - - - ?? - - - ?? - - - - - ?? - - - - - RESERVED - - - ?? - - - ?? - - - ?? - - - - - ?? - - - - - Error on Q to reduce IQ mismatch Image - - - - - Error on I to reduce IQ mismatch Image - - - - - PM Compensation Shift - - - PM Compensation Bypass -1'b0:: enable -1'b1:: bypass - - - AM Compensation Bypass -1'b0:: enable -1'b1:: bypass - - - AMAM Compensation Coef0 - - - - - AMAM Compensation Coef1 - - - - - AMAM Compensation Coef2 - - - - - AMAM Compensation Coef3 - - - - - AMAM Compensation Coef4 - - - - - AMAM Compensation Coef5 - - - - - AMAM Compensation Coef6 - - - - - AMAM Compensation Coef7 - - - - - AMAM Compensation Coef8 - - - - - AMAM Compensation Coef9 - - - - - AMAM Compensation Coef10 - - - - - AMAM Compensation Coef11 - - - - - AMAM Compensation Coef12 - - - - - AMAM Compensation Coef13 - - - - - AMAM Compensation Coef14 - - - - - AMAM Compensation Coef15 - - - - - AMAM Compensation Coef16 - - - - - AMPM Compensation Coef0 - - - - - AMPM Compensation Coef1 - - - - - AMPM Compensation Coef2 - - - - - AMPM Compensation Coef3 - - - - - AMPM Compensation Coef4 - - - - - AMPM Compensation Coef5 - - - - - AMPM Compensation Coef6 - - - - - AMPM Compensation Coef7 - - - - - AMPM Compensation Coef8 - - - - - AMPM Compensation Coef9 - - - - - AMPM Compensation Coef10 - - - - - AMPM Compensation Coef11 - - - - - AMPM Compensation Coef12 - - - - - AMPM Compensation Coef13 - - - - - AMPM Compensation Coef14 - - - - - AMPM Compensation Coef15 - - - - - AMPM Compensation Coef16 - - - - - Notch Filter Coefficient B - - - - - Notch Filter Coefficient A - - - EDR3 Adapt Demodulation Enable -1'b0:: disable -1'b1:: enable - - - second u_err of the dpsk 2/32 - - - second u_dc of the dpsk 2/512 - - - - - EDR3 Adapt Demodulation Threshold - - - - - auto gfsk digital gain high 4bits. Tx_power=3'h7 - - - auto gfsk digital gain high 4bits. Tx_power=3'h6 - - - auto gfsk digital gain high 4bits. Tx_power=3'h5 - - - auto gfsk digital gain high 4bits. Tx_power=3'h4 - - - - - auto gfsk digital gain high 4bits. Tx_power=3'h3 - - - auto gfsk digital gain high 4bits. Tx_power=3'h2 - - - auto gfsk digital gain high 4bits. Tx_power=3'h1 - - - auto gfsk digital gain high 4bits. Tx_power=3'h0 - - - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h7 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h6 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h5 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h4 - - - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h3 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h2 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h1 - - - auto gfsk edr digital gain high 4bits. Tx_power=3'h0 - - - - - auto dpsk digital gain high 4bits. Tx_power=3'h7 - - - auto dpsk digital gain high 4bits. Tx_power=3'h6 - - - auto dpsk digital gain high 4bits. Tx_power=3'h5 - - - auto dpsk digital gain high 4bits. Tx_power=3'h4 - - - - - auto dpsk digital gain high 4bits. Tx_power=3'h3 - - - auto dpsk digital gain high 4bits. Tx_power=3'h2 - - - auto dpsk digital gain high 4bits. Tx_power=3'h1 - - - auto dpsk digital gain high 4bits. Tx_power=3'h0 - - - - - GFSK modulation equalization gain - - - - - Phase path delay number 2, with 26MHz clk step - - - Phase path delay number 1, with 26MHz clk step - - - GFSK Low pass filter bypass -1'h0 Not bypass -1'h1 bypass -Note: -IQ Tx mode: register_c9[5:4]=00 -Polar Loop & IQ Tx mode: register_c9[5:4]=01 -All Polar Loop Tx mode: register_c9[5:4]=11 - - - GFSK low pass filter enable -1'h0: Enable LPFil, output low pass gfsk signal -1'h1: Disable LPFil, output is zero - - - GFSK low pass filter pass band width select -1: lpfil_freq_tx_bw_ct[4]=0 -BW = 100K + lpfil_freq_tx_bw_ct* 20 -2: lpfil_freq_tx_bw_ct[4]=1 -BW = 50K - - - - - Delay of the gfsk and dpsk mixed phase - - - I/Q path delay number 1, with 26MHz clk step - - - I/Q path delay number 2, with 26MHz clk step - - - High frequency path delay - - - - - amp tmp delay - - - tx polar modulation mode selected -1'b0::phase mode -1'b1::frequency mode - - - tx polar modulation all pass filter bypass ctl -1'b1::bypass -1'b0::no bypass - - - - - tx polar modulation apf num coe-2.14 - - - - - tx polar modulation apf num coe - - - - - tx polar modulation apf num coe - - - - - tx polar modulation apf num coe - - - - - tx polar modulation apf den coe-2.14 - - - - - tx polar modulation apf den coe - - - - - tx polar modulation apf den coe - - - - - ErrSum beta coef -3'h0:: 1div2 -3'h1:: 1div4 -3'h2:: 1div8 -3'h3:: 1div16 -3'h4:: 1div32 -3'h5:: 1div64 - - - third u_err of the dpsk 8/32 - - - third u_dc of the dpsk 1/512 - - - - - - - - - 0: block7, protect disabled or access permitted -1: block7, protect enabled or access forbidden - - - 0: block6, protect disabled or access permitted -1: block6, protect enabled or access forbidden - - - 0: block5, protect disabled or access permitted -1: block5, protect enabled or access forbidden - - - 0: block4, protect disabled or access permitted -1: block4, protect enabled or access forbidden - - - 0: block3, protect disabled or access permitted -1: block3, protect enabled or access forbidden - - - 0: block2, protect disabled or access permitted -1: block2, protect enabled or access forbidden - - - 0: block1, protect disabled or access permitted -1: block1, protect enabled or access forbidden - - - 0: block0, protect disabled or access permitted -1: block0, protect enabled or access forbidden - - - 0: block7, cache remap disabled -1: block7, cache remap enabled - - - 0: block6, cache remap disabled -1: block6, cache remap enabled - - - 0: block5, cache remap disabled -1: block5, cache remap enabled - - - 0: block4, cache remap disabled -1: block4, cache remap enabled - - - 0: block3, cache remap disabled -1: block3, cache remap enabled - - - 0: block2, cache remap disabled -1: block2, cache remap enabled - - - 0: block1, cache remap disabled -1: block1, cache remap enabled - - - 0: block0, cache remap disabled -1: block0, cache remap enabled - - - 0: block7, cache disabled -1: block7, cache enabled - - - 0: block6, cache disabled -1: block6, cache enabled - - - 0: block5, cache disabled -1: block5, cache enabled - - - 0: block4, cache disabled -1: block4, cache enabled - - - 0: block3, cache disabled -1: block3, cache enabled - - - 0: block2, cache disabled -1: block2, cache enabled - - - 0: block1, cache disabled -1: block1, cache enabled - - - 0: block0, cache disabled -1: block0, cache enabled - - - - - block 1 start address - - - - - block 2 start address - - - - - block 3 start address - - - - - block 4 start address - - - - - block 5 start address - - - - - block 6 start address - - - - - block 7 start address - - - - - block 0 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk0_remap_offset - - - - - block 1 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk1_remap_offset - - - - - block 2 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk2_remap_offset - - - - - block 3 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk3_remap_offset - - - - - block 4 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk4_remap_offset - - - - - block 5 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk5_remap_offset - - - - - block 6 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk6_remap_offset - - - - - block 7 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk7_remap_offset - - - - - cache debug mode enable: -0: normal mode -1: debug mode -This bit MUST always be cleared during cache operating - - - 0: (recommended) software can run in cacheable region during software command processing -1: software cannot run in cacheable region during software command processing - - - cache size selection: -0: 4K Byte -1: 8K Byte -2: 16K Byte -3: 32K Byte - - - hprot control register which provide 4bit hprot for cache ctrl AHB? - - - hprot control register which provide 4bit hprot for cache bus AHB - - - Bit [5]: -1b1: hprot[3] from CM4 go through cache controller without modification -1b0: hprot[3] is provided by cache controller register -Bit [4]: -1b1: hprot[2] from CM4 go through cache controller without modification -1b0: hprot[2] is provided by cache controller register -Bit [3]: -1b1: hprot[1] from CM4 go through cache controller without modification -1b0: hprot[1] is provided by cache controller register -Bit [2]: -1b1: hprot[0] from CM4 go through cache controller without modification -1b0: hprot[0] is provided by cache controller register - - - cache write operation mode -2b00: write through -2b01: write back, no write allocate -2b10: write back, write allocate - - - - - trigging address for protect block? - - - - - rf_write_ongoing, this is a status register for write through mode to avoid potential coherence issue. -1b1: the cache is still doing AHB write transaction to the main memory and the data is not written into the main memory. -1b0: the cache has finished AHB write transaction and the data is written into the main memory. - - - rf_cmd_st - - - rf_cache_st - - - - - - cmd_all : not used -cmd_range : start address -cmd_entry : entry address - - - - - cmd_all : not used -cmd_range : start address -cmd_entry : entry address - - - - - software command start: -write 1 to this bit to issue one command - - - software command type: -6h0 : clean all -6h1 : clean range -6h2 : clean entry -6h3 : reserved -6h4 : invalid all -6h5 : invalid range -6h6 : invalid entry -6h7 : reserved -6h8 : clean and invalid all -6h9 : clean and invalid range -6hA : clean and invalid entry -6hB : reserved - - - - - - interrupt enable for protect block trigging? - - - interrupt enable for software command done - - - - - interrupt raw status for protect block trigging - - - interrupt raw status for software command done? - - - - - interrupt masked status for protect block trigging - - - interrupt masked status for software command done? - - - - - interrupt clear for protect block trigging - - - interrupt clear for software command done? - - - - - Cache write hit times. When cache write hit, the counter value increment by 1 - - - - - clear write counter values to zero? - - - 1: write hit/miss counter will run -0: write hit/miss counter will stop - - - Cache write hit times. When cache write hit, the counter value increment by 1 - - - - - Cache read hit times. When cache read hit, the counter value increment by 1? - - - - - clear read counter values to zero? - - - 1: read hit/miss counter will run -0: read hit/miss counter will stop - - - Cache read miss times. When cache read miss, the counter value increment by 1 - - - - - Cache master AHB active cycles in total. When master AHB is active (hsel and htrans[1]), the counter value increment by 1? - - - - - clear HACT and HRDY counter values to zero - - - 1: HACT and HRDY counters will run -0: HACT and HRDY counters will stop - - - The HRDY counter counts the valid cycles of HREADY signal from the cache controller to the master when the master AHB is active. When HREADY signal to the master is high and the master AHB is active, the counter value increment by 1? - - - - - - - - - Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg - - - - - - - number of snapshot - - - - - When read from the Xcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask -When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask - - - When read from the Xcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask -When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask - - - - - bit type is changed from rs to r. - When read: returns the value of the Irq1_Mask register. - When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged. - The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 - - - bit type is changed from rs to r. - When read: returns the value of the Irq0_Mask register. - When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged. - The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 - - - - - bit type is changed from rc to r. - When read: returns the value of the Irq1_Mask register. - When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged. - The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1 - - - bit type is changed from rc to r. - When read: returns the value of the Irq0_Mask register. - When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged. - The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 - - - - - bit type is changed from rs to r. - When read, returns the value of the set/clear register. - When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. - These bits can also trigger interrupts on the XCPU/BCPU if enabled - - - bit type is changed from rs to r. - When read, returns the value of the set/clear register. - When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. - These bits can also trigger interrupts on the XCPU/BCPU if enabled. - - - - - bit type is changed from rc to r. - When read, returns the value of the set/clear register. - When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. - These bits can also trigger interrupts on the XCPU/BCPU if enabled. - - - bit type is changed from rc to r. - When read, returns the value of the set/clear register. - When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. - These bits can also trigger interrupts on the XCPU/BCPU if enabled - - - - - - - - - debug bus master enable - - - - - transfer word length - - - data selection - - - dump trigger selection -select trigger from soft or hardware - - - wrap the whole fifo, when EOF, keep on write by the start addr - - - burst type -2'b00:: single -2'b01:: incr4 -2'b10:: incr8 -2'b11:: incrx - - - length of burst when incrx -max incr16 - - - - - start address of transfer - - - - - mask for transfer error - - - mask for ovfl - - - mask for comp half - - - mask for comp end - - - - - bit type is changed from w1c to rc. - interrupt for ahb transfer error - - - bit type is changed from w1c to rc. - interrupt from fifo overfolw - - - bit type is changed from w1c to rc. - half interrupt from transfer complete - - - bit type is changed from w1c to rc. - end interrupt from transfer complete - - - bit type is changed from w1c to rc. - data_packer soft reset done - - - - - bit type is changed from wos to s. - soft reset - - - - - bit type is changed from wos to s. - dump trigger from soft - - - - - - - - - TX data I. Everytime this register is read, the data will be popped out of the tx_data_fifo. - - - TX data Q. Everytime this register is read, the data will be popped out of the tx_data_fifo. - - - - - revision id. - - - - - debug output enable. - - - 1'd0:: unsigned -1'd1:: 2s_complementary - - - force clock on. - - - tx data enable. -1'd0:: disable -1'd1:: enable - - - i2s delay 1t enable. - - - i2s enable. -1'd0:: disable -1'd1:: enable - - - coherent fmdemsource selection. -1'd0:: output_lpfil -1'd1:: output_dig_gain - - - offset source selection. -1'd0:: output_afc -1'd1:: output_offset_filter - - - rssi source during seek seelction. -1'd0:: rssi_db1 -1'd1:: signal_db1 - - - noise cancel source source selection. -1'd0:: noise_db2 -1'd1:: rssi_db2 - - - noise source selection. -2'd0:: dangle0 -2'd1:: dangle1 -2'd2:: dangle 2 - - - adc clock invert. - - - pilot phase. -1'd0:: sin -1'd1:: cos - - - bypass deemphasis. - - - bypass 15KHz LPF. - - - bypass fircut during seeking. - - - bypass fircut. - - - LR swap. - - - IQ swap for fmdem. - - - IQ swap after 125KHz mixer. - - - IQ swap before 125KHz mixer. - - - lo selection. -1'd0:: low -low if; Default is +125KHz. -1'd1:: high -high if. Default is -125KHz - - - AFC disable. -1'd0:: enable -1'd1:: disable - - - soft blend off. -1'd0:: enable -1'd1:: disable - - - soft mute enable. -1'd0:: disable -1'd1:: enable - - - de-emphasis. -1'd0:: 75us -1'd1:: 50us - - - mono select. -1'd0:: force : mono -1'd1:: stereo - - - mute. -1'd0:: normal -1'd1:: mute - - - - - the number of data words in tx fifowhich are valid for read. - - - tx fifo underflow. User reads tx_fifo_rdata while no data valid in it. - - - tx fifo overflow. User is not able to read tx_fifo_rdata in time so that fm_dsp discard valid data. - - - clear tx fifo. - - - tx data selection. - - - - - SNR counter threshold. - - - delta rssi threshold during UPPER/LOWER seeking. Unit is db. - - - threshold for SNR. Unit is db. - - - seek upper/lower adjacent freq setting. Unit is 5.12KHz. - - - 1'd0:: disable -disable afc during seeking; -1'd1:: enable -enable afc during seeking. - - - seek mode. -3'd0:: seek_current_only -3'd1:: seek_current_or_adjacent -success when either current or adjacent freq is successful; -3'd2:: seek_current_and_adjacent -success when both current and adjacent freq are successful; -3'd3:: snr_st -test mode. stop at SNR_ST; -3'd4:: center_st -test mode. stop at CENTER_ST; -3'd5:: upper_st -test mode. stop at UPPER_ST; -3'd6:: lower_st -testmode. stop at LOWER_ST; -3'd7:: seek_bypass - - - 1'd0: disable -1'd1: enable -[4]: seek with pilot; -[3]: seek with offset; -[2]: seek with snr; -[1]: seek with rssi; -[0]: seek with noise. - - - - - pilot counter threshold. - - - rssi counter threshold. - - - noise counter threshold. - - - offset counter threshold. - - - - - noise low threshold. Unit is db. - - - noise high threshold. Unit is db. - - - RSSI low threshold. Unit is db. - - - RSSI high threshold. Unit is db. - - - - - offset low threshold. Unit is db. - - - offset high threshold. Unit is db. - - - pilot low threshold. Unit is db. - - - pilot high threshold. Unit is db. - - - - - seek time for SNR detect. Unit is 0.75ms. - - - seek time for upper/lower adjacent freq. Unit is 0.75ms. - - - seek time for current freq. Unit is 0.75ms. - - - seek time for agc/afc stable. Unit is 0.75ms. - - - - - [5:3]: afc dc filter bandwidth setting during seeking. -[2:0]: afc acc step setting during seeking. - - - [5:3]: afc dc filter bandwidth setting during seek is ready. -[2:0]: afc acc step setting during seek is ready. - - - afc following range. Unit is 2.5KHz. - - - inverse afc adjust value. - - - - - agc target power. Unit is 2db. - - - agc test mode. Fix gain. - - - agc loop gain during normal. - - - agc loop gian during seeking. - - - agc update time during normal. - - - agc update time during seeking. - - - agc digital gain threshold. Unit is 2db. - - - agc initial index. - - - agc enable delay time after reset. -3'd0:: 0 : 0.375us -3'd1:: 1 : 3us -3'd2:: 2 : 6us -3'd3:: 3 : 9.74us -3'd4:: 4 : 13.875us -3'd5:: 5 : 18us -3'd6:: 6 : 21us -3'd7: 7 : 24us - - - - - basic dig gain. Unit is db. - - - agc IIR bandwidth. - - - [5:3]: agc loop sub step when sinc_over or log_agc>log_agc_th -[2:0]: agc loop sub step when acc I saturation. - - - threshold for agc lopp adjust. Unit is 1db. - - - if 1, adjust agc_index sub step when log_agc>log_agc_th - - - - - ana gain rssi for agc_index=3 - - - ana gain rssi for agc_index=2 - - - ana gain rssi for agc_index=1 - - - ana gain rssi for agc_index=0 - - - - - ana gain rssi for agc_index=7 - - - ana gain rssi for agc_index=6 - - - ana gain rssi for agc_index=5 - - - ana gain rssi for agc_index=4 - - - - - ana gain rssi for agc_index=b - - - ana gain rssi for agc_index=a - - - ana gain rssi for agc_index=9 - - - ana gain rssi for agc_index=8 - - - - - ana gain rssi for agc_index=f - - - ana gain rssi for agc_index=e - - - ana gain rssi for agc_index=d - - - ana gain rssi for agc_index=c - - - - - fircut/gain38k change low threshold for RSSI. Unit is 1db. - - - fircut/gain38k change high threshold for RSSI. Unit is 1db. - - - threshold. Unit is 2db. - - - threshold. Unit is 2db. - - - 1'd0: select cordic fmdem -1'd1: select dpll fmdem. -[2]: for seeing; -[1]: for nosie<th_min; -[0]: for noise>th_max. - - - - - fircut/gain38k change force on - - - fircut bandwidth select during seeking UPPER/LOWER[2:0] and CENTER[5:3]. [40KHz:20KHz:180KHz] - - - fircut bandwidth select during seeready and bad conditiong. Offset is over th. CENTER. [40KHz:20KHz:180KHz] - - - fircut bandwidth select during seek ready and bad condition. Offset is under th. [40KHz:20KHz:180KHz] - - - fircut bandwidth select during seek ready and good condition. [40KHz:20KHz:180KHz] - - - bandwidth threshold. Unit is 2db - - - - - fircut bandwidth select during bad condition. [40KHz:20KHz:180KHz] - - - bandwidth threshold. Unit is 2db - - - - - - - - - [8:6]: gain for mpx signal. -[5:0]: gain for stereo. [5:3]:6db;[2:1]:2db;[0]:1db. - - - dig gain change delay setting. Unit is 0.375us - - - dig gain for signal before 125KHz mixer. -2'd0:: 0db -2'd1:: 6db -2'd2:: 12db -3'd3:: 18db - - - [2]: enable over threshold detection. -[1:0]: over threshold selection. -2'd0:: 0 : 0.75 -2'd1:: 1 : 0.9 -2'd2:: 2 : 0.95 -2'd3:: 3 : 1 - - - 1'd0: *0.75 -1'd1: *1 -for sinc_limit. - - - dc cancel control. -[3]: dccancel mode. 1'd0: bypass; 1'd1: enable -[2:0]: bandwidth. - - - - - 19kHz tone detect bandwidthduring normal. - - - 19kHz tone detect bandwidth during seeking. - - - nco 2ord bandwidth. - - - nco dc bandwidth. - - - softmute threshold for RSSI. - - - softmute threshold for noise. - - - softmute threshold for SNR. - - - - - softmute threshold for offset. - - - softmute rate. Fast->slow. - - - softmute attenu setting. - - - softblend threshold for RSSI. - - - softblend threshold for noise. - - - offset filter bandwidth. - - - - - - - direct deemphasis hcc reg. - - - - - step 19k value - - - interval value - - - - - - - - - - - - - - - - - [5:3]: noise_db1 bandwidth -[2:0]: noise_db2 bandwidth - - - [5:3]: signal_db1 bandwidth -[2:0]: signal_db2 bandwidth - - - [5:3]: rssi_db1 bandwidth -[2:0]: rssi_db2 bandwidth - - - [5:3]: pilot_db1 bandwidth -[2:0]: pilot_db2 bandwitdh - - - - - - - - - rssi. Unit is db. - - - snr. Unit is db. - - - signal. Unit is db. - - - frequency offset. Unit is db. - - - - - - - - - - - [4]: 19k pilot flag -[3]: offset flag -[2]: snr flag -[1]: rssi flag -[0]: noise flag - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - interrupt enable - - - - - interrupt pending - - - - - bit type is changed from w1s to rs. - set interrupt pending - - - - - bit type is changed from w1c to rc. - clear interrupt pending - - - - - - - - - Enable sleep - - - - - sleep stauts -0: not_sleep -1: sleep - - - - - - - - - when 1 written,core enters debug mode, when 0 written, core exits debug mode -when read, 1 means core is in debug mode - - - single step enable - - - - - set when the core is a sleeping state and wait for an event - - - single-step hit, sticky bit that must be cleared by external debugger - - - - - environment call for M-mode - - - store access fault (together with laf) - - - store address Misaligned (never traps) - - - load access fault (together with saf) - - - load access Misaligned (never traps) - - - ebreak instruction causes trap - - - illegal instruction - - - instruction access fault (not implemented) - - - instruction address misaligned (never traps) - - - - - interrupt caused us to enter debug mode - - - exception/interrupt number - - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - general purpose register - - - - - - Next PC to be executed - - - - - previous PC, already executed - - - - - - Statically 2'b11 and cannot be altered - - - Interrupt enable: -When an exception is encountered, Interrupt Enable will be set to 1'b0. -When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS. -If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code. - - - - - - When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. -When an eret instruction is executed, the value from MEPC replaces the current program counter. - - - - - this bit is set when the exception was triggerd by an interrupt - - - exception code - - - - - - hardware loop 0 start - - - - - hardware loop 0 end - - - - - hardware loop 0 counter - - - - - - hardware loop 1 start - - - - - hardware loop 1 end - - - - - hardware loop 1 counter - - - - - - Statically 2'b11 and cannot be altered - - - Interrupt enable: -When an exception is encountered, the current value of MSTATUS is saved in MESTATUS. -When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register. - - - - - - read as 0, which means RV32I - - - RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0. - - - - - - - - - - - - ID of the cluster - - - ID of the within the cluster - - - - - - - - - Revision ID. - - - - - - - BT channel control selection. -1'h0:: bt -1'h1:: reg - - - fm adc clock mode. -1'd0:: divider -divider of pll -1'd1:: adpll -43.008MHz - - - enable bt hopping while channel is muliplier of 26MHz during rx procedure. -If this bit is set to 1'd1, rf_interface will change the ADC clock to 28/56MHz generated by adpll instead of 26/52MHz crystal clock to avoid the receiving interference caused by 26MHz adc clock. - - - enable BT ARFCN tune diff mode. -If this bit is set to 1'd1, rf_interface will redo the rx/tx procedure (including pll calibration process) if ARFCN changes during one rx/tx procedure. - - - enable all digital clock. -If this bit is set to 1'd1, all digital clocks including gating ones will be forcely on. - - - RF mode. -2'd0:: BT -2'd1:: WIFI -2'd2:: FM - - - Chip self_cal enable. -Self cal process will be triggered at posedge of chip_self_cal_enable. - - - soft reset. Active low. - - - - - BT channel type. -1'd0:: normal -1'd1:: multiplier -Multiplier of 26MHz. _x000D_ - - - BT Channel number. _x000D_ -7'h00 : Channel0 _x000D_ -7'h4E : Channel78 - - - - - frequency direct reg. u7.10, unit is MHz - - - WIFI freq mode. -1'd0:: channel -channel number mode. Channel Freq = 2407MHz + 5MH*wf_chn -1'd1:: direct -direct mode. Channel Freq = 2412MH + wf_freq_direct - - - WIFI channel. - - - Start tune. -WIFI will be started at the posedge of wf_tune. - - - - - frequency direct reg. u6.10, unit is MHz - - - FM band select. -2'd0:: 87_108MHz : (US/Europe) -2'd1:: 76_91MHz : (Japan) -2'd2:: 76_108MHz : (World Wide) -2'd3:: 65_76MHz : (East Europe) - - - FM freq mode. -1'd0:: channel -channel number mode. Channel Freq = 25KHz*fm_chan_reg + bottom freq -1'd1:: direct -direct mode. Channel Freq = bottom freq + fm_freq_direct - - - FM channel. - - - Start tune. -FM will be started at the posedge of fm_tune. - - - - - FM intermediate frequency mode. -1'd0:: positive -1'd1:: negtive - - - FM intermediate freqeuncy. u1.10. Unit is Mhz. Default is 125KHz. _x000D_ - - - enable zero intermediate frequency. -1'd0:: use_bt_freq -use intermediate frequency defined by bt_digital_lo_freq; -1'd1:: use_0hz -use 0Hz intermediate frequency. - - - BT intermediate frequency mode. -1'd0:: positive -1'd1:: negtive - - - BT intermediate freqeuncy. u1.10. Unit is Mhz. Default is740KHz. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - To be used when pll_pll_freq_dr=1._x000D_ -Fomula is freq*2^24/(mdll_div*crystal_clk) - - - - - If 1, pll frequency is decided by freq register;_x000D_ - - - - - - - - - If 1, adpll sdm resetn uses sdm_resetn_reg; _x000D_ -if 0, use logic value. - - - adpll Sdm modulator module reset register - - - Invert SDM clock edge. - - - - - SDM dither bypass enable. - - - - - To be used when adpll_sdm_freq_dr=1._x000D_ -Fomula is freq*2^23/crystal_clk - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Pll_vco_band_reg direct reg enable. - - - VCO band setting. - - - - - Vco bit hold time when vco bit changed during pll vco band calibration._x000D_ -3'd0:: vco_bit_hold_time_0 : 0.25us_x000D_ -3'd1:: vco_bit_hold_time_1 : 0.5us_x000D_ -3'd2:: vco_bit_hold_time_2 : 0.75us_x000D_ -3'd3:: vco_bit_hold_time_3 : 1us_x000D_ -3'd4:: vco_bit_hold_time_4 : 1.25us_x000D_ -3'd5:: vco_bit_hold_time_5 : 1.5us_x000D_ -3'd6:: vco_bit_hold_time_6 : 1.75us_x000D_ -3'd7:: vco_bit_hold_time_7 : 2us - - - If 1, select the best vco band bit - - - pll cal count time select_x000D_ -3'd0:: each_cnt_time_0 : 0.5us_x000D_ -3'd1:: each_cnt_time_1 : 1us_x000D_ -3'd2:: each_cnt_time_2 : 2us_x000D_ -3'd4:: each_cnt_time_3 : 4us_x000D_ -3'd5:: each_cnt_time_4 : 8us - - - Define pll_cal initial delay, which is the time between RXON(TXON) and rxpll_cal_enable._x000D_ Unit is us. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Global reset. -1:: unreset -0:: reset - - - debug host uart clock domain reset, active low - - - riscv debug unit rstb. Active low. - - - watch dog reset wcn system enable, 1 enable the reset, else no. - - - wake up logic reset. - - - for bt hclk reset. -1:: unreset -0:: reset - - - for bt 32k clock reset. -1:: unreset -0:: reset - - - uart clock domain reset. -1:: unreset -0:: reset - - - watch dog clock domain reset, 32k actually. -1:: unreset -0:: reset - - - bt master clock reset. -1:: unreset -0:: reset - - - bt core's debug master bus reset. -1:: unreset -0:: reset - - - AUDIFC function reset. Active low. -1:: unreset -0:: reset - - - sys_ifc module bus reset. -1:: unreset -0:: reset - - - riscv jtag-> ahb protocol bus reset. -1:: unreset -0:: reset - - - riscv reset. -1:: unreset -0:: reset - - - bt_dig memory datapath reset. -1:: unreset -0:: reset - - - not used, reserved - - - - - bus clock selection: 0 sel hclk, 1 sel 26m, others sel 32k - - - wake up logic clock enable - - - bt core master clock indicator, 13M as default. - - - bt master clock divider's denom, bt_master_clk = bus_clk/reg_bt_master_clk_denom - - - bit type is changed from w1s to rs. - load the bt_master_clk_denom into the clock divider. - - - bt master clock divider enable, this divider source is hclk. - - - low power clock enable for bt - - - jtag bus clock enable - - - manually to set the sys_ifc bus clock to be open always. - - - manually to set the sys_ifc channels' clock to be open always. - - - manually to set the aud_ifc bus clock to be open always. - - - manually to set the aud_ifc channel 0' clock to be open always. - - - bt_dig memory module's bus clock enable - - - bt core's bus clock enable - - - debug master bus clock enable - - - manually to set the uart clock to be open always. - - - manually to set the uart sys(function) clock to be open always. - - - watch dog clock enable - - - riscv bus clock enable - - - apb bus clock to be open always. - - - memory access with clock enable. - - - - - 13m from osc 26m, for bt master clock sel. - - - bit[21] when 1 sel the result of bit[20], otherwise from hclk divider; bit [20] when 1 sel 26m otherwise 13m - - - bt_master_clk to bt core. - - - ifc debug host dma hclk force on. - - - debug host pclk force enable - - - debug uart pclk force enable - - - debug host sclk force enable - - - bit type is changed from w1s to rs. - use new div parameters for divider. - - - uart clock divider enable. - - - uart clock divider denom's configuration - - - - - bit type is changed from w1s to rs. - Debug host uart clock load configuration - - - Debug host uart clock numerator - - - Debug host uart clock denominator - - - Debug host clock divider enable - - - bit type is changed from w1s to rs. - use new div parameters for divider. - - - clock 208m divider enable. - - - clock 208m divider num's configuration - - - clock 208m divider denom's configuration - - - - - sys to bt irq, read only for check - - - wdt gen irq to system enable control, 1 indicates enable. - - - reserved for future use, the wakeup to sys now use comregs's. - - - generate interrupt to system - - - - - the start address for riscv - - - - - RF Register Interface Selection -1:: SPI -0:: APB - - - - - tx clk sel -1'b1::selected sdm div clk as tx clk - - - tx clk sel -1'b1::selected sdm ref clk as tx clk - - - RX Mode -0:: BT -1:: FM -2:: WLAN - - - Data Source for LVDS Output -1:: internal DFE TX -0:: internal ADC - - - Data Source for Internal DAC -1:: external DFE TX -0:: internal DFE TX - - - Data Source for Internal DFE RX -1:: external ADC -0:: internal ADC - - - - - Debug trigger selection - - - The triger is forced to 0 when disabled. - - - Debug clock selection - - - The debug clock is forced to 0 when disabled. - - - nibble shift mode -0:: nibble_shift_mode0 -Ouptut is {dbg_out[11::0], dbg_out[15::12]} -1:: nibble_shift_mode1 -Ouptut is {dbg_out[15::12], dbg_out[7::4], dbg_out[11::8], dbg_out[3::0]} - - - nibble shift enable -0:: nibble_shift_disable -Output is dbg_out[15::0] -1:: nibble_shift_en -Output is prcoess according dbg_out_nibble_mode - - - Byte swap of dbg_out - - - Half Byte swap of dbg_out - - - when 0, all the mux data is forced to be 0. - - - Debug out selection - - - - - enable external wakeup request - - - enable hci uart break wakeup request - - - enable hci activity wakeup request - - - bt2host wakeup mode -1::level mode -0::pulse mode - - - bt2host wakeup level mode active cycle - - - - - bit type is changed from wos to s. - bt2host wakeup trigger - - - - - bt2host wakeup status - - - - - - - - - - - - - i2s_sel when 1, select the i2s output, else select the pcm. - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - LS+RME+RM(4Bits) + PGEN +KEN +EMA(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - dual port: LS + RMEB + TEST1B + RMB(4Bits)+RMEA+TEST1A+RMA(4Bits)+RET1N+EMAA/EMB(3Bits) - - - - - LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) - - - - - the unit is 1M, 48M in 8910m as default. - - - - - the address for riscv branch from rom, configured by ap - - - - - - - - - - CPU Interactive reg1 - - - CPU Interactive reg0 - - - - - - - - - This field indicates which standard channel to use. -Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. -After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable_ in the control register of the channel to release the channel. -4'h0::use_ch0: use Channel0 -4'h1::use_ch1: use Channel1 -4'h2::use_ch2: use Channel2 -4'h3::use_ch3: use Channel3 -4'h4::use_ch4: use Channel4 -4'h5::use_ch5: use Channel5 -4'h6::use_ch6: use Channel6 -4'h7::use_ch7: use Channel7 -4'hf::all_busy: all channels are busy - - - - - This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is eNonebled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel - - - This register indicates which channel is eNonebled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:: -8'h00::all_ch_disabled: all channel disabled -8'h01::ch0_enabled: Ch0 enabled -8'h02::ch1_enabled: Ch1 enabled -8'h04::ch2_enabled: Ch2 enabled -8'h05::ch_0_2_enabled: Ch0 and Ch2 enabled -8'h07::ch_0_1_2_enabled: Ch0, Ch1 and Ch2 enabled -8'hff::ch_all_enabled: all channels eNonebled - - - - - Debug Channel Status . -0:: dbg_ch_run: The debug channel is running (not idle) -1::dbg_ch_idle: The debug channel is in idle mode - - - - - - When one, flush the interNonel FIFO channel. -This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. -Before writting back this bit to zero the interNonel fifo must empty. - - - Select DMA Request source -0:: SYS_ID_TX_UART -1:: SYS_ID_RX_UART -2:: SYS_ID_TX_SDMMC -3:: SYS_ID_RX_SDMMC -4:: SYS_ID_TX_SPI1 -5:: SYS_ID_RX_SPI1 -6:: SYS_ID_TX_DEBUG_UART -7:: SYS_ID_RX_DEBUG_UART - - - Peripheral Size -0::per_size_8: 8-bit peripheral -1::per_size_32: 32-bit peripheral - - - Set Auto-disable_ mode -0::auto_disable_close: when TC reach zero the channel is not automatically released. -1::auto_disable_open: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. - - - Set Auto-disable_ mode -0:: auto_dis_mode0: when TC reach zero the channel is not automatically released. -1:: auto_dis_mode1: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. - - - Read FIFO data exchange high 8-bit and low 8-bit. -0:: Exchange -1:: No_exchange - - - bit type is changed from wrc to rc. - Channel Disable, write one in this bit disable_ the channel. -When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d. - - - bit type is changed from wrc to rc. - Channel Enable, write one in this bit eNoneble the channel. -When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. - - - - - The internal channel fifo is empty - - - Enable bit, when '1' the channel is running - - - - - AHB Address. This field represent the start address of the transfer. -For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - Transfer Count, this field indicated the transfer size_ in bytes to perform. -During a transfer a write in this register add the new value to the current TC. -A read of this register return the current current transfer count. - - - - - When one, flush the interNonel FIFO channel. -This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. -Before writting back this bit to zero the interNonel fifo must empty. - - - Select DMA Request source -0:: SYS_ID_TX_UART -1:: SYS_ID_RX_UART -2:: SYS_ID_TX_SDMMC -3:: SYS_ID_RX_SDMMC -4:: SYS_ID_TX_SPI1 -5:: SYS_ID_RX_SPI1 -6:: SYS_ID_TX_DEBUG_UART -7:: SYS_ID_RX_DEBUG_UART - - - Peripheral Size -0::per_size_8: 8-bit peripheral -1::per_size_32: 32-bit peripheral - - - Set Auto-disable_ mode -0::auto_disable_close: when TC reach zero the channel is not automatically released. -1::auto_disable_open: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. - - - Set Auto-disable_ mode -0:: auto_dis_mode0: when TC reach zero the channel is not automatically released. -1:: auto_dis_mode1: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. - - - Read FIFO data exchange high 8-bit and low 8-bit. -0:: Exchange -1:: No_exchange - - - bit type is changed from wrc to rc. - Channel Disable, write one in this bit disable_ the channel. -When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d. - - - bit type is changed from wrc to rc. - Channel Enable, write one in this bit eNoneble the channel. -When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. - - - - - The internal channel fifo is empty - - - Enable bit, when '1' the channel is running - - - - - AHB Address. This field represent the start address of the transfer. -For a 32-bit peripheral, this address must be aligned 32-bit. - - - - - Transfer Count, this field indicated the transfer size_ in bytes to perform. -During a transfer a write in this register add the new value to the current TC. -A read of this register return the current current transfer count. - - - - - - - - - indicates the counter decreasing to 0. - - - indicates clock source, 0 is reference clock, 1 is mcu clk. - - - interrupte enable - - - systick counter enable - - - - - the value to load into cvr when counter decreases to 0. - - - - - the current cvr value. - - - - - indicates whether ref clk is implemented. 0 means implemented. - - - indicates whether 10ms calibration value is exact. - - - calibration value of the reload value to be used for 10ms timing - - - - - clear the interrupte. - - - - - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - address to be trapped. Range 0x00000000~0x0003fffc - - - - - trap enable for 32 channels - - - - - base address to trapped to. Should be 32 words aligned (such as 0x00053e80 or 0x0004ff00).For the nth patch, the actual address is trap_out_base+4n - - - - - - - - - Length of a break, in number of bits. - - - Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept. - - - When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). - - - Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped. -1::ENABLE -0:: DISABLE - - - Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. -0:: DISABLE -1::ENABLE - - - When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details). - - - Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16. -0 = (BCLK = SCLK / 4) -1 = (BCLK = SCLK / 16) -0:div_4 -1:div_16 - - - Controls the parity format when parity is enabled: -0::odd: an odd number of received 1 bits is checked, or transmitted (the parity bit is included). -1::even: an even number of received 1 bits is checked or transmitted (the parity bit is included). -2::space: space a space is generated and received as parity bit. -3::mark: a mark is generated and received as parity bit. - - - Parity is enabled when this bit is set. -0::NO -1:: YES - - - Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0). -0::1_bit :one stop bit is transmitted in the serial data. -1:: 2_bits:two stop bits are generated and transmitted in the serial data out. - - - Number of data bits per character (least significant bit first): -0::7_bits -1::8_bits - - - Allows to turn off the UART: -0:: Disable -1::Enable - - - - - This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early. - - - Current value of the DTR line. - - - current value of the Uart_CTS line. -1::Tx_allow_n:Tx not allowed. -0::Tx_alllow:Tx allowed. - - - This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. - - - This bit indicates that the UART is receiving a byte. - - - This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. - - - Those bits indicate the number of space available in the Tx Fifo. - - - Those bits indicate the number of data available in the Rx Fifo. Those data can be read. - - - - - The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. - - - - - Falling edge detected on the UART_DTR signal. - - - Rising edge detected on the UART_DTR signal. - - - In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. - - - Pulse detected on Uart_Dma_Rx_Done_H signal - - - Pulse detected on Uart_Dma_Tx_Done_H signal. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. - - - No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. - - - Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). - - - Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). - - - Clear to send signal change detected. - - - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - Same as previous, not masked. - - - This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register. - - - This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register. - - - In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. - - - This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. - - - This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. - - - Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. - - - No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. - - - Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. - - - Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. - - - Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. - - - - - Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC). -The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. - - - Defines the empty threshold level at which the Data Needed Interrupt will be generated. -The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. - - - Defines the empty threshold level at which the Data Available Interrupt will be generated. -The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. - - - - - Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared. - - - Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared. - - - bit type is changed from w1s to rs. - this bit is set to 1 when writing 1, cleared to 0 when corresponding filed is cleared in UART_CMD_CLR - - - bit type is changed from w1s to rs. - refer to bit [5] - - - bit type is changed from w1s to rs. - refer to bit [5] - - - bit type is changed from w1s to rs. - refer to bit [5] - - - bit type is changed from w1s to rs. - refer to bit [5] - - - bit type is changed from w1s to rs. - refer to bit [5] - - - - - bit type is changed from w1c to rc. - this bit is cleared to 0 when writing 1, set to 1 when corresponding filed is set in UART_CMD_SET - - - bit type is changed from w1c to rc. - refer to bit [5] - - - bit type is changed from w1c to rc. - refer to bit [5] - - - bit type is changed from w1c to rc. - refer to bit [5] - - - bit type is changed from w1c to rc. - refer to bit [5] - - - bit type is changed from w1c to rc. - refer to bit [5] - - - - - - - - - - - - - - - - - - - - - wdt_cvr0_count_value_0 - - - - - wdt_cvr1_count_value_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0: enalbe, 1: disable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Ap APB base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - System AHB base - - - - - - - - - - PSRAM base - - - - - - - PSRAM base - - - - - - - ADI mst base - - - - - - - - - - - - - - - - - - - - - - - System AON APB base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COREISHGT Base - - - - - - - - - - - - - - - - - - - - - - - - - - - - BB_SYS ADDR base - - - - - - - - - - - - - - - - - - - - - - - - - ZSP_SYS ADDR base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GGE_BB_APB ADDR base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GGE_SYS_APB ADDR base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RF_APB ADDR base - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WCN SYS APB ADDR base - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/config.ini b/4G/tools/_temp/uis_tools/setting/chips/8910/config.ini deleted file mode 100644 index 8acefcf..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/config.ini +++ /dev/null @@ -1,60 +0,0 @@ -[DiagPort] -Enable=0 -Com= -BaudRate=2000000 - -[ChannelServer] -Enable=0 -IP=127.0.0.1 -Port=36666 - -[DebugHost] -Enable=0 -Com= -BaudRate=921600 - -[DebugUart] -Enable=0 -Com= -BaudRate=921600 - -[Uart] -Enable=0 -Com= -BaudRate=921600 - -[CoolHost] -Enable=0 -IP=127.0.0.1 -Port=7726 - -[T32Cmm] -Enable=1 -File=E:/luatools_py3/log/ramdump/2025-02-17_103343_CSDK_V0001_UIS8910_352273017386340_COM185/loadbin.cmm -Mips=0 - -[Daplink] -Enable=0 -ID= -Type=openocd -Core=AP - -[UIEnable] -frmDebugHost=1 -frmCoolHost=1 -frmDebugUart=1 -frmUart=1 -frmDiagPort=0 -frmChannelServer=0 -frmDapLink=1 -frmT32=1 - -[Ping] -Address=0x80008000 - -[ELF] -CheckVersion=1 -CheckPanic=1 -AP=E:/luatos-sdk-rda8910/idh.code/hex/csdk_test_debug/csdk.elf -CP= -App= diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910.xml b/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910.xml deleted file mode 100644 index bca15cd..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910.xml +++ /dev/null @@ -1,116 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910_CX.xml b/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910_CX.xml deleted file mode 100644 index 6ea8108..0000000 --- a/4G/tools/_temp/uis_tools/setting/chips/8910/fota8910_CX.xml +++ /dev/null @@ -1,116 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/4G/tools/_temp/uis_tools/setting/config.ini b/4G/tools/_temp/uis_tools/setting/config.ini deleted file mode 100644 index 9cebcda..0000000 --- a/4G/tools/_temp/uis_tools/setting/config.ini +++ /dev/null @@ -1,53 +0,0 @@ -[Chip] -Chip=8910 - -[GdbServer] -GdbExe=default gdb -Mode=8910AP -NoThread=0 - -[HeapReport] -Type=8811 - -[BlueScreenDump] -Dir=BlueScreen - -[AutoTest] -AutoConnect=0 -AutoBSDump=0 -RestartAfterCrashDump=0 -DaplinkDump=0 -DaplinkFirst=0 -Interval=7000 - -[MiscDump] -Profile=0 -Power=0 -HeapRecord=0 - -[ELF] -CheckVersion=1 -CheckPanic=1 -8811= - -[Pyocd] -Python= - -[Log] -More=0 -TimeStamp=1 -WriteToFile=0 -MaxFileSize=100 -AutoScroll=1 - -[ScriptServer] -Port=17100 - -[RegView] -SearchName=1 -SearchAddr=1 -SearchDesc=1 -SearchSize=1 - -[Path] -BlueScreenDataDir=E:/luatools_py3/log/ramdump/2025-02-17_103343_CSDK_V0001_UIS8910_352273017386340_COM185 diff --git a/4G/tools/_temp/uis_tools/setting/diagmonitor.ini b/4G/tools/_temp/uis_tools/setting/diagmonitor.ini deleted file mode 100644 index b673ba6..0000000 --- a/4G/tools/_temp/uis_tools/setting/diagmonitor.ini +++ /dev/null @@ -1,5 +0,0 @@ -[cfg] -host=127.0.0.1 -port=36666 -WarningTime=10 -ErrorTime=30 diff --git a/4G/tools/_temp/uis_tools/setting/dtools_completion b/4G/tools/_temp/uis_tools/setting/dtools_completion deleted file mode 100644 index ffd6aa8..0000000 --- a/4G/tools/_temp/uis_tools/setting/dtools_completion +++ /dev/null @@ -1,23 +0,0 @@ -# bash completion for dtools -# -# Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). -# All rights reserved. -# -# This software is supplied "AS IS" without any warranties. -# RDA assumes no responsibility or liability for the use of the software, -# conveys no license or title under any patent, copyright, or mask work -# right to the product. RDA reserves the right to make changes in the -# software without notification. RDA also make no representation or -# warranty that such application will be suitable for the specified use -# without further testing or modification. - -__dtools_complete() { - if [[ "1" -eq "$COMP_CWORD" ]]; then - local _program=$1 - local _cmdlist=$(${_program/\~/$HOME} cmdlist) - COMPREPLY=($(compgen -W "$_cmdlist" -- "${COMP_WORDS[COMP_CWORD]}")) - return - fi -} -complete -o nospace -o default -F __dtools_complete dtools -complete -o nospace -o default -F __dtools_complete dtools.exe diff --git a/4G/tools/config/global.ini b/4G/tools/config/global.ini deleted file mode 100644 index 107526a..0000000 --- a/4G/tools/config/global.ini +++ /dev/null @@ -1,12 +0,0 @@ -[mode] -type = 1 - -[ui] -ui_x = 1420 -ui_y = 977 -ui_project_x = 1024 -ui_project_y = 768 - -[lua] -debug = True - diff --git a/4G/tools/config/self.json b/4G/tools/config/self.json deleted file mode 100644 index ea1b6b5..0000000 --- a/4G/tools/config/self.json +++ /dev/null @@ -1 +0,0 @@ -{"id": "6c840c7d103b4024b6d8f4a6f603dfe9"} \ No newline at end of file diff --git a/4G/tools/config/tips.zip b/4G/tools/config/tips.zip deleted file mode 100644 index f58cad6..0000000 Binary files a/4G/tools/config/tips.zip and /dev/null differ diff --git a/4G/tools/config/tips_time.bin b/4G/tools/config/tips_time.bin deleted file mode 100644 index c817413..0000000 --- a/4G/tools/config/tips_time.bin +++ /dev/null @@ -1 +0,0 @@ -1773636048.527883 \ No newline at end of file diff --git a/4G/tools/log/tools_20260316.txt b/4G/tools/log/tools_20260316.txt deleted file mode 100644 index 2d7ea3a..0000000 --- a/4G/tools/log/tools_20260316.txt +++ /dev/null @@ -1,50 +0,0 @@ -2026-03-16 12:40:44.081 core.py:75 INFO 3.1.11 start! -2026-03-16 12:40:44.307 usb_device.py:346 INFO 本地工具解压开始 -2026-03-16 12:40:44.375 ui_main.py:93 INFO 初始化主界面 (143, 45) (1420, 977) -2026-03-16 12:40:44.578 ui_main.py:102 INFO 本地编码集utf-8 -2026-03-16 12:40:44.654 ui_main.py:302 INFO 当前语言设置: auto -2026-03-16 12:40:44.655 ui_main.py:311 INFO 选取语言: zh_CN -2026-03-16 12:40:44.733 usb_device.py:1510 INFO usb device trace -2026-03-16 12:40:44.740 my_api.py:114 INFO [None, None] -2026-03-16 12:40:44.741 usb_device.py:3399 INFO enter Trace -2026-03-16 12:40:44.817 ui_main.py:463 INFO ui start -2026-03-16 12:40:44.821 ui_main.py:2348 INFO 日志清理线程结束,共删除文件 0 个,共删除 0 M字节 -2026-03-16 12:40:46.159 usb_device.py:3389 INFO usb device ready! -2026-03-16 12:40:46.695 usb_device.py:366 INFO 本地工具解压完成, 耗时: 2.39秒 -2026-03-16 12:40:56.451 ui_project.py:235 INFO 载入项目文件 -2026-03-16 12:40:56.458 ui_project.py:257 INFO 载入项目文件 - 完成, 共1个 -2026-03-16 12:41:17.793 usb_device.py:1504 INFO usb device sleep -2026-03-16 12:41:17.793 my_api.py:114 INFO [None, None] -2026-03-16 12:41:17.794 my_api.py:114 INFO [None, None] -2026-03-16 12:41:17.794 usb_device.py:3408 INFO quit Trace -2026-03-16 12:41:17.903 my_api.py:114 INFO [None, None] -2026-03-16 12:41:17.904 host_device.py:506 INFO task quit -2026-03-16 12:41:17.904 my_api.py:114 INFO [None, None] -2026-03-16 12:41:17.905 usb_device.py:3420 INFO task quit -2026-03-16 12:41:18.181 core.py:220 INFO event loop closed -2026-03-16 12:41:18.696 core.py:245 INFO end! -2026-03-16 12:41:35.368 core.py:75 INFO 3.1.11 start! -2026-03-16 12:41:35.578 usb_device.py:346 INFO 本地工具解压开始 -2026-03-16 12:41:35.644 ui_main.py:93 INFO 初始化主界面 (143, 45) (1420, 977) -2026-03-16 12:41:35.814 ui_main.py:102 INFO 本地编码集utf-8 -2026-03-16 12:41:35.833 ui_main.py:302 INFO 当前语言设置: auto -2026-03-16 12:41:35.834 ui_main.py:311 INFO 选取语言: zh_CN -2026-03-16 12:41:35.911 usb_device.py:1510 INFO usb device trace -2026-03-16 12:41:35.911 my_api.py:114 INFO [None, None] -2026-03-16 12:41:35.911 usb_device.py:3399 INFO enter Trace -2026-03-16 12:41:35.945 ui_main.py:463 INFO ui start -2026-03-16 12:41:35.950 ui_main.py:2348 INFO 日志清理线程结束,共删除文件 0 个,共删除 0 M字节 -2026-03-16 12:41:37.402 usb_device.py:3389 INFO usb device ready! -2026-03-16 12:41:37.770 usb_device.py:366 INFO 本地工具解压完成, 耗时: 2.19秒 -2026-03-16 12:41:39.379 ui_project.py:235 INFO 载入项目文件 -2026-03-16 12:41:39.380 ui_project.py:257 INFO 载入项目文件 - 完成, 共1个 -2026-03-16 12:41:48.975 usb_device.py:1504 INFO usb device sleep -2026-03-16 12:41:48.976 my_api.py:114 INFO [None, None] -2026-03-16 12:41:48.976 my_api.py:114 INFO [None, None] -2026-03-16 12:41:48.977 usb_device.py:3408 INFO quit Trace -2026-03-16 12:41:49.091 my_api.py:114 INFO [None, None] -2026-03-16 12:41:49.091 host_device.py:506 INFO task quit -2026-03-16 12:41:49.091 my_api.py:114 INFO [None, None] -2026-03-16 12:41:49.091 usb_device.py:3420 INFO task quit -2026-03-16 12:41:49.375 core.py:220 INFO event loop closed -2026-03-16 12:41:49.888 core.py:245 INFO end! diff --git a/4G/tools/project/鐧剧憺浜戝揩鍏4G浜屾寮鍙.ini b/4G/tools/project/鐧剧憺浜戝揩鍏4G浜屾寮鍙.ini deleted file mode 100644 index c14ae6c..0000000 --- a/4G/tools/project/鐧剧憺浜戝揩鍏4G浜屾寮鍙.ini +++ /dev/null @@ -1,74 +0,0 @@ -[info] -core_path = C:\Users\Administrator\Desktop\yunkuaichong\4G\code\bin\LuatOS-Air_V4035_RDA8910_BT_FLOAT.pac -type = .pac -active = False -lib = -demo = -output_path = -output_suffix_enable = False -output_suffix = -code_enable = False -code = -print_mode = 2 -add_core = False -only_code = False -only_luac_code = False - -[C:\Users\Administrator\Desktop\yunkuaichong\4G\code\lib] -agps.lua = -agps9701.lua = -agpsHxxt.lua = -agpsZkw.lua = -aLiYun.lua = -aLiYunOta.lua = -audio.lua = -cc.lua = -clib.lua = -common.lua = -console.lua = -errDump.lua = -ftp.lua = -gps.lua = -gps9701.lua = -gpsHxxt.lua = -gpsZkw.lua = -http.lua = -lbsLoc.lua = -led.lua = -link.lua = -log.lua = -misc.lua = -mqtt.lua = -net.lua = -netLed.lua = -ntp.lua = -nvm.lua = -patch.lua = -pb.lua = -pins.lua = -pm.lua = -powerKey.lua = -record.lua = -ril.lua = -scanCode.lua = -sim.lua = -sms.lua = -socket.lua = -socket4G.lua = -socketCh395.lua = -socketESP8266.lua = -sys.lua = -sysplus.lua = -uiWin.lua = -update.lua = -utils.lua = -wdt.lua = -websocket.lua = -wifiRil.lua = -wifiScan.lua = - -[C:\Users\Administrator\Desktop\yunkuaichong\4G\code\core] -main.lua = -cmd.lua = -linksocket.lua = - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22.zip b/4G/tools/resource/soc_script/v2025.12.31.22.zip deleted file mode 100644 index 8c67c85..0000000 Binary files a/4G/tools/resource/soc_script/v2025.12.31.22.zip and /dev/null differ diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/air153C_wtd.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/air153C_wtd.lua deleted file mode 100644 index e03b00b..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/air153C_wtd.lua +++ /dev/null @@ -1,60 +0,0 @@ ---[[ -@module air153C_wtd -@summary 娣诲姞杞欢鐪嬮棬鐙楀姛鑳斤紝闃叉姝绘満 -@data 2023.5.23 -@author 缈熺鐮 -@usage ---local air153C_wtd = require ("air153C_wtd") --- 鐢ㄦ硶瀹炰緥 --- sys.taskInit(function () --- air153C_wtd.init(28) --- air153C_wtd.feed_dog(28,10)--28涓虹湅闂ㄧ嫍寮曡剼锛10涓鸿缃杺鐙楁椂闂 --- --air153C_wtd.set_time(1)--寮鍚畾鏃舵ā寮忓啀鎵撳紑姝や唬鐮侊紝鍚﹀垯鏃犳晥 --- end) -]] -local sys = require "sys" -_G.sysplus = require("sysplus") -air153C_wtd={} ---[[ -鍒濆鍖栧紩鑴 -@api air153C_wtd.init(watchdogPin) -@int 鐪嬮棬鐙楁帶鍒跺紩鑴 -@return nil 鏃犺繑鍥炲 -@usage -air153C_wtd.init(28) -]] -function air153C_wtd.init(watchdogPin) - gpio.setup(watchdogPin,0,gpio.PULLDOWN) - gpio.set(watchdogPin,0) -end -function air153C_wtd.callback(watchdogPin) - gpio.set(watchdogPin,0) -end ---[[ -璋冪敤姝ゅ嚱鏁拌繘琛屽杺鐙 -@api air153C_wtd.feed_dog(watchdogPin) -@int watchdogPin璁剧疆鐪嬮棬鐙楁帶鍒跺紩鑴 -@return nil 鏃犺繑鍥炲 -@usage -air153C_wtd.feed_dog(28) -]] -function air153C_wtd.feed_dog(watchdogPin) - local watchdogFeedDuration = 400 - gpio.set(watchdogPin,1) - sys.timerStart(air153C_wtd.callback,watchdogFeedDuration,watchdogPin) -end ---[[ -璋冪敤姝ゅ嚱鏁板叧闂杺鐙楋紝璋ㄦ厧浣跨敤! -@api air153C_wtd.close_watch_dog(watchdogPin) -@int watchdogPin璁剧疆鐪嬮棬鐙楁帶鍒跺紩鑴 -@return nil 鏃犺繑鍥炲 -@usage -air153C_wtd.close_watch_dog(28) -]] -function air153C_wtd.close_watch_dog(watchdogPin) - local watchdogStopDuration = 700 - gpio.set(watchdogPin,1) - sys.timerStart(air153C_wtd.callback,watchdogStopDuration,watchdogPin) -end - -return air153C_wtd diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/airlbs.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/airlbs.lua deleted file mode 100644 index 2d68bcf..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/airlbs.lua +++ /dev/null @@ -1,239 +0,0 @@ ---[[ -@module airlbs -@summary airlbs 瀹氫綅鏈嶅姟(鏀惰垂鏈嶅姟锛岄渶鑷鑱旂郴閿鍞敵璇) -@version 1.1 -@date 2024.12.30 -@author Dozingfiretruck -@usage --- lbsloc 鏄紓姝ュ洖璋冩帴鍙ｏ紝 --- lbsloc2 鏄槸鍚屾鎺ュ彛銆 --- lbsloc姣攍bsloc2澶氫簡涓涓姹傚湴鍧鏂囨湰鐨勫姛鑳姐 --- lbsloc 鍜 lbsloc2 閮芥槸鍏嶈垂LBS瀹氫綅鐨勫疄鐜版柟寮忥紱 --- airlbs 鎵╁睍搴撴槸鏀惰垂 LBS 鐨勫疄鐜版柟寮忋 -]] - - -sys = require("sys") -sysplus = require("sysplus") -libnet = require "libnet" - -local airlbs_host = "airlbs.openluat.com" -local airlbs_port = 12413 - -local lib_name = "airlbs" -local lib_topic = lib_name .. "topic" - -local location_data = 0 -local disconnect = -1 -local airlbs_timeout = 15000 - -local airlbs = {} - -local function airlbs_task(task_name, buff, timeout, adapter) - local netc = socket.create(nil, lib_name) - socket.config(netc, nil, true) -- udp - - sysplus.cleanMsg(lib_name) - local result = libnet.connect(lib_name, 15000, netc, airlbs_host, airlbs_port) - if result then - log.info(lib_name, "鏈嶅姟鍣ㄨ繛涓婁簡") - libnet.tx(lib_name, 0, netc, buff) - else - log.info(lib_name, "鏈嶅姟鍣ㄦ病杩炰笂浜!!!") - sys.publish(lib_topic, disconnect) - libnet.close(lib_name, 5000, netc) - return - end - buff:del() - while result do - local succ, param = socket.rx(netc, buff) - if not succ then - log.error(lib_name, "鏈嶅姟鍣ㄦ柇寮浜", succ, param) - sys.publish(lib_topic, disconnect) - break - end - if buff:used() > 0 then - local location = nil - local data = buff:query(0, 1) -- 鑾峰彇鏁版嵁 - if data:toHex() == '00' then - location = json.decode(buff:query(1)) - else - log.error(lib_name, "not json data") - end - sys.publish(lib_topic, location_data, location) - buff:del() - break - end - result, param, param2 = libnet.wait(lib_name, timeout, netc) - log.info(lib_name, "wait", result, param, param2) - if param == false then - log.error(lib_name, "鏈嶅姟鍣ㄦ柇寮浜", succ, param) - sys.publish(lib_topic, disconnect) - break - end - end - libnet.close(lib_name, 5000, netc) -end - --- 澶勭悊鏈瘑鍒殑缃戠粶娑堟伅 -local function netCB(msg) - log.info("鏈鐞嗘秷鎭", msg[1], msg[2], msg[3], msg[4]) -end - ---[[ -鑾峰彇瀹氫綅鏁版嵁 -@api airlbs.request(param) -@param table 鍙傛暟(鑱旂郴閿鍞幏鍙杋d涓巏ey) project_id:椤圭洰ID project_key:椤圭洰瀵嗛挜 timeout:瓒呮椂鏃堕棿,鍗曚綅姣 榛樿15000 adapter: 缃戠粶閫傞厤鍣╥d,鍙,榛樿鏄钩鍙拌嚜甯︾殑缃戠粶鍗忚鏍 -@return bool 鎴愬姛杩斿洖true,澶辫触浼氳繑鍥瀎alse -@return table 瀹氫綅鎴愬姛鐢熸晥锛屾垚鍔熻繑鍥炲畾浣嶆暟鎹 -@usage ---娉ㄦ剰:鍑芥暟鍐呭洜浣跨敤浜唖ys.waitUntil闃诲鎺ュ彛锛屾墍浠pi闇瑕佸湪鍗忕▼涓娇鐢 ---娉ㄦ剰:浣跨敤鍓嶉渶鍚屾鏃堕棿 - -local airlbs = require "airlbs" - -sys.taskInit(function() - -- 绛夊緟缃戠粶灏辩华 - sys.waitUntil("IP_READY") - -- 鎵ц鏃堕棿鍚屾 - socket.sntp() - sys.waitUntil("NTP_UPDATE", 10000) - while 1 do - -- airlbs璇锋眰瀹氫綅 - local result ,data = airlbs.request({ - project_id = airlbs_project_id, - project_key = airlbs_project_key, - timeout = 10000, - adapter = socket.LWIP_STA - }) - if result then - log.info("airlbs", json.encode(data)) - end - sys.wait(20000) - end -end) -]] -function airlbs.request(param) - if not param or param.project_id == nil or param.project_key == nil then - log.error(lib_name, "param error") - return false - end - - if not mobile and not param.wifi_info then - log.error(lib_name, "no mobile and no wifi_info") - return false - end - - local udp_buff = zbuff.create(1500) - local auth_type = 0x01 - local lbs_data_type = 0x00 - local project_id = param.project_id - if project_id:len() ~= 6 then - log.error("airlbs", "project_id len not 6") - end - local mac1 = netdrv.mac(socket.LWIP_STA) - local mac = "MAC" .. mac1 - log.info("mac", mac) - local timestamp = os.time() - local project_key = param.project_key - local nonce = crypto.trng(6) - local hmac_data - local bsp = rtos.bsp() - log.info("纭欢鍨嬪彿", rtos.bsp()) - if bsp == "Air8101" then - -- 姝ゅ鐢变簬鐩墠灞炰簬娴嬭瘯闃舵锛屽厛灏唌uid鍐欐锛屽悗缁細杩涜淇敼 - -- local muid = mcu.muid() or "" - local muid = "12345678901234567890123456789012" - log.info("muid", muid) - hmac_data = crypto.hmac_sha1(project_id .. mac .. muid .. timestamp .. nonce, project_key) - else - local imei = mobile and mobile.imei() or "" - local muid = mobile and mobile.muid() or "" - hmac_data = crypto.hmac_sha1(project_id .. imei .. muid .. timestamp .. nonce, project_key) - end - -- log.debug(lib_name,"hmac_sha1", hmac_data) - local lbs_data = {} - if mobile then - mobile.reqCellInfo(60) - sys.waitUntil("CELL_INFO_UPDATE", param.timeout or airlbs_timeout) - lbs_data.cells = {} - -- log.info("cell", json.encode(mobile.getCellInfo())) - for k, v in pairs(mobile.getCellInfo()) do - lbs_data.cells[k] = {} - lbs_data.cells[k][1] = v.mcc - lbs_data.cells[k][2] = v.mnc - lbs_data.cells[k][3] = v.tac - lbs_data.cells[k][4] = v.cid - lbs_data.cells[k][5] = v.rssi or v.rsrp - lbs_data.cells[k][6] = v.snr - lbs_data.cells[k][7] = v.pci - lbs_data.cells[k][8] = v.rsrp - lbs_data.cells[k][9] = v.rsrq - lbs_data.cells[k][10] = v.earfcn - end - end - if param.wifi_info and #param.wifi_info > 0 then - lbs_data.macs = {} - for k, v in pairs(param.wifi_info) do - lbs_data.macs[k] = {} - lbs_data.macs[k][1] = v.bssid:toHex():gsub("(%x%x)", "%1:"):sub(1, -2) - lbs_data.macs[k][2] = v.rssi - end - end - local lbs_jdata = json.encode(lbs_data) - log.info("鎵弿鍑虹殑鏁版嵁",lbs_jdata) - local bsp = rtos.bsp() - if bsp == "Air8101" then - -- 姝ゅ鐢变簬鐩墠灞炰簬娴嬭瘯闃舵锛屽厛灏唌uid鍐欐锛屽悗缁細杩涜淇敼 - -- local muid = mcu.muid() or "" - local muid = "12345678901234567890123456789012" - udp_buff:write(string.char(auth_type) .. project_id .. mac .. muid .. timestamp .. nonce .. hmac_data:fromHex() .. string.char(lbs_data_type) .. lbs_jdata) - else - local imei = mobile and mobile.imei() or "" - local muid = mobile and mobile.muid() or "" - udp_buff:write(string.char(auth_type) .. project_id .. imei .. muid .. timestamp .. nonce .. hmac_data:fromHex() .. string.char(lbs_data_type) .. lbs_jdata) - end - - sysplus.taskInitEx(airlbs_task, lib_name, netCB, lib_name, udp_buff, param.timeout or airlbs_timeout, param.adapter) - - while 1 do - local result, tp, data = sys.waitUntil(lib_topic, param.timeout or airlbs_timeout) - log.info("瀹氫綅璇锋眰鐨勭粨鏋", result, "瓒呮椂鏃堕棿", tp, data) - if not result then - return false, "timeout" - elseif tp == location_data then - if not data then - log.error(lib_name, "鏃犳暟鎹, 璇锋鏌roject_id鍜宲roject_key") - return false - -- data.result 0-鎵句笉鍒 1-鎴愬姛 2-qps瓒呴檺 3-娆犺垂 4-鍏朵粬閿欒 - elseif data.result == 0 then - log.error(lib_name, "no location(鍩虹珯瀹氫綅鏈嶅姟鍣ㄦ煡璇㈠綋鍓嶅湴鍧澶辫触)") - return false - elseif data.result == 1 then - log.info("澶氬熀绔欒姹傛垚鍔,鏈嶅姟鍣ㄨ繑鍥炵殑鍘熷鏁版嵁", data) - return true, { - lng = data.lng, - lat = data.lat - } - elseif data.result == 2 then - log.error(lib_name, "qps limit(褰撳墠璇锋眰宸插埌杈鹃檺鍒,璇锋鏌ュ綋鍓嶈姹傛槸鍚﹁繃浜庨绻))") - return false - elseif data.result == 3 then - log.error(lib_name, "褰撳墠璁惧宸叉瑺璐,璇疯仈绯婚攢鍞厖鍊") - return false - elseif data.result == 4 then - log.error(lib_name, "other error") - return false - else - log.error("鍏朵粬閿欒,閿欒鐮", data.result, lib_name) - end - else - log.error(lib_name, "net error") - return false - end - end - -end - -return airlbs - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/bf30a2.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/bf30a2.lua deleted file mode 100644 index 6dba74c..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/bf30a2.lua +++ /dev/null @@ -1,26 +0,0 @@ -local config = { - mode = 0, - is_msb = 0, - rx_bit = 1, - seq_type = 0, - is_ddr = 0, - i2c_slave_addr = 0x6e, - width = 240, - height = 320, - init_cmds = {{0xf2, 0x01}, {0xcf, 0xb0}, {0x12, 0x20}, {0x15, 0x80}, {0x6b, 0x71}, {0x00, 0x40}, {0x04, 0x00}, - {0x06, 0x26}, {0x08, 0x07}, {0x1c, 0x12}, {0x20, 0x20}, {0x21, 0x20}, {0x34, 0x02}, {0x35, 0x02}, - {0x36, 0x21}, {0x37, 0x13}, {0xca, 0x23}, {0xcb, 0x22}, {0xcc, 0x89}, {0xcd, 0x4c}, {0xce, 0x6b}, - {0xa0, 0x8e}, {0x01, 0x1b}, {0x02, 0x1d}, {0x13, 0x08}, {0x87, 0x13}, {0x8b, 0x08}, {0x70, 0x17}, - {0x71, 0x43}, {0x72, 0x0a}, {0x73, 0x62}, {0x74, 0xa2}, {0x75, 0xbf}, {0x76, 0x00}, {0x77, 0xcc}, - {0x40, 0x32}, {0x41, 0x28}, {0x42, 0x26}, {0x43, 0x1d}, {0x44, 0x1a}, {0x45, 0x14}, {0x46, 0x11}, - {0x47, 0x0f}, {0x48, 0x0e}, {0x49, 0x0d}, {0x4B, 0x0c}, {0x4C, 0x0b}, {0x4E, 0x0a}, {0x4F, 0x09}, - {0x50, 0x09}, {0x24, 0x30}, {0x25, 0x36}, {0x80, 0x00}, {0x81, 0x20}, {0x82, 0x40}, {0x83, 0x30}, - {0x84, 0x50}, {0x85, 0x30}, {0x86, 0xd8}, {0x89, 0x45}, {0x8a, 0x33}, {0x8f, 0x81}, {0x91, 0xff}, - {0x92, 0x08}, {0x94, 0x82}, {0x95, 0xfd}, {0x9a, 0x20}, {0x9e, 0xbc}, {0xf0, 0x87}, {0x51, 0x06}, - {0x52, 0x25}, {0x53, 0x2b}, {0x54, 0x0f}, {0x57, 0x2a}, {0x58, 0x22}, {0x59, 0x2c}, {0x23, 0x33}, - {0xa1, 0x93}, {0xa2, 0x0f}, {0xa3, 0x2a}, {0xa4, 0x08}, {0xa5, 0x26}, {0xa7, 0x80}, {0xa8, 0x80}, - {0xa9, 0x1e}, {0xaa, 0x19}, {0xab, 0x18}, {0xae, 0x50}, {0xaf, 0x04}, {0xc8, 0x10}, {0xc9, 0x15}, - {0xd3, 0x0c}, {0xd4, 0x16}, {0xee, 0x06}, {0xef, 0x04}, {0x55, 0x34}, {0x56, 0x9c}, {0xb1, 0x98}, - {0xb2, 0x98}, {0xb3, 0xc4}, {0xb4, 0x0c}, {0xa0, 0x8f}, {0x13, 0x07}} -} -return config diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/dhcpsrv.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/dhcpsrv.lua deleted file mode 100644 index ae00733..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/dhcpsrv.lua +++ /dev/null @@ -1,395 +0,0 @@ ---[[ -@module dhcpsrv -@summary DHCP鏈嶅姟鍣ㄧ -@version 1.0.0 -@date 2025.04.15 -@author wendal -@usage --- 鍙傝僤hcpsrv.create鍑芥暟 -]] -local dhcpsrv = {} - -local udpsrv = require("udpsrv") - -local TAG = "dhcpsrv" - ----- --- 鍙傝冨湴鍧 --- https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol - -local function dhcp_decode(buff) - -- buff:seek(0) - local dst = {} - -- 寮濮嬭В鏋恉hcp - dst.op = buff[0] - dst.htype = buff[1] - dst.hlen = buff[2] - dst.hops = buff[3] - buff:seek(4) - dst.xid = buff:read(4) - - _, dst.secs = buff:unpack(">H") - _, dst.flags = buff:unpack(">H") - dst.ciaddr = buff:read(4) - dst.yiaddr = buff:read(4) - dst.siaddr = buff:read(4) - dst.giaddr = buff:read(4) - dst.chaddr = buff:read(16) - - -- 璺宠繃192瀛楄妭 - buff:seek(192, zbuff.SEEK_CUR) - - -- 瑙ｆ瀽magic - _, dst.magic = buff:unpack(">I") - - -- 瑙ｆ瀽option - local opt = {} - while buff:len() > buff:used() do - local tag = buff:read(1):byte() - if tag ~= 0 then - local len = buff:read(1):byte() - if tag == 0xFF or len == 0 then - break - end - local data = buff:read(len) - if tag == 53 then - -- 53: DHCP Message Type - dst.msgtype = data:byte() - end - table.insert(opt, {tag, data}) - -- log.info(TAG, "tag", tag, "data", data:toHex()) - end - end - if dst.msgtype == nil then - return -- 娌℃湁瑙ｆ瀽鍒癿sgtype锛岀洿鎺ヨ繑鍥 - end - dst.opts = opt - return dst -end - -local function dhcp_buff2ip(buff) - return string.format("%d.%d.%d.%d", buff:byte(1), buff:byte(2), buff:byte(3), buff:byte(4)) -end - -local function dhcp_print_pkg(pkg) - log.info(TAG, "XID", pkg.xid:toHex()) - log.info(TAG, "secs", pkg.secs) - log.info(TAG, "flags", pkg.flags) - log.info(TAG, "chaddr", pkg.chaddr:sub(1, pkg.hlen):toHex()) - log.info(TAG, "yiaddr", dhcp_buff2ip(pkg.yiaddr)) - log.info(TAG, "siaddr", dhcp_buff2ip(pkg.siaddr)) - log.info(TAG, "giaddr", dhcp_buff2ip(pkg.giaddr)) - log.info(TAG, "ciaddr", dhcp_buff2ip(pkg.ciaddr)) - log.info(TAG, "magic", string.format("%08X", pkg.magic)) - for _, opt in pairs(pkg.opts) do - if opt[1] == 53 then - log.info(TAG, "msgtype", opt[2]:byte()) - elseif opt[1] == 60 then - log.info(TAG, "auth", opt[2]) - elseif opt[1] == 57 then - log.info(TAG, "Maximum DHCP message size", opt[2]:byte() * 256 + opt[2]:byte(2)) - elseif opt[1] == 61 then - log.info(TAG, "Client-identifier", opt[2]:toHex()) - elseif opt[1] == 55 then - log.info(TAG, "Parameter request list", opt[2]:toHex()) - elseif opt[1] == 12 then - log.info(TAG, "Host name", opt[2]) - -- elseif opt[1] == 58 then - -- log.info(TAG, "Renewal (T1) time value", opt[2]:unpack(">I")) - end - end -end - -local function dhcp_encode(pkg, buff) - -- 鍚堟垚DHCP鍖 - buff:seek(0) - buff[0] = pkg.op - buff[1] = pkg.htype - buff[2] = pkg.hlen - buff[3] = pkg.hops - buff:seek(4) - -- 鍐欏叆XID - buff:write(pkg.xid) - -- 鍑犱釜閲嶈鐨勫弬鏁 - buff:pack(">H", pkg.secs) - buff:pack(">H", pkg.flags) - buff:write(pkg.ciaddr) - buff:write(pkg.yiaddr) - buff:write(pkg.siaddr) - buff:write(pkg.giaddr) - -- 鍐欏叆MAC鍦板潃 - buff:write(pkg.chaddr) - -- 璺宠繃192瀛楄妭 - buff:seek(192, zbuff.SEEK_CUR) - -- 鍐欏叆magic - buff:pack(">I", pkg.magic) - -- 鍐欏叆option - for _, opt in pairs(pkg.opts) do - buff:write(opt[1]) - buff:write(#opt[2]) - buff:write(opt[2]) - end - buff:write(0xFF, 0x00) -end - ----- - -local function dhcp_send_x(srv, pkg, client, msgtype) - local buff = zbuff.create(300) - pkg.op = 2 - pkg.ciaddr = "\0\0\0\0" - pkg.yiaddr = string.char(srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], client.ip) - pkg.siaddr = string.char(srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], srv.opts.gw[4]) - pkg.giaddr = "\0\0\0\0" - pkg.secs = 0 - - pkg.opts = {} -- 澶嶄綅option - table.insert(pkg.opts, {53, string.char(msgtype)}) - table.insert(pkg.opts, {1, string.char(srv.opts.mark[1], srv.opts.mark[2], srv.opts.mark[3], srv.opts.mark[4])}) - table.insert(pkg.opts, {3, string.char(srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], srv.opts.gw[4])}) - table.insert(pkg.opts, {51, "\x00\x00\x1E\x00"}) -- 7200绉, 澶ф - table.insert(pkg.opts, {54, string.char(srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], srv.opts.gw[4])}) - table.insert(pkg.opts, {6, string.char(223, 5, 5, 5)}) - table.insert(pkg.opts, {6, string.char(119, 29, 29, 29)}) - table.insert(pkg.opts, {6, string.char(srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], srv.opts.gw[4])}) - - dhcp_encode(pkg, buff) - - local dst = "255.255.255.255" - if 4 == msgtype then - dst = string.format("%d.%d.%d.%d", srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], client.ip) - end - -- log.info(TAG, "鍙戦", msgtype, dst, buff:query():toHex()) - srv.udp:send(buff, dst, 68) -end - -local function dhcp_send_offer(srv, pkg, client) - dhcp_send_x(srv, pkg, client, 2) -end - -local function dhcp_send_ack(srv, pkg, client) - dhcp_send_x(srv, pkg, client, 5) -end - -local function dhcp_send_nack(srv, pkg, client) - dhcp_send_x(srv, pkg, client, 6) -end - -local function dhcp_handle_discover(srv, pkg) - local mac = pkg.chaddr:sub(1, pkg.hlen) - -- 鐪嬬湅鏄笉鏄凡缁忓垎閰嶄簡ip - for _, client in pairs(srv.clients) do - if client.mac == mac then - log.info(TAG, "鍙戠幇宸茬粡鍒嗛厤鐨刴ac鍦板潃, send offer") - dhcp_send_offer(srv, pkg, client) - return - end - end - -- TODO 娓呯悊宸茬粡杩囨湡鐨処P鍒嗛厤璁板綍 - -- 鍒嗛厤涓涓柊鐨刬p - if #srv.clients >= (srv.opts.ip_end - srv.opts.ip_start) then - log.info(TAG, "娌℃湁鍙垎閰嶇殑ip浜") - return - end - local ip = nil - for i = srv.opts.ip_start, srv.opts.ip_end, 1 do - if srv.clients[i] == nil then - ip = i - break - end - end - if ip == nil then - log.info(TAG, "娌℃湁鍙垎閰嶇殑ip浜") - return - end - log.info(TAG, "鍒嗛厤ip", mac:toHex(), string.format("%d.%d.%d.%d", srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], ip)) - local client = { - mac = mac, - ip = ip, - tm = mcu.ticks() // mcu.hz(), - stat = 1 - } - srv.clients[ip] = client - log.info(TAG, "send offer") - dhcp_send_offer(srv, pkg, client) -end - -local function dhcp_handle_request(srv, pkg) - local mac = pkg.chaddr:sub(1, pkg.hlen) - -- 鐪嬬湅鏄笉鏄凡缁忓垎閰嶄簡ip - for _, client in pairs(srv.clients) do - if client.mac == mac then - log.info(TAG, "request,鍙戠幇宸茬粡鍒嗛厤鐨刴ac鍦板潃, send ack", mac:toHex()) - client.tm = mcu.ticks() // mcu.hz() - stat = 3 - dhcp_send_ack(srv, pkg, client) - if srv.opts.ack_cb then - local cip = string.format("%d.%d.%d.%d", srv.opts.gw[1], srv.opts.gw[2], srv.opts.gw[3], client.ip) - srv.opts.ack_cb(cip, mac:toHex()) - end - return - end - end - -- 娌℃湁鎵惧埌, 閭ｅ簲璇ヨ繑鍥濶ACK - log.info(TAG, "request,瀵瑰簲mac鍦板潃娌℃湁鍒嗛厤ip, send nack") - dhcp_send_nack(srv, pkg, {ip=pkg.yiaddr:byte(1)}) -end - -local function dhcp_pkg_handle(srv, pkg) - -- 杩涜鍩烘湰鐨勬鏌 - if pkg.magic ~= 0x63825363 then - log.warn(TAG, "dhcp鏁版嵁鍖呯殑magic涓嶅鍔,蹇界暐璇ユ暟鎹寘", pkg.magic) - return - end - if pkg.op ~= 1 then - log.info(TAG, "op涓嶅,蹇界暐璇ユ暟鎹寘", pkg.op) - return - end - if pkg.htype ~= 1 or pkg.hlen ~= 6 then - log.warn(TAG, "htype/hlen 涓嶈璇, 蹇界暐璇ユ暟鎹寘") - return - end - -- 鐪嬬湅鏄笉鏄兘澶勭悊鐨勭被鍨, 褰撳墠鍙鐞哾iscover/request - if pkg.msgtype == 1 or pkg.msgtype == 3 then - else - log.warn(TAG, "msgtype涓嶆槸discover/request, 蹇界暐璇ユ暟鎹寘", pkg.msgtype) - return - end - -- 妫鏌ヤ竴涓媘ac鍦板潃鏄惁鍚堟硶 - local mac = pkg.chaddr:sub(1, pkg.hlen) - if mac == "\0\0\0\0\0\0" or mac == "\xFF\xFF\xFF\xFF\xFF\xFF" then - log.warn(TAG, "mac鍦板潃涓虹┖, 蹇界暐璇ユ暟鎹寘") - return - end - - -- 澶勭悊discover鍖 - if pkg.msgtype == 1 then - log.info(TAG, "鏄痙iscover鍖", mac:toHex()) - dhcp_handle_discover(srv, pkg) - elseif pkg.msgtype == 3 then - log.info(TAG, "鏄痳equest鍖", mac:toHex()) - dhcp_handle_request(srv, pkg) - end - -- TODO 澶勭悊缁撴潫, 鎵撳嵃涓涓嬪鎴风殑鍒楄〃? -end - -local function dhcp_task(srv) - while 1 do - -- log.info("ulwip", "绛夊緟DHCP鏁版嵁") - local result, data = sys.waitUntil(srv.udp_topic, 1000) - if result then - -- log.info("ulwip", "鏀跺埌dhcp鏁版嵁鍖", data:toHex()) - -- 瑙ｆ瀽DHCP鏁版嵁鍖 - local pkg = dhcp_decode(zbuff.create(#data, data)) - if pkg then - -- dhcp_print_pkg(pkg) - dhcp_pkg_handle(srv, pkg) - end - end - end -end - ---[[ -鍒涘缓涓涓猟hcp鏈嶅姟鍣 -@api dhcpsrv.create(opts) -@table 閫夐」,鍙傝冨簱鐨勮鏄, 鍙奷emo鐨勭敤娉 -@return table 鏈嶅姟鍣ㄥ璞 -@usage --- 鍒涘缓涓涓猟hcp鏈嶅姟鍣, 鏈绠浠嬬殑鐗堟湰 -dhcpsrv.create({adapter=socket.LWIP_AP}) --- 璇︾粏鐨勭増鏈 --- 鍒涘缓涓涓猟hcp鏈嶅姟鍣 -local dhcpsrv_opts = { - adapter=socket.LWIP_AP, -- 鐩戝惉鍝釜缃戝崱, 蹇呴』濉啓 - mark = {255, 255, 255, 0}, -- 缃戠粶鎺╃爜, 榛樿 255.255.255.0 - gw = {192, 168, 4, 1}, -- 缃戝叧, 榛樿鑷姩鑾峰彇缃戝崱IP锛屽鏋滆幏鍙栧け璐ュ垯浣跨敤 192.168.4.1 - ip_start = 100, -- ip璧峰鍦板潃, 榛樿100 - ip_end = 200, -- ip缁撴潫鍦板潃, 榛樿200 - ack_cb = function(ip, mac) end, -- ack鍥炶皟, 鏈夊鎴风杩炴帴涓婃潵鏃惰Е鍙, ip鍜宮ac鍦板潃浼氫紶杩涙潵 -} -local mydhcpsrv = dhcpsrv.create(dhcpsrv_opts) - --- 浠ヤ笅鏄竴涓墦鍗板鎴风鍒楄〃鐨勪緥瀛, 闈炲繀閫, 浠呬緵鍙傝 --- clients鏄竴涓猼able, 鍖呭惈MAC鍜孖P鐨勫搴斿叧绯, 娉ㄦ剰, IP鍙褰曚簡鏈鍚庝竴娈垫暟瀛, 闈炲畬鏁碔P --- 娉ㄦ剰, clients鏄姩鎬佸彉鍖栫殑杩囩▼, mydhcpsrv瀵硅薄鐨勫叾浠栧睘鎬у垏鍕夸慨鏀, 浠呮彁渚沜lients鐨勫彧璇诲姛鑳 -sys.taskInit(function() - while true do - sys.wait(10000) - -- 杩欓噷鍙互鎵撳嵃涓涓嬪綋鍓嶇殑瀹㈡埛绔垪琛 - for ip, client in pairs(mydhcpsrv.clients) do - log.info(TAG, "client", ip, client.mac:toHex(), client.tm, client.stat) - end - end -end) - --- 鑷姩鍒嗛厤缃戞鍔熻兘璇存槑锛 --- 濡傛灉涓嶆寚瀹歡w鍙傛暟锛岀郴缁熶細鑷姩鑾峰彇缃戝崱IP浣滀负缃戝叧鍦板潃 --- 杩欐牱鍙互纭繚DHCP鍒嗛厤鐨処P涓庣綉鍗P鍦ㄥ悓涓缃戞 -]] -function dhcpsrv.create(opts) - local srv = {} - if not opts then - opts = {} - end - srv.udp_topic = "dhcpd_inc" - - -- 鑷姩鑾峰彇缃戝崱IP鍦板潃鐨勫嚱鏁 - local function get_adapter_ip() - if not opts.adapter then - return nil - end - - -- 鑾峰彇缃戝崱IP鍦板潃 - local ip = netdrv.ipv4(opts.adapter) - if not ip or ip == "0.0.0.0" then - return nil - end - - -- 绠鍗曡В鏋怚P鍦板潃锛192.168.4.1 -> {192, 168, 4, 1} - local a, b, c, d = ip:match("(%d+)%.(%d+)%.(%d+)%.(%d+)") - if a and b and c and d then - return {tonumber(a), tonumber(b), tonumber(c), tonumber(d)} - end - - return nil - end - - -- 琛ュ厖鍙傛暟 - if not opts.mark then - opts.mark = {255, 255, 255, 0} - end - - -- 濡傛灉娌℃湁鎸囧畾缃戝叧锛屽垯鑷姩鑾峰彇缃戝崱IP浣滀负缃戝叧 - if not opts.gw then - local adapter_ip = get_adapter_ip() - if adapter_ip then - opts.gw = adapter_ip - log.info(TAG, "鑷姩鑾峰彇缃戝崱IP浣滀负缃戝叧", string.format("%d.%d.%d.%d", adapter_ip[1], adapter_ip[2], adapter_ip[3], adapter_ip[4])) - else - opts.gw = {192, 168, 4, 1} - log.warn(TAG, "鏃犳硶鑾峰彇缃戝崱IP锛屼娇鐢ㄩ粯璁ょ綉鍏", string.format("%d.%d.%d.%d", opts.gw[1], opts.gw[2], opts.gw[3], opts.gw[4])) - end - end - - if not opts.dns then - opts.dns = opts.gw - end - - -- 鏍规嵁缃戝叧IP鑷姩璁剧疆IP鍒嗛厤鑼冨洿 - if not opts.ip_start then - opts.ip_start = 100 - end - if not opts.ip_end then - opts.ip_end = 200 - end - - srv.clients = {} - srv.opts = opts - - srv.udp = udpsrv.create(67, srv.udp_topic, opts.adapter) - srv.task = sys.taskInit(dhcp_task, srv) - return srv -end - - -return dhcpsrv diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/dnsproxy.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/dnsproxy.lua deleted file mode 100644 index 744c0e2..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/dnsproxy.lua +++ /dev/null @@ -1,125 +0,0 @@ ---[[ -@module dnsproxy -@summary DNS浠ｇ悊杞彂 -@version 1.0 -@date 2024.4.20 -@author wendal -@demo socket -@tag LUAT_USE_NETWORK -@usage --- 鍏蜂綋鐢ㄦ硶璇锋煡闃卍emo -]] - -local sys = require "sys" - -local dnsproxy = { - server = "119.29.29.29", - srvs = {}, - map = {}, - txid = 0x123, - rxbuff = zbuff.create(1500) -} - -function dnsproxy.on_request(sc, event, adapter) - if event == socket.EVENT then - local rxbuff = dnsproxy.rxbuff - while 1 do - rxbuff:seek(0) - local succ, data_len, remote_ip, remote_port = socket.rx(sc, rxbuff) - if succ and data_len and data_len > 0 then - -- log.info("dnsproxy", "鏀跺埌DNS鏌ヨ鏁版嵁", rxbuff:query():toHex()) - if remote_ip and #remote_ip == 5 then - local ip1,ip2,ip3,ip4 = remote_ip:byte(2),remote_ip:byte(3),remote_ip:byte(4),remote_ip:byte(5) - remote_ip = string.format("%d.%d.%d.%d", ip1, ip2, ip3, ip4) - local txid_request = rxbuff[0] + rxbuff[1] * 256 - local txid_map = dnsproxy.txid - dnsproxy.txid = dnsproxy.txid + 1 - if dnsproxy.txid > 65000 then - dnsproxy.txid = 0x123 - end - table.insert(dnsproxy.map, {txid_request, txid_map, remote_ip, remote_port, adapter}) - rxbuff[0] = txid_map % 256 - rxbuff[1] = txid_map // 256 - socket.tx(dnsproxy.main_sc, rxbuff, dnsproxy.server or "223.5.5.5", 53) - end - else - break - end - end - end -end - -function dnsproxy.on_response(sc, event) - if event == socket.EVENT then - local rxbuff = dnsproxy.rxbuff - while 1 do - rxbuff:seek(0) - local succ, data_len = socket.rx(sc, rxbuff) - if succ and data_len and data_len > 0 then - if true then - -- local ip1,ip2,ip3,ip4 = remote_ip:byte(2),remote_ip:byte(3),remote_ip:byte(4),remote_ip:byte(5) - -- remote_ip = string.format("%d.%d.%d.%d", ip1, ip2, ip3, ip4) - local txid_resp = rxbuff[0] + rxbuff[1] * 256 - local index = -1 - for i, mapit in pairs(dnsproxy.map) do - if mapit[2] == txid_resp then - local txid_request = mapit[1] - local remote_ip = mapit[3] - local remote_port = mapit[4] - rxbuff[0] = txid_request % 256 - rxbuff[1] = txid_request // 256 - local adapter = mapit[5] - -- log.info("dnsproxy", "杞彂DNS鍝嶅簲鏁版嵁", adapter, dnsproxy.srvs[adapter]) - socket.tx(dnsproxy.srvs[adapter], rxbuff, remote_ip, remote_port) - index = i - break - end - end - if index > 0 then - table.remove(dnsproxy.map, index) - end - end - else - break - end - end - end -end - ---[[ -鍒涘缓UDP鏈嶅姟鍣 -@api dnsproxy.setup(adapter, main_adapter) -@int 鐩戝惉鐨勭綉缁滈傞厤鍣╥d -@int 缃戠粶閫傞厤缂栧彿, 榛樿涓簄il,鍙 -@return table UDP鏈嶅姟鐨勫疄浣, 鑻ュ垱寤哄け璐ヤ細杩斿洖nil -]] -function dnsproxy.setup(adapter, main_adapter) - log.info("dnsproxy", adapter, main_adapter) - if dnsproxy.main_sc == nil then - dnsproxy.main_sc = socket.create(main_adapter, dnsproxy.on_response) - socket.config(dnsproxy.main_sc, 1053, true) - end - if dnsproxy.srvs[adapter] == nil then - dnsproxy.srvs[adapter] = socket.create(adapter, function(sc, event) - dnsproxy.on_request(sc, event, adapter) - end) - socket.config(dnsproxy.srvs[adapter], 53, true) - end - dnsproxy.on_ip_ready() - return true -end - -function dnsproxy.on_ip_ready() - log.info("dnsproxy", "寮濮嬬洃鍚") - if not dnsproxy.main_sc then return end - socket.close(dnsproxy.main_sc) - for k, v in pairs(dnsproxy.srvs) do - socket.close(v) - socket.connect(v, "255.255.255.255", 0) - end - socket.connect(dnsproxy.main_sc, dnsproxy.server or "223.5.5.5", 53) -end - -sys.subscribe("IP_READY", dnsproxy.on_ip_ready) - -return dnsproxy diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exaudio.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exaudio.lua deleted file mode 100644 index 9f7cebc..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exaudio.lua +++ /dev/null @@ -1,544 +0,0 @@ ---[[ -@module exaudio -@summary exaudio鎵╁睍搴 -@version 1.1 -@date 2025.09.01 -@author 姊佸仴 -@usage -]] -local exaudio = {} - --- 甯搁噺瀹氫箟 -local I2S_ID = 0 -local I2S_MODE = 0 -- 0:涓绘満 1:浠庢満 -local I2S_SAMPLE_RATE = 16000 -local I2S_CHANNEL_FORMAT = i2s.MONO_R -local I2S_COMM_FORMAT = i2s.MODE_LSB -- 鍙塎ODE_I2S, MODE_LSB, MODE_MSB -local I2S_CHANNEL_BITS = 16 -local MULTIMEDIA_ID = 0 -local EX_MSG_PLAY_DONE = "playDone" -local ES8311_ADDR = 0x18 -- 7浣嶅湴鍧 -local CHIP_ID_REG = 0x00 -- 鑺墖ID瀵勫瓨鍣ㄥ湴鍧 - --- 妯″潡甯搁噺 -exaudio.PLAY_DONE = 1 -- 闊抽鎾斁瀹屾瘯鐨勪簨浠朵箣涓 -exaudio.RECORD_DONE = 1 -- 闊抽褰曢煶瀹屾瘯鐨勪簨浠朵箣涓 -exaudio.AMR_NB = 0 -exaudio.AMR_WB = 1 -exaudio.PCM_8000 = 2 -exaudio.PCM_16000 = 3 -exaudio.PCM_24000 = 4 -exaudio.PCM_32000 = 5 -exaudio.PCM_48000 = 6 - - --- 榛樿閰嶇疆鍙傛暟 -local audio_setup_param = { - model = "es8311", -- dac绫诲瀷: "es8311","es8211" - i2c_id = 0, -- i2c_id: 0,1 - pa_ctrl = 0, -- 闊抽鏀惧ぇ鍣ㄧ數婧愭帶鍒剁鑴 - dac_ctrl = 0, -- 闊抽缂栬В鐮佽姱鐗囩數婧愭帶鍒剁鑴 - dac_delay = 3, -- DAC鍚姩鍓嶅啑浣欐椂闂(100ms) - pa_delay = 100, -- DAC鍚姩鍚庡欢杩熸墦寮PA鐨勬椂闂(ms) - dac_time_delay = 600, -- 鎾斁瀹屾瘯鍚嶱A涓嶥AC鍏抽棴闂撮殧(ms) - bits_per_sample = 16, -- 閲囨牱浣嶆暟 - pa_on_level = 1 -- PA鎵撳紑鐢靛钩 1:楂 0:浣 -} - -local audio_play_param = { - type = 0, -- 0:鏂囦欢 1:TTS 2:娴佸紡 - content = nil, -- 鎾斁鍐呭 - cbfnc = nil, -- 鎾斁瀹屾瘯鍥炶皟 - priority = 0, -- 浼樺厛绾(鏁板艰秺澶ц秺楂) - sampling_rate = 16000, -- 閲囨牱鐜(浠呮祦寮) - sampling_depth = 16, -- 閲囨牱浣嶆繁(浠呮祦寮) - signed_or_unsigned = true -- PCM鏄惁鏈夌鍙(浠呮祦寮) -} - -local audio_record_param = { - format = 0, -- 褰曞埗鏍煎紡锛屾敮鎸乪xaudio.AMR_NB锛宔xaudio.AMR_WB,exaudio.PCM_8000,exaudio.PCM_16000,exaudio.PCM_24000,exaudio.PCM_32000,exaudio.PCM_48000 - time = 5, -- 褰曞埗鏃堕棿(绉) - path = nil, -- 鏂囦欢璺緞鎴栨祦寮忓洖璋 - cbfnc = nil -- 褰曢煶瀹屾瘯鍥炶皟 -} - --- 鍐呴儴鍙橀噺 -local pcm_buff0 = nil -local pcm_buff1 = nil -local voice_vol = 55 -local mic_vol = 80 - --- 瀹氫箟鍏ㄥ眬闃熷垪琛 -local audio_play_queue = { - data = {}, -- 瀛樺偍瀛楃涓茬殑鏁扮粍 - sequenceIndex = 1 -- 鐢ㄤ簬璺熻釜鎻掑叆椤哄簭鐨勭储寮 -} - --- 鍚戦槦鍒椾腑娣诲姞瀛楃涓诧紙鎸夎皟鐢ㄩ『搴忔彃鍏ワ級 -local function audio_play_queue_push(str) - if type(str) == "string" then - -- 瀛樺偍鏍煎紡: {index = 椤哄簭绱㈠紩, value = 瀛楃涓插紏 - table.insert(audio_play_queue.data, { - index = audio_play_queue.sequenceIndex, - value = str - }) - audio_play_queue.sequenceIndex = audio_play_queue.sequenceIndex + 1 - return true - end - return false -end - --- 浠庨槦鍒椾腑鍙栧嚭鏈鏃╂彃鍏ョ殑瀛楃涓诧紙鎸夐『搴忓彇鍑猴級 -local function audio_play_queue_pop() - if #audio_play_queue.data > 0 then - -- 鍙栧嚭骞剁Щ闄ょ涓涓厓绱 - local item = table.remove(audio_play_queue.data, 1) - return item.value -- 杩斿洖鍊 - end - return nil -end --- 娓呯┖闃熷垪涓墍鏈夋暟鎹 -function audio_queue_clear() - -- 娓呯┖鏁扮粍 - audio_play_queue.data = {} - -- 閲嶇疆椤哄簭绱㈠紩 - audio_play_queue.sequenceIndex = 1 - return true -end - --- 宸ュ叿鍑芥暟锛氬弬鏁版鏌 -local function check_param(param, expected_type, name) - if type(param) ~= expected_type then - log.error(string.format("鍙傛暟閿欒: %s 搴斾负 %s 绫诲瀷", name, expected_type)) - return false - end - return true -end - --- 闊抽鍥炶皟澶勭悊 -local function audio_callback(id, event, point) - -- log.info("audio_callback", "event:", event, - -- "MORE_DATA:", audio.MORE_DATA, - -- "DONE:", audio.DONE, - -- "RECORD_DATA:", audio.RECORD_DATA, - -- "RECORD_DONE:", audio.RECORD_DONE) - - if event == audio.MORE_DATA then - audio.write(MULTIMEDIA_ID,audio_play_queue_pop()) - elseif event == audio.DONE then - if type(audio_play_param.cbfnc) == "function" then - audio_play_param.cbfnc(exaudio.PLAY_DONE) - end - audio_queue_clear() -- 娓呯┖娴佸紡鎾斁鏁版嵁闃熷垪 - sys.publish(EX_MSG_PLAY_DONE) - - elseif event == audio.RECORD_DATA then - if type(audio_record_param.path) == "function" then - local buff, len = point == 0 and pcm_buff0 or pcm_buff1, - point == 0 and pcm_buff0:used() or pcm_buff1:used() - audio_record_param.path(buff, len) - end - - elseif event == audio.RECORD_DONE then - if type(audio_record_param.cbfnc) == "function" then - audio_record_param.cbfnc(exaudio.RECORD_DONE) - end - end -end - --- 璇诲彇ES8311鑺墖ID -local function read_es8311_id() - - - -- 鍙戦佽鍙栬姹 - local send_ok = i2c.send(audio_setup_param.i2c_id, ES8311_ADDR, CHIP_ID_REG) - if not send_ok then - log.error("鍙戦佽姱鐗嘔D璇诲彇璇锋眰澶辫触") - return false - end - - -- 璇诲彇鏁版嵁 - local data = i2c.recv(audio_setup_param.i2c_id, ES8311_ADDR, 1) - if data and #data == 1 then - return true - end - - log.error("璇诲彇ES8311鑺墖ID澶辫触") - return false -end - --- 闊抽纭欢鍒濆鍖 -local function audio_setup() - -- I2C閰嶇疆 - if not i2c.setup(audio_setup_param.i2c_id, i2c.FAST) then - log.error("I2C鍒濆鍖栧け璐") - return false - end - -- 鍒濆鍖朓2S - local result, data = i2s.setup( - I2S_ID, - I2S_MODE, - I2S_SAMPLE_RATE, - audio_setup_param.bits_per_sample, - I2S_CHANNEL_FORMAT, - I2S_COMM_FORMAT, - I2S_CHANNEL_BITS - ) - - if not result then - log.error("I2S璁剧疆澶辫触") - return false - end - -- 閰嶇疆闊抽閫氶亾 - audio.config( - MULTIMEDIA_ID, - audio_setup_param.pa_ctrl, - audio_setup_param.pa_on_level, - audio_setup_param.dac_delay, - audio_setup_param.pa_delay, - audio_setup_param.dac_ctrl, - 1, -- power_on_level - audio_setup_param.dac_time_delay - ) - -- 璁剧疆鎬荤嚎 - audio.setBus( - MULTIMEDIA_ID, - audio.BUS_I2S, - { - chip = audio_setup_param.model, - i2cid = audio_setup_param.i2c_id, - i2sid = I2S_ID, - voltage = audio.VOLTAGE_1800 - } - ) - - - -- 璁剧疆闊抽噺 - audio.vol(MULTIMEDIA_ID, voice_vol) - audio.micVol(MULTIMEDIA_ID, mic_vol) - audio.pm(MULTIMEDIA_ID, audio.RESUME) - - -- 妫鏌ヨ姱鐗囪繛鎺 - if audio_setup_param.model == "es8311" and not read_es8311_id() then - log.error("ES8311閫氳澶辫触锛岃妫鏌ョ‖浠") - return false - end - - -- 娉ㄥ唽鍥炶皟 - audio.on(MULTIMEDIA_ID, audio_callback) - return true -end - --- 妯″潡鎺ュ彛锛氬垵濮嬪寲 -function exaudio.setup(audioConfigs) - -- 妫鏌ュ繀瑕佸弬鏁 - if not audio then - log.error("涓嶆敮鎸乤udio 搴,璇烽夋嫨鏀寔audio 鐨刢ore") - return false - end - if not audioConfigs or type(audioConfigs) ~= "table" then - log.error("閰嶇疆鍙傛暟蹇呴』涓簍able绫诲瀷") - return false - end - -- 妫鏌odec鍨嬪彿 - if not audioConfigs.model or - (audioConfigs.model ~= "es8311" and audioConfigs.model ~= "es8211") then - log.error("璇锋寚瀹氭纭殑codec鍨嬪彿(es8311鎴杄s8211)") - return false - end - audio_setup_param.model = audioConfigs.model - -- 閽堝ES8311鐨勭壒娈婃鏌 - if audioConfigs.model == "es8311" then - if not check_param(audioConfigs.i2c_id, "number", "i2c_id") then - return false - end - audio_setup_param.i2c_id = audioConfigs.i2c_id - end - - -- 妫鏌ュ姛鐜囨斁澶у櫒鎺у埗绠¤剼 - if audioConfigs.pa_ctrl == nil then - log.warn("pa_ctrl(鍔熺巼鏀惧ぇ鍣ㄦ帶鍒剁鑴)鏄帶鍒秔op 闊崇殑閲嶈绠¤剼,寤鸿纭欢璁捐鍔犱笂") - end - audio_setup_param.pa_ctrl = audioConfigs.pa_ctrl - - -- 妫鏌ュ姛鐜囨斁澶у櫒鎺у埗绠¤剼 - if audioConfigs.dac_ctrl == nil then - log.warn("dac_ctrl(闊抽缂栬В鐮佹帶鍒剁鑴)鏄帶鍒秔op 闊崇殑閲嶈绠¤剼,寤鸿纭欢璁捐鍔犱笂") - end - audio_setup_param.dac_ctrl = audioConfigs.dac_ctrl - - - -- 澶勭悊鍙夊弬鏁 - local optional_params = { - {name = "dac_delay", type = "number"}, - {name = "pa_delay", type = "number"}, - {name = "dac_time_delay", type = "number"}, - {name = "bits_per_sample", type = "number"}, - {name = "pa_on_level", type = "number"} - } - - for _, param in ipairs(optional_params) do - if audioConfigs[param.name] ~= nil then - if check_param(audioConfigs[param.name], param.type, param.name) then - audio_setup_param[param.name] = audioConfigs[param.name] - else - return false - end - end - end - - -- 纭繚閲囨牱浣嶆暟鏈夐粯璁ゅ - audio_setup_param.bits_per_sample = audio_setup_param.bits_per_sample or 16 - return audio_setup() -end - --- 妯″潡鎺ュ彛锛氬紑濮嬫挱鏀 -function exaudio.play_start(playConfigs) - if not playConfigs or type(playConfigs) ~= "table" then - log.error("鎾斁閰嶇疆蹇呴』涓簍able绫诲瀷") - return false - end - - -- 妫鏌ユ挱鏀剧被鍨 - if not check_param(playConfigs.type, "number", "type") then - log.error("type蹇呴』涓烘暟鍊(0:鏂囦欢,1:TTS,2:娴佸紡)") - return false - end - audio_play_param.type = playConfigs.type - - -- 澶勭悊浼樺厛绾 - if playConfigs.priority ~= nil then - if check_param(playConfigs.priority, "number", "priority") then - if playConfigs.priority > audio_play_param.priority then - log.error("鏄惁瀹屾垚鎾斁",audio.isEnd(MULTIMEDIA_ID)) - if not audio.isEnd(MULTIMEDIA_ID) then - if audio.play(MULTIMEDIA_ID) ~= true then - return false - end - sys.waitUntil(EX_MSG_PLAY_DONE) - end - audio_play_param.priority = playConfigs.priority - end - else - return false - end - end - - -- 澶勭悊涓嶅悓鎾斁绫诲瀷 - local play_type = audio_play_param.type - if play_type == 0 then -- 鏂囦欢鎾斁 - if not playConfigs.content then - log.error("鏂囦欢鎾斁闇瑕佹寚瀹歝ontent(鏂囦欢璺緞鎴栬矾寰勮〃)") - return false - end - - local content_type = type(playConfigs.content) - if content_type == "table" then - for _, path in ipairs(playConfigs.content) do - if type(path) ~= "string" then - log.error("鎾斁鍒楄〃鍏冪礌蹇呴』涓哄瓧绗︿覆璺緞") - return false - end - end - elseif content_type ~= "string" then - log.error("鏂囦欢鎾斁content蹇呴』涓哄瓧绗︿覆鎴栬矾寰勮〃") - return false - end - - audio_play_param.content = playConfigs.content - if audio.play(MULTIMEDIA_ID, audio_play_param.content) ~= true then - return false - end - - elseif play_type == 1 then -- TTS鎾斁 - if not audio.tts then - log.error("鏈浐浠朵笉鏀寔TTS,璇锋洿鎹㈡敮鎸乀TS 鐨勫浐浠") - return false - end - if not check_param(playConfigs.content, "string", "content") then - log.error("TTS鎾斁content蹇呴』涓哄瓧绗︿覆") - return false - end - audio_play_param.content = playConfigs.content - if audio.tts(MULTIMEDIA_ID, audio_play_param.content) ~= true then - return false - end - - elseif play_type == 2 then -- 娴佸紡鎾斁 - if not check_param(playConfigs.sampling_rate, "number", "sampling_rate") then - return false - end - if not check_param(playConfigs.sampling_depth, "number", "sampling_depth") then - return false - end - - audio_play_param.content = playConfigs.content - audio_play_param.sampling_rate = playConfigs.sampling_rate - audio_play_param.sampling_depth = playConfigs.sampling_depth - - if playConfigs.signed_or_unsigned ~= nil then - audio_play_param.signed_or_unsigned = playConfigs.signed_or_unsigned - end - - audio.start( - MULTIMEDIA_ID, - audio.PCM, - 1, - playConfigs.sampling_rate, - playConfigs.sampling_depth, - audio_play_param.signed_or_unsigned - ) - -- 鍙戦佸垵濮嬫暟鎹 - if audio.write(MULTIMEDIA_ID, string.rep("\0", 512)) ~= true then - return false - end - end - - -- 澶勭悊鍥炶皟鍑芥暟 - if playConfigs.cbfnc ~= nil then - if check_param(playConfigs.cbfnc, "function", "cbfnc") then - audio_play_param.cbfnc = playConfigs.cbfnc - else - return false - end - else - audio_play_param.cbfnc = nil - end - return true -end - --- 妯″潡鎺ュ彛锛氭祦寮忔挱鏀炬暟鎹啓鍏 -function exaudio.play_stream_write(data) - audio_play_queue_push(data) - return true -end - --- 妯″潡鎺ュ彛锛氬仠姝㈡挱鏀 -function exaudio.play_stop() - return audio.play(MULTIMEDIA_ID) -end - --- 妯″潡鎺ュ彛锛氭鏌ユ挱鏀炬槸鍚︾粨鏉 -function exaudio.is_end() - return audio.isEnd(MULTIMEDIA_ID) -end - --- 妯″潡鎺ュ彛锛氳幏鍙栭敊璇俊鎭 -function exaudio.get_error() - return audio.getError(MULTIMEDIA_ID) -end - --- 妯″潡鎺ュ彛锛氬紑濮嬪綍闊 -function exaudio.record_start(recodConfigs) - if not recodConfigs or type(recodConfigs) ~= "table" then - log.error("褰曢煶閰嶇疆蹇呴』涓簍able绫诲瀷") - return false - end - -- 妫鏌ュ綍闊虫牸寮 - if recodConfigs.format == nil or type(recodConfigs.format) ~= "number" or recodConfigs.format > 6 then - log.error("璇锋寚瀹氭纭殑褰曢煶鏍煎紡") - return false - end - audio_record_param.format = recodConfigs.format - - -- 澶勭悊褰曢煶鏃堕棿 - if recodConfigs.time ~= nil then - if check_param(recodConfigs.time, "number", "time") then - audio_record_param.time = recodConfigs.time - else - return false - end - else - audio_record_param.time = 0 - end - - -- 澶勭悊瀛樺偍璺緞/鍥炶皟 - if not recodConfigs.path then - log.error("蹇呴』鎸囧畾褰曢煶璺緞鎴栨祦寮忓洖璋冨嚱鏁") - return false - end - audio_record_param.path = recodConfigs.path - - -- 杞崲褰曢煶鏍煎紡 - local recod_format, amr_quailty - if audio_record_param.format == exaudio.AMR_NB then - recod_format = audio.AMR_NB - amr_quailty = 7 - elseif audio_record_param.format == exaudio.AMR_WB then - recod_format = audio.AMR_WB - amr_quailty = 8 - elseif audio_record_param.format == exaudio.PCM_8000 then - recod_format = 8000 - elseif audio_record_param.format == exaudio.PCM_16000 then - recod_format = 16000 - elseif audio_record_param.format == exaudio.PCM_24000 then - recod_format = 24000 - elseif audio_record_param.format == exaudio.PCM_32000 then - recod_format = 32000 - elseif audio_record_param.format == exaudio.PCM_48000 then - recod_format = 48000 - end - - -- 澶勭悊鍥炶皟鍑芥暟 - if recodConfigs.cbfnc ~= nil then - if check_param(recodConfigs.cbfnc, "function", "cbfnc") then - audio_record_param.cbfnc = recodConfigs.cbfnc - else - return false - end - else - audio_record_param.cbfnc = nil - end - -- 寮濮嬪綍闊 - local path_type = type(audio_record_param.path) - if path_type == "string" then - return audio.record( - MULTIMEDIA_ID, - recod_format, - audio_record_param.time, - amr_quailty, - audio_record_param.path - ) - elseif path_type == "function" then - -- 鍒濆鍖栫紦鍐插尯 - if not pcm_buff0 or not pcm_buff1 then - pcm_buff0 = zbuff.create(16000) - pcm_buff1 = zbuff.create(16000) - end - return audio.record( - MULTIMEDIA_ID, - recod_format, - audio_record_param.time, - amr_quailty, - nil, - 3, - pcm_buff0, - pcm_buff1 - ) - end - log.error("褰曢煶璺緞蹇呴』涓哄瓧绗︿覆鎴栧嚱鏁") - return false -end - --- 妯″潡鎺ュ彛锛氬仠姝㈠綍闊 -function exaudio.record_stop() - return audio.recordStop(MULTIMEDIA_ID) -end - --- 妯″潡鎺ュ彛锛氳缃煶閲 -function exaudio.vol(play_volume) - if check_param(play_volume, "number", "闊抽噺鍊") then - return audio.vol(MULTIMEDIA_ID, play_volume) - end - return false -end - --- 妯″潡鎺ュ彛锛氳缃害鍏嬮闊抽噺 -function exaudio.mic_vol(record_volume) - if check_param(record_volume, "number", "楹﹀厠椋庨煶閲忓") then - return audio.micVol(MULTIMEDIA_ID, record_volume) - end - return false -end - -return exaudio \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/excamera.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/excamera.lua deleted file mode 100644 index 76b6ad5..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/excamera.lua +++ /dev/null @@ -1,425 +0,0 @@ ---[[ -@module excamera -@summary excamera鎵╁睍搴 -@version 1.0 -@date 2025.10.21 -@author 闄堝彇寰 -@usage - 鐢ㄦ硶瀹炰緥 - 娉ㄦ剰锛歟xcamera.lua閫傜敤鐨勪骇鍝佽寖鍥 - Air780绯诲垪銆丄ir700绯诲垪銆丄ir8000绯诲垪锛氭敮鎸丼PI鎽勫儚澶 - Air8101绯诲垪锛氭敮鎸乁SB鎽勫儚銆丏VP鎽勫儚澶 - 鍚堝畽鎵鏈夊瀷鍙风殑soc浜у搧閮戒粎鏀寔涓璺憚鍍忓ご锛屾墍浠xcamera搴撲笉闇瑕佺鐞哻amera id锛屽彧闇瑕佽皟鐢ㄦ憚鍍忓ご鐨勫紑鍏冲拰鎷嶇収鍔熻兘鍗冲彲 - - 浣跨敤excamera搴撴椂浼氭湁涓ょ搴旂敤鍦烘櫙 - 1銆佹媿鐓фā寮忥細浣跨敤鎷嶇収妯″紡鏃 - 鎸夌収瀹為檯浣跨敤鐨勬憚鍍忓ご绫诲瀷濉啓閰嶇疆琛 - 鍒涘缓鎽勫儚澶磂xcamera.open() - 鎷嶇収excamera.photo() - 鍏抽棴鎽勫儚澶 excamera.close()鐨勯昏緫浣跨敤 - 2銆佹壂鎻忔ā寮忥細褰撳墠USB鍜孌VP鎽勫儚澶翠笉鏀寔鎵弿妯″紡锛屼粎SPI鎽勫儚澶村彲浣跨敤 - 鎸夌収瀹為檯浣跨敤鐨勬憚鍍忓ご绫诲瀷濉啓閰嶇疆琛 - 鍒涘缓鎽勫儚澶磂xcamera.open() - 鎵弿excamera.scan() - 鍏抽棴鎽勫儚澶 excamera.close()鐨勯昏緫浣跨敤 - -local excamera = require "excamera" - -local spi_camera_param = { - id = "gc032a", -- SPI鎽勫儚澶翠粎鏀寔"gc032a"銆"gc0310"銆"bf30a2"锛岃甯﹀紩鍙峰～鍐 - i2c_id = 1, -- 妯″潡涓婁娇鐢ㄧ殑I2C缂栧彿 - work_mode = 0, -- 宸ヤ綔妯″紡锛0涓烘媿鐓фā寮忥紝1涓烘壂鎻忔ā寮 - save_path = "ZBUFF", -- 鎷嶇収缁撴灉瀛樺偍璺緞锛屽彲鐢"ZBUFF"浜ょ敱excamera搴撳唴閮ㄧ鐞 - camera_pwr = 2 , -- 鎽勫儚澶翠娇鑳界鑴氾紝濉啓GPIO鍙峰嵆鍙紝鏃犲垯濉玭il - camera_pwdn = 5 , -- 鎽勫儚澶磒wdn寮鍏宠剼锛屽～鍐橤PIO鍙峰嵆鍙紝鏃犲垯濉玭il - camera_light = 25 -- 鎽勫儚澶磋ˉ鍏夌伅鎺у埗绠¤剼锛屽～鍐橤PIO鍙峰嵆鍙紝鏃犲垯濉玭il -} - -local usb_camera_param = { - id = camera.USB , -- 鎽勫儚澶寸被鍨嬶紝榛樿camera.USB - sensor_width = 1280, -- 鎽勫儚澶村儚绱犲搴︼紝鏍规嵁鎽勫儚澶村疄闄呭弬鏁板～鍐欐暟鍊 - sensor_height = 720, -- 鎽勫儚澶村儚绱犻珮搴︼紝鏍规嵁鎽勫儚澶村疄闄呭弬鏁板～鍐欐暟鍊 - usb_port = 1 , - save_path = "/ram/test.jpg" -} - -local dvp_camera_param = { - id = camera.DVP, -- 鎽勫儚澶寸被鍨嬶紝榛樿camera.DVP - sensor_width = 1280, -- 鎽勫儚澶村儚绱犲搴︼紝鏍规嵁鎽勫儚澶村疄闄呭弬鏁板～鍐欐暟鍊 - sensor_height = 720, -- 鎽勫儚澶村儚绱犻珮搴︼紝鏍规嵁鎽勫儚澶村疄闄呭弬鏁板～鍐欐暟鍊 - save_path = "/ram/test.jpg" -} - -sys.taskInit(function() - local camera_id - while true do - sys.waitUntil("ONCE_CAPTURE") - camera_id = excamera.open(spi_camera_param) - log.info("鍒濆鍖栫姸鎬", camera_id) - local result ,data = excamera.photo() - log.info("鎷嶅畬浜",data) - excamera.close() - end -end) -sys.run() -]] -- -local excamera = {} -local h, w -local camera_id, path, camera_buff, camera_i2c, data, result -local cam_pwr, cam_pwdn, cam_light - --- 璁惧鎵撳紑鍑芥暟锛氬垵濮嬪寲鎸囧畾绫诲瀷鐨勬憚鍍忓ご璁惧 --- 鍙傛暟锛歝amera_param - 鎽勫儚澶撮厤缃弬鏁拌〃锛屽寘鍚玦d銆乮2c_id銆亀ork_mode绛夐厤缃 --- 杩斿洖鍊硷細鎴愬姛杩斿洖camera_id锛屽け璐ヨ繑鍥瀎alse --- 鏀寔SPI鎽勫儚銆乁SB鎽勫儚澶淬丏VP鎽勫儚澶翠娇鐢 --- 鑷姩澶勭悊寮傛鍥炶皟鍑芥暟锛屽皢鎽勫儚澶翠笟鍔℃祦绋嬫敼涓哄悓姝ユ祦绋 --- 鏀寔ZBUFF澶勭悊鐓х墖锛屾敮鎸佹枃浠惰矾寰勫鐞嗙収鐗 -function excamera.open(camera_param) - -- 鍒ゆ柇鎽勫儚澶寸被鍨嬫槸鍚︿负瀛楃涓茬被鍨嬶紙鐢ㄤ簬鏀寔涓嶅悓鍨嬪彿鐨勬憚鍍忓ご妯″潡锛 - if type(camera_param.id) == "string" then - -- 鍒ゆ柇鏄惁闇瑕佺鐞嗕緵鐢典娇鑳 - if type(camera_param.camera_pwr) == "number" then - cam_pwr = gpio.setup(camera_param.camera_pwr, 1) - end - -- 鍒ゆ柇鏄惁闇瑕佺鐞嗘憚鍍忓ごpwdn寮鍏 - if type(camera_param.camera_pwdn) == "number" then - cam_pwdn = gpio.setup(camera_param.camera_pwdn, 0) - -- 涓8000鏆傛椂鍏煎锛屽悗缁増鏈細绉婚櫎 - sys.wait(10) - end - -- 閰嶇疆I2C鎺ュ彛锛岀敤浜庝笌鎽勫儚澶撮氫俊 - if i2c.setup(camera_param.i2c_id, i2c.FAST) then - -- 淇濆瓨I2C鎺ュ彛ID鍒癱amera_i2c锛岀敤浜庡眬鍐呰皟鐢 - camera_i2c = camera_param.i2c_id - -- 淇濇姢鎵ц閰嶇疆鏂囦欢鍔犺浇锛屽苟璧嬪肩粰camera_module锛屼究浜庡悗缁皟鐢ㄩ厤缃〃淇℃伅 - local result, camera_module = pcall(require, camera_param.id) - if not result then - log.error("excamera.open", camera_param.id .. ".lua鏂囦欢鍔犺浇澶辫触") - return false - end - -- 閫氳繃鎽勫儚澶撮厤缃〃淇℃伅鍒濆鍖栨憚鍍忓ご - camera_id = camera.init(1, 24000000, camera_module.mode, camera_module.is_msb, camera_module.rx_bit, - camera_module.seq_type, camera_module.is_ddr, camera_param.work_mode, camera_param.work_mode, - camera_module.width, camera_module.height) - if not camera_id then - log.error("excamera.open", "camera.init澶辫触") - return false - end - -- 閫氳繃I2C鍚戞憚鍍忓ご鍙戦侀厤缃俊鎭 - for i = 1, #camera_module.init_cmds do - result = i2c.send(camera_param.i2c_id, camera_module.i2c_slave_addr, camera_module.init_cmds[i], 1) - if not result then - log.error("excamera.open", "i2c.send澶辫触") - return false - end - end - else - -- I2C閰嶇疆澶辫触锛岃褰曢敊璇棩蹇 - log.info("I2C閰嶇疆閿欒,璇风‘璁2C鎺ュ彛閰嶇疆鏄惁姝ｇ‘") - return false - end - else - -- 濡傛灉涓嶆槸SPI鎽勫儚澶达紝鍒欐寜鐓VP/USB鎽勫儚澶寸殑鍒濆鍖栨柟寮忓鐞 - -- 濡傛灉鏃笉鏄疭PI鎽勫儚澶达紝涔熶笉鏄疍VP/USB鎽勫儚澶达紝鍒欒繑鍥為敊璇 - if not camera.init(camera_param) then - log.info( - "閰嶇疆琛ㄤ腑鈥渋d鈥濆弬鏁版湭閰嶇疆姝ｇ‘,DVP/USB鎽勫儚澶磋浣跨敤camera.USB or camera.DVP杩欐牱鐨勫父閲,涓嶉渶瑕佸姞寮曞彿,璇锋鏌ラ厤缃〃,閫夋嫨姝ｇ‘绫诲瀷鐨勯厤缃〃濉啓") - return false - end - camera_id = camera_param.id - - end - - -- 娉ㄥ唽鎽勫儚澶翠簨浠跺洖璋冨鐞 - camera.on(camera_id, "scanned", function(id, str) - -- 濡傛灉杩斿洖瀛楃涓诧紝琛ㄧず鎵爜鎴愬姛骞惰幏寰楃粨鏋 - if type(str) == 'string' then - log.info("鎵爜缁撴灉", str) - sys.publish("SCAN_DONE", str) - -- 濡傛灉杩斿洖false锛岃〃绀烘憚鍍忓ご娌℃湁鏈夋晥鏁版嵁 - elseif str == false then - log.error("鎽勫儚澶存病鏈夋暟鎹") - -- 濡傛灉杩斿洖true鎴栨暟瀛楋紝琛ㄧず鎴愬姛鎹曡幏鍒板浘鍍忔枃浠跺ぇ灏 - elseif str == true or type(str) == 'number' then - log.info("鎽勫儚澶存暟鎹", str) - -- 鍙戝竷CAPTURE_DONE浜嬩欢锛岄氱煡鍏朵粬浠诲姟鎷嶇収宸插畬鎴 - sys.publish("CAPTURE_DONE", true) - end - end) - -- 鍋滄鎽勫儚澶村綋鍓嶉噰闆嗭紝閲婃斁鍐呭瓨绌洪棿 - camera.stop(camera_id) - - -- 澶勭悊鍥惧儚淇濆瓨璺緞锛屾敮鎸佸唴瀛樼紦鍐插尯(ZBUFF)鎴栨枃浠惰矾寰 - if camera_param.save_path == "ZBUFF" then - -- 鏍规嵁鎽勫儚澶村瀷鍙疯缃浘鍍忓垎杈ㄧ巼 - if camera_param.id == "bf30a2" then - h, w = 240, 320 -- BF30A2鎽勫儚澶村垎杈ㄧ巼 - elseif camera_param.id == "gc032a" or "gc0310" then - h, w = 640, 480 -- GC032A/GC0310鎽勫儚澶村垎杈ㄧ巼 - elseif camera_param.id == camera.USB or camera.DVP then - -- USB鎴朌VP鎽勫儚澶翠娇鐢ㄤ紶鍏ョ殑鍒嗚鲸鐜囧弬鏁 - h, w = camera_param.sensor_height, camera_param.sensor_width - end - - -- 鍒涘缓ZBUFF鍐呭瓨缂撳啿鍖猴紝鐢ㄤ簬瀛樺偍鍥惧儚鏁版嵁 - -- 鍙傛暟1: 缂撳啿鍖哄ぇ灏忥紙瀹*楂*2锛2瀛楄妭/鍍忕礌锛 - -- 鍙傛暟2: 瀵归綈鏂瑰紡 - camera_buff = zbuff.create(h * w * 2, 0) - if camera_buff == nil then - -- 缂撳啿鍖哄垱寤哄け璐 - log.info("ZBUFF鍒涘缓澶辫触") - return false - else - -- 缂撳啿鍖哄垱寤烘垚鍔燂紝淇濆瓨鍒皃ath鍙橀噺 - path = camera_buff - end - else - -- 濡傛灉鏄枃浠惰矾寰勫垯璧嬪煎埌path锛屼究浜庡悗闈㈣皟鐢 - path = camera_param.save_path - end - -- 鍒ゆ柇鏄惁闇瑕佺鐞嗘憚鍍忓ご琛ュ厜鐏 - if type(camera_param.camera_light) == "number" then - cam_light = gpio.setup(camera_param.camera_light, 0) - end - -- 杩斿洖鍒濆鍖栧姩浣滅粨鏋 - return true -end - --- 鎷嶇収鍑芥暟锛氫娇鐢ㄦ寚瀹氭憚鍍忓ご鎷嶆憚鐓х墖骞朵繚瀛 --- 鍙傛暟锛歺, y, w, h - 鍙夛紝鎸囧畾鎷嶆憚鍖哄煙鐨勮捣濮嬪潗鏍囧拰灏哄锛堣鍓尯鍩燂級 --- 杩斿洖鍊硷細鎴愬姛杩斿洖(true, 淇濆瓨璺緞)锛屽け璐ヨ繑鍥瀎alse --- 浣跨敤ZBUFF澶勭悊鐓х墖鏃讹紝姣忔璋冪敤璇ユ帴鍙ｄ负浜嗛伩鍏嶅唴瀛樼垎婊★紝浼氳鐩栧啓鍏BUFF鍖猴紝淇濊瘉ZBUFF鍖哄缁堝彧鏈変竴寮犵収鐗囷紝澶勭悊涓婁紶鎴栬呭瓨鍌ㄥ悗鍐嶈皟鐢ㄨ鎺ュ彛锛岄伩鍏嶇収鐗囦涪澶 -function excamera.photo(x, y, w, h) - if not camera_id then - log.info("鎽勫儚澶村垵濮嬪寲澶辫触锛岃閲嶆柊纭杞‖浠堕厤缃") - return false - end - -- 寮濮嬫憚鍍忓ご鍥惧儚閲囬泦 - camera.start(camera_id) - -- 濡傛灉浣跨敤鍐呭瓨缂撳啿鍖轰繚瀛橈紝閲嶇疆缂撳啿鍖轰綅缃寚閽堝埌寮濮嬩綅缃 - if type(path) == "userdata" then - camera_buff:seek(0) - end - -- 淇濇姢鎵ц鎵撳紑琛ュ厜鐏紝濡傛灉涓婇潰娌℃湁閰嶇疆琛ュ厜鐏紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_light, 1) - log.info("鐓х墖瀛樺偍璺緞", path) - -- 鎵ц鎷嶇収鎿嶄綔锛屼繚瀛樺埌鎸囧畾璺緞 - if camera.capture(camera_id, path, 1, x, y, w, h) then - -- 绛夊緟鎷嶇収瀹屾垚浜嬩欢锛岃秴鏃舵椂闂5000ms - result = sys.waitUntil("CAPTURE_DONE", 5000) - -- 淇濇姢鎵ц鍏抽棴琛ュ厜鐏紝濡傛灉涓婇潰娌℃湁閰嶇疆琛ュ厜鐏紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_light, 0) - -- 鍋滄鎽勫儚澶撮噰闆嗭紝閲婃斁鍐呭瓨绌洪棿 - camera.stop(camera_id) - if result then - -- 鎷嶇収鎴愬姛 - log.info("鎷嶇収瀹屾垚") - else - -- 鎷嶇収瓒呮椂 - log.info("鎷嶇収鎴愬姛锛屾棤鐓х墖鐢熸垚") - return false - end - else - -- 淇濇姢鎵ц鍏抽棴琛ュ厜鐏紝濡傛灉涓婇潰娌℃湁閰嶇疆琛ュ厜鐏紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_light, 0) - -- 鍋滄鎽勫儚澶撮噰闆嗭紝閲婃斁鍐呭瓨绌洪棿 - camera.stop(camera_id) - -- 鎷嶇収鎿嶄綔澶辫触 - log.info("鎷嶇収澶辫触锛岃閲嶈瘯") - return false - end - - -- 杩斿洖鎴愬姛鐘舵佸拰鐓х墖淇濆瓨璺緞 - return true, path -end - --- 鎵弿鍑芥暟锛氫娇鐢ㄦ憚鍍忓ご杩涜鎵弿锛堝浜岀淮鐮/鏉″舰鐮佹壂鎻忥級 --- 鍙傛暟锛氭壂鎻忔椂闀縨s锛屽崟浣嶆绉 --- 杩斿洖鍊硷細鎴愬姛杩斿洖(true, 鎵弿鏁版嵁)锛岃秴鏃舵湭鏈夋壂鎻忕粨鏋滆繑鍥瀎alse -function excamera.scan(ms) - if not camera_id then - log.info("鎽勫儚澶村垵濮嬪寲澶辫触锛岃閲嶆柊纭杞‖浠堕厤缃") - return false - end - -- 寮濮嬫憚鍍忓ご鍥惧儚閲囬泦 - camera.start(camera_id) - -- 淇濇姢鎵ц鎵撳紑琛ュ厜鐏紝濡傛灉涓婇潰娌℃湁閰嶇疆琛ュ厜鐏紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_light, 1) - -- 绛夊緟SCAN_DONE浜嬩欢锛岃秴鏃舵椂闂存牴鎹敤鎴烽厤缃 - result, data = sys.waitUntil("SCAN_DONE", ms) - -- 鍋滄鎽勫儚澶撮噰闆嗭紝閲婃斁鍐呭瓨绌洪棿 - camera.stop(camera_id) - -- 淇濇姢鎵ц鍏抽棴琛ュ厜鐏紝濡傛灉涓婇潰娌℃湁閰嶇疆琛ュ厜鐏紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_light, 0) - if result then - log.info("鎵弿瀹屾垚锛屾壂鎻忕粨鏋滀负锛", data) - else - log.info(ms .. "绉掑唴鏈壂鎻忔垚鍔燂紝璇峰皢鎽勫儚澶村鍑嗕簩缁寸爜") - return false - end - -- 杩斿洖鎴愬姛鐘舵佸拰鎵弿鍒扮殑鏁版嵁 - return true, data -end - --- 褰曞儚鍑芥暟锛氫娇鐢ㄦ寚瀹氭憚鍍忓ご褰曞埗瑙嗛骞跺瓨鍏f鍗′腑 --- 鍙傛暟锛 --- file_path - 瑙嗛淇濆瓨璺緞锛屽"/sd/video.mp4" --- duration - 褰曞埗鏃堕暱锛屽崟浣嶆绉 --- fps - 鍙夛紝甯х巼閰嶇疆 --- 杩斿洖鍊硷細鎴愬姛杩斿洖(true, 淇濆瓨璺緞)锛屽け璐ヨ繑鍥瀎alse --- 娉ㄦ剰锛氬湪浣跨敤姝ゅ嚱鏁板墠锛岄渶瑕佸厛浣跨敤excamera.open閰嶇疆鎽勫儚澶 - --- spi_id,pin_cs -local function fatfs_spi_pin() - local rtos_bsp = rtos.bsp() - if rtos_bsp == "AIR101" then - return 0, pin.PB04 - elseif rtos_bsp == "AIR103" then - return 0, pin.PB04 - elseif rtos_bsp == "AIR105" then - return 2, pin.PB03 - elseif rtos_bsp == "ESP32C3" then - return 2, 7 - elseif rtos_bsp == "ESP32S3" then - return 2, 14 - elseif rtos_bsp == "EC618" then - return 0, 8 - elseif string.find(rtos_bsp,"EC718") then - return 0, 8 - elseif string.find(rtos_bsp,"Air810") then - gpio.setup(13, 1, gpio.PULLUP) - gpio.setup(28, 1, gpio.PULLUP) - return 0, 3, fatfs.SDIO - else - log.info("main", "bsp not support") - return - end -end - --- TF鍗℃寕杞藉嚱鏁 -local function mount_tf_card() - -- 妫鏌F鍗℃槸鍚﹀凡缁忔寕杞 - local result = io.open("/sd/test.txt", "w") - if result then - result:close() - os.remove("/sd/test.txt") - log.info("excamera.mount_tf_card", "TF鍗″凡缁忔寕杞") - return true - end - - -- 灏濊瘯鎸傝浇TF鍗 - local spi_id, pin_cs, tp = fatfs_spi_pin() - if not spi_id then - log.error("excamera.mount_tf_card", "涓嶆敮鎸佺殑骞冲彴") - return false - end - - -- SPI妯″紡闇瑕佸垵濮嬪寲SPI鎬荤嚎 - if tp and tp == fatfs.SPI then - spi.setup(spi_id, nil, 0, 0, 8, 400 * 1000) - gpio.setup(pin_cs, 1) - end - - -- 鎸傝浇TF鍗 - local ret = fatfs.mount(tp or fatfs.SPI, "/sd", spi_id, pin_cs, 24 * 1000 * 1000) - if ret then - log.info("excamera.mount_tf_card", "TF鍗℃寕杞芥垚鍔") - -- 妫鏌ョ┖闂 - local free_info = fatfs.getfree("/sd") - if free_info then - log.info("excamera.mount_tf_card", "鍓╀綑绌洪棿:", free_info.free_kb/1024, "MB") - end - return true - else - log.error("excamera.mount_tf_card", "TF鍗℃寕杞藉け璐") - return false - end -end - -function excamera.video(file_path, duration, fps) - - if not file_path or not duration then - log.error("excamera.video", "鍙傛暟閿欒") - return false - end - - if not camera_id then - log.error("excamera.video", "鎽勫儚澶存湭鍒濆鍖") - return false - end - - -- 濡傛灉鏂囦欢璺緞浠/sd寮澶达紝纭繚TF鍗″凡鎸傝浇 - if string.sub(file_path, 1, 4) == "/sd/" then - if not mount_tf_card() then - log.error("excamera.video", "TF鍗℃寕杞藉け璐ワ紝鏃犳硶褰曞埗瑙嗛") - return false - end - end - - log.info("excamera.video", "寮濮嬪綍鍒惰棰戝埌", file_path) - - -- 濡傛灉鎸囧畾浜嗗抚鐜囷紝鍒欒缃憚鍍忓ご甯х巼 - if fps and fps > 0 then - camera.config(camera_id, camera.CONF_UVC_FPS, fps) - end - - -- 鎵撳嵃鍐呭瓨淇℃伅 - log.info("excamera.video", "lua鍐呭瓨:", rtos.meminfo()) - log.info("excamera.video", "sys鍐呭瓨:", rtos.meminfo("sys")) - - -- 1. 鍚姩鎽勫儚澶 - if camera.start(camera_id) then - -- 2. 寮濮婱P4褰曞埗 - if camera.capture(camera_id, file_path, 1) then - -- 3. 绛夊緟褰曞埗鏃堕暱 - sys.wait(duration) - - -- 4. 鍋滄褰曞埗 - camera.stop(camera_id) - - -- 5. 鍏抽棴鎽勫儚澶达紝閲婃斁璧勬簮 - camera.close(camera_id) - - -- 鍐嶆鎵撳嵃鍐呭瓨淇℃伅 - log.info("excamera.video", "lua鍐呭瓨:", rtos.meminfo()) - log.info("excamera.video", "sys鍐呭瓨:", rtos.meminfo("sys")) - - log.info("excamera.video", "瑙嗛褰曞埗瀹屾垚", file_path) - return true, file_path - else - -- 褰曞埗鍚姩澶辫触锛屽叧闂憚鍍忓ご - camera.stop(camera_id) - camera.close(camera_id) - log.error("excamera.video", "鏃犳硶寮濮嬪綍鍒") - return false - end - else - log.error("excamera.video", "鏃犳硶鍚姩鎽勫儚澶") - camera.close(camera_id) - return false - end -end - --- 鍏抽棴鍑芥暟锛氶噴鏀炬憚鍍忓ご璧勬簮 --- 鍙傛暟锛歝amera_id - 鎽勫儚澶碔D -function excamera.close() - if camera_id then - -- 鍏抽棴鎽勫儚澶达紝閲婃斁鎽勫儚澶寸‖浠惰祫婧 - camera.close(camera_id) - end - -- 鍏抽棴SPI鎽勫儚澶存椂闇瑕佸叧闂璉2C鎺ュ彛锛岄噴鏀鹃氫俊鎬荤嚎璧勬簮 - -- USB鍜孌VP鎽勫儚澶翠笉闇瑕佸叧闂璱2c,鎵浠ラ渶瑕佸垽鏂憚鍍忓ごID杩斿洖鍊硷紝USB涓32锛孌VP涓0锛孲PI涓1 - if camera_id == 1 then - i2c.close(camera_i2c) - end - -- 淇濇姢鎵ц鎽勫儚澶翠娇鑳藉叧闂紝濡傛灉涓婇潰娌℃湁閰嶇疆鎽勫儚澶翠娇鑳界鑴氾紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_pwr, 0) - -- 淇濇姢鎵ц鎽勫儚澶村紑鍏冲叧闂紝濡傛灉涓婇潰娌℃湁閰嶇疆鎽勫儚澶村紑鍏崇鑴氾紝璇ュ嚱鏁颁篃涓嶄細鎶ラ敊 - pcall(cam_pwdn, 1) - -- 濡傛灉浣跨敤浜嗗唴瀛樼紦鍐插尯锛岄噴鏀剧浉鍏宠祫婧 - if type(path) == "userdata" then - -- 缃┖缂撳啿鍖哄紩鐢紝渚夸簬鍨冨溇鍥炴敹 - camera_buff:free() - camera_buff = nil - path = nil - -- 璁板綍褰撳墠绯荤粺鍓╀綑鍐呭瓨鎯呭喌 - log.info("鍓╀綑鍐呭瓨", rtos.meminfo("sys")) - end - return -end - -return excamera diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/excloud.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/excloud.lua deleted file mode 100644 index 6a62d9d..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/excloud.lua +++ /dev/null @@ -1,2484 +0,0 @@ ---[[ -@summary excloud鎵╁睍搴 -@version 1.0 -@date 2025.09.22 -@author 瀛熶紵 -@usage --- 搴旂敤鍦烘櫙 -璇ユ墿灞曞簱閫傜敤浜庡悇绉嶇墿鑱旂綉璁惧锛堝4G/WiFi/浠ュお缃戣澶囷級涓庝簯绔湇鍔″櫒杩涜鏁版嵁浜や簰鐨勫満鏅 -鍙敤浜庤澶囩姸鎬佷笂鎶ャ佹暟鎹噰闆嗐佽繙绋嬫帶鍒剁瓑鐗╄仈缃戝簲鐢ㄣ - -瀹炵幇鐨勫姛鑳斤細 -1. 鏀寔澶氱璁惧绫诲瀷锛4G/WiFi/浠ュお缃戯級鐨勬帴鍏ヨ璇 -2. 鎻愪緵TCP鍜孧QTT涓ょ浼犺緭鍗忚閫夋嫨 -3. 瀹炵幇璁惧涓庝簯绔殑鍙屽悜閫氫俊锛堟暟鎹笂鎶ュ拰鍛戒护涓嬪彂锛 -4. 鏀寔鏁版嵁鐨凾LV鏍煎紡缂栬В鐮 -5. 鎻愪緵鑷姩閲嶈繛鏈哄埗锛屼繚璇佽繛鎺ョǔ瀹氭 -6. 鏀寔涓嶅悓鏁版嵁绫诲瀷锛堟暣鏁般佹诞鐐规暟銆佸竷灏斿笺佸瓧绗︿覆銆佷簩杩涘埗绛夛級鐨勪紶杈 - --- 鐢ㄦ硶瀹炰緥 -鏈墿灞曞簱瀵瑰鎻愪緵浜嗕互涓6涓帴鍙ｏ細 -1. excloud.setup(params) - 璁剧疆閰嶇疆鍙傛暟 -2. excloud.on(cbfunc) - 娉ㄥ唽鍥炶皟鍑芥暟 -3. excloud.open() - 寮鍚痚xcloud鏈嶅姟 -4. excloud.send(data, need_reply, is_auth_msg) - 鍙戦佹暟鎹 -5. excloud.close() - 鍏抽棴excloud鏈嶅姟 -6. excloud.status() - 鑾峰彇褰撳墠鐘舵 -7. excloud.start_heartbeat(interval, custom_data) - 鍚姩鑷姩蹇冭烦鏈哄埗锛屽畾鏈熷悜浜戝钩鍙板彂閫佸績璺虫秷鎭紱 -8. excloud.stop_heartbeat() -鍋滄鑷姩蹇冭烦鏈哄埗锛 -9. excloud.upload_image(file_path, file_name) -涓婁紶鍥剧墖鏂囦欢鍒颁簯骞冲彴锛涙敞鎰忥紝闇瑕佸惎鐢╣etip鏈嶅姟 -10. excloud.upload_audio(file_path, file_name) -涓婁紶闊抽鏂囦欢鍒颁簯骞冲彴锛涙敞鎰忥紝闇瑕佸惎鐢╣etip鏈嶅姟 -11. excloud.get_server_info() - 鑾峰彇getip鑾峰彇鐨勬湇鍔″櫒淇℃伅 -12. excloud.mtn_log(tag, ...) - 璁板綍杩愮淮鏃ュ織锛 - - -]] -local excloud = {} -local httpplus = require "httpplus" -local exmtn = require "exmtn" - -local config = { - device_type = 1, -- 榛樿璁惧绫诲瀷: 4G - device_id = "", -- 璁惧ID - protocol_version = 1, -- 鍗忚鐗堟湰 - transport = "", -- 浼犺緭鍗忚: tcp/mqtt - host = "", -- 鏈嶅姟鍣ㄥ湴鍧 - port = nil, -- 鏈嶅姟鍣ㄧ鍙 - auth_key = nil, -- 鐢ㄦ埛閴存潈瀵嗛挜 - keepalive = 300, -- mqtt蹇冭烦 - auto_reconnect = true, -- 鏄惁鑷姩閲嶈繛 - reconnect_interval = 10, -- 閲嶈繛闂撮殧(绉) - max_reconnect = 3, -- 鏈澶ч噸杩炴鏁 - timeout = 30, -- 杩炴帴瓒呮椂鏃堕棿(绉) - qos = 0, -- MQTT QoS绛夌骇 - retain = 0, -- MQTT retain鏍囧織 - clean_session = true, -- MQTT clean session鏍囧織 - ssl = false, -- 鏄惁浣跨敤SSL - username = nil, -- MQTT鐢ㄦ埛鍚 - password = nil, -- MQTT瀵嗙爜 - udp_auth_key = nil, -- UDP閴存潈瀵嗛挜 - - -- 鏂板socket閰嶇疆鍙傛暟 - local_port = nil, -- 鏈湴绔彛鍙凤紝nil琛ㄧず鑷姩鍒嗛厤 - keep_idle = nil, -- TCP keepalive idle鏃堕棿(绉) - keep_interval = nil, -- TCP keepalive 鎺㈡祴闂撮殧(绉) - keep_cnt = nil, -- TCP keepalive 鎺㈡祴娆℃暟 - server_cert = nil, -- 鏈嶅姟鍣–A璇佷功鏁版嵁 - client_cert = nil, -- 瀹㈡埛绔瘉涔︽暟鎹 - client_key = nil, -- 瀹㈡埛绔閽ユ暟鎹 - client_password = nil, -- 瀹㈡埛绔閽ュ彛浠 - use_getip = true, -- 鏄惁浣跨敤getip鏈嶅姟鍙戠幇锛岄粯璁や负true - -- MQTT鎵╁睍鍙傛暟 - -- mqtt_rx_size = 32 * 1024, -- MQTT鎺ユ敹缂撳啿鍖哄ぇ灏忥紝榛樿32K - -- mqtt_conn_timeout = 30, -- MQTT杩炴帴瓒呮椂鏃堕棿 - -- mqtt_ipv6 = false, -- 鏄惁浣跨敤IPv6杩炴帴 - -- getip鐩稿叧閰嶇疆 - getip_url = "https://gps.openluat.com/iam/iot/getip", -- 鏍规嵁鍗忚淇URL - current_conninfo = {}, -- 褰撳墠杩炴帴淇℃伅 - current_imginfo = nil, -- 褰撳墠鍥剧墖涓婁紶淇℃伅 - current_audinfo = nil, -- 褰撳墠闊抽涓婁紶淇℃伅 - current_mtninfo = nil, -- 鏂板锛氳繍缁存棩蹇椾笂浼犱俊鎭 - getip_retry_count = 0, -- getip閲嶈瘯娆℃暟 - max_getip_retry = 3, -- 鏈澶etip閲嶈瘯娆℃暟 - - -- 铏氭嫙璁惧鐩稿叧閰嶇疆 - virtual_phone_number = nil, -- 鎵嬫満鍙 - virtual_serial_num = 0, -- 搴忓垪鍙凤紙0-999锛 - - -- 杩愮淮鏃ュ織閰嶇疆 - mtn_log_enabled = false, -- 鏄惁鍚敤杩愮淮鏃ュ織 - aircloud_mtn_log_enabled = false, -- 鏄惁鍚敤aircloud杩愮淮鏃ュ織锛歵rue-寮鍚紝false-鍏抽棴锛涘紑鍚悗璁惧璁よ瘉/閲嶈繛绛夊叧閿簨浠朵細鑷姩璁板綍鍒拌繍缁存棩蹇楁枃浠讹紝渚夸簬浜戠缁熶竴鏀堕泦鍒嗘瀽 - mtn_log_blocks = 1, -- 姣忎釜鏂囦欢鐨勫潡鏁 - mtn_log_write_way = exmtn.CACHE_WRITE, -- 鍐欏叆鏂瑰紡 - -} - -local callback_func = nil -- 鍥炶皟鍑芥暟 -local is_open = false -- 鏈嶅姟鏄惁寮鍚 -local is_connected = false -- 鏄惁宸茶繛鎺 -local is_authenticated = false -- 鏄惁宸查壌鏉 -local sequence_num = 1 -- 娴佹按鍙 - --- 杈呭姪鍑芥暟锛氭瀯寤簃ultipart/form-data璇锋眰浣 -local function build_multipart_form_data(forms, files) - local boundary = "----WebKitFormBoundary" .. tostring(os.time()) - local body = {} - - -- 娣诲姞琛ㄥ崟鏁版嵁 - if forms then - for k, v in pairs(forms) do - table.insert(body, "--" .. boundary .. "\r\n") - table.insert(body, string.format("Content-Disposition: form-data; name=\"%s\"\r\n\r\n", k)) - table.insert(body, tostring(v) .. "\r\n") - end - end - - -- 娣诲姞鏂囦欢鏁版嵁 - if files then - for k, file_path in pairs(files) do - local fd = io.open(file_path, "rb") - if fd then - local file_content = fd:read("*a") - fd:close() - - local file_name = file_path:match("[^/\\]+$" or "") - local content_type = "application/octet-stream" - - -- 鏍规嵁鏂囦欢鎵╁睍鍚嶈缃瓹ontent-Type - local ext = file_name:match("%.(%w+)$" or ""):lower() - local content_types = { - txt = "text/plain", - jpg = "image/jpeg", - jpeg = "image/jpeg", - png = "image/png", - gif = "image/gif", - mp3 = "audio/mpeg", - wav = "audio/wav", - json = "application/json", - html = "text/html" - } - if content_types[ext] then - content_type = content_types[ext] - end - - table.insert(body, "--" .. boundary .. "\r\n") - table.insert(body, string.format("Content-Disposition: form-data; name=\"%s\"; filename=\"%s\"\r\n", k, file_name)) - table.insert(body, "Content-Type: " .. content_type .. "\r\n\r\n") - table.insert(body, file_content .. "\r\n") - end - end - end - - -- 娣诲姞缁撴潫杈圭晫 - table.insert(body, "--" .. boundary .. "--\r\n") - - return table.concat(body), boundary -end -local connection = nil -- 杩炴帴瀵硅薄 -local device_id_binary = nil -- 浜岃繘鍒舵牸寮忕殑璁惧ID -local reconnect_timer = nil -- 閲嶈繛瀹氭椂鍣 -local reconnect_count = 0 -- 閲嶈繛娆℃暟 -local pending_messages = {} -- 寰呭彂閫佹秷鎭槦鍒 -local rxbuff = nil -- 鎺ユ敹缂撳啿鍖 -local connect_timeout_timer = nil -- 杩炴帴瓒呮椂瀹氭椂鍣 -local heartbeat_timer = nil -- 蹇冭烦瀹氭椂鍣 -local heartbeat_interval = 300 -- 蹇冭烦闂撮殧(绉)锛岄粯璁5鍒嗛挓 -local heartbeat_data = {} -- 蹇冭烦鏁版嵁锛岄粯璁ょ┖琛 -local is_heartbeat_running = false -- 蹇冭烦鏄惁姝ｅ湪杩愯 -local is_mtn_log_uploading = false -- 杩愮淮鏃ュ織鏄惁姝ｅ湪涓婁紶 - --- 鏁版嵁绫诲瀷瀹氫箟 -local DATA_TYPES = { - INTEGER = 0x0, -- 鏁存暟 - FLOAT = 0x1, -- 娴偣鏁 - BOOLEAN = 0x2, -- 甯冨皵鍊 - ASCII = 0x3, -- ASCII瀛楃涓 - BINARY = 0x4, -- 浜岃繘鍒舵暟鎹 - UNICODE = 0x5 -- Unicode瀛楃涓 -} - --- 瀛楁鍚箟瀹氫箟 -local FIELD_MEANINGS = { - -- 鎺у埗淇′护绫诲瀷 (16-255) - AUTH_REQUEST = 16, -- 閴存潈璇锋眰 - AUTH_RESPONSE = 17, -- 閴存潈鍥炲 - REPORT_RESPONSE = 18, -- 涓婃姤鍥炲簲 - CONTROL_COMMAND = 19, -- 鎺у埗鍛戒护 - CONTROL_RESPONSE = 20, -- 鎺у埗鍥炲簲 - IRTU_DOWN = 21, -- iRTU涓嬭鍛戒护 - IRTU_UP = 22, -- iRTU涓婅鍥炲 - -- 鏂囦欢涓婁紶鎺у埗淇′护 (23-24) - FILE_UPLOAD_START = 23, -- 鏂囦欢涓婁紶寮濮嬮氱煡 - FILE_UPLOAD_FINISH = 24, -- 鏂囦欢涓婁紶瀹屾垚閫氱煡 - - -- 杩愮淮鏃ュ織鎺у埗淇′护 (25-27) - MTN_LOG_UPLOAD_REQ_SIGNAL = 25, -- 杩愮淮鏃ュ織涓婁紶璇锋眰 - 涓嬭锛堜俊浠ょ被鍨嬶級 - MTN_LOG_UPLOAD_RESP_SIGNAL = 26, -- 杩愮淮鏃ュ織涓婁紶鍝嶅簲 - 涓婅锛堜俊浠ょ被鍨嬶級 - MTN_LOG_UPLOAD_STATUS_SIGNAL = 27, -- 杩愮淮鏃ュ織涓婁紶鐘舵 - 涓婅锛堜俊浠ょ被鍨嬶級 - - -- 浼犳劅绫 (256-511) - TEMPERATURE = 256, -- 娓╁害 - HUMIDITY = 257, -- 婀垮害 - PARTICULATE = 258, -- 棰楃矑鏁 - ACIDITY = 259, -- 閰稿害 - ALKALINITY = 260, -- 纰卞害 - ALTITUDE = 261, -- 娴锋嫈 - WATER_LEVEL = 262, -- 姘翠綅 - ENV_TEMPERATURE = 263, -- CPU娓╁害/鐜娓╁害 - POWER_METERING = 264, -- 鐢甸噺璁￠噺 - - -- 璧勪骇绠＄悊绫 (512-767) - GNSS_LONGITUDE = 512, -- GNSS缁忓害 - GNSS_LATITUDE = 513, -- GNSS绾害 - SPEED = 514, -- 琛岄┒閫熷害 - GNSS_CN = 515, -- 鏈寮虹殑4棰桮NSS鍗槦鐨凜N - SATELLITES_TOTAL = 516, -- 鎼滃埌鐨勬墍鏈夊崼鏄熸暟 - SATELLITES_VISIBLE = 517, -- 鍙鍗槦鏁 - HEADING = 518, -- 鑸悜瑙 - LOCATION_METHOD = 519, -- 鍩虹珯瀹氫綅/GNSS瀹氫綅鏍囪瘑 - GNSS_INFO = 520, -- GNSS鑺墖鍨嬪彿鍜屽浐浠剁増鏈彿 - DIRECTION = 521, -- 鏂瑰悜 - - -- 璁惧鍙傛暟绫 (768-1023) - HEIGHT = 768, -- 楂樺害 - WIDTH = 769, -- 瀹藉害 - ROTATION_SPEED = 770, -- 杞 - BATTERY_LEVEL = 771, -- 鐢甸噺(mV) - SERVING_CELL = 772, -- 椹荤暀棰戞 - CELL_INFO = 773, -- 椹荤暀灏忓尯鍜岄偦鍖 - COMPONENT_MODEL = 774, -- 鍏冨櫒浠跺瀷鍙 - GPIO_LEVEL = 775, -- GPIO楂樹綆鐢靛钩 - BOOT_REASON = 776, -- 寮鏈哄師鍥 - BOOT_COUNT = 777, -- 寮鏈烘鏁 - SLEEP_MODE = 778, -- 浼戠湢妯″紡 - WAKE_INTERVAL = 779, -- 瀹氭椂鍞ら啋闂撮殧 - NETWORK_IP_TYPE = 780, -- 璁惧鍏ョ綉鐨処P绫诲瀷 - NETWORK_TYPE = 781, -- 褰撳墠鑱旂綉鏂瑰紡 - SIGNAL_STRENGTH_4G = 782, --4G淇″彿寮哄害 - SIM_ICCID = 783, -- SIM鍗CCID - - -- 鏂囦欢涓婁紶涓氬姟瀛楁 (784-787) - FILE_UPLOAD_TYPE = 784, -- 鏂囦欢涓婁紶绫诲瀷锛1:鍥剧墖, 2:闊抽锛 - FILE_NAME = 785, -- 鏂囦欢鍚嶇О - FILE_SIZE = 786, -- 鏂囦欢澶у皬 - UPLOAD_RESULT_STATUS = 787, -- 涓婁紶缁撴灉鐘舵 - - -- 杩愮淮鏃ュ織涓氬姟瀛楁 (788-792) - MTN_LOG_FILE_INDEX = 788, -- 杩愮淮鏃ュ織鏂囦欢搴忓彿 - MTN_LOG_FILE_TOTAL = 789, -- 杩愮淮鏃ュ織鏂囦欢鎬绘暟 - MTN_LOG_FILE_SIZE = 790, -- 杩愮淮鏃ュ織鏂囦欢澶у皬 - MTN_LOG_UPLOAD_STATUS_FIELD = 791, -- 杩愮淮鏃ュ織涓婁紶鐘舵 - MTN_LOG_FILE_NAME = 792, -- 杩愮淮鏃ュ織鏂囦欢鍚嶇О - - -- 宸ョ墝璁惧鍙傛暟瀛楁 (793-797) - 鏂板 - BADGE_TOTAL_DISK = 793, -- 宸ョ墝鎬荤鐩樼┖闂 - BADGE_AVAILABLE_DISK = 794, -- 宸ョ墝鍓╀綑纾佺洏绌洪棿 - BADGE_TOTAL_MEM = 795, -- 宸ョ墝鎬诲唴瀛 - BADGE_AVAILABLE_MEM = 796, -- 宸ョ墝鍓╀綑鍐呭瓨 - BADGE_RECORD_COUNT = 797, -- 宸ョ墝褰曢煶鏁伴噺 - - -- 杞欢鏁版嵁绫 (1024-1279) - LUA_CORE_ERROR = 1024, -- Lua鏍稿績搴撻敊璇笂鎶 - LUA_EXT_ERROR = 1025, -- Lua鎵╁睍鍗￠敊璇笂鎶 - LUA_APP_ERROR = 1026, -- Lua涓氬姟閿欒涓婃姤 - FIRMWARE_VERSION = 1027, -- 鍥轰欢鐗堟湰鍙 - SMS_FORWARD = 1028, -- SMS杞彂 - CALL_FORWARD = 1029, -- 鏉ョ數杞彂 - - -- 璁惧鏃犲叧鏁版嵁绫 (1280-1535) - TIMESTAMP = 1280, -- 鏃堕棿 - RANDOM_DATA = 1281 -- 鏃犳剰涔夋暟鎹 -} - --- 杩愮淮鏃ュ織涓婁紶鐘舵 -local MTN_LOG_STATUS = { - START = 0, -- 寮濮嬩笂浼 - SUCCESS = 1, -- 涓婁紶鎴愬姛 - FAILED = 2 -- 涓婁紶澶辫触 -} - --- 灏嗘暟瀛楄浆鎹负澶х瀛楄妭搴忓垪 -local function to_big_endian(num, bytes) - local result = {} - for i = bytes, 1, -1 do - result[i] = string.char(num % 256) - num = math.floor(num / 256) - end - return table.concat(result) -end - --- 浠庡ぇ绔瓧鑺傚簭鍒楄浆鎹负鏁板瓧 -local function from_big_endian(data, start, length) - local value = 0 - for i = start, start + length - 1 do - value = value * 256 + data:byte(i) - end - -- log.info("[excloud]from_big_endian", value) - return value -end - --- 灏嗚澶嘔D杩涜缂栫爜 -local function packDeviceInfo(deviceType, deviceId) - -- 楠岃瘉璁惧绫诲瀷 - if deviceType ~= 1 and deviceType ~= 2 and deviceType ~= 9 then - log.info("[excloud]璁惧绫诲瀷閿欒: 4G璁惧搴斾负1, WIFI璁惧搴斾负2") - end - - -- 璁惧绫诲瀷瀛楄妭 - local result = { string.char(deviceType) } - - -- 娓呯悊璁惧ID锛堢Щ闄ら潪鏁板瓧鍜屽瓧姣嶅瓧绗︼紝骞惰浆鎹负澶у啓锛 - local cleanId = deviceId:gsub("[^%w]", ""):upper() - - -- 澶勭悊涓嶅悓绫诲瀷鐨勮澶嘔D - if deviceType == 1 then - -- 4G璁惧 - IMEI澶勭悊 - -- 鍙彇鍓14浣嶆暟瀛楋紝蹇界暐绗15浣 - cleanId = cleanId:gsub("%D", ""):sub(1, 14) - - -- 纭繚闀垮害涓14浣嶏紙涓嶈冻鏃跺墠闈㈣ˉ0锛 - if #cleanId < 14 then - cleanId = string.rep("0", 14 - #cleanId) .. cleanId - end - - -- 杞崲涓築CD鏍煎紡鐨勫瓧鑺 - for i = 1, 14, 2 do - local byte = (tonumber(cleanId:sub(i, i)) * 16) + tonumber(cleanId:sub(i + 1, i + 1)) - table.insert(result, string.char(byte)) - end - elseif deviceType == 2 then - -- WIFI璁惧 - MAC鍦板潃澶勭悊 - -- 绉婚櫎闈炲崄鍏繘鍒跺瓧绗 - cleanId = cleanId:gsub("[^0-9A-Fa-f]", "") - - -- 纭繚闀垮害涓12涓崄鍏繘鍒跺瓧绗︼紙6瀛楄妭锛 - if #cleanId < 12 then - cleanId = string.rep("0", 12 - #cleanId) .. cleanId - else - cleanId = cleanId:sub(1, 12) - end - - -- 杞崲涓哄瓧鑺 - local bytes = {} - for i = 1, 12, 2 do - local byteStr = cleanId:sub(i, i + 1) - table.insert(bytes, string.char(tonumber(byteStr, 16))) - end - - -- 纭繚鏈7涓瓧鑺傦紙涓嶈冻鏃跺墠闈㈣ˉ0锛 - while #bytes < 7 do - table.insert(bytes, 1, string.char(0)) - end - - -- 娣诲姞鍒扮粨鏋滀腑 - for _, byte in ipairs(bytes) do - table.insert(result, byte) - end - elseif deviceType == 9 then - -- 铏氭嫙璁惧澶勭悊锛11浣嶆墜鏈哄彿 + 3浣嶅簭鍒楀彿 - cleanId = cleanId:gsub("%D", ""):sub(1, 14) - if #cleanId < 14 then - cleanId = string.rep("0", 14 - #cleanId) .. cleanId - end - - -- 杞崲涓築CD鏍煎紡鐨勫瓧鑺傦紙姣2浣嶆暟瀛楄浆鎹负1涓瓧鑺傦級 - for i = 1, 14, 2 do - local byte = (tonumber(cleanId:sub(i, i)) * 16) + tonumber(cleanId:sub(i + 1, i + 1)) - table.insert(result, string.char(byte)) - end - else - log.info("[excloud]鏈煡璁惧绫诲瀷 ") - return deviceId - end - - -- 杩斿洖8瀛楄妭鐨勪簩杩涘埗鏁版嵁 - return table.concat(result) -end - --- 缂栫爜鏁版嵁鍊 -local function encode_value(data_type, value) - -- 娣诲姞鍙傛暟绫诲瀷妫鏌 - if data_type == nil or value == nil then - log.info("[excloud]Data type or value is nil") - return "" - end - if data_type == DATA_TYPES.INTEGER then - -- 楠岃瘉value鏄惁涓烘暟瀛 - if type(value) ~= "number" then - log.info("[excloud]Integer value must be a number") - return "" - end - return to_big_endian(math.floor(value), 4) - elseif data_type == DATA_TYPES.FLOAT then - -- 楠岃瘉value鏄惁涓烘暟瀛 - if type(value) ~= "number" then - log.info("[excloud]Float value must be a number") - return "" - end - -- 绠鍖栧鐞嗭細灏嗘诞鐐规暟杞崲涓烘暣鏁帮紝涔樹互1000浠ヤ繚鐣欎笁浣嶅皬鏁 - return to_big_endian(math.floor(value * 1000), 4) - elseif data_type == DATA_TYPES.BOOLEAN then - return value and "\1" or "\0" - elseif data_type == DATA_TYPES.ASCII or data_type == DATA_TYPES.BINARY or data_type == DATA_TYPES.UNICODE then - -- 纭繚value鏄瓧绗︿覆绫诲瀷 - return tostring(value) - else - log.info("[excloud]Unsupported data type: " .. tostring(data_type)) - -- 杩斿洖绌哄瓧绗︿覆鑰屼笉鏄痭il锛岄伩鍏嶅悗缁鐞嗗嚭閿 - return "" - end -end - --- 瑙ｇ爜鏁版嵁鍊 -local function decode_value(data_type, value) - if data_type == DATA_TYPES.INTEGER then - return from_big_endian(value, 1, #value) - elseif data_type == DATA_TYPES.FLOAT then - -- 绠鍖栧鐞嗭細灏嗘暣鏁拌浆鎹负娴偣鏁帮紙瀹為檯搴斾娇鐢↖EEE 754鏍煎紡锛 - return from_big_endian(value, 1, #value) / 1000 - elseif data_type == DATA_TYPES.BOOLEAN then - return value:byte(1) ~= 0 - elseif data_type == DATA_TYPES.ASCII then - return value - elseif data_type == DATA_TYPES.BINARY then - return value - elseif data_type == DATA_TYPES.UNICODE then - return value - else - log.info("[excloud]Unsupported data type: " .. data_type) - return nil - end -end - --- 鏋勫缓娑堟伅澶 --- @param need_reply boolean 鏄惁闇瑕佹湇鍔″櫒鍥炲 --- @param has_auth_key boolean 鏄惁鎼哄甫閴存潈key --- @param data_length number 鏁版嵁闀垮害 -local function build_header(need_reply, is_udp_transport, data_length) - sequence_num = sequence_num + 1 - if sequence_num > 65535 then - sequence_num = 1 - end - - -- 娑堟伅鏍囪瘑瀛楁 - local flags = config.protocol_version -- bit0-3: 鍗忚鐗堟湰鍙 - if need_reply then - flags = flags + 16 -- bit4: 鏄惁闇瑕佸洖澶 - end - if is_udp_transport then - flags = flags + 32 -- bit5: 鏄惁鏄疷DP鎵胯浇 - end - log.info("[excloud]鏋勫缓娑堟伅澶", device_id_binary, to_big_endian(sequence_num, 2), to_big_endian(data_length, 2), - to_big_endian(flags, 4)) - return device_id_binary .. - to_big_endian(sequence_num, 2) .. - to_big_endian(data_length, 2) .. - to_big_endian(flags, 4) -end - --- 鏋勫缓TLV瀛楁 -local function build_tlv(field_meaning, data_type, value) - if field_meaning == nil or data_type == nil or value == nil then - log.info("[excloud]鏋勫缓tlv鍙傛暟涓嶈兘涓虹┖") - return false - end - local value_encoded = encode_value(data_type, value) - if value_encoded == nil then - log.info("[excloud]鏋勫缓tlv鎵撳寘鏁版嵁鏃堕暱搴︿负0") - -- 娣诲姞绌哄瓧绗︿覆浣滀负榛樿鍊硷紝閬垮厤鍚庣画鑾峰彇闀垮害鏃跺嚭閿 - value_encoded = "" - end - local length = #value_encoded - -- 瀛楁绫诲瀷锛堝瓧娈靛惈涔 + 鏁版嵁绫诲瀷锛 - local head = (field_meaning & 0x0FFF) | (data_type << 12) -- 2 瀛楄妭澶 - return true, to_big_endian(head, 2) .. - to_big_endian(length, 2) .. - value_encoded -end - --- 瑙ｆ瀽娑堟伅澶 -local function parse_header(header) - if #header < 16 then - log.info("[excloud]娑堟伅澶磋В鏋愬け璐", "Header too short") - return nil, "Header too short" - end - - local device_id = header:sub(1, 8) - local seq_num = from_big_endian(header, 9, 2) - local msg_length = from_big_endian(header, 11, 2) - local flags = from_big_endian(header, 13, 4) - - -- 鎻愬彇鏍囧織浣 - local protocol_version = flags % 16 - local need_reply = (flags % 32) >= 16 - local is_udp_transport = (flags % 64) >= 32 - - -- 鎵撳嵃瑙ｆ瀽缁撴灉锛屾柟渚胯皟璇 - -- log.info("[excloud]娑堟伅澶磋В鏋愮粨鏋", - -- string.format( - -- "device_id: %s, sequence_num: %d, msg_length: %d, protocol_version: %d, need_reply: %s, is_udp_transport: %s", - -- string.toHex(device_id), seq_num, msg_length, protocol_version, - -- tostring(need_reply), tostring(is_udp_transport))) - - return { - device_id = string.toHex(device_id), - sequence_num = seq_num, - msg_length = msg_length, - protocol_version = protocol_version, - need_reply = need_reply, - is_udp_transport = is_udp_transport - } -end - --- 宸ュ叿鍑芥暟锛氳В鏋怲LV -local function parse_tlv(data, startPos) - -- 妫鏌ユ暟鎹槸鍚﹁冻澶熻В鏋怲LV鐨凾鐨勯暱搴︺ - if #data < startPos + 3 then - return nil, startPos, "TLV data too short" - end - - local fieldType = from_big_endian(data, startPos, 2) - local length = from_big_endian(data, startPos + 2, 2) - -- 鎻愬彇鍘熷瀛楄妭鍊 - local value = data:sub(startPos + 4, startPos + 4 + length - 1) - --瑙ｆ瀽TLV瀛楁涓殑T - -- bit0-11: 瀛楁鍚箟 - -- bit12-15: 鏁版嵁绫诲瀷 - local field_meaning = fieldType & 0x0FFF -- 鍙栦綆12浣嶄綔涓哄瓧娈靛惈涔 - local data_type = fieldType >> 12 -- 鍙栭珮4浣嶄綔涓烘暟鎹被鍨 - - local decoded_value = decode_value(data_type, value) - -- log.info("[excloud]娑堟伅浣撹В鏋愮粨鏋", field_meaning, data_type, decoded_value) - return { - field = field_meaning, - type = data_type, - value = decoded_value, - length = length, --鏁版嵁闀垮害 - }, startPos + 4 + length -end - --- 瑙ｆ瀽瀹屾暣娑堟伅 -local function parse_message(data) - local header, err = parse_header(data:sub(1, 16)) - if not header then - return nil, err - end - local auth_key = nil - local body_start = 17 - - -- 濡傛灉鏄疷DP浼犺緭锛岃В鏋愯璇乲ey - if header.is_udp_transport then - if #data >= body_start + 64 - 1 then - auth_key = data:sub(body_start, body_start + 64 - 1) - body_start = body_start + 64 - else - return nil, "Incomplete UDP authentication key" - end - end - - -- 瑙ｆ瀽TLV瀛楁 - local tlvs = {} - local pos = body_start - local end_pos = 16 + (header.msg_length) - - if #data < end_pos then - return nil, "Message incomplete" - end - while pos < end_pos do - local tlv, new_pos, err = parse_tlv(data, pos) - if not tlv then - return nil, "Failed to parse TLV at position " .. err - end - table.insert(tlvs, tlv) - -- 鏇存柊瑙ｆ瀽浣嶇疆涓鸿В鏋愬畬褰撳墠TLV瀛楁鍚庣殑鏂颁綅缃紝浠ヤ究缁х画瑙ｆ瀽鍚庣画鐨凾LV瀛楁 - pos = new_pos - end - - return { - header = header, - auth_key = auth_key, - tlvs = tlvs - } -end - --- 鍙戦侀壌鏉冭姹 -local function send_auth_request() - if not config.auth_key then - return false, "No auth key configured" - end - local auth_data - --璁惧瀹炴祴鏃舵墦寮 - if config.device_type == 1 then - auth_data = config.auth_key .. "-" .. mobile.imei() .. "-" .. mobile.muid() - elseif config.device_type == 2 then - auth_data = config.auth_key .. "-" .. wlan.getMac(nil, true) .. "-" .. mcu.unique_id():toHex() - elseif config.device_type == 9 then --铏氭嫙璁惧 - auth_data = config.auth_key .. "-" .. config.device_id - else - auth_data = config.auth_key .. "-" - end - - local message = { - { - field_meaning = FIELD_MEANINGS.AUTH_REQUEST, - data_type = DATA_TYPES.ASCII, - value = auth_data - } - } - -- log.info("[excloud]send auth request", message,message[1].value,message[1].data_type,message[1].field_meaning) - return excloud.send(message, true, true) -- 閴存潈娑堟伅闇瑕佽缃 is_auth_msg 涓 true -end - --- 澶勭悊璁よ瘉鍝嶅簲 --- local function handle_auth_response(tlvs) --- for _, tlv in ipairs(tlvs) do --- if tlv.field_meaning == FIELD_MEANINGS.AUTH_RESPONSE then --- local success = (tlv.value == "OK" or tlv.value == "SUCCESS") --- is_authenticated = true - --- -- 璁板綍璁よ瘉缁撴灉鍒拌繍缁存棩蹇 --- if config.aircloud_mtn_log_enabled then --- exmtn.log("info", "aircloud","auth", "璁よ瘉缁撴灉", "success", success, "message", tlv.value) --- end - - --- if callback_func then --- callback_func("auth_result", { --- success = success, --- message = tlv.value --- }) --- end - --- -- 璁よ瘉鎴愬姛锛屽彂閫佸緟澶勭悊娑堟伅 --- if success then --- for _, msg in ipairs(pending_messages) do --- excloud.send(msg.data, msg.need_reply) --- end --- pending_messages = {} --- end - --- return success --- end --- end - --- return false --- end - --- 鍒濆鍖栬繍缁存棩蹇楁ā鍧 -local function init_mtn_log() - if not config.mtn_log_enabled then - log.info("[excloud]aircloud杩愮淮鏃ュ織鍔熻兘宸茬鐢") - return true - end - - local ok, err = exmtn.init(config.mtn_log_blocks, config.mtn_log_write_way) - if not ok then - log.error("[excloud]杩愮淮鏃ュ織鍒濆鍖栧け璐:", err) - return false, err - end - - log.info("[excloud]杩愮淮鏃ュ織鍒濆鍖栨垚鍔") - return true -end - --- 鎵弿杩愮淮鏃ュ織鏂囦欢 -local function scan_mtn_log_files() - local log_files = {} - - -- 浣跨敤exmtn绠＄悊鐨勬枃浠朵俊鎭 - for i = 1, 4 do -- exmtn绠＄悊4涓棩蹇楁枃浠 - local file_path = string.format("/hzmtn%d.trc", i) - if io.exists(file_path) then - local file_size = io.fileSize(file_path) - if file_size > 0 then - table.insert(log_files, { - name = string.format("hzmtn%d.trc", i), - path = file_path, - size = file_size, - index = i - }) - log.info("鍙戠幇杩愮淮鏃ュ織鏂囦欢", "璺緞:", file_path, "澶у皬:", file_size, "搴忓彿:", i) - else - log.info("杩愮淮鏃ュ織鏂囦欢涓虹┖", "璺緞:", file_path) - end - else - log.info("杩愮淮鏃ュ織鏂囦欢涓嶅瓨鍦", "璺緞:", file_path) - end - end - - -- 鎸夋枃浠跺簭鍙锋帓搴 - table.sort(log_files, function(a, b) - return a.index < b.index - end) - - log.info("鎵弿杩愮淮鏃ュ織鏂囦欢瀹屾垚", "鏈夋晥鏂囦欢鏁伴噺:", #log_files) - return log_files -end - --- 鏋勫缓杩愮淮鏃ュ織鍝嶅簲TLV鏁版嵁 -local function build_mtn_log_response_tlv(total_files, latest_index) - local sub_tlvs = "" - - -- 鏂囦欢鎬绘暟 - local success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_FILE_TOTAL, DATA_TYPES.INTEGER, total_files) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.error("鏋勫缓鏂囦欢鎬绘暟TLV澶辫触") - return "" - end - - -- 褰撳墠鏈鏂版枃浠跺簭鍙 - success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_FILE_INDEX, DATA_TYPES.INTEGER, latest_index) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.error("鏋勫缓鏈鏂版枃浠跺簭鍙稵LV澶辫触") - return "" - end - - log.info("鏋勫缓杩愮淮鏃ュ織鍝嶅簲TLV", "鏂囦欢鎬绘暟:", total_files, "鏈鏂板簭鍙:", latest_index) - return sub_tlvs -end - --- 鍙戦佽繍缁存棩蹇椾笂浼犵姸鎬 -local function send_mtn_log_status(status, file_index, file_name, file_size) - local sub_tlvs = "" - - -- 涓婁紶鐘舵侊紙蹇呴』锛 - local success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_UPLOAD_STATUS_FIELD, DATA_TYPES.INTEGER, status) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.error("鏋勫缓杩愮淮鏃ュ織涓婁紶鐘舵乀LV澶辫触") - return false, "鏋勫缓鐘舵乀LV澶辫触" - end - - -- 鏂囦欢搴忓彿 - success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_FILE_INDEX, DATA_TYPES.INTEGER, file_index) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.error("鏋勫缓鏂囦欢搴忓彿TLV澶辫触") - return false, "鏋勫缓鏂囦欢搴忓彿TLV澶辫触" - end - - -- 鏍规嵁鐘舵佹坊鍔犱笉鍚岀殑瀛楁 - if status == MTN_LOG_STATUS.START then - -- 寮濮嬩笂浼狅細鍖呭惈鏂囦欢鍚 - if file_name then - success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_FILE_NAME, DATA_TYPES.ASCII, file_name) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.warn("鏋勫缓鏂囦欢鍚峊LV澶辫触锛屼絾缁х画鍙戦佺姸鎬") - end - else - log.warn("寮濮嬩笂浼犵姸鎬佺己灏戞枃浠跺悕") - end - elseif status == MTN_LOG_STATUS.SUCCESS then - -- 涓婁紶鎴愬姛锛氬寘鍚枃浠跺ぇ灏 - if file_size then - success, tlv_data = build_tlv(FIELD_MEANINGS.MTN_LOG_FILE_SIZE, DATA_TYPES.INTEGER, file_size) - if success then - sub_tlvs = sub_tlvs .. tlv_data - else - log.warn("鏋勫缓鏂囦欢澶у皬TLV澶辫触锛屼絾缁х画鍙戦佺姸鎬") - end - else - log.warn("涓婁紶鎴愬姛鐘舵佺己灏戞枃浠跺ぇ灏") - end - end - -- 涓婁紶澶辫触锛氬彧闇瑕佺姸鎬佸拰搴忓彿 - - -- 鍙戦佺姸鎬佹秷鎭 - local ok, err_msg = excloud.send({ - { - field_meaning = FIELD_MEANINGS.MTN_LOG_UPLOAD_STATUS_SIGNAL, - data_type = DATA_TYPES.BINARY, - value = sub_tlvs - } - }, false) - - if not ok then - log.error("鍙戦佽繍缁存棩蹇椾笂浼犵姸鎬佸け璐: " .. (err_msg or "鏈煡閿欒")) - return false, err_msg - end - - log.info("杩愮淮鏃ュ織涓婁紶鐘舵佸彂閫佹垚鍔", - "鐘舵:", status, - "鏂囦欢搴忓彿:", file_index, - "鏂囦欢鍚:", file_name or "N/A", - "鏂囦欢澶у皬:", file_size or "N/A") - - return true -end --- 涓婁紶杩愮淮鏃ュ織鏂囦欢 -local function upload_mtn_log_files() - - sys.taskInit(function() - -- 璁剧疆涓婁紶鏍囧織浣嶄负true - is_mtn_log_uploading = true - - local total_files = 4 -- 鍥哄畾涓4涓棩蹇楁枃浠 - local success_count = 0 - local failed_count = 0 - local processed_count = 0 - - -- -- 閫氱煡寮濮嬩笂浼 - -- if callback_func then - -- callback_func("mtn_log_upload_start", { - -- file_count = total_files - -- }) - -- end - - -- 鎸夐『搴忔鏌ュ苟涓婁紶姣忎釜鏃ュ織鏂囦欢 - for i = 1, 4 do - local file_path = string.format("/hzmtn%d.trc", i) - local file_name = string.format("/hzmtn%d.trc", i) - - -- 鍦ㄤ笂浼犲墠鍐嶆妫鏌ユ枃浠舵槸鍚﹀瓨鍦ㄤ笖涓嶄负绌 - local file_size = io.fileSize(file_path) - if file_size and file_size > 0 then - processed_count = processed_count + 1 - - -- 鍙戦佸紑濮嬩笂浼犵姸鎬 - send_mtn_log_status(MTN_LOG_STATUS.START, i, file_name, file_size) - - log.info("[excloud]寮濮嬩笂浼犺繍缁存棩蹇楁枃浠", "鏂囦欢:", file_name, "澶у皬:", file_size) - - -- 涓婁紶鏂囦欢 - local success, err_msg = excloud.upload_mtnlog(file_path, file_name) - - if success then - -- 鍙戦佷笂浼犳垚鍔熺姸鎬 - log.info("杩愮淮鏃ュ織鏂囦欢涓婁紶鎴愬姛", "鏂囦欢:", file_name, "澶у皬:", file_size) - send_mtn_log_status(MTN_LOG_STATUS.SUCCESS, i, file_name, file_size) - success_count = success_count + 1 - - -- 璁板綍涓婁紶鎴愬姛鐨勮繍缁存棩蹇 - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "mtn_upload", "鏂囦欢涓婁紶鎴愬姛", "file", file_name, "size", file_size) - end - else - -- 鍙戦佷笂浼犲け璐ョ姸鎬 - log.error("杩愮淮鏃ュ織鏂囦欢涓婁紶澶辫触", "鏂囦欢:", file_name, "閿欒:", err_msg) - send_mtn_log_status(MTN_LOG_STATUS.FAILED, i, file_name, file_size) - failed_count = failed_count + 1 - - -- 璁板綍涓婁紶澶辫触鐨勮繍缁存棩蹇 - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "mtn_upload_error", "鏂囦欢涓婁紶澶辫触", "file", file_name, "error", err_msg) - end - end - - -- 閫氱煡涓婁紶杩涘害 - if callback_func then - callback_func("mtn_log_upload_progress", { - current_file = processed_count, - total_files = total_files, - file_name = file_name, - file_size = file_size, - status = success and "success" or "failed", - error_msg = err_msg - }) - end - else - -- 鏂囦欢涓嶅瓨鍦ㄦ垨涓虹┖锛岃烦杩囦笂浼 - log.info("杩愮淮鏃ュ織鏂囦欢涓嶅瓨鍦ㄦ垨涓虹┖锛岃烦杩囦笂浼", "鏂囦欢:", file_name) - end - -- -- 鏂囦欢闂村欢杩燂紝閬垮厤鍚屾椂涓婁紶澶氫釜鏂囦欢 - -- if i < 4 then - -- sys.wait(2000) - -- end - end - - log.info("杩愮淮鏃ュ織涓婁紶瀹屾垚", "鎴愬姛:", success_count, "澶辫触:", failed_count, "鎬昏:", processed_count) - - -- 璁板綍涓婁紶瀹屾垚鏃ュ織 - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "mtn_upload", "杩愮淮鏃ュ織涓婁紶瀹屾垚", "success", success_count, "failed", failed_count, - "total", processed_count) - end - - -- 閫氱煡涓婁紶瀹屾垚 - if callback_func then - callback_func("mtn_log_upload_complete", { - success_count = success_count, - failed_count = failed_count, - total_files = processed_count - }) - end - - -- 涓婁紶瀹屾垚锛岃缃爣蹇椾綅涓篺alse - is_mtn_log_uploading = false - end) -end - --- 澶勭悊杩愮淮鏃ュ織涓婁紶璇锋眰 -local function handle_mtn_log_upload_request() - -- 妫鏌ユ槸鍚︽鍦ㄤ笂浼狅紝濡傛灉鏄垯鐩存帴杩斿洖锛屾姏寮冩柊璇锋眰 - if is_mtn_log_uploading then - log.info("[excloud]杩愮淮鏃ュ織姝ｅ湪涓婁紶涓紝鎶涘純鏂扮殑涓婁紶璇锋眰") - return - end - - local total_files = 4 -- 鍥哄畾涓4涓棩蹇楁枃浠 - local latest_index = 4 -- 鏈鏂板簭鍙峰浐瀹氫负4 - - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "cloud_cmd", "鏀跺埌杩愮淮鏃ュ織涓婁紶璇锋眰", "file_count", total_files) - end - - log.info("寮濮嬪鐞嗚繍缁存棩蹇椾笂浼犺姹", "鏂囦欢鎬绘暟:", total_files, "鏈鏂板簭鍙:", latest_index) - - -- 鍙戦佽繍缁存棩蹇椾笂浼犲搷搴旓紙淇′护26锛- 鍦ㄥ紑濮嬩笂浼犲墠鍙戦 - local response_ok, err_msg = excloud.send({ - { - field_meaning = FIELD_MEANINGS.MTN_LOG_UPLOAD_RESP_SIGNAL, -- 浣跨敤淇′护绫诲瀷 - data_type = DATA_TYPES.BINARY, - value = build_mtn_log_response_tlv(total_files, latest_index) - } - }, false) - - if not response_ok then - log.error("鍙戦佽繍缁存棩蹇椾笂浼犲搷搴斿け璐: " .. err_msg) - return - end - - log.info("杩愮淮鏃ュ織涓婁紶鍝嶅簲宸插彂閫", "鏂囦欢鎬绘暟:", total_files, "鏈鏂板簭鍙:", latest_index) - - -- 寮濮嬩笂浼犳棩蹇楁枃浠 - sys.timerStart(function() - upload_mtn_log_files() - end, 10) -end - - - --- 鎺ユ敹娑堟伅瑙ｆ瀽澶勭悊 -local function parse_data(data) - local message, err = parse_message(data) - if not message then - log.info("[excloud]Failed to parse message: " .. err) - return - end - - -- 澶勭悊杩愮淮鏃ュ織涓婁紶璇锋眰锛堜俊浠25锛 - for _, tlv in ipairs(message.tlvs) do - if tlv.field == FIELD_MEANINGS.MTN_LOG_UPLOAD_REQ_SIGNAL then - log.info("[excloud]鏀跺埌杩愮淮鏃ュ織涓婁紶璇锋眰") - handle_mtn_log_upload_request() - return - end - end - - -- 澶勭悊璁よ瘉鍝嶅簲 - -- if not is_authenticated then - -- for _, tlv in ipairs(message.tlvs) do - -- if tlv.field == FIELD_MEANINGS.AUTH_RESPONSE then - -- handle_auth_response(message.tlvs) - -- return - -- end - -- end - --end - - --鏁版嵁杩斿洖缁欏洖璋 - if callback_func then - callback_func("message", message) - end - - -- -- 濡傛灉闇瑕佸洖澶嶏紝鍙戦佺‘璁AA - -- if message.header.need_reply then - -- local response = { - -- { - -- field_meaning = FIELD_MEANINGS.REPORT_RESPONSE, - -- data_type = DATA_TYPES.ASCII, - -- value = "ACK" - -- } - -- } - -- excloud.send(response, false) - -- end -end - -function excloud.getip(getip_type) - getip_type = getip_type or 3 -- 榛樿浣跨敤AirCloud TCP鍗忚 - - -- 娣诲姞鍙傛暟楠岃瘉 - if not config.auth_key or not config.device_id then - return false, "缂哄皯蹇呰鐨勮璇佸弬鏁: auth_key 鎴 device_id" - end - - local key = config.auth_key .. "-" .. config.device_id - log.info("[excloud]excloud.getip", "绫诲瀷:", getip_type, "key:", key) - - -- 鎵цHTTP璇锋眰 - local code, response = httpplus.request( - { - method = "POST", - url = config.getip_url, - forms = { key = key, type = getip_type } - }) - - log.info("[excloud]excloud.getip鍝嶅簲", "HTTP Code:", code, "Body:", response.body:query()) - -- 娣诲姞瀵笻TTP鍝嶅簲涓虹┖鍊肩殑澶勭悊 - if not response or not response.body then - log.error("[excloud]getip璇锋眰澶辫触", "HTTP鍝嶅簲涓虹┖") - return false, "HTTP鍝嶅簲涓虹┖" - end - - local response_body = response.body:query() - if not response_body or response_body == "" then - log.error("[excloud]getip璇锋眰澶辫触", "鍝嶅簲浣撲负绌") - return false, "鍝嶅簲浣撲负绌" - end - - log.info("[excloud]excloud.getip鍝嶅簲", "HTTP Code:", code, "Body:", response_body) - - -- 澶勭悊HTTP閿欒鐮 - if code ~= 200 then - log.info("[excloud]getip璇锋眰澶辫触", "HTTP Code:", code) - return false, "HTTP璇锋眰澶辫触: " .. tostring(code) - end - - -- 瑙ｆ瀽JSON鍝嶅簲锛屾坊鍔犲瑙ｆ瀽澶辫触鐨勫鐞 - local response_json = json.decode(response_body) - if not response_json then - return false, "JSON瑙ｆ瀽澶辫触: " .. tostring(err) - end - - -- 妫鏌ユ湇鍔″櫒杩斿洖鐘舵 - if not response_json.msg then - log.error("[excloud]getip鍝嶅簲鏍煎紡閿欒", "缂哄皯msg瀛楁") - return false, "鏈嶅姟鍣ㄥ搷搴旀牸寮忛敊璇: 缂哄皯msg瀛楁" - end - - if response_json.msg ~= "ok" then - log.error("[excloud]鏈嶅姟鍣ㄨ繑鍥為敊璇", "娑堟伅:", response_json.msg) - return false, "鏈嶅姟鍣ㄨ繑鍥為敊璇: " .. tostring(response_json.msg) - end - - - if getip_type >= 3 and getip_type <= 5 then - -- AirCloud涓氬姟 - if response_json.conninfo then - config.current_conninfo = response_json.conninfo - - -- 鏍规嵁杩炴帴绫诲瀷澶勭悊涓嶅悓鐨勮繛鎺ヤ俊鎭 - if getip_type == 5 then -- MQTT杩炴帴 - log.info("[excloud]鑾峰彇鍒癕QTT杩炴帴淇℃伅", - "host:", response_json.conninfo.ssl, - "port:", response_json.conninfo.port, - "username:", response_json.conninfo.username, - "password:", response_json.conninfo.password) - log.info("[excloud]瀹為檯MQTT杩炴帴灏嗕娇鐢ㄨ澶囦俊鎭:", - "client_id:", mobile.imei(), - "username:", mobile.imei(), - "password:", mobile.muid()) - else -- TCP/UDP杩炴帴 - log.info("[excloud]鑾峰彇鍒癟CP/UDP杩炴帴淇℃伅", - "host:", response_json.conninfo.ipv4, - "port:", response_json.conninfo.port) - end - else - log.warn("[excloud]鏈幏鍙栧埌杩炴帴淇℃伅") - end - - if response_json.imginfo then - config.current_imginfo = response_json.imginfo - log.info("[excloud]鑾峰彇鍒板浘鐗囦笂浼犱俊鎭") - else - log.warn("[excloud]鏈幏鍙栧埌鍥剧墖涓婁紶淇℃伅") - end - - if response_json.audinfo then - config.current_audinfo = response_json.audinfo - log.info("[excloud]鑾峰彇鍒伴煶棰戜笂浼犱俊鎭") - else - log.warn("[excloud]鏈幏鍙栧埌闊抽涓婁紶淇℃伅") - end - -- 鏂板锛氳繍缁存棩蹇椾笂浼犱俊鎭 (mtninfo) - if response_json.mtninfo then - config.current_mtninfo = response_json.mtninfo - log.info("[excloud]鑾峰彇鍒拌繍缁存棩蹇椾笂浼犱俊鎭") - else - log.warn("[excloud]鏈幏鍙栧埌杩愮淮鏃ュ織涓婁紶淇℃伅") - end - end - - -- 濡傛灉鑾峰彇鍒拌繛鎺ヤ俊鎭紝鑷姩鏇存柊閰嶇疆 - if config.current_conninfo then - -- 鏍规嵁杩炴帴绫诲瀷璁剧疆涓嶅悓鐨勪富鏈哄瓧娈 - if getip_type == 5 then -- MQTT杩炴帴 - if config.current_conninfo.ssl then - config.host = config.current_conninfo.ssl - else - log.warn("[excloud]MQTT杩炴帴淇℃伅涓己灏慡SL鍩熷悕") - end - else -- TCP/UDP杩炴帴 - if config.current_conninfo.ipv4 then - config.host = config.current_conninfo.ipv4 - else - log.warn("[excloud]TCP/UDP杩炴帴淇℃伅涓己灏慖P鍦板潃") - end - end - - if config.current_conninfo.port then - config.port = config.current_conninfo.port - else - log.warn("[excloud]杩炴帴淇℃伅涓己灏戠鍙ｅ彿") - end - - -- 鏇存柊MQTT璁よ瘉淇℃伅 - if getip_type == 5 then - if config.current_conninfo.username then - config.username = config.current_conninfo.username - end - if config.current_conninfo.password then - config.password = config.current_conninfo.password - end - end - - log.info("[excloud]excloud.getip", "鏇存柊閰嶇疆:", config.host, config.port) - else - log.warn("[excloud]鏈幏鍙栧埌鏈夋晥鐨勮繛鎺ヤ俊鎭紝灏嗕娇鐢ㄥ師鏈夐厤缃") - end - - return true, config.current_conninfo -end - --- 甯﹂噸璇曠殑getip璇锋眰 -function excloud.getip_with_retry(getip_type) - local retry_count = 0 - local max_retry = config.max_getip_retry or 3 - local success, result - - while retry_count < max_retry do - success, result = excloud.getip(getip_type) - if success and result then - log.info("[excloud]excloud.getip", "鎴愬姛:", success, "缁撴灉:", json.encode(result)) - config.getip_retry_count = 0 - return true, result - end - - retry_count = retry_count + 1 - config.getip_retry_count = retry_count - log.warn("excloud.getip閲嶈瘯", "娆℃暟:", retry_count, "閿欒:", result) - - if retry_count < max_retry then - sys.wait(5000) -- 绛夊緟5绉掑悗閲嶈瘯 - end - end - - return false, "getip璇锋眰澶辫触锛屽凡杈炬渶澶ч噸璇曟鏁: " .. (result or "鏈煡閿欒") -end - --- 鍙戦佹枃浠朵笂浼犲紑濮嬮氱煡 -local function send_file_upload_start(file_type, file_name, file_size) - -- 鏋勫缓瀛怲LV鏁版嵁 - -- local sub_tlvs = "" - - -- 鏂囦欢涓婁紶绫诲瀷瀛怲LV - -- local success, tlv_data = build_tlv(FIELD_MEANINGS.FILE_UPLOAD_TYPE, DATA_TYPES.INTEGER, file_type) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - - -- 鏂囦欢鍚嶇О瀛怲LV - -- success, tlv_data = build_tlv(FIELD_MEANINGS.FILE_NAME, DATA_TYPES.ASCII, file_name) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - - -- 鏂囦欢澶у皬瀛怲LV - -- success, tlv_data = build_tlv(FIELD_MEANINGS.FILE_SIZE, DATA_TYPES.INTEGER, file_size) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - local sub_tlvs = 0 - -- 涓籘LV锛堟枃浠朵笂浼犲紑濮嬮氱煡锛 - local message = { - { - field_meaning = FIELD_MEANINGS.FILE_UPLOAD_START, - data_type = DATA_TYPES.INTEGER, - value = sub_tlvs -- 瀛怲LV鏁版嵁浣滀负浜岃繘鍒跺 - }, - { - field_meaning = FIELD_MEANINGS.FILE_UPLOAD_TYPE, - data_type = DATA_TYPES.INTEGER, - value = file_type - }, - { - field_meaning = FIELD_MEANINGS.FILE_NAME, - data_type = DATA_TYPES.ASCII, - value = file_name - }, - { - field_meaning = FIELD_MEANINGS.FILE_SIZE, - data_type = DATA_TYPES.INTEGER, - value = file_size - } - } - - return excloud.send(message, false) -end - --- 鍙戦佹枃浠朵笂浼犲畬鎴愰氱煡 -local function send_file_upload_finish(file_type, file_name, file_success) - -- 鏋勫缓瀛怲LV鏁版嵁 - -- local sub_tlvs = "" - - -- -- 鏂囦欢涓婁紶绫诲瀷瀛怲LV - -- local success, tlv_data = build_tlv(FIELD_MEANINGS.FILE_UPLOAD_TYPE, DATA_TYPES.INTEGER, file_type) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - - -- 鏂囦欢鍚嶇О瀛怲LV - -- success, tlv_data = build_tlv(FIELD_MEANINGS.FILE_NAME, DATA_TYPES.ASCII, file_name) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - - -- 涓婁紶缁撴灉鐘舵佸瓙TLV - -- success, tlv_data = build_tlv(FIELD_MEANINGS.UPLOAD_RESULT_STATUS, DATA_TYPES.INTEGER, file_success and 0 or 1) - -- if success then - -- sub_tlvs = sub_tlvs .. tlv_data - -- end - local sub_tlvs = 0 - -- 涓籘LV锛堟枃浠朵笂浼犲畬鎴愰氱煡锛 - local message = { - - { - field_meaning = FIELD_MEANINGS.FILE_UPLOAD_FINISH, - data_type = DATA_TYPES.INTEGER, - value = sub_tlvs -- 瀛怲LV鏁版嵁浣滀负浜岃繘鍒跺 - }, - - { - field_meaning = FIELD_MEANINGS.FILE_UPLOAD_TYPE, - data_type = DATA_TYPES.INTEGER, - value = file_type - }, - - { - field_meaning = FIELD_MEANINGS.FILE_NAME, - data_type = DATA_TYPES.ASCII, - value = file_name - }, - - { - field_meaning = FIELD_MEANINGS.UPLOAD_RESULT_STATUS, - data_type = DATA_TYPES.INTEGER, - value = file_success and 0 or 1 - } - - } - - return excloud.send(message, false) -end - -local function upload_file(file_type, file_path, file_name) - local upload_info - if file_type == 1 then - upload_info = config.current_imginfo - elseif file_type == 2 then - upload_info = config.current_audinfo - elseif file_type == 3 then - upload_info = config.current_mtninfo -- 鏂板锛氳繍缁存棩蹇椾笂浼 - else - return false, "涓嶆敮鎸佺殑鏂囦欢绫诲瀷" - end - - if not upload_info then - return false, "鏈幏鍙栧埌涓婁紶閰嶇疆淇℃伅锛岃鍏堟墽琛実etip" - end - - if not upload_info.url then - return false, "涓婁紶URL涓虹┖" - end - local file_size = io.fileSize(file_path) - if not file_size or file_size == 0 then - log.info("[excloud]鏂囦欢涓嶅瓨鍦ㄦ垨涓虹┖", "鏂囦欢:", file_name,file_size) - return false, "鏂囦欢涓嶅瓨鍦ㄦ垨涓虹┖" - end - - log.info("[excloud]寮濮嬫枃浠朵笂浼", "绫诲瀷:", file_type, "鏂囦欢:", file_path, "澶у皬:", file_size) - log.info("[excloud]寮濮嬫枃浠朵笂浼", "绫诲瀷:", file_type, "鏂囦欢:", file_name, "澶у皬:", file_size) - - -- 鍙戦佷笂浼犲紑濮嬮氱煡锛堣繍缁存棩蹇椾笉闇瑕侊級 - if file_type ~= 3 then - local ok, err = send_file_upload_start(file_type, file_name, file_size) - if not ok then - log.warn("鍙戦佷笂浼犲紑濮嬮氱煡澶辫触", err) - end - end - - -- 鎵цHTTP璇锋眰锛屾坊鍔犻噸浼犳満鍒 - local max_retries = 1 - local retry_count = 0 - local code, headers, body - local upload_success = false - local result_msg = "" - - while retry_count <= max_retries do - -- 鏋勫缓multipart/form-data璇锋眰浣 - local forms = { ["key"] = upload_info.data_param.key } - local files = { [upload_info.data_key or "f"] = file_path } - local request_body, boundary = build_multipart_form_data(forms, files) - - -- 鏋勫缓璇锋眰澶 - local headers = { - ["Content-Type"] = "multipart/form-data; boundary=" .. boundary, - ["Content-Length"] = tostring(#request_body) - } - - -- 鍙戦丠TTP璇锋眰 - log.info("[excloud]寮濮嬪彂閫丠TTP璇锋眰", "URL:", upload_info.url) - code, headers, body = http.request("POST", upload_info.url, headers, request_body, {timeout=30000}).wait() - - -- 妫鏌ュ搷搴 - if code == 200 then - log.info("[excloud]excloud.getip鏂囦欢涓婁紶鍝嶅簲", "HTTP Code:", code, "Body:", body and (#body > 512 and #body or body) or "nil") - - local resp_data, err = json.decode(body) - if resp_data and resp_data.code == 0 then - upload_success = true - result_msg = "涓婁紶鎴愬姛" - log.info("[excloud]鏂囦欢涓婁紶鎴愬姛", "URL:", resp_data.value and resp_data.value.uri or "鏈煡") - break - else - result_msg = "鏈嶅姟鍣ㄨ繑鍥為敊璇: " .. (resp_data and tostring(resp_data.code) or "鏈煡") - log.error("鏂囦欢涓婁紶澶辫触", result_msg, "鍝嶅簲:", body) - end - else - result_msg = "HTTP璇锋眰澶辫触: " .. tostring(code) - log.error("鏂囦欢涓婁紶HTTP璇锋眰澶辫触", result_msg, "Headers:", headers, "Body:", body) - end - - -- 濡傛灉澶辫触涓旀湭杈惧埌鏈澶ч噸璇曟鏁帮紝鍒欓噸璇 - if not upload_success and retry_count < max_retries then - retry_count = retry_count + 1 - log.info("[excloud]鏂囦欢涓婁紶澶辫触锛屽紑濮嬬" .. retry_count .. "娆￠噸璇") - sys.wait(1000) -- 绛夊緟1绉掑悗閲嶈瘯 - else - break - end - end - - -- 鍙戦佷笂浼犲畬鎴愰氱煡锛堣繍缁存棩蹇椾笉闇瑕侊級 - if file_type ~= 3 then - local notify_ok, notify_err = send_file_upload_finish(file_type, file_name, upload_success) - if not notify_ok then - log.warn("鍙戦佷笂浼犲畬鎴愰氱煡澶辫触", notify_err) - end - end - - return upload_success, result_msg -end - --- 杩愮淮鏃ュ織涓婁紶鎺ュ彛 -function excloud.upload_mtnlog(file_path, file_name) - -- 鍒ゆ柇鏄惁鏄墜鍔ㄥ～鍐橧P锛屼笉鏄痝etip鐨勮瘽锛屼笉鍏佽涓婁紶鏂囦欢 - if not config.use_getip then - log.warn("[excloud]鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶鏂囦欢") - return false, "鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶鏂囦欢" - end - - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if not io.exists(file_path) then - return false, "鏂囦欢涓嶅瓨鍦: " .. file_path - end - log.info("[excloud]excloud.upload_mtnlog", "鏂囦欢璺緞:", file_path, "鏂囦欢鍚:", file_name) - -- 濡傛灉娌℃湁鏂囦欢涓婁紶閰嶇疆锛屽厛鑾峰彇 - if not config.current_mtninfo then - log.info("[excloud]鑾峰彇杩愮淮鏃ュ織涓婁紶閰嶇疆...") - local getip_type = config.transport == "tcp" and 3 or - config.transport == "udp" and 4 or - config.transport == "mqtt" and 5 or 3 - - - local ok, err = excloud.getip_with_retry(getip_type) - if not ok then - return false, "鑾峰彇杩愮淮鏃ュ織涓婁紶閰嶇疆澶辫触: " .. err - end - end - log.info("[excloud]excloud.upload_mtnlog", "鏂囦欢璺緞:", file_path, "鏂囦欢鍚:", file_name) - return upload_file(3, file_path, file_name) -- 鏂囦欢绫诲瀷涓3 -end - --- 鍥剧墖涓婁紶鎺ュ彛 -function excloud.upload_image(file_path, file_name) - -- 鍒ゆ柇鏄惁鏄墜鍔ㄥ～鍐橧P锛屼笉鏄痝etip鐨勮瘽锛屼笉鍏佽涓婁紶鏂囦欢 - if not config.use_getip then - log.warn("[excloud]鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶鍥剧墖鏂囦欢") - return false, "鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶鍥剧墖鏂囦欢" - end - if not io.exists(file_path) then - return false, "鏂囦欢涓嶅瓨鍦: " .. file_path - end - -- 娌℃湁杩炴帴鏃剁洿鎺ラ鍑 - if not is_connected then - return false, "娌℃湁杩炴帴鍒版湇鍔″櫒" - end - file_name = file_name or "image_" .. os.time() .. ".jpg" - - -- 濡傛灉娌℃湁鍥剧墖涓婁紶閰嶇疆锛屽厛鑾峰彇 - if not config.current_imginfo then - log.info("[excloud]excloud.upload_image", "鑾峰彇鍥剧墖涓婁紶閰嶇疆...") - local getip_type = config.transport == "tcp" and 3 or - config.transport == "udp" and 4 or - config.transport == "mqtt" and 5 or 3 - local ok, err = excloud.getip_with_retry(getip_type) - if not ok then - return false, "鑾峰彇鍥剧墖涓婁紶閰嶇疆澶辫触: " .. err - end - end - - return upload_file(1, file_path, file_name) -end - --- 闊抽涓婁紶鎺ュ彛 -function excloud.upload_audio(file_path, file_name) - -- 鍒ゆ柇鏄惁鏄墜鍔ㄥ～鍐橧P锛屼笉鏄痝etip鐨勮瘽锛屼笉鍏佽涓婁紶鏂囦欢 - if not config.use_getip then - log.warn("[excloud]鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶闊抽鏂囦欢") - return false, "鎵嬪姩濉啓IP鏃朵笉鍏佽涓婁紶闊抽鏂囦欢" - end - if not io.exists(file_path) then - return false, "鏂囦欢涓嶅瓨鍦: " .. file_path - end - -- 娌℃湁杩炴帴鏃剁洿鎺ラ鍑 - if not is_connected then - return false, "娌℃湁杩炴帴鍒版湇鍔″櫒" - end - file_name = file_name or "audio_" .. os.time() .. ".mp3" - - -- 濡傛灉娌℃湁闊抽涓婁紶閰嶇疆锛屽厛鑾峰彇 - if not config.current_audinfo then - log.info("[excloud]excloud.upload_audio", "鑾峰彇闊抽涓婁紶閰嶇疆...") - local getip_type = config.transport == "tcp" and 3 or - config.transport == "udp" and 4 or - config.transport == "mqtt" and 5 or 3 - local ok, err = excloud.getip_with_retry(getip_type) - if not ok then - return false, "鑾峰彇闊抽涓婁紶閰嶇疆澶辫触: " .. err - end - end - - return upload_file(2, file_path, file_name) -end - --- 璁板綍杩愮淮鏃ュ織 ---[[ -杈撳嚭杩愮淮鏃ュ織骞跺啓鍏ユ枃浠 -@api excloud.mtn_log(level, tag, ...) -@string level 鏃ュ織绾у埆锛屽繀椤绘槸 "info", "warn", 鎴 "error" -@string tag 鏃ュ織鏍囪瘑锛屽繀椤绘槸瀛楃涓 -@... 闇鎵撳嵃鐨勫弬鏁 -@return boolean 鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage -excloud.mtn_log("info", "message", 123) -excloud.mtn_log("warn", "message", 456) -excloud.mtn_log("error", "message", 789) -]] -function excloud.mtn_log(level, tag, ...) - if not config.mtn_log_enabled then - return false, "杩愮淮鏃ュ織鍔熻兘宸茬鐢" -- 绂佺敤鏃惰繑鍥炲け璐 - end - exmtn.log(level, tag, ...) - return true -end - --- 鑾峰彇杩愮淮鏃ュ織鐘舵 -function excloud.get_mtn_log_status() - if not config.mtn_log_enabled then - return { - enabled = false, - message = "杩愮淮鏃ュ織鍔熻兘宸茬鐢" - } - end - - local config_info = exmtn.get_config() - local log_files = scan_mtn_log_files() - local total_size = 0 - - for _, file in ipairs(log_files) do - total_size = total_size + file.size - end - - return { - enabled = true, - config = config_info, - file_count = #log_files, - total_size = total_size, - files = log_files, - last_error = exmtn.get_last_error() - } -end - --- 閲嶈繛 -local function schedule_reconnect() - -- 妫鏌ユ槸鍚﹀凡缁忓叧闂湇鍔 - if not is_open then - log.info("[excloud]鏈嶅姟宸插叧闂紝鍋滄閲嶈繛") - return - end - - -- 妫鏌ユ槸鍚﹁揪鍒版渶澶ч噸杩炴鏁 - if reconnect_count >= config.max_reconnect then - log.info("[excloud]鍒拌揪鏈澶ч噸杩炴鏁 " .. reconnect_count .. "/" .. config.max_reconnect) - - -- 浣跨敤鍗忕▼鎵ц澶嶆潅鐨勯噸杩為昏緫 - sys.taskInit(function() - -- 鎵ц绱фュ唴瀛樻竻鐞 - collectgarbage("collect") - pending_messages = {} - - -- 鏍规嵁use_getip鍐冲畾鏄惁閲嶆柊鑾峰彇鏈嶅姟鍣ㄤ俊鎭 - if config.use_getip then - log.info("[excloud]TCP杩炴帴澶氭澶辫触锛岄噸鏂拌幏鍙栨湇鍔″櫒淇℃伅...") - local getip_type = config.transport == "tcp" and 3 or - config.transport == "udp" and 4 or - config.transport == "mqtt" and 5 or 3 - - -- 娓呴櫎褰撳墠杩炴帴淇℃伅锛屽己鍒堕噸鏂拌幏鍙 - config.current_conninfo = nil - - local ok, result = excloud.getip_with_retry(getip_type) - if ok then - log.info("[excloud]閲嶆柊鑾峰彇鏈嶅姟鍣ㄤ俊鎭垚鍔燂紝閲嶇疆閲嶈繛璁℃暟", - "host:", config.host, - "port:", config.port, - "transport:", config.transport) - - -- 閲嶇疆閲嶈繛璁℃暟 - reconnect_count = 0 - - -- 浣跨敤鏂扮殑鏈嶅姟鍣ㄤ俊鎭噸鏂拌繛鎺ワ紙鍏堝叧闂啀鎵撳紑锛 - excloud.close() -- 纭繚瀹屽叏鍏抽棴 - sys.wait(200) -- 鍦ㄥ崗绋嬩腑鍙互瀹夊叏浣跨敤 wait - excloud.open() -- 閲嶆柊鎵撳紑 - else - log.error("[excloud]閲嶆柊鑾峰彇鏈嶅姟鍣ㄤ俊鎭け璐ワ紝鍋滄閲嶈繛") - if callback_func then - callback_func("reconnect_failed", { - count = reconnect_count, - max_reconnect = config.max_reconnect, - getip_failed = true - }) - end - -- 褰诲簳鍋滄閲嶈繛 - is_open = false - end - else - -- 涓嶄娇鐢╣etip锛岀洿鎺ュ仠姝㈤噸杩 - log.info("[excloud]杈惧埌鏈澶ч噸杩炴鏁帮紝鍋滄閲嶈繛") - if callback_func then - callback_func("reconnect_failed", { - count = reconnect_count, - max_reconnect = config.max_reconnect - }) - end - is_open = false - end - end) - return - end - - -- 澧炲姞閲嶈繛璁℃暟 - reconnect_count = reconnect_count + 1 - log.info("[excloud]瀹夋帓绗 " .. - reconnect_count .. "/" .. config.max_reconnect .. " 娆￠噸杩烇紝绛夊緟 " .. config.reconnect_interval .. " 绉") - - -- 浣跨敤瀹氭椂鍣ㄥ畨鎺掗噸杩烇紝鍦ㄥ崗绋嬩腑鎵ц - reconnect_timer = sys.timerStart(function() - sys.taskInit(function() - log.info("[excloud]鎵ц绗 " .. reconnect_count .. "/" .. config.max_reconnect .. " 娆￠噸杩") - - -- 鍦ㄩ噸杩炲墠妫鏌ユ湇鍔＄姸鎬 - if not is_open then - log.info("[excloud]鏈嶅姟宸插叧闂紝鍙栨秷閲嶈繛") - return - end - - -- 鍏堟墽琛屽唴瀛樻竻鐞 - collectgarbage("collect") - - -- 濡傛灉杩炴帴瀵硅薄瀛樺湪浣嗚繛鎺ュ凡鏂紑锛屽厛娓呯悊 - if connection and not is_connected then - log.info("[excloud]娓呯悊娈嬬暀鐨勮繛鎺ュ璞") - if config.transport == "tcp" then - socket.close(connection) - socket.release(connection) - elseif config.transport == "mqtt" then - connection:disconnect() - connection:close() - end - connection = nil - sys.wait(50) -- 鍦ㄥ崗绋嬩腑瀹夊叏绛夊緟 - end - - -- 閲嶇疆杩炴帴鐘舵佷絾淇濇寔鏈嶅姟寮鍚姸鎬 - is_connected = false - is_authenticated = false - - -- 鎵ц閲嶈繛 - local success, err = excloud.open() - if not success then - log.error("[excloud]閲嶈繛澶辫触:", err) - -- 閲嶈繛澶辫触浼氬啀娆¤Е鍙憇chedule_reconnect - else - log.info("[excloud]閲嶈繛鎿嶄綔宸插彂璧") - end - end) - end, config.reconnect_interval * 1000) -end - --- TCP socket浜嬩欢鍥炶皟鍑芥暟 -local function tcp_socket_callback(netc, event, param) - log.info("[excloud]socket cb", netc, event, param) - -- 鍙栨秷杩炴帴瓒呮椂瀹氭椂鍣 - if connect_timeout_timer then - sys.timerStop(connect_timeout_timer) - connect_timeout_timer = nil - end - - -- 璁板綍杩炴帴鐘舵佸彉鍖栫殑杩愮淮鏃ュ織 - if config.aircloud_mtn_log_enabled then - if event == socket.LINK then - exmtn.log("info", "aircloud", "net_conn", "缃戠粶杩炴帴鎴愬姛") - elseif event == socket.ON_LINE then - exmtn.log("info", "aircloud", "net_conn", "TCP杩炴帴鎴愬姛", "host", config.host, "port", config.port) - elseif event == socket.CLOSED then - exmtn.log("info", "aircloud", "net_conn", "TCP杩炴帴鏂紑", "param", param) - end - end - - if param ~= 0 then - log.info("[excloud]socket", "杩炴帴鏂紑") - is_connected = false - is_authenticated = false - - if callback_func then - callback_func("disconnect", {}) - end - -- 杩炴帴鏂紑锛岄噴鏀捐祫婧 - socket.release(connection) - connection = nil - - -- 灏濊瘯閲嶈繛 - if config.auto_reconnect and is_open then - -- is_open = false - schedule_reconnect() - end - return - end - if event == socket.LINK then - -- 缃戠粶杩炴帴鎴愬姛 - log.info("[excloud]socket", "缃戠粶杩炴帴鎴愬姛") - elseif event == socket.ON_LINE then - -- TCP杩炴帴鎴愬姛 - log.info("[excloud]socket", "TCP杩炴帴鎴愬姛") - is_connected = true - - -- 閲嶇疆閲嶈繛璁℃暟锛屽鏋滄槸閲嶈繛鐨勮瘽锛岃繛鎺ヤ笂鏈嶅姟鍣ㄧ粰閲嶈繛璁℃暟閲嶇疆涓0 - reconnect_count = 0 - if callback_func then - callback_func("connect_result", { success = true }) - end - -- 鍙戦佽璇佽姹 - send_auth_request() - elseif event == socket.EVENT then - -- 鏈夋暟鎹埌杈 - socket.rx(netc, rxbuff) - if rxbuff:used() > 0 then - local data = rxbuff:query() - log.info("[excloud]socket", "鏀跺埌鏁版嵁", #data, "瀛楄妭", data:toHex()) - -- 澶勭悊鎺ユ敹鍒扮殑鏁版嵁 - parse_data(data) - end - -- -- 娓呯┖缂撳啿鍖 - rxbuff:del() - elseif event == socket.TX_OK then - socket.wait(netc) - log.info("[excloud]socket", "鍙戦佸畬鎴") - elseif event == socket.CLOSED then - -- 杩炴帴閿欒鎴栧叧闂 - socket.release(connection) - connection = nil - log.info("[excloud]socket", "涓诲姩鏂紑閾炬帴") - end -end - --- mqtt client鐨勪簨浠跺洖璋冨嚱鏁 -local function mqtt_client_event_cbfunc(connected, event, data, payload, metas) - log.info("[excloud]mqtt_client_event_cbfunc", event, data, payload, json.encode(metas)) - -- 鍙栨秷杩炴帴瓒呮椂瀹氭椂鍣 - if connect_timeout_timer then - sys.timerStop(connect_timeout_timer) - connect_timeout_timer = nil - end - - -- 璁板綍MQTT鐘舵佸彉鍖栫殑杩愮淮鏃ュ織 - if config.aircloud_mtn_log_enabled then - if event == "conack" then - exmtn.log("info", "aircloud", "mqtt_conn", "MQTT杩炴帴鎴愬姛", "host", config.host) - elseif event == "disconnect" then - exmtn.log("info", "aircloud", "mqtt_conn", "MQTT杩炴帴鏂紑") - elseif event == "error" then - exmtn.log("info", "aircloud", "mqtt_error", "MQTT閿欒", "type", data, "code", payload) - end - end - - -- mqtt杩炴帴鎴愬姛 - if event == "conack" then - is_connected = true - log.info("[excloud]MQTT connected") - -- 閲嶇疆閲嶈繛璁℃暟锛屽鏋滄槸閲嶈繛鐨勮瘽锛岃繛鎺ヤ笂鏈嶅姟鍣ㄧ粰閲嶈繛璁℃暟閲嶇疆涓0 - reconnect_count = 0 - -- 璁㈤槄涓婚 - local device_id_hex = string.toHex(device_id_binary) - local auth_topic = "/AirCloud/down/" .. device_id_hex .. "/auth" - local all_topic = "/AirCloud/down/" .. device_id_hex .. "/all" - log.info("[excloud]mqtt_client_event_cbfunc", "璁㈤槄涓婚", auth_topic, all_topic) - connection:subscribe(auth_topic, 0) - connection:subscribe(all_topic, 0) - - if callback_func then - callback_func("connect_result", { success = true }) - end - -- 鍙戦佽璇佽姹 - send_auth_request() - - -- 璁㈤槄鎴愬姛 - elseif event == "suback" then - -- 鍙栨秷璁㈤槄鎴愬姛 - elseif event == "unsuback" then - -- 鎺ユ敹鍒版湇鍔″櫒涓嬪彂鐨刾ublish鏁版嵁 - -- data锛歴tring绫诲瀷锛岃〃绀簍opic - -- payload锛歴tring绫诲瀷锛岃〃绀簆ayload - -- metas锛歵able绫诲瀷锛屾暟鎹唴瀹瑰涓 - -- { - -- qos: number绫诲瀷锛屽彇鍊艰寖鍥0,1,2 - -- retain锛歯umber绫诲瀷锛屽彇鍊艰寖鍥0,1 - -- dup锛歯umber绫诲瀷锛屽彇鍊艰寖鍥0,1 - -- message_id: number绫诲瀷 - -- } - elseif event == "recv" then - log.info("[excloud]鎺ユ敹鍒癕QTT娑堟伅", - "涓婚:", data, - "鏁版嵁闀垮害:", #payload, - "QoS:", metas and metas.qos or "unknown", - "娑堟伅ID:", metas and metas.message_id or "unknown") - - -- 瀵规帴鏀跺埌鐨刾ublish鏁版嵁澶勭悊 - parse_data(payload) - - -- 鍙戦佹垚鍔焢ublish鏁版嵁 - -- data锛歯umber绫诲瀷锛岃〃绀簃essage id - elseif event == "sent" then - -- 鏈嶅姟鍣ㄦ柇寮mqtt杩炴帴 - elseif event == "disconnect" then - is_connected = false - is_authenticated = false - log.info("[excloud]MQTT disconnected") - - if callback_func then - callback_func("disconnect", {}) - end - - -- 灏濊瘯閲嶈繛 - if config.auto_reconnect and is_open then - -- is_open = false - schedule_reconnect() - end - - -- 鏀跺埌鏈嶅姟鍣ㄧ殑蹇冭烦搴旂瓟 - elseif event == "pong" then - -- 涓ラ噸寮傚父锛屾湰鍦颁細涓诲姩鏂紑杩炴帴 - -- data锛歴tring绫诲瀷锛岃〃绀哄叿浣撶殑寮傚父锛屾湁浠ヤ笅鍑犵锛 - -- "connect"锛歵cp杩炴帴澶辫触 - -- "tx"锛氭暟鎹彂閫佸け璐 - -- "conack"锛歮qtt connect鍚庯紝鏈嶅姟鍣ㄥ簲绛擟ONNACK閴存潈澶辫触锛屽け璐ョ爜涓簆ayload锛坣umber绫诲瀷锛 - -- "other"锛氬叾浠栧紓甯 - elseif event == "error" then - is_connected = false - is_authenticated = false - local error_msg = "Unknown MQTT error" - - if data == "connect" then - error_msg = "TCP connection failed" - -- 杩炴帴澶辫触锛屽簲璇ヨ冭檻閲嶆柊鑾峰彇鏈嶅姟鍣ㄤ俊鎭 - if reconnect_count >= config.max_reconnect and config.use_getip then - log.info("[excloud]MQTT杩炴帴澶氭澶辫触锛岄渶瑕侀噸鏂拌幏鍙栨湇鍔″櫒淇℃伅") - config.current_conninfo = nil - end - elseif data == "tx" then - error_msg = "Data transmission failed" - elseif data == "conack" then - error_msg = "MQTT authentication failed with code: " .. tostring(payload) - else - error_msg = "Other MQTT error: " .. tostring(data) - end - - log.info("[excloud]MQTT error: " .. error_msg) - - if callback_func then - callback_func("disconnect", { error = error_msg }) - end - -- 瀹夊叏閲婃斁杩炴帴璧勬簮 - if connection then - connection:disconnect() - connection:close() - connection = nil - end - -- 灏濊瘯閲嶈繛 - if config.auto_reconnect and is_open then - -- is_open = false - schedule_reconnect() - end - end -end - --- 璁剧疆閰嶇疆鍙傛暟 -function excloud.setup(params) - if is_open then - return false, "excloud is already open" - end - - -- 鍚堝苟閰嶇疆鍙傛暟 - for k, v in pairs(params) do - config[k] = v - end - - -- 楠岃瘉蹇呰鍙傛暟 - if not config.auth_key then - return false, "auth_key is required" - end - if config.device_type == 1 then - config.device_id = mobile.imei() - log.info("[excloud]4G璁惧", "IMEI:", config.device_id, "MUID:", mobile.muid()) - elseif config.device_type == 2 then - config.device_id = wlan.getMac(nil, true) - --浠ュお缃戣澶 - elseif config.device_type == 4 then - config.device_id = netdrv.mac(socket.LWIP_ETH) - elseif config.device_type == 9 then - -- 铏氭嫙璁惧锛氶獙璇佹墜鏈哄彿鍜屽簭鍒楀彿 - if not config.virtual_phone_number then - return false, "铏氭嫙璁惧闇瑕侀厤缃 virtual_phone_number" - end - - -- 楠岃瘉鎵嬫満鍙锋牸寮忥紙11浣嶆暟瀛楋級 - local phone_clean = config.virtual_phone_number:gsub("%D", "") - if #phone_clean ~= 11 then - return false, "铏氭嫙鎵嬫満鍙峰繀椤讳负11浣嶆暟瀛" - end - - -- 璁剧疆榛樿搴忓垪鍙凤紙濡傛灉鏈彁渚涳級 - if config.virtual_serial_num == nil then - config.virtual_serial_num = 0 - end - - -- 搴忓垪鍙疯寖鍥存鏌ワ紙0-999锛 - config.virtual_serial_num = config.virtual_serial_num % 1000 - - -- 鐢熸垚璁惧ID锛氭墜鏈哄彿 + 3浣嶅簭鍒楀彿 - local serial_str = string.format("%03d", config.virtual_serial_num) - config.device_id = phone_clean .. serial_str - - log.info("铏氭嫙璁惧閰嶇疆", "鎵嬫満鍙:", config.virtual_phone_number, "搴忓垪鍙:", serial_str, "璁惧ID:", config.device_id) - else - log.info("[excloud]鏈煡璁惧绫诲瀷", config.device_type) - config.device_id = "unknown" - end - - -- 鎵撳寘璁惧id - device_id_binary = packDeviceInfo(config.device_type, config.device_id) - - -- 鍒濆鍖栬繍缁存棩蹇楁ā鍧 - local mtn_ok, mtn_err = init_mtn_log() - if not mtn_ok then - log.warn("[excloud]杩愮淮鏃ュ織鍒濆鍖栧け璐ワ紝浣嗙户缁璭xcloud鍒濆鍖:", mtn_err) - end - - log.info("[excloud]excloud.setup", "鍒濆鍖栨垚鍔", "璁惧ID:", config.device_id) - return true -end - --- 娉ㄥ唽鍥炶皟鍑芥暟 -function excloud.on(cbfunc) - if type(cbfunc) ~= "function" then - return false, "Callback must be a function" - end - - callback_func = cbfunc - return true -end - --- 寮鍚痚xcloud鏈嶅姟 -function excloud.open() - -- 濡傛灉涔嬪墠杩炴帴寮傚父鏂紑锛屼絾鐘舵佹湭閲嶇疆锛屽厛娓呯悊 - if is_open and not is_connected then - log.warn("[excloud]妫娴嬪埌鐘舵佷笉涓鑷达紝鍏堟竻鐞嗘畫鐣欑姸鎬") - excloud.close() - end - -- 妫鏌ユ槸鍚﹀凡鎵撳紑 - if is_open and is_connected then - return false, "excloud is already open and connected" - end - reconnect_count = 0 - -- 鍒ゆ柇鏄惁鍒濆鍖 - if not device_id_binary then - return false, "excloud 娌℃湁鍒濆鍖栵紝璇峰厛璋冪敤setup" - end - - -- 鏍规嵁use_getip鍐冲畾鏄惁浣跨敤getip鏈嶅姟 - if config.use_getip then - -- 浣跨敤getip鏈嶅姟鍙戠幇 - local getip_type - if config.transport == "tcp" then - getip_type = 3 - elseif config.transport == "udp" then - getip_type = 4 - elseif config.transport == "mqtt" then - getip_type = 5 - else - return false, "涓嶆敮鎸佺殑浼犺緭鍗忚: " .. config.transport - end - - -- 鑾峰彇鏈嶅姟鍣ㄨ繛鎺ヤ俊鎭 - if not config.current_conninfo or (config.transport ~= "mqtt" and not config.current_conninfo.ipv4) or - (config.transport == "mqtt" and not config.current_conninfo.ssl) then - log.info("[excloud]棣栨杩炴帴锛岃幏鍙栨湇鍔″櫒淇℃伅...") - local ok, result = excloud.getip_with_retry(getip_type) - if not ok then - return false, "鑾峰彇鏈嶅姟鍣ㄤ俊鎭け璐: " .. result - end - - -- 鏇存柊杩炴帴閰嶇疆 - log.info("[excloud]鏈嶅姟鍣ㄤ俊鎭幏鍙栨垚鍔", "host:", config.host, "port:", config.port, "transport:", config.transport) - - -- 淇濆瓨鏂囦欢涓婁紶淇℃伅 - if result.imginfo then - config.current_imginfo = result.imginfo - end - if result.audinfo then - config.current_audinfo = result.audinfo - end - end - else - -- 涓嶄娇鐢╣etip锛岀洿鎺ヤ娇鐢ㄧ敤鎴烽厤缃殑host鍜宲ort - log.info("浣跨敤鎵嬪姩閰嶇疆鐨勬湇鍔″櫒鍦板潃", config.host, config.port) - if not config.host or not config.port then - return false, "use_getip涓篺alse鏃讹紝蹇呴』閰嶇疆host鍜宲ort" - end - end - - -- 鏍规嵁浼犺緭鍗忚鍒涘缓杩炴帴 - if config.transport == "tcp" then - -- 鍒涘缓鎺ユ敹缂撳啿鍖 - rxbuff = zbuff.create(2048) - -- 鍒涘缓TCP杩炴帴 - log.info("[excloud]鍒涘缓TCP杩炴帴") - connection = socket.create(nil, tcp_socket_callback) - if not connection then - return false, "Failed to create socket" - end - - -- 鍑嗗SSL閰嶇疆鍙傛暟 - local ssl_config = nil - if config.ssl then - if type(config.ssl) == "table" then - -- 浣跨敤璇︾粏鐨凷SL閰嶇疆 - ssl_config = config.ssl - else - -- 绠鍗曠殑SSL鍚敤 - ssl_config = true - end - end - - -- 閰嶇疆socket鍙傛暟 - local config_success = socket.config( - connection, - config.local_port, -- 鏈湴绔彛鍙 - false, -- 鏄惁鏄疷DP锛孴CP杩炴帴涓篺alse - ssl_config and true or false, -- 鏄惁鏄姞瀵嗕紶杈 - config.keep_idle, -- keepalive idle鏃堕棿 - config.keep_interval, -- keepalive 鎺㈡祴闂撮殧 - config.keep_cnt, -- keepalive 鎺㈡祴娆℃暟 - ssl_config and ssl_config.server_cert or nil, -- 鏈嶅姟鍣–A璇佷功 - ssl_config and ssl_config.client_cert or nil, -- 瀹㈡埛绔瘉涔 - ssl_config and ssl_config.client_key or nil, -- 瀹㈡埛绔閽 - ssl_config and ssl_config.client_password or nil -- 瀹㈡埛绔閽ュ彛浠 - ) - if not config_success then - socket.release(connection) - connection = nil - return false, "Socket config failed" - end - - socket.debug(connection, true) - - -- 璁剧疆杩炴帴瓒呮椂瀹氭椂鍣 - connect_timeout_timer = sys.timerStart(function() - if not is_connected then - log.error("TCP connection timeout") - if connection then - socket.close(connection) - socket.release(connection) - connection = nil - end - - if callback_func then - callback_func("connect_result", { success = false, error = "Connection timeout" }) - end - - -- 灏濊瘯閲嶈繛 - if config.auto_reconnect and is_open then - -- is_open = false - schedule_reconnect() - end - end - end, config.timeout * 1000) - - -- 杩炴帴鍒版湇鍔″櫒 - local ok, result = socket.connect(connection, config.host, config.port, config.mqtt_ipv6) - log.info("[excloud]TCP杩炴帴缁撴灉", ok, result) - if not ok then - --鍙戠敓寮傚父锛屽己鍒禼lose - socket.close(connection) - --閲婃斁璧勬簮 - socket.release(connection) - connection = nil - - if config.auto_reconnect then - is_open = false - schedule_reconnect() - end - return false, result - end - elseif config.transport == "mqtt" then - -- 鍑嗗MQTT SSL閰嶇疆 - MQTT杩炴帴榛樿浣跨敤SSL鍔犲瘑 - local ssl_config = true -- 鏈绠鍗曠殑SSL鍔犲瘑锛屼笉楠岃瘉鏈嶅姟鍣ㄨ瘉涔 - - -- 濡傛灉鏈夎缁嗙殑SSL閰嶇疆锛屼娇鐢ㄨ缁嗛厤缃 - if config.ssl and type(config.ssl) == "table" then - ssl_config = config.ssl - end - - -- 鍑嗗MQTT鎵╁睍鍙傛暟 - local mqtt_opts = { - rxSize = config.mqtt_rx_size or 32 * 1024, -- MQTT鎺ユ敹缂撳啿鍖哄ぇ灏忥紝榛樿32K - conn_timeout = config.mqtt_conn_timeout or 30, -- MQTT杩炴帴瓒呮椂鏃堕棿锛岄粯璁30绉 - ipv6 = config.mqtt_ipv6 or false -- 鏄惁浣跨敤IPv6杩炴帴锛岄粯璁alse - } - - -- 鍒涘缓MQTT瀹㈡埛绔 - connection = mqtt.create(nil, config.host, config.port, ssl_config, mqtt_opts) - if not connection then - return false, "Failed to create MQTT client" - end - - -- 寮鍚皟璇曚俊鎭紙鍙夛級 - if config.debug then - connection:debug(true) - end - - -- 璁剧疆鐪熷疄鐨凪QTT璁よ瘉淇℃伅 - local client_id, username, password - - if config.device_type == 1 then -- 4G璁惧 - client_id = mobile.imei() - username = mobile.imei() - password = mobile.muid() - -- elseif config.device_type == 2 then -- WIFI璁惧 - -- client_id = wlan.getMac(nil, true) - -- username = wlan.getMac(nil, true) - -- password = mobile.muid():toHex() - -- elseif config.device_type == 4 then -- 浠ュお缃戣澶 - -- client_id = netdrv.mac(socket.LWIP_ETH) - -- username = netdrv.mac(socket.LWIP_ETH) - -- password = mobile.muid():toHex() - -- elseif config.device_type == 9 then -- 铏氭嫙璁惧 - -- -- 铏氭嫙璁惧浣跨敤閰嶇疆鐨勮澶嘔D - -- client_id = config.device_id - -- username = config.device_id - -- password = config.auth_key or config.device_id - else - return false, "MQTT connect failed, device_type not supported" - end - - log.info("[excloud]MQTT璁よ瘉淇℃伅", - "client_id:", client_id, - "username:", username, - "password:", password) - - -- 璁剧疆璁よ瘉淇℃伅锛堜娇鐢ㄧ湡瀹炵殑璁惧淇℃伅锛岃屼笉鏄痝etip杩斿洖鐨勬彁绀猴級 - connection:auth(client_id, username, password, config.clean_session) - - -- 璁剧疆淇濇寔杩炴帴闂撮殧 - connection:keepalive(config.keepalive or 240) -- 榛樿240绉 - - -- 璁剧疆閬楀槺娑堟伅锛堝鏋滈渶瑕侊級 - if config.will_topic and config.will_payload then - local will_result = connection:will( - config.will_topic, - config.will_payload, - config.will_qos or 0, - config.will_retain or 0 - ) - if not will_result then - log.warn("[excloud]璁剧疆閬楀槺娑堟伅澶辫触") - end - end - - -- 璁剧疆鑷姩閲嶈繛 - if config.auto_reconnect then - connection:autoreconn(true, (config.reconnect_interval or 10) * 1000) -- 杞崲涓烘绉 - end - - -- 娉ㄥ唽浜嬩欢鍥炶皟 - connection:on(mqtt_client_event_cbfunc) - - -- 璁剧疆杩炴帴瓒呮椂瀹氭椂鍣 - connect_timeout_timer = sys.timerStart(function() - if not is_connected then - log.error("MQTT connection timeout") - if connection then - connection:disconnect() - connection:close() - connection = nil - end - - if callback_func then - callback_func("connect_result", { success = false, error = "Connection timeout" }) - end - - -- 灏濊瘯閲嶈繛 - if config.auto_reconnect and is_open then - -- is_open = false - schedule_reconnect() - end - end - end, config.timeout * 1000) - - -- 杩炴帴鍒版湇鍔″櫒 - local ok = connection:connect() - if not ok then - --杩炴帴澶辫触锛岄噴鏀捐祫婧 - connection:close() - connection = nil - -- 鍙戣捣杩炴帴澶辫触锛屽皾璇曢噸杩 - if config.auto_reconnect then - is_open = false - schedule_reconnect() - end - return false, "MQTT connect failed" - end - else - return false, "Unsupported transport: " .. config.transport - end - - is_open = true - - - -- 璁板綍鏈嶅姟鍚姩鏃ュ織 - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "system", "excloud鏈嶅姟鍚姩", "transport", config.transport, "host", config.host, "port", - config.port) - end - - log.info("[excloud]excloud service started") - - return true -end - --- 鍙戦佹暟鎹 --- 鍙戦佹秷鎭埌浜戠 --- @param data table 寰呭彂閫佺殑鏁版嵁锛屾瘡涓厓绱犳槸涓涓寘鍚 field_meaning銆乨ata_type 鍜 value 鐨勮〃 --- @param need_reply boolean 鏄惁闇瑕佹湇鍔″櫒鍥炲锛岄粯璁や负 false --- @param is_auth_msg boolean 鏄惁鏄壌鏉冩秷鎭紝榛樿涓 false -function excloud.send(data, need_reply, is_auth_msg) - if not is_open then - return false, "excloud鏈嶅姟鏈紑鍚" - end - - if not is_connected then - return false, "鏈繛鎺ュ埌鏈嶅姟鍣" - end - - -- if not is_authenticated and not is_auth_msg then - -- return false, "璁惧鏈璇" - -- end - -- 妫鏌ュ弬鏁版槸鍚︿负table - if type(data) ~= "table" then - return false, "data must be table" - end - if need_reply == nil then - need_reply = false - end - if is_auth_msg == nil then - is_auth_msg = false - end - -- 妫鏌ユ湇鍔℃槸鍚﹀紑鍚 - if not is_open then - if callback_func then - callback_func("send_result", { - success = false, - error_msg = "excloud not open" - }) - end - return false, "excloud not open" - end - - -- 妫鏌ユ槸鍚﹀凡杩炴帴 - if not is_connected then - if callback_func then - callback_func("send_result", { - success = false, - error_msg = "excloud not connected" - }) - end - return false, "excloud not connected" - end - - -- 淇濆瓨褰撳墠搴忓垪鍙风敤浜庡洖璋 - local current_sequence = sequence_num - -- 鏋勫缓娑堟伅浣 - local message_body = "" - local parts = {} - for _, item in ipairs(data) do - log.info("[excloud]鏋勫缓鍙戦佹暟鎹", item.field_meaning, item.data_type, item.value, message_body) - local success, tlv = build_tlv(item.field_meaning, item.data_type, item.value) - if not success then - return false, "excloud.send data is failed" - end - table.insert(parts, tlv) - -- message_body = message_body .. tlv - end - if #parts > 0 then - message_body = table.concat(parts) - parts = {} - else - log.warn("[excloud]娌℃湁鏈夋晥鐨凾LV鏁版嵁鍙彂閫") - -- return false, "No valid TLV data to send" - end - - -- 妫鏌ユ秷鎭暱搴 - local udp_auth_key = config.udp_auth_key and true or false - local total_length = #message_body + (udp_auth_key and 64 or 0) - - log.info("[excloud]tlv鍙戦佹暟鎹暱搴4", total_length) - - -- 鏋勫缓娑堟伅澶 - local is_udp_transport = (config.transport == "udp") - local header = build_header(need_reply, is_udp_transport, total_length) - - -- -- 娣诲姞閴存潈key锛堝鏋滄槸UDP鐨勮瘽锛 - local auth_key_part = "" - if config.transport == "udp" and udp_auth_key then - auth_key_part = config.udp_auth_key - if #auth_key_part < 64 then - auth_key_part = auth_key_part .. string.rep("\0", 64 - #auth_key_part) - elseif #auth_key_part > 64 then - auth_key_part = auth_key_part:sub(1, 64) - end - end - local full_message - -- 鍙戦佸畬鏁存秷鎭 - if config.transport == "udp" then - full_message = header .. auth_key_part .. message_body - else - full_message = header .. message_body - end - - log.info("[excloud]鍙戦佹秷鎭暱搴", #header, #message_body, #full_message, full_message:toHex()) - - local success, err_msg - if config.transport == "tcp" then - if not connection then - err_msg = "TCP connection not available" - success = false - else - success, err_msg = socket.tx(connection, full_message) - end - elseif config.transport == "mqtt" then - -- 鏍规嵁鏄惁涓洪壌鏉冩秷鎭夋嫨涓嶅悓鐨則opic - local topic - local device_id_hex = string.toHex(device_id_binary) - if is_auth_msg then - topic = "/AirCloud/up/" .. device_id_hex .. "/auth" - else - topic = "/AirCloud/up/" .. device_id_hex .. "/all" - end - log.info("[excloud]鍙戝竷涓婚", topic, #full_message, full_message:toHex()) - local message_id = connection:publish(topic, full_message, config.qos, config.retain) - if message_id then - success = true - if config.qos and config.qos > 0 then - log.info("[excloud]MQTT娑堟伅鍙戝竷鎴愬姛", "娑堟伅ID:", message_id) - else - log.info("[excloud]MQTT娑堟伅鍙戝竷鎴愬姛") - end - else - success = false - err_msg = "MQTT publish failed" - end - end - - -- 閫氳繃鍥炶皟杩斿洖鍙戦佺粨鏋 - if callback_func then - callback_func("send_result", { - success = success, - error_msg = success and "Send successful" or err_msg, - sequence_num = current_sequence - }) - end - collectgarbage("collect") - if success then - log.info("[excloud]鏁版嵁鍙戦佹垚鍔", #full_message, "瀛楄妭") - return true - else - log.error("鏁版嵁鍙戦佸け璐", err_msg) - return false, err_msg - end -end - --- 鍏抽棴excloud鏈嶅姟 -function excloud.close() - if not is_open then - return false, "excloud not open" - end - - -- 鍋滄鎵鏈夊畾鏃跺櫒 - if reconnect_timer then - sys.timerStop(reconnect_timer) - reconnect_timer = nil - end - if connect_timeout_timer then - sys.timerStop(connect_timeout_timer) - connect_timeout_timer = nil - end - -- 鍋滄蹇冭烦 - excloud.stop_heartbeat() - -- 鍏抽棴杩炴帴 - if connection then - if config.transport == "tcp" then - socket.close(connection) - socket.release(connection) - elseif config.transport == "mqtt" then - -- 鏂紑杩炴帴骞堕噴鏀捐祫婧 - connection:disconnect() - connection:close() - end - connection = nil - end - -- 閲婃斁缂撳啿鍖 - if rxbuff then - rxbuff = nil - end - -- 娓呯┖闃熷垪 - pending_messages = {} - callback_func = nil - -- 璁板綍鏈嶅姟鍏抽棴鏃ュ織 - if config.aircloud_mtn_log_enabled then - exmtn.log("info", "aircloud", "system", "excloud鏈嶅姟鍏抽棴") - end - - -- 閲嶇疆鐘舵 - is_open = false - is_connected = false - is_authenticated = false - pending_messages = {} - rxbuff = nil - reconnect_count = 0 - is_heartbeat_running = false - collectgarbage("collect") - log.info("[excloud]excloud service stopped") - return true -end - --- 鑾峰彇褰撳墠鐘舵 -function excloud.status() - return { - is_open = is_open, - is_connected = is_connected, - is_authenticated = is_authenticated, - sequence_num = sequence_num, - reconnect_count = reconnect_count, - pending_messages = #pending_messages, - } -end - --- 鍙戦佸績璺虫秷鎭 --- @param custom_data table 鍙夊弬鏁帮紝鑷畾涔夊績璺冲唴瀹 --- @param need_reply boolean 鏄惁闇瑕佹湇鍔″櫒鍥炲锛岄粯璁や负false --- @return boolean 鏄惁鍙戦佹垚鍔 --- @return string 閿欒淇℃伅锛堝鏋滃け璐ワ級 -function excloud.heartbeat(custom_data, need_reply) - -- 濡傛灉蹇冭烦鏁版嵁鏈彁渚涳紝鍒欎娇鐢ㄩ粯璁ょ殑蹇冭烦鏁版嵁锛堢┖琛級 - local data = custom_data or heartbeat_data - - -- 璁剧疆榛樿涓嶉渶瑕佸洖澶 - if need_reply == nil then - need_reply = false - end - - -- 璋冪敤send鍑芥暟鍙戦佸績璺虫暟鎹 - return excloud.send(data, need_reply, false) -end - --- 鍚姩鑷姩蹇冭烦 --- @param interval number 蹇冭烦闂撮殧(绉)锛岄粯璁300绉(5鍒嗛挓) --- @param custom_data table 鑷畾涔夊績璺冲唴瀹癸紝榛樿绌鸿〃 --- @return boolean 鏄惁鍚姩鎴愬姛 -function excloud.start_heartbeat(interval, custom_data) - -- 鍋滄鐜版湁鐨勫績璺冲畾鏃跺櫒 - if is_heartbeat_running then - excloud.stop_heartbeat() - end - - -- 璁剧疆蹇冭烦闂撮殧锛岄粯璁5鍒嗛挓 - heartbeat_interval = interval or 300 - - -- 璁剧疆蹇冭烦鏁版嵁 - heartbeat_data = custom_data or {} - - -- 鍒涘缓骞跺惎鍔ㄥ績璺冲畾鏃跺櫒 - heartbeat_timer = sys.timerLoopStart(function() - if is_open and is_connected then - local ok, err_msg = excloud.heartbeat() - if not ok then - log.info("[excloud]excloud", "蹇冭烦鍙戦佸け璐: " .. err_msg) - else - log.info("[excloud]excloud", "蹇冭烦鍙戦佹垚鍔") - end - end - end, heartbeat_interval * 1000) -- 杞崲涓烘绉 - - is_heartbeat_running = true - log.info("[excloud]excloud", "鑷姩蹇冭烦宸插惎鍔紝闂撮殧 " .. heartbeat_interval .. " 绉") - return true -end - --- 鍋滄鑷姩蹇冭烦 --- @return boolean 鏄惁鍋滄鎴愬姛 -function excloud.stop_heartbeat() - if heartbeat_timer then - sys.timerStop(heartbeat_timer) - heartbeat_timer = nil - is_heartbeat_running = false - log.info("[excloud]excloud", "鑷姩蹇冭烦宸插仠姝") - return true - end - return false -end - --- 鑾峰彇褰撳墠鏈嶅姟鍣ㄤ俊鎭 -function excloud.get_server_info() - return { - conninfo = config.current_conninfo, - imginfo = config.current_imginfo, - audinfo = config.current_audinfo, - mtninfo = config.current_mtninfo -- 鏂板锛氳繍缁存棩蹇椾笂浼犱俊鎭 - } -end - --- 寮哄埗鍒锋柊鏈嶅姟鍣ㄤ俊鎭 --- function excloud.refresh_server_info() --- config.current_conninfo = nil --- config.current_imginfo = nil --- config.current_audinfo = nil --- return true --- end --- 瀵煎嚭甯搁噺 -excloud.DATA_TYPES = DATA_TYPES -excloud.FIELD_MEANINGS = FIELD_MEANINGS -excloud.MTN_LOG_STATUS = MTN_LOG_STATUS -excloud.MTN_LOG_CACHE_WRITE = exmtn.CACHE_WRITE -excloud.MTN_LOG_ADD_WRITE = exmtn.ADD_WRITE - -return excloud diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exeasyui.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exeasyui.lua deleted file mode 100644 index 6e0ba72..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exeasyui.lua +++ /dev/null @@ -1,4005 +0,0 @@ ---[[ -exEasyUI v1.7.1 -浣滆咃細鏇惧竻銆佹睙璁 -鏃ユ湡锛2025-12-26 -================================ -缁撴瀯璇存槑锛 -1. 甯搁噺瀹氫箟 - UI棰滆壊甯搁噺鍜岃皟璇曢厤缃 -2. 纭欢渚濊禆 - LCD/TP 鍒濆鍖栥佸瓧浣撳悗绔閰 -3. 鏍稿績閮ㄥ垎 - 3.1 娓叉煋瀛愮郴缁 - 3.2 杩愯鏃朵笌浜嬩欢绯荤粺 - 3.3 璋冭瘯妯″潡 - 3.4 Widget 鍩虹被 -4. 宸ュ叿鍑芥暟 - 缁樺浘宸ュ叿銆佸瓧浣撳伐鍏枫佹枃鏈鐞嗗伐鍏 -5. 缁勪欢閮ㄥ垎 - 缁勪欢鎸夊悕绉版嫾闊虫帓搴忥紝缁勪欢鍒楄〃锛 - button銆 - check_box銆 - combo_box銆 - input銆 - keyboard銆 - label銆 - message_box銆 - picture銆 - progress_bar銆 - window銆 -6. 瀵瑰鎺ュ彛瀵煎嚭 -]] - -local ui = { - version = "1.7.1", - hw = {}, - runtime = {}, - render = {}, - widget = {}, - debug = {} -} - --- 渚濊禆妯″潡锛堢敱 LuatOS 渚ф彁渚涳級 -local exlcd = require "exlcd" -local extp = require "extp" -local lcd = lcd -local spi = spi -local gtfont = gtfont -local hzfont = hzfont or rawget(_G, "hzfont") - --- 鍓嶇疆澹版槑锛堜究浜庡垎娈电粍缁囷級 -local clamp -local now_ms -local fill_rect -local stroke_rect -local font_line_height -local font_measure -local font_draw -local Canvas -local canvas -local handle_debug_stats - -local render_state - --- 杩愯鏃惰〃鎻愬墠澹版槑锛屼究浜庣‖浠舵ā鍧楀紩鐢 -local runtime = { - roots = {}, - pointer_capture = nil, - input_bound = false, - last_pointer = { x = 0, y = 0 }, - touch_anchor_x = 0, - touch_anchor_y = 0 -} -ui.runtime = runtime - --- 璋冭瘯鐘舵佽〃鎻愬墠澹版槑 -local debug_state = { - enabled = false, - last_stats = nil, - last_log_ms = 0, - accum_frame_ms = 0, - accum_start_ms = 0, - timer_id = nil -} - --- ================================ --- 1. 甯搁噺瀹氫箟 --- ================================ - -local COLOR_WHITE = 0xFFFF -local COLOR_BLACK = 0x0000 -local COLOR_GRAY = 0x8410 -local COLOR_BLUE = 0x001F -local COLOR_RED = 0xF800 -local COLOR_GREEN = 0x07E0 -local COLOR_YELLOW = 0xFFE0 -local COLOR_CYAN = 0x07FF -local COLOR_MAGENTA = 0xF81F -local COLOR_ORANGE = 0xFC00 -local COLOR_PINK = 0xF81F -local COLOR_SKY_BLUE = 0x65BE -local COLOR_WIN11_LIGHT_DIALOG_BG = 0xF79E -local COLOR_WIN11_LIGHT_BUTTON_BG = 0xFFDF -local COLOR_WIN11_LIGHT_BUTTON_BORDER = 0xE73C -local COLOR_WIN11_DARK_DIALOG_BG = 0x2104 -local COLOR_WIN11_DARK_BUTTON_BG = 0x3186 -local COLOR_WIN11_DARK_BUTTON_BORDER = 0x4A69 - -ui.COLOR_WHITE = COLOR_WHITE -ui.COLOR_BLACK = COLOR_BLACK -ui.COLOR_GRAY = COLOR_GRAY -ui.COLOR_BLUE = COLOR_BLUE -ui.COLOR_RED = COLOR_RED -ui.COLOR_GREEN = COLOR_GREEN -ui.COLOR_YELLOW = COLOR_YELLOW -ui.COLOR_CYAN = COLOR_CYAN -ui.COLOR_MAGENTA = COLOR_MAGENTA -ui.COLOR_ORANGE = COLOR_ORANGE -ui.COLOR_PINK = COLOR_PINK -ui.COLOR_SKY_BLUE = COLOR_SKY_BLUE -ui.COLOR_WIN11_LIGHT_DIALOG_BG = COLOR_WIN11_LIGHT_DIALOG_BG -ui.COLOR_WIN11_LIGHT_BUTTON_BG = COLOR_WIN11_LIGHT_BUTTON_BG -ui.COLOR_WIN11_LIGHT_BUTTON_BORDER = COLOR_WIN11_LIGHT_BUTTON_BORDER -ui.COLOR_WIN11_DARK_DIALOG_BG = COLOR_WIN11_DARK_DIALOG_BG -ui.COLOR_WIN11_DARK_BUTTON_BG = COLOR_WIN11_DARK_BUTTON_BG -ui.COLOR_WIN11_DARK_BUTTON_BORDER = COLOR_WIN11_DARK_BUTTON_BORDER - -local DEBUG_LOG_INTERVAL_MS = 1000 -local current_theme = "light" -gtfont_dev = gtfont_dev or nil - -local FontAdapter = { - _backend = "default", - _size = 12, - _gray = false, - _name = nil, - _hz_antialias = -1 -} - --- ================================ --- 2. 纭欢渚濊禆 --- ================================ - -local function configure_font_backend(opts) - opts = opts or {} - local function fallback_default() - FontAdapter._backend = "default" - FontAdapter._size = 12 - FontAdapter._gray = false - FontAdapter._name = opts.name - FontAdapter._hz_antialias = -1 - if lcd and lcd.setFont and lcd.font_opposansm12_chinese then - lcd.setFont(lcd.font_opposansm12_chinese) - log.info("exEasyUI", "浣跨敤榛樿鐨刦ont_opposansm12_chinese瀛椾綋") - else - log.warn("exEasyUI", "璇ュ浐浠朵笉鏀寔榛樿鐨刦ont_opposansm12_chinese瀛椾綋锛屽皢娌℃湁涓枃鏀寔锛岃鏇存崲鏀寔璇ュ瓧浣撶殑鍥轰欢 ") - end - end - if opts.type == "gtfont" and gtfont and spi then - local spi_id = (opts.spi and opts.spi.id) or 0 - local spi_cs = (opts.spi and opts.spi.cs) or 8 - local spi_clk = 20 * 1000 * 1000 - gtfont_dev = spi.deviceSetup(spi_id, spi_cs, 0, 0, 8, spi_clk, spi.MSB, 1, 0) - local ok = gtfont_dev and gtfont.init(gtfont_dev) - if ok then - FontAdapter._backend = "gtfont" - FontAdapter._size = tonumber(opts.size or 16) - FontAdapter._gray = false - log.info("exEasyUI", "gtfont enabled", spi_id, spi_cs, FontAdapter._size) - return - else - log.warn("exEasyUI", "gtfont init failed, fallback") - end - elseif opts.type == "hzfont" and hzfont then - local cache_size = tonumber(opts.cache_size) or 256 - cache_size = (cache_size == 128 or cache_size == 256 or cache_size == 512 or cache_size == 1024 or cache_size == 2048) and - cache_size or 256 - local ok = hzfont.init(opts.path, cache_size) - if ok then - FontAdapter._backend = "hzfont" - FontAdapter._size = tonumber(opts.size or 16) - local aa = tonumber(opts.antialias or -1) or -1 - if not (aa == -1 or aa == 1 or aa == 2 or aa == 4) then - aa = -1 - end - FontAdapter._hz_antialias = aa - log.info("exEasyUI", "hzfont enabled", opts.path or "builtin", FontAdapter._size) - return - else - log.warn("exEasyUI", "hzfont init failed, fallback") - end - end - fallback_default() -end - -function ui.hw_init(opts) - if not opts then - log.error("ui.hw_init", "opts is nil") - return false - end - local lcd_ok = exlcd.init(opts.lcd_config) - if not lcd_ok then - log.error("exEasyUI", "LCD init failed") - return false - end - if opts.enable_buffer ~= false and lcd and lcd.setupBuff then - lcd.setupBuff(nil, true) - log.info("exEasyUI", "framebuffer enabled") - end - if lcd and lcd.autoFlush then - lcd.autoFlush(false) - end - if lcd and lcd.setAcchw and lcd.ACC_HW_JPEG then - lcd.setAcchw(lcd.ACC_HW_JPEG, opts.enable_hardware_decode and true or false) - end - - -- 鍒濆鍖栬Е鎽窱C - -- 浣跨敤閰嶇疆琛ㄤ腑鐨勫弬鏁板垵濮嬪寲瑙︽懜 - local tp_config = opts.tp_config - extp.init(tp_config) - - -- 璁剧疆娑堟伅鍙戝竷鐘舵 - if tp_config and tp_config.message_enabled then - if type(tp_config.message_enabled) == "table" then - for msg_type, enabled in pairs(tp_config.message_enabled) do - if type(msg_type) == "string" and type(enabled) == "boolean" then - local success = extp.set_publish_enabled(msg_type, enabled) - if not success then - log.warn("exEasyUI", "璁剧疆娑堟伅鍙戝竷鐘舵佸け璐:", msg_type, enabled) - end - end - end - elseif type(tp_config.message_enabled) == "string" then - local success = extp.set_publish_enabled(tp_config.message_enabled, true) - if not success then - log.warn("exEasyUI", "璁剧疆娑堟伅鍙戝竷鐘舵佸け璐:", tp_config.message_enabled) - end - end - end - - -- 璁剧疆婊戝姩闃堝 - if tp_config and tp_config.swipe_threshold then - if type(tp_config.swipe_threshold) == "number" and tp_config.swipe_threshold > 0 then - extp.set_swipe_threshold(tp_config.swipe_threshold) - end - end - - -- 璁剧疆闀挎寜闃堝 - if tp_config and tp_config.long_press_threshold then - if type(tp_config.long_press_threshold) == "number" and tp_config.long_press_threshold > 0 then - extp.set_long_press_threshold(tp_config.long_press_threshold) - end - end - - runtime.bindInput() - - local width, height - - if opts.lcd_config and opts.lcd_config.w then - width = (opts.lcd_config and opts.lcd_config.w) or (render_state and render_state.viewport_w) - height = (opts.lcd_config and opts.lcd_config.h) or (render_state and render_state.viewport_h) - else - width, height = lcd.getSize() - end - - -- 璁惧畾瀛椾綋渚濊禆 - configure_font_backend(opts.font_config or {}) - ui.render.set_viewport(width, height) - return true -end - --- ================================ --- 3. 鏍稿績閮ㄥ垎 --- ================================ - --- 3.1 娓叉煋瀛愮郴缁 - ---[[ 鍒锋柊鏈哄埗璇存槑锛 -exEasyUI 褰撳墠鐨勭敾闈㈠埛鏂版満鍒堕噰鐢ㄤ簡鈥滆剰鍖烘敹闆 + 寤惰繜鎵归噺娓叉煋鈥濈瓥鐣ワ細 - -1. 鑴忓尯鏀堕泦锛氬綋 UI 缁勪欢闇瑕佸埛鏂版椂锛堝嵆 invalidate锛夛紝浼氬皢鑴忓尯鍩 push 鍒 render_state.dirty_regions锛屾垨鑰呮爣璁板叏灞忛渶鍒锋柊锛岃屼笉浼氱珛鍒昏皟鐢ㄦ覆鏌撱 -2. 寤惰繜鎵归噺瀹氭椂锛氭瘡娆℃湁鏂扮殑鑴忓尯鍔犲叆鏃讹紝濡傛灉鍒锋柊瀹氭椂鍣ㄦ湭鍚姩锛屽垯浼氬惎鍔ㄤ竴涓 30ms 鐨勫欢鏃跺畾鏃跺櫒锛坮ender_state.batch_timer锛夛紝澶氭 invalidate 浼氳仛鍚堝湪涓璧凤紝瀹氭椂鍣ㄥ洖璋冩椂缁熶竴鍒锋柊銆 -3. 鎵归噺娓叉煋锛氬畾鏃跺櫒瑙﹀彂鍚庯紝缁熶竴鎵ц涓娆℃覆鏌擄紙濡 render_dirty_regions_once 鎴 request_render锛夛紝鏍规嵁鑴忓尯鍒楄〃/鍏ㄥ睆鏍囧織娓叉煋杩欎簺鍖哄煙锛屽苟璋冪敤 lcd.flush()銆傛覆鏌撳悗娓呯┖鑴忓尯鍜屽畾鏃跺櫒鏍囪锛屽噯澶囦笅涓杞 -4. 浼樺娍锛氳繖鏍疯兘鏈夋晥鍚堝苟澶氱粍浠剁殑鍒峰睆鎿嶄綔锛堝涓娆′簨浠跺紩鍙戝涓尯鍩熷彉鍖栵級锛屽ぇ骞呭噺灏戞棤璋撶殑閲嶅娓叉煋鍜屽睆骞曞埛鏂拌皟鐢紝鎻愰珮鎬ц兘骞跺噺灏戦棯鐑併 - -鎬讳箣锛宔asyui 鍒锋柊鏈哄埗閫氳繃鈥滆剰鍖烘敹闆 + 寤惰繜鎵归噺+鍚堝苟鈥濆疄鐜颁簡鍝嶅簲鐏垫椿涓旈珮鏁堢殑 UI 鏇存柊锛屾湁鍒╀簬澶嶆潅浜や簰鍦烘櫙涓嬬殑鎬ц兘浼樺寲鍜屼綋楠屾彁鍗囥 -]] - -render_state = { - dirty_regions = {}, -- 褰撳墠甯ч渶瑕佸埛鏂扮殑鍖哄煙鍒楄〃锛堟暟缁勶級 - full_refresh = true, -- 鏄惁闇瑕佸叏灞忓埛鏂 - need_present = false, -- 鏄惁闇瑕丩CD閲嶆柊鏄剧ず - viewport_w = 320, -- 娓叉煋瑙嗗彛瀹藉害锛岄粯璁320 - viewport_h = 240, -- 娓叉煋瑙嗗彛楂樺害锛岄粯璁240 - clear_color = COLOR_BLACK, -- 娓呭睆棰滆壊 - render_in_progress = false, -- 鏄惁姝ｅ湪娓叉煋 - render_pending = false, -- 鏄惁鏈夊緟娓叉煋璇锋眰 - batch_timer_id = nil, -- 鎵归噺鍒锋柊瀹氭椂鍣↖D - batch_delay_ms = 30 -- 鎵归噺鍒锋柊寤惰繜锛堝崟浣峬s锛 -} - --- 璁＄畻褰撳墠鑴忓尯鐨勭旱鍚戣寖鍥达紝杩斿洖 min_y/max_y锛堢敤浜庡眬閮ㄥ埛鏂颁紭鍖栵級 -local function accumulate_dirty_y_range() - if render_state.full_refresh then - return 0, render_state.viewport_h - 1 - end - if #render_state.dirty_regions == 0 then - return nil, nil - end - local min_y = render_state.viewport_h - local max_y = 0 - for i = 1, #render_state.dirty_regions do - local r = render_state.dirty_regions[i] - local rmin = clamp(r.y, 0, render_state.viewport_h - 1) - local rmax = clamp(r.y + r.h - 1, 0, render_state.viewport_h - 1) - if rmin < min_y then min_y = rmin end - if rmax > max_y then max_y = rmax end - end - if min_y > max_y then - return nil, nil - end - return min_y, max_y -end - --- 閲嶇疆鑴忓尯鐘舵侊紝浣夸笅涓甯т粠绌虹櫧鐘舵佸紑濮 -local function reset_dirty_state() - render_state.dirty_regions = {} - render_state.full_refresh = false - render_state.need_present = false -end - --- 閫掑綊缁樺埗鏁翠釜 widget 鏍戯紝浼犲叆鑴忓尯鑼冨洿鐢ㄤ簬灞閮ㄦ覆鏌 -local function draw_widget_tree(widget, dirty, stats) - if not widget.visible then return end - if stats then stats.widgets = stats.widgets + 1 end - if widget.draw then - widget:draw(canvas, dirty) - end - if widget.children then - for i = 1, #widget.children do - draw_widget_tree(widget.children[i], dirty, stats) - end - end -end - --- 鎵ц涓娆¤剰鍖烘覆鏌擄細鍙湪纭疄鏈夎剰鍖烘椂鎵嶈皟鐢紝缁樺埗鍚庣珛鍗抽噸缃剰鍖 --- 娓叉煋鍣ㄦ牳蹇冿細鏍规嵁褰撳墠绉疮鐨 dirty_regions 娓叉煋鏁翠釜 widget 鏍 --- 濡傛灉娌¤剰鍖虹洿鎺ヨ繑鍥烇紝閬垮厤鏃犺皳鐨勭粯鍒 -local function render_dirty_regions_once() - if not render_state.need_present then - if lcd and lcd.flush then - lcd.flush() - end - return false - end - local start_ms = now_ms() - local y_min, y_max = accumulate_dirty_y_range() - if not y_min then - reset_dirty_state() - return false - end - if render_state.full_refresh and canvas and canvas.clear then - canvas:clear(render_state.clear_color) - end - local stats = { - widgets = 0, - dirty_span = (y_max and y_min) and (y_max - y_min + 1) or 0, - full_refresh = render_state.full_refresh - } - local dirty_span = { y_min = y_min, y_max = y_max } - for i = 1, #runtime.roots do - draw_widget_tree(runtime.roots[i], dirty_span, stats) - end - stats.frame_ms = now_ms() - start_ms - handle_debug_stats(stats) - if lcd and lcd.flush then - lcd.flush() - end - reset_dirty_state() - return true -end - --- 璇锋眰涓娆℃覆鏌擄細璁剧疆 need_present 骞朵覆琛岃皟鐢 render_frame锛岀‘淇濆綋鍓嶆覆鏌撳畬鎴愬墠涓嶄細鍐嶆鍚姩 --- 鐢ㄤ簬 `invalidate`/`background` 绛夋帴鍙 --- 璇锋眰涓娆¤剰鍖烘覆鏌擄細鍙湁鍦ㄥ綋鍓嶆病鏈夋鍦ㄦ覆鏌撶殑鎯呭喌涓嬫墠鎵ц锛屽惁鍒欒缃 pending 璁╁綋鍓嶅抚缁撴潫鍚庣户缁覆鏌 -local function cancel_batch_timer() - if render_state.batch_timer_id and sys and sys.timerStop then - sys.timerStop(render_state.batch_timer_id) - end - render_state.batch_timer_id = nil -end - -local function request_render() - cancel_batch_timer() - render_state.need_present = true - if render_state.render_in_progress then - render_state.render_pending = true - return false - end - local result = false - repeat - -- 姣忚疆鍏堟竻闄 pending 鏍囪鍐嶆墽琛 - render_state.render_pending = false - render_state.render_in_progress = true - result = render_dirty_regions_once() - render_state.render_in_progress = false - -- 濡傛灉鍦 render_dirty_regions_once 涓張浜х敓鏂扮殑 invalidate锛屽氨缁х画娓叉煋 - until not render_state.render_pending - return result -end - --- 鎵归噺娓叉煋璋冨害鍑芥暟锛氬悎骞剁煭鏃堕棿鍐呭娆℃覆鏌撹姹傦紝鍙皟搴︿竴娆″畾鏃舵覆鏌 -local function schedule_batched_render() - render_state.need_present = true -- 鏍囪闇瑕佹覆鏌 - -- 濡傛灉涓嶆敮鎸 sys.timerStart 鎴栨湭璁剧疆鎵归噺寤惰繜锛屾垨鎵归噺寤惰繜涓0锛屽垯鐩存帴娓叉煋 - if not sys or not sys.timerStart or (render_state.batch_delay_ms or 0) <= 0 then - return request_render() - end - -- 宸叉湁瀹氭椂鍣ㄤ换鍔″湪鎺掗槦锛屼笉閲嶅璋冨害 - if render_state.batch_timer_id then - return - end - -- 鍚姩涓娆″畾鏃跺櫒锛屽埌鏈熷悗鎵ц娓叉煋骞舵竻闄よ鏃跺櫒ID - render_state.batch_timer_id = sys.timerStart(function() - render_state.batch_timer_id = nil - request_render() - end, render_state.batch_delay_ms) -end - --- 璁剧疆閫昏緫鍒嗚鲸鐜囷紙涓昏鐢辩‖浠跺垵濮嬪寲鏃惰皟鐢級 -ui.render.set_viewport = function(w, h) - if w then render_state.viewport_w = w end - if h then render_state.viewport_h = h end -end - --- 鐩存帴濉厖鑳屾櫙鑹插苟寮哄埗鏍囪鍏ㄥ睆鑴忓尯 -ui.render.background = function(color) - render_state.clear_color = color or COLOR_BLACK - render_state.full_refresh = true - schedule_batched_render() -end - --- 鏍囪涓涓剰鍖哄苟瑙﹀彂娓叉煋锛涗紶鍏 nil 鎰忓懗鐫鍏ㄥ睆鍒锋柊 -ui.render.invalidate = function(rect) - if not rect then - render_state.full_refresh = true - else - render_state.dirty_regions[#render_state.dirty_regions + 1] = rect - end - schedule_batched_render() -end - --- 璁剧疆鎵归噺娓叉煋寤惰繜锛堝崟浣嶏細姣锛夛紝鐢ㄤ簬鍚堝苟澶氭鍒锋柊璇锋眰锛屽噺灏戝埛鏂版鏁 -ui.render.set_batch_delay = function(ms) - local delay = tonumber(ms) - if delay and delay >= 0 then - render_state.batch_delay_ms = delay - else - render_state.batch_delay_ms = 0 - end -end - -ui.render.present = request_render - --- 3.1.1 鍥剧墖缂撳瓨绠＄悊鍣 -local image_cache = { - _zbuff_cache = {}, -- 璺緞 -> zbuff 鏄犲皠 - _loading = {}, -- 姝ｅ湪鍔犺浇鐨勮矾寰勯泦鍚堬紙闃叉閲嶅鍔犺浇锛 - _failed = {} -- 鍔犺浇澶辫触鐨勮矾寰勯泦鍚堬紙閬垮厤閲嶅灏濊瘯锛 -} - --- 鑾峰彇鍥剧墖 zbuff锛堟寜闇鍔犺浇锛 -function image_cache.get_zbuff(path) - if not path or type(path) ~= "string" or path == "" then - return nil - end - - -- 妫鏌ユ槸鍚﹀凡缂撳瓨 - if image_cache._zbuff_cache[path] then - return image_cache._zbuff_cache[path] - end - - -- 妫鏌ユ槸鍚︽鍦ㄥ姞杞斤紙闃叉閲嶅鍔犺浇锛 - if image_cache._loading[path] then - return nil - end - - -- 妫鏌ユ槸鍚﹀凡澶辫触 - if image_cache._failed[path] then - return nil - end - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if io and io.exists then - if not io.exists(path) then - image_cache._failed[path] = true - log.warn("image_cache", "鍥剧墖鏂囦欢涓嶅瓨鍦", path) - return nil - end - end - - -- 妫鏌 lcd.image2raw 鏄惁鍙敤 - if not lcd or not lcd.image2raw then - return nil - end - - -- 鏍囪涓烘鍦ㄥ姞杞 - image_cache._loading[path] = true - - -- 瑙ｇ爜鍥剧墖 - local ok, zbuff = pcall(lcd.image2raw, path) - image_cache._loading[path] = false - - if ok and zbuff then - -- 缂撳瓨鎴愬姛 - image_cache._zbuff_cache[path] = zbuff - return zbuff - else - -- 瑙ｇ爜澶辫触 - image_cache._failed[path] = true - log.warn("image_cache", "鍥剧墖瑙ｇ爜澶辫触", path) - return nil - end -end - --- 棰勫姞杞藉浘鐗 -function image_cache.preload(path) - if not path or type(path) ~= "string" or path == "" then - return false - end - - -- 濡傛灉宸茬紦瀛橈紝鐩存帴杩斿洖 - if image_cache._zbuff_cache[path] then - return true - end - - -- 灏濊瘯鍔犺浇 - local zbuff = image_cache.get_zbuff(path) - return zbuff ~= nil -end - --- 娓呴櫎缂撳瓨 -function image_cache.clear(path) - if path then - -- 娓呴櫎鎸囧畾璺緞 - image_cache._zbuff_cache[path] = nil - image_cache._loading[path] = nil - image_cache._failed[path] = nil - else - -- 娓呴櫎鎵鏈夌紦瀛 - image_cache._zbuff_cache = {} - image_cache._loading = {} - image_cache._failed = {} - end -end - --- 妫鏌ョ紦瀛樼姸鎬 -function image_cache.is_cached(path) - if not path then return false end - return image_cache._zbuff_cache[path] ~= nil -end - -ui.image_cache = image_cache - --- 3.2 杩愯鏃朵笌浜嬩欢绯荤粺 -local function dispatch_pointer(evt, a, b) - for i = #runtime.roots, 1, -1 do - local root = runtime.roots[i] - if root:dispatch_pointer(evt, a, b) then - return true - end - end - return false -end - -local function debug_touch_log(evt, rawA, rawB, cursorX, cursorY) - if not debug_state.enabled then return end - local function sval(v) - if v == nil then return "nil" end - return tostring(v) - end - -- log.info("exEasyUI.debug.tp", string.format("evt=%s raw=(%s,%s) cursor=(%s,%s)", - -- tostring(evt or ""), sval(rawA), sval(rawB), sval(cursorX), sval(cursorY))) -end - -local function handle_touch_event(evt, a, b) - local rawA = a - local rawB = b - if evt == "TOUCH_DOWN" or evt == "SINGLE_TAP" or evt == "LONG_PRESS" then - runtime.last_pointer.x = tonumber(a) or 0 - runtime.last_pointer.y = tonumber(b) or 0 - runtime.touch_anchor_x = runtime.last_pointer.x - runtime.touch_anchor_y = runtime.last_pointer.y - debug_touch_log(evt, rawA, rawB, runtime.last_pointer.x, runtime.last_pointer.y) - return dispatch_pointer(evt, runtime.last_pointer.x, runtime.last_pointer.y) - end - if evt == "MOVE_X" then - local delta = tonumber(a) or 0 - if runtime.touch_anchor_x == nil then - runtime.touch_anchor_x = runtime.last_pointer.x - end - runtime.last_pointer.x = (runtime.touch_anchor_x or 0) + delta - debug_touch_log(evt, rawA, rawB, runtime.last_pointer.x, runtime.last_pointer.y) - return dispatch_pointer(evt, runtime.last_pointer.x, runtime.last_pointer.y) - elseif evt == "MOVE_Y" then - local delta = tonumber(b) or 0 - if runtime.touch_anchor_y == nil then - runtime.touch_anchor_y = runtime.last_pointer.y - end - runtime.last_pointer.y = (runtime.touch_anchor_y or 0) + delta - debug_touch_log(evt, rawA, rawB, runtime.last_pointer.x, runtime.last_pointer.y) - return dispatch_pointer(evt, runtime.last_pointer.x, runtime.last_pointer.y) - else - local ax = tonumber(a) - local ay = tonumber(b) - debug_touch_log(evt, rawA, rawB, ax, ay) - return dispatch_pointer(evt, ax, ay) - end -end - -function runtime.bindInput() - if runtime.input_bound then return end - sys.subscribe("BASE_TOUCH_EVENT", handle_touch_event) - runtime.input_bound = true -end - -function runtime.add(widget) - runtime.roots[#runtime.roots + 1] = widget - widget.root = true - if widget.on_mount then widget:on_mount() end - widget:invalidate() - return widget -end - -function runtime.remove(widget) - for i = #runtime.roots, 1, -1 do - if runtime.roots[i] == widget then - table.remove(runtime.roots, i) - if widget.on_unmount then widget:on_unmount() end - render_state.full_refresh = true - request_render() - return true - end - end - return false -end - -local function debug_emit_summary() - local total = debug_state.accum_frame_ms or 0 - local usage = (total / DEBUG_LOG_INTERVAL_MS) * 100 - log.info("exEasyUI.debug", string.format("鏈杩1s缁樺埗鑰楁椂=%.1fms 鑰楁椂鍗犳瘮=%.1f%%", total, usage)) - debug_state.accum_frame_ms = 0 - debug_state.accum_start_ms = now_ms() -end - -local function debug_timer_tick() - if not debug_state.enabled then return end - debug_emit_summary() -end - -handle_debug_stats = function(stats) - debug_state.last_stats = stats - if not debug_state.enabled then return end - if stats and stats.frame_ms then - log.info("exEasyUI.debug", string.format("鍗曟缁樺埗鑰楁椂=%.1fms 缁樺埗缁勪欢=%d 鑴忓尯楂樺害=%dpx 缁樺埗鏂瑰紡=%s", - stats.frame_ms or 0, - stats.widgets or 0, - stats.dirty_span or 0, - stats.full_refresh and "鍏ㄥ睆" or "灞閮")) - debug_state.accum_frame_ms = (debug_state.accum_frame_ms or 0) + (stats.frame_ms or 0) - end - if not debug_state.timer_id then - local now = now_ms() - if debug_state.accum_start_ms == 0 then - debug_state.accum_start_ms = now - end - local window_ms = DEBUG_LOG_INTERVAL_MS - if now - debug_state.accum_start_ms >= window_ms then - debug_emit_summary() - end - end -end - -function ui.debug.enable(enabled) - enabled = not not enabled - if enabled and not debug_state.enabled then - debug_state.enabled = true - debug_state.accum_frame_ms = 0 - debug_state.accum_start_ms = now_ms() - if sys and sys.timerLoopStart then - debug_state.timer_id = sys.timerLoopStart(debug_timer_tick, DEBUG_LOG_INTERVAL_MS) - end - elseif (not enabled) and debug_state.enabled then - debug_state.enabled = false - if debug_state.timer_id and sys and sys.timerStop then - sys.timerStop(debug_state.timer_id) - end - debug_state.timer_id = nil - debug_state.accum_frame_ms = 0 - debug_state.accum_start_ms = 0 - end -end - -function ui.debug.set_level(level) - if level == "off" then - ui.debug.enable(false) - else - ui.debug.enable(true) - end -end - -function ui.debug.get_stats() - return debug_state.last_stats -end - -setmetatable(ui.debug, { - __call = function(_, enabled) - ui.debug.enable(enabled) - end -}) - --- 3.4 Widget 鍩虹被 -local BaseWidget = {} -BaseWidget.__index = BaseWidget - -function BaseWidget:new(opts) - opts = opts or {} - local o = setmetatable({}, self) - o.x = opts.x or 0 - o.y = opts.y or 0 - o.w = opts.w or 0 - o.h = opts.h or 0 - o.visible = opts.visible ~= false - o.enabled = opts.enabled ~= false - o.children = {} - o.theme = opts.theme - return o -end - -function BaseWidget:get_absolute_position() - local x = self.x or 0 - local y = self.y or 0 - local parent = self.parent - while parent do - x = x + (parent.x or 0) - y = y + (parent.y or 0) - if parent._scroll then - x = x + (parent._scroll.offset_x or 0) - y = y + (parent._scroll.offset_y or 0) - end - parent = parent.parent - end - return x, y -end - -function BaseWidget:add(child) - self.children[#self.children + 1] = child - child.parent = self - child:invalidate() - return child -end - -function BaseWidget:get_bounds() - local ax, ay = self:get_absolute_position() - return { x = ax, y = ay, w = self.w, h = self.h } -end - -function BaseWidget:invalidate(rect) - local bounds = rect or self:get_bounds() - ui.render.invalidate(bounds) -end - -function BaseWidget:contains_point(px, py) - local bounds = self:get_bounds() - return px >= bounds.x and py >= bounds.y and - px <= (bounds.x + bounds.w) and py <= (bounds.y + bounds.h) -end - -function BaseWidget:handle_event() - return false -end - -function BaseWidget:dispatch_pointer(evt, x, y) - if not self.visible or not self.enabled then - return false - end - if self.children then - for i = #self.children, 1, -1 do - if self.children[i]:dispatch_pointer(evt, x, y) then - return true - end - end - end - if self.handle_event ~= BaseWidget.handle_event then - return self:handle_event(evt, x, y) - end - return false -end - -ui.widget.Base = BaseWidget - --- ================================ --- 4. 宸ュ叿鍑芥暟 --- ================================ - -clamp = function(v, minv, maxv) - if v < minv then return minv end - if v > maxv then return maxv end - return v -end - -now_ms = function() - if mcu and mcu.ticks then - return mcu.ticks() - end - if sys and sys.tick then - return sys.tick() - end - return (os.time() or 0) * 1000 -end - -fill_rect = function(x1, y1, x2, y2, color) - if not lcd or not lcd.fill then return end - lcd.fill(x1, y1, x2, y2 + 1, color) -end - -stroke_rect = function(x1, y1, x2, y2, color) - if not lcd then return end - if lcd.drawLine then - lcd.drawLine(x1, y1, x2, y1, color) - lcd.drawLine(x2, y1, x2, y2, color) - lcd.drawLine(x2, y2, x1, y2, color) - lcd.drawLine(x1, y2, x1, y1, color) - end -end - -font_line_height = function(style) - if FontAdapter._backend == "gtfont" or FontAdapter._backend == "hzfont" then - return tonumber(style and style.size or FontAdapter._size or 16) - end - if lcd and style and style.size then - local guess = "font_opposansm" .. tostring(style.size) .. "_chinese" - if lcd[guess] then - return tonumber(style.size) - end - end - return FontAdapter._size or 12 -end - -font_measure = function(text, style) - if not text or text == "" then return 0 end - style = style or {} - if FontAdapter._backend == "gtfont" and lcd and lcd.getGtfontStrWidth then - return lcd.getGtfontStrWidth(text, tonumber(style.size or FontAdapter._size or 16)) - end - if FontAdapter._backend == "hzfont" and lcd and lcd.getHzFontStrWidth then - return lcd.getHzFontStrWidth(text, tonumber(style.size or FontAdapter._size or 16)) - end - if lcd and lcd.getStrWidth then - return lcd.getStrWidth(text) - end - local width = 0 - local i = 1 - local size = tonumber(style.size) or FontAdapter._size or 12 - while i <= #text do - local byte = string.byte(text, i) - if byte < 128 then - width = width + math.ceil(size / 2) - i = i + 1 - else - width = width + size - i = i + 3 - end - end - return width -end - -font_draw = function(text, x, y, color, style) - if not lcd then return end - style = style or {} - color = color or COLOR_WHITE - if FontAdapter._backend == "gtfont" and lcd.drawGtfontUtf8 then - local sz = tonumber(style.size or FontAdapter._size or 16) - if FontAdapter._gray and lcd.drawGtfontUtf8Gray then - lcd.drawGtfontUtf8Gray(text, sz, 4, x, y, color) - return - end - lcd.drawGtfontUtf8(text, sz, x, y, color) - return - end - if FontAdapter._backend == "hzfont" and lcd.drawHzfontUtf8 then - local sz = tonumber(style.size or FontAdapter._size or 16) - local lh = font_line_height(style) - lcd.drawHzfontUtf8(x, y + lh, text, sz, color, FontAdapter._hz_antialias or -1) - return - end - if lcd.setFont then - if FontAdapter._name and lcd["font_" .. FontAdapter._name] then - lcd.setFont(lcd["font_" .. FontAdapter._name]) - elseif style.size then - local guess = "font_opposansm" .. tostring(style.size) .. "_chinese" - if lcd[guess] then - lcd.setFont(lcd[guess]) - elseif lcd.font_opposansm12_chinese then - lcd.setFont(lcd.font_opposansm12_chinese) - end - elseif lcd.font_opposansm12_chinese then - lcd.setFont(lcd.font_opposansm12_chinese) - end - end - local lh = font_line_height(style) - if lcd.drawStr then - lcd.drawStr(x, y + lh, text, color) - end -end - -Canvas = {} -Canvas.__index = Canvas - -function Canvas:new() - return setmetatable({}, Canvas) -end - -function Canvas:clear(color) - if lcd and lcd.clear then - lcd.clear(color or COLOR_BLACK) - end -end - -function Canvas:fill_rect(x, y, w, h, color) - if w <= 0 or h <= 0 then return end - fill_rect(x, y, x + w - 1, y + h - 1, color) -end - -function Canvas:stroke_rect(x, y, w, h, color) - if w <= 0 or h <= 0 then return end - stroke_rect(x, y, x + w - 1, y + h - 1, color) -end - -function Canvas:draw_text(text, x, y, color, style) - font_draw(text, x, y, color, style) -end - -function Canvas:text_width(text, style) - return font_measure(text, style) -end - -function Canvas:line_height(style) - return font_line_height(style) -end - -function Canvas:draw_text_in_rect_centered(x, y, w, h, text, opts) - opts = opts or {} - local padding = opts.padding or 0 - local style = opts.style or {} - local color = opts.color or COLOR_WHITE - local tw = self:text_width(text or "", style) - local lh = self:line_height(style) - local inner_w = math.max(0, w - padding * 2) - local inner_h = math.max(0, h - padding * 2) - local tx = x + padding + (inner_w - tw) // 2 - local ty = y + padding + (inner_h - lh) // 2 - self:draw_text(text or "", tx, ty, color, style) -end - -canvas = Canvas:new() - -local function get_utf8_char(text, i) - if not text or i > #text then return "", 0 end - local byte = string.byte(text, i) - if not byte then return "", 0 end - if byte < 128 then - return string.sub(text, i, i), 1 - elseif byte >= 224 and byte < 240 then - if i + 2 <= #text then - return string.sub(text, i, i + 2), 3 - else - return string.sub(text, i, i), 1 - end - elseif byte >= 192 and byte < 224 then - if i + 1 <= #text then - return string.sub(text, i, i + 1), 2 - else - return string.sub(text, i, i), 1 - end - elseif byte >= 240 then - if i + 3 <= #text then - return string.sub(text, i, i + 3), 4 - else - return string.sub(text, i, i), 1 - end - end - return string.sub(text, i, i), 1 -end - -local function wrap_text_lines(text, maxWidth, style) - if not text or text == "" then return { "" } end - if not maxWidth or maxWidth <= 0 then return { text } end - local lines = {} - local currentLine = "" - local currentWidth = 0 - local wordBuffer = "" - local wordWidth = 0 - local i = 1 - while i <= #text do - local char, charLen = get_utf8_char(text, i) - local charWidth = font_measure(char, style) - local byte = string.byte(text, i) - local isAlphaNum = (byte and ((byte >= 48 and byte <= 57) or (byte >= 65 and byte <= 90) or (byte >= 97 and byte <= 122))) - if isAlphaNum then - wordBuffer = wordBuffer .. char - wordWidth = wordWidth + charWidth - i = i + charLen - else - if wordBuffer ~= "" then - if currentWidth + wordWidth > maxWidth then - if currentLine ~= "" then - table.insert(lines, currentLine) - currentLine = wordBuffer - currentWidth = wordWidth - else - currentLine = wordBuffer - currentWidth = wordWidth - end - else - currentLine = currentLine .. wordBuffer - currentWidth = currentWidth + wordWidth - end - wordBuffer = "" - wordWidth = 0 - end - if char == " " then - if currentWidth + charWidth <= maxWidth then - currentLine = currentLine .. char - currentWidth = currentWidth + charWidth - else - if currentLine ~= "" then - table.insert(lines, currentLine) - end - currentLine = "" - currentWidth = 0 - end - else - if currentWidth + charWidth > maxWidth then - if currentLine ~= "" then - table.insert(lines, currentLine) - end - currentLine = char - currentWidth = charWidth - else - currentLine = currentLine .. char - currentWidth = currentWidth + charWidth - end - end - i = i + charLen - end - end - if wordBuffer ~= "" then - if currentWidth + wordWidth > maxWidth and currentLine ~= "" then - table.insert(lines, currentLine) - currentLine = wordBuffer - else - currentLine = currentLine .. wordBuffer - end - end - if currentLine ~= "" then - table.insert(lines, currentLine) - end - if #lines == 0 then - lines = { "" } - end - return lines -end - -local function fit_text_to_width(text, maxWidth, style, opts) - opts = opts or {} - if not text then return "" end - if not maxWidth or maxWidth <= 0 then return text end - if font_measure(text, style) <= maxWidth then - return text - end - local ellipsis = opts.ellipsis and "..." or "" - local reserve = opts.ellipsis and font_measure("...", style) or 0 - local limit = maxWidth - reserve - if limit <= 0 then - return opts.ellipsis and "..." or "" - end - local truncated = "" - local used = 0 - local i = 1 - while i <= #text do - local char, len = get_utf8_char(text, i) - local cw = font_measure(char, style) - if used + cw > limit then - break - end - truncated = truncated .. char - used = used + cw - i = i + len - end - if opts.ellipsis then - return truncated .. "..." - end - return truncated -end - -local function draw_text_direct(x, y, text, opts) - opts = opts or {} - font_draw(text or "", x, y, opts.color or COLOR_WHITE, opts.style or {}) -end - -local function draw_text_in_rect_centered(x, y, w, h, text, opts) - opts = opts or {} - local padding = opts.padding or 0 - local style = opts.style or {} - local color = opts.color or COLOR_WHITE - local tw = font_measure(text or "", style) - local lh = font_line_height(style) - local inner_w = math.max(0, w - padding * 2) - local inner_h = math.max(0, h - padding * 2) - local tx = x + padding + (inner_w - tw) // 2 - local ty = y + padding + (inner_h - lh) // 2 - font_draw(text or "", tx, ty, color, style) -end - -local function draw_image_placeholder(x, y, w, h, bg_color, border_color) - bg_color = bg_color or COLOR_GRAY - border_color = border_color or COLOR_WHITE - fill_rect(x, y, x + w - 1, y + h - 1, bg_color) - stroke_rect(x, y, x + w - 1, y + h - 1, border_color) - if lcd and lcd.drawLine then - lcd.drawLine(x, y, x + w - 1, y + h - 1, border_color) - lcd.drawLine(x + w - 1, y, x, y + h - 1, border_color) - if w >= 20 and h >= 20 then - local margin = math.min(w, h) // 8 - lcd.drawLine(x + margin, y + margin, x + w - 1 - margin, y + h - 1 - margin, border_color) - lcd.drawLine(x + w - 1 - margin, y + margin, x + margin, y + h - 1 - margin, border_color) - end - end -end - --- 绠ご缁樺埗宸ュ叿锛堝湪缁欏畾鐭╁舰鍐呯粯鍒朵笂涓嬪乏鍙崇澶达級 -local function draw_arrow_icon(x, y, w, h, direction, color) - local cx = x + w // 2 - local cy = y + h // 2 - -- 鎺у埗绠ご灏哄锛堝澶у唴杈硅窛锛屾暣浣撶缉鐭害 1/3锛 - local padX = math.max(1, w // 3) - local padY = math.max(1, h // 3) - local leftX = x + padX - local rightX = x + w - padX - local topY = y + padY - local bottomY = y + h - padY - - if direction == "up" then - lcd.drawLine(leftX, bottomY, cx, topY, color) - lcd.drawLine(rightX, bottomY, cx, topY, color) - elseif direction == "down" then - lcd.drawLine(leftX, topY, cx, bottomY, color) - lcd.drawLine(rightX, topY, cx, bottomY, color) - elseif direction == "left" then - -- 宸︿晶涓偣 -> 鍙充笂/鍙充笅锛<锛 - lcd.drawLine(leftX, cy, rightX, topY, color) - lcd.drawLine(leftX, cy, rightX, bottomY, color) - elseif direction == "right" then - -- 鍙充晶涓偣 -> 宸︿笂/宸︿笅锛>锛 - lcd.drawLine(rightX, cy, leftX, topY, color) - lcd.drawLine(rightX, cy, leftX, bottomY, color) - end -end --- ================================ --- 5. 缁勪欢閮ㄥ垎锛堟寜鎷奸煶鎺掑簭锛 --- 缁勪欢鍒楄〃锛歜utton銆乧heck_box銆乧ombo_box銆乮nput銆乲eyboard銆乴abel銆乵essage_box銆乸icture銆乸rogress_bar銆亀indow --- ================================ - --- 5.1 button -local button = setmetatable({}, { __index = BaseWidget }) -button.__index = button - -function button:new(opts) - opts = opts or {} - opts.w = opts.w or opts.width or 100 - opts.h = opts.h or opts.height or 36 - local o = BaseWidget.new(self, opts) - local dark = (current_theme == "dark") - o.text = opts.text or "Button" - o.text_style = { size = opts.text_size or 12 } - o.colors = { - bg = opts.bg_color or (dark and COLOR_GRAY or COLOR_WHITE), - pressed = opts.pressed_color or COLOR_SKY_BLUE, - border = opts.border_color or (dark and COLOR_WHITE or COLOR_BLACK), - text = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK) - } - o.src = opts.src - o.src_pressed = opts.src_pressed - o.src_toggled = opts.src_toggled - o.toggle = opts.toggle or false - o.toggled = opts.toggled or false - o.on_toggle = opts.on_toggle - o.on_click = opts.on_click - o.pressed = false - o._imageCache = {} - return o -end - -local function button_resolve_image(self) - if not self.src then return nil end - if self.toggle and self.toggled then - return self.src_toggled or self.src - elseif self.pressed then - return self.src_pressed or self.src - end - return self.src -end - -function button:draw(ctx) - if not self.visible then return end - local ax, ay = self:get_absolute_position() - local img = button_resolve_image(self) - - -- 浼樺厛浣跨敤鍥剧墖缂撳瓨锛坙cd.image2raw + lcd.draw锛 - if img and lcd and lcd.image2raw and lcd.draw then - local zbuff = ui.image_cache.get_zbuff(img) - if zbuff then - -- 浣跨敤 zbuff 缁樺埗锛宭cd.draw 浼氳嚜鍔ㄤ娇鐢 zbuff 鍐呴儴鐨 width 鍜 height - lcd.draw(ax, ay, nil, nil, zbuff) - return - end - end - - -- 缁樺埗鎸夐挳鑳屾櫙鍜屾枃鏈 - local bg = self.pressed and self.colors.pressed or self.colors.bg - ctx:fill_rect(ax, ay, self.w, self.h, bg) - ctx:stroke_rect(ax, ay, self.w, self.h, self.colors.border) - local text_w = ctx:text_width(self.text or "", self.text_style) - local text_h = ctx:line_height(self.text_style) - local tx = ax + math.max(0, (self.w - text_w) // 2) - local ty = ay + math.max(0, (self.h - text_h) // 2) - ctx:draw_text(self.text or "", tx, ty, self.colors.text, self.text_style) -end - -function button:set_text(new_text) - self.text = tostring(new_text or "") - self:invalidate() -end - -function button:handle_event(evt, x, y) - if not self.enabled then return false end - local inside = self:contains_point(x or 0, y or 0) - if evt == "TOUCH_DOWN" and inside then - self.pressed = true - self._capture = true - self:invalidate() - return true - elseif (evt == "MOVE_X" or evt == "MOVE_Y") and self._capture then - local new_pressed = inside - if new_pressed ~= self.pressed then - self.pressed = new_pressed - self:invalidate() - end - return true - elseif evt == "SINGLE_TAP" then - local was_pressed = self.pressed - self.pressed = false - self._capture = false - if was_pressed and inside then - if self.toggle then - self.toggled = not self.toggled - if self.on_toggle then - pcall(self.on_toggle, self.toggled, self) - end - end - if self.on_click then - pcall(self.on_click, self) - end - self:invalidate() - return true - end - self:invalidate() - return was_pressed - elseif evt == "LONG_PRESS" or evt == "SWIPE_LEFT" or evt == "SWIPE_RIGHT" or evt == "SWIPE_UP" or evt == "SWIPE_DOWN" then - if self._capture then - self.pressed = false - self._capture = false - self:invalidate() - return true - end - end - return false -end - -ui.button = function(opts) - return button:new(opts) -end - --- 5.2 CheckBox -local check_box = setmetatable({}, { __index = BaseWidget }) -check_box.__index = check_box - -function check_box:new(opts) - opts = opts or {} - opts.box_size = opts.box_size or 20 - local text_style = { size = opts.font_size or 12 } - local text_width = opts.text and font_measure(opts.text, text_style) or 0 - opts.w = math.max(opts.w or 0, opts.box_size + (opts.text and (10 + text_width) or 0)) - opts.h = math.max(opts.h or 0, opts.box_size, font_line_height(text_style)) - local o = BaseWidget.new(self, opts) - o.text = opts.text or "" - o.text_style = text_style - o.box_size = opts.box_size - o.checked = opts.checked or false - o.on_change = opts.on_change - local dark = (current_theme == "dark") - o.colors = { - border = opts.border_color or (dark and COLOR_WHITE or COLOR_BLACK), - bg = opts.bg_color or (dark and COLOR_BLACK or COLOR_WHITE), - tick = opts.tick_color or COLOR_SKY_BLUE, - text = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK) - } - return o -end - -function check_box:set_checked(v) - local nv = not not v - if nv == self.checked then return end - self.checked = nv - self:invalidate() - if self.on_change then - pcall(self.on_change, self.checked, self) - end -end - -function check_box:toggle() - self:set_checked(not self.checked) -end - -function check_box:draw(ctx) - local ax, ay = self:get_absolute_position() - local size = self.box_size - ctx:stroke_rect(ax, ay, size, size, self.colors.border) - ctx:fill_rect(ax + 2, ay + 2, size - 4, size - 4, self.colors.bg) - if self.checked then - ctx:fill_rect(ax + 4, ay + 4, size - 8, size - 8, self.colors.tick) - end - if self.text and self.text ~= "" then - local lh = ctx:line_height(self.text_style) - local ty = ay + (self.h - lh) // 2 - ctx:draw_text(self.text, ax + size + 10, ty, self.colors.text, self.text_style) - end -end - -function check_box:handle_event(evt, x, y) - if evt == "SINGLE_TAP" then - if x and y and self:contains_point(x, y) then - self:toggle() - return true - end - elseif evt == "TOUCH_DOWN" then - return self:contains_point(x or 0, y or 0) - end - return false -end - -ui.check_box = function(opts) - return check_box:new(opts) -end - --- 5.3 ComboBox -local dropdown_panel = setmetatable({}, { __index = BaseWidget }) -dropdown_panel.__index = dropdown_panel - -function dropdown_panel:new(owner) - local o = BaseWidget.new(self, { x = 0, y = 0, w = 0, h = 0 }) - o.owner = owner - o.visible = false - o.item_height = (owner and owner.dropdown_item_height) or 32 - o.padding = 4 - o.scroll_offset = 0 - o.max_scroll_offset = 0 - o.hovered_index = -1 - o.pressed_index = -1 - o.scroll_threshold = 10 - o.drag_start_y = 0 - o.scroll_base_offset = 0 - o.is_dragging = false - o._host_is_window = false - return o -end - -function dropdown_panel:update_layout() - local owner = self.owner - if not owner then return end - self.w = owner.w - local itemCount = #(owner.options or {}) - local maxVisible = math.max(1, math.min(itemCount, owner.max_visible_items or 5)) - self.visible_count = maxVisible - self.h = maxVisible * self.item_height + self.padding * 2 - self.max_scroll_offset = math.max(0, itemCount - maxVisible) - self.scroll_offset = clamp(self.scroll_offset, 0, self.max_scroll_offset) - if self._host_is_window and owner._parentWindow then - self.x = owner.x - self.y = owner.y + owner.h - else - local ax, ay = owner:get_absolute_position() - self.x = ax - self.y = ay + owner.h - end -end - -function dropdown_panel:draw(ctx) - if not self.visible then return end - local owner = self.owner - if not owner then return end - local ax, ay = self:get_absolute_position() - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - ctx:fill_rect(ax, ay, self.w, self.h, bg_color ) - ctx:stroke_rect(ax, ay, self.w, self.h, border_color) - local startIdx = self.scroll_offset + 1 - local endIdx = math.min(#owner.options, startIdx + (self.visible_count or owner.max_visible_items or 5) - 1) - local textStyle = owner.text_style - local lh = ctx:line_height(textStyle) - for i = startIdx, endIdx do - local itemY = ay + self.padding + (i - startIdx) * self.item_height - local isHovered = (i == self.hovered_index) - local isPressed = (i == self.pressed_index) - local isSelected = (i == owner.selected_index) - if isPressed then - ctx:fill_rect(ax + self.padding, itemY, self.w - self.padding * 2, self.item_height, COLOR_GRAY) - elseif isHovered then - ctx:fill_rect(ax + self.padding, itemY, self.w - self.padding * 2, self.item_height, COLOR_SKY_BLUE) - end - local labelColor = owner.colors.text - if isHovered then - labelColor = COLOR_WHITE - end - local text = owner:_normalize_option_text(owner.options[i]) - local textX = ax + self.padding + 6 - local textY = itemY + (self.item_height - lh) // 2 - if isSelected then - ctx:draw_text("*", textX, textY, labelColor, textStyle) - textX = textX + ctx:text_width("*", textStyle) + 4 - end - ctx:draw_text(text, textX, textY, labelColor, textStyle) - end - - -- 缁樺埗婊氬姩鎸囩ず鍣紙濡傛灉闇瑕佹粴鍔級 - if self.max_scroll_offset > 0 then - local scrollBarWidth = 4 - local scrollBarX = ax + self.w - scrollBarWidth - 2 - local scrollBarHeight = self.h - 4 - local scrollBarY = ay + 2 - - -- 婊氬姩鏉¤儗鏅 - ctx:fill_rect(scrollBarX, scrollBarY, scrollBarWidth, scrollBarHeight, COLOR_WHITE) - - -- 婊氬姩鏉℃粦鍧楋紙鍩轰簬婊氬姩鍋忕Щ璁＄畻锛 - local maxVisibleItems = self.visible_count or owner.max_visible_items or 5 - local totalItems = #owner.options - local thumbHeight = math.max(10, math.floor(scrollBarHeight * maxVisibleItems / totalItems)) - - -- 璁＄畻婊戝潡浣嶇疆锛氬熀浜庡綋鍓嶆粴鍔ㄥ亸绉婚噺 - local thumbY - if self.max_scroll_offset > 0 then - thumbY = scrollBarY + - math.floor((self.scroll_offset / self.max_scroll_offset) * (scrollBarHeight - thumbHeight)) - else - thumbY = scrollBarY - end - - ctx:fill_rect(scrollBarX, thumbY, scrollBarWidth, thumbHeight, border_color) - end -end - -function dropdown_panel:handle_event(evt, x, y) - if not (self.visible and self.owner and self.owner.enabled) then return false end - local inside = self:contains_point(x, y) - if not inside then - if evt == "SINGLE_TAP" or evt == "LONG_PRESS" then - self:hide() - return true - end - return false - end - local owner = self.owner - local ax, ay = self:get_absolute_position() - if evt == "TOUCH_DOWN" then - self.drag_start_y = y - self.scroll_base_offset = self.scroll_offset - self.is_dragging = false - local relativeY = y - ay - self.padding - local pressedIndex = math.floor(relativeY / self.item_height) + self.scroll_offset + 1 - if pressedIndex >= 1 and pressedIndex <= #owner.options then - self.pressed_index = pressedIndex - else - self.pressed_index = -1 - end - self._capture = true - self:invalidate() - return true - elseif (evt == "MOVE_X" or evt == "MOVE_Y") and self._capture then - local dy = y - self.drag_start_y - if not self.is_dragging and math.abs(dy) >= self.scroll_threshold then - self.is_dragging = true - self.pressed_index = -1 - self.hovered_index = -1 - self:invalidate() - end - if self.is_dragging then - local newOffset = self.scroll_base_offset + math.floor(-dy / self.item_height) - newOffset = clamp(newOffset, 0, self.max_scroll_offset) - if newOffset ~= self.scroll_offset then - self.scroll_offset = newOffset - self:invalidate() - end - else - local relativeY = y - ay - self.padding - local hoverIndex = math.floor(relativeY / self.item_height) + self.scroll_offset + 1 - if hoverIndex >= 1 and hoverIndex <= #owner.options then - if hoverIndex ~= self.hovered_index then - self.hovered_index = hoverIndex - self:invalidate() - end - else - if self.hovered_index ~= -1 then - self.hovered_index = -1 - self:invalidate() - end - end - end - return true - elseif evt == "SINGLE_TAP" and self._capture then - self._capture = false - local relativeY = y - ay - self.padding - local clickedIndex = math.floor(relativeY / self.item_height) + self.scroll_offset + 1 - self.pressed_index = -1 - if self.hovered_index ~= -1 then - self.hovered_index = -1 - self:invalidate() - end - if not self.is_dragging and clickedIndex >= 1 and clickedIndex <= #owner.options then - owner:set_selected(clickedIndex) - self:hide() - return true - end - self.is_dragging = false - return true - elseif evt == "LONG_PRESS" or evt == "SWIPE_LEFT" or evt == "SWIPE_RIGHT" or evt == "SWIPE_UP" or evt == "SWIPE_DOWN" then - self._capture = false - if self.pressed_index ~= -1 or self.hovered_index ~= -1 then - self.pressed_index = -1 - self.hovered_index = -1 - self:invalidate() - end - self.is_dragging = false - return true - end - return false -end - -function dropdown_panel:show() - local owner = self.owner - if not owner then return end - if self.visible then return end - self._host_is_window = owner._parentWindow ~= nil - if self._host_is_window and owner._parentWindow then - owner._parentWindow:add(self) - else - runtime.add(self) - end - self:update_layout() - self.visible = true - self.hovered_index = owner.selected_index or -1 - self.pressed_index = -1 - self.is_dragging = false - self:invalidate() -end - -function dropdown_panel:hide() - if not self.visible then return end - self.visible = false - self.hovered_index = -1 - self.pressed_index = -1 - self.is_dragging = false - self._capture = false - if self._host_is_window and self.parent then - self.parent:remove(self) - else - runtime.remove(self) - end - self._host_is_window = false -end - -local combo_box = setmetatable({}, { __index = BaseWidget }) -combo_box.__index = combo_box - -function combo_box:new(opts) - opts = opts or {} - opts.w = opts.width or opts.w or 200 - opts.h = opts.height or opts.h or 36 - local o = BaseWidget.new(self, opts) - o.options = opts.options or {} - o.selected_index = clamp(opts.selected or 1, 1, math.max(1, #o.options)) - o.placeholder = opts.placeholder or "璇烽夋嫨" - o.max_visible_items = opts.max_visible_items or 5 - o.dropdown_item_height = opts.item_height or 32 - o.text_style = { size = opts.text_size or opts.size or 12 } - local dark = (current_theme == "dark") - o.colors = { - bg = opts.bg_color or (dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG), - border = opts.border_color or (dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER), - text = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK), - arrow = opts.arrow_color or COLOR_SKY_BLUE - } - o.on_select = opts.on_select - o.pressed = false - o._dropdown = dropdown_panel:new(o) - return o -end - -function combo_box:_normalize_option_text(item) - if type(item) == "table" then - return tostring(item.text or item.value or "") - end - return tostring(item or "") -end - -function combo_box:set_options(options) - self.options = options or {} - if self.selected_index > #self.options then - self.selected_index = #self.options > 0 and #self.options or 1 - end - self:invalidate() -end - -function combo_box:set_selected(index) - if index < 1 or index > #self.options then return end - self.selected_index = index - self:invalidate() - if self.on_select then - local ok, err = pcall(self.on_select, self:get_selected_value(), index, self:get_selected_text()) - if not ok then - log.warn("ComboBox", "on_select error", err) - end - end -end - -function combo_box:get_selected_index() - return self.selected_index or 0 -end - -function combo_box:get_selected_text() - if not self.options or #self.options == 0 then - return self.placeholder - end - return self:_normalize_option_text(self.options[self.selected_index]) -end - -function combo_box:get_selected_value() - if not self.options or #self.options == 0 then - return nil - end - local item = self.options[self.selected_index] - if type(item) == "table" then - return item.value - end - return item -end - -function combo_box:draw(ctx) - if not self.visible then return end - local ax, ay = self:get_absolute_position() - local bg_color = self.pressed and COLOR_GRAY or self.colors.bg - ctx:fill_rect(ax, ay, self.w, self.h, bg_color ) - ctx:stroke_rect(ax, ay, self.w, self.h, self.colors.border) - local textPadding = 8 - local arrowSpace = 20 - local style = self.text_style - local maxTextWidth = math.max(0, self.w - textPadding * 2 - arrowSpace) - local text = self:get_selected_text() - text = fit_text_to_width(text, maxTextWidth, style, { ellipsis = true }) - local textY = ay + (self.h - ctx:line_height(style)) // 2 - ctx:draw_text(text, ax + textPadding, textY, self.colors.text, style) - if lcd and lcd.drawLine then - local arrowX = ax + self.w - arrowSpace // 2 - 4 - local arrowY = ay + self.h // 2 - if self._dropdown.visible then - lcd.drawLine(arrowX - 5, arrowY + 2, arrowX, arrowY - 2, self.colors.arrow) - lcd.drawLine(arrowX, arrowY - 2, arrowX + 5, arrowY + 2, self.colors.arrow) - else - lcd.drawLine(arrowX - 5, arrowY - 2, arrowX, arrowY + 2, self.colors.arrow) - lcd.drawLine(arrowX, arrowY + 2, arrowX + 5, arrowY - 2, self.colors.arrow) - end - end -end - -function combo_box:handle_event(evt, x, y) - if not self.enabled then return false end - local inside = self:contains_point(x or 0, y or 0) - if evt == "TOUCH_DOWN" and inside then - self.pressed = true - return true - elseif (evt == "MOVE_X" or evt == "MOVE_Y") and self.pressed then - self.pressed = inside - return true - elseif evt == "SINGLE_TAP" then - local was_pressed = self.pressed - self.pressed = false - if was_pressed and inside then - if self._dropdown.visible then - self._dropdown:hide() - else - self._dropdown:show() - end - return true - end - elseif evt == "LONG_PRESS" or evt == "SWIPE_LEFT" or evt == "SWIPE_RIGHT" or evt == "SWIPE_UP" or evt == "SWIPE_DOWN" then - self.pressed = false - end - return false -end - -function combo_box:on_unmount() - if self._dropdown and self._dropdown.visible then - self._dropdown:hide() - end -end - -ui.combo_box = function(opts) - return combo_box:new(opts) -end - --- 5.4 Label -local label = setmetatable({}, { __index = BaseWidget }) -label.__index = label - -function label:new(opts) - opts = opts or {} - local o = BaseWidget.new(self, opts) - o.text = tostring(opts.text or "") - o.text_style = { size = opts.size or opts.text_size } - local dark = (current_theme == "dark") - o.color = opts.color or (dark and COLOR_WHITE or COLOR_BLACK) - o.word_wrap = not not opts.word_wrap - o._autoWidth = not opts.w - o:_reflow() - return o -end - -function label:_reflow() - local style = self.text_style - if self.word_wrap and not self._autoWidth and self.w and self.w > 0 then - self._lines = wrap_text_lines(self.text, self.w, style) - local lh = font_line_height(style) - self.h = math.max(self.h or 0, #self._lines * lh) - else - self._lines = nil - if self._autoWidth then - self.w = font_measure(self.text, style) - end - self.h = font_line_height(style) - end -end - -function label:set_text(text) - self.text = tostring(text or "") - self:_reflow() - self:invalidate() -end - -function label:set_size(sz) - self.text_style.size = tonumber(sz) or self.text_style.size - self:_reflow() - self:invalidate() -end - -function label:draw(ctx) - if not self.visible then return end - local ax, ay = self:get_absolute_position() - local style = self.text_style - if self.word_wrap and self._lines then - local lh = ctx:line_height(style) - for i = 1, #self._lines do - ctx:draw_text(self._lines[i], ax, ay + (i - 1) * lh, self.color, style) - end - else - local text = self.text - if not self._autoWidth and self.w and self.w > 0 then - text = fit_text_to_width(text, self.w, style, { ellipsis = false }) - end - ctx:draw_text(text, ax, ay, self.color, style) - end -end - -function label:handle_event() - return false -end - -ui.label = function(opts) - return label:new(opts) -end - --- 5.5 Input -local input = setmetatable({}, { __index = BaseWidget }) -input.__index = input - -function input:new(opts) - opts = opts or {} - opts.w = opts.w or opts.width or 200 - opts.h = opts.h or opts.height or 36 - local o = BaseWidget.new(self, opts) - - -- 鏂囨湰灞炴 - o.text = opts.text or "" - o.placeholder = opts.placeholder or "璇疯緭鍏ユ枃鏈" - o.max_length = opts.max_length - - -- 杈撳叆绫诲瀷 - o.input_type = opts.input_type or "text" -- text/number/password/email - - -- 澶栬灞炴 - local dark = (current_theme == "dark") - o.bg_color = opts.bg_color or (dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG) - o.text_color = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK) - o.placeholder_color = opts.placeholder_color or COLOR_GRAY - o.border_color = opts.border_color or (dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER) - o.focused_border_color = opts.focused_border_color or COLOR_SKY_BLUE - o.text_style = { size = opts.text_size or opts.size or 12 } - - -- 鐘舵佸睘鎬 - o.focused = false - o.keyboard = nil -- 鍏宠仈鐨勯敭鐩樺疄渚 - - -- 鍥炶皟鍑芥暟 - o.on_text_changed = opts.on_text_changed - o.on_focus_changed = opts.on_focus_changed - o.on_confirm = opts.on_confirm - - -- 鍐呴儴鐘舵 - o._textOffset = 0 -- 鏂囨湰婊氬姩鍋忕Щ锛堢敤浜庨暱鏂囨湰鏄剧ず锛 - o._pressed = false -- TOUCH_DOWN 鏃剁殑瑙嗚鍙嶉 - - -- 閿洏閰嶇疆 - o.keyboard_click_effect = opts.keyboard_click_effect ~= false - - return o -end - --- 鏂囨湰鎿嶄綔鏂规硶 -function input:set_text(text) - local newText = tostring(text or "") - if self.max_length and #newText > self.max_length then - newText = string.sub(newText, 1, self.max_length) - end - - if self.text ~= newText then - self.text = newText - self:invalidate() - if self.on_text_changed then - pcall(self.on_text_changed, self.text, self) - end - end -end - -function input:get_text() - return self.text -end - --- 鍒悕鏂规硶锛堝吋瀹归┘宄板懡鍚嶏級 -function input:getText() - return self:get_text() -end - -function input:setText(text) - return self:set_text(text) -end - -function input:set_placeholder(text) - self.placeholder = tostring(text or "") - self:invalidate() -end - -function input:insert_text(text) - if not text or text == "" then return end - local newText = self.text .. text - self:set_text(newText) -end - -function input:delete_text(start_pos, length) - if not self.text or self.text == "" then return end - - length = length or 1 - start_pos = math.max(1, math.min(start_pos, #self.text + 1)) - local end_pos = math.min(start_pos + length - 1, #self.text) - - if start_pos > end_pos then return end - - local beforeText = string.sub(self.text, 1, start_pos - 1) - local afterText = string.sub(self.text, end_pos + 1) - self:set_text(beforeText .. afterText) -end - --- 鐒︾偣绠＄悊 -function input:focus() - if self.focused then return end - - -- 闅愯棌鍏朵粬 Input 鐨勯敭鐩橈紙纭繚鍚屾椂鍙湁涓涓 Input 鏈夌劍鐐癸級 - for i = 1, #runtime.roots do - local root = runtime.roots[i] - if root and root._isKeyboard and root ~= self.keyboard then - root:hide() - end - end - - self.focused = true - - -- 鍒涘缓閿洏瀹炰緥锛堟瘡涓 Input 鎷ユ湁鑷繁鐨 keyboard 瀹炰緥锛 - if not self.keyboard then - -- 閫氳繃 ui.keyboard 璁块棶锛坘eyboard 缁勪欢鍦ㄥ悗闈㈠畾涔夛級 - if ui.keyboard then - self.keyboard = ui.keyboard({ - input = self, - enable_click_effect = self.keyboard_click_effect - }) - self.keyboard._isKeyboard = true -- 鏍囪涓洪敭鐩樼粍浠 - end - end - - -- 鏄剧ず閿洏 - if self.keyboard then - self.keyboard:show() -- 閿洏浣嶇疆鍦 show() 鍐呴儴璁＄畻锛堝睆骞曚腑涓嬪榻愬簳杈癸級 - self.keyboard:set_input_type(self.input_type) - end - - -- 瑙﹀彂鐒︾偣鍙樺寲鍥炶皟 - if self.on_focus_changed then - pcall(self.on_focus_changed, true, self) - end -end - -function input:blur() - if not self.focused then return end - - self.focused = false - - -- 闅愯棌閿洏 - if self.keyboard and self.keyboard:is_visible() then - self.keyboard:hide() - end - - -- 瑙﹀彂鐒︾偣鍙樺寲鍥炶皟 - if self.on_focus_changed then - pcall(self.on_focus_changed, false, self) - end - - self:invalidate() -end - -function input:is_focused() - return self.focused -end - --- 缁樺埗鏂规硶 -function input:draw(ctx) - if not self.visible then return end - - local ax, ay = self:get_absolute_position() - - -- 缁樺埗鑳屾櫙 - ctx:fill_rect(ax, ay, self.w, self.h, self.bg_color) - - -- 缁樺埗杈规 - local border_color = (self.focused or self._pressed) and self.focused_border_color or self.border_color - ctx:stroke_rect(ax, ay, self.w, self.h, border_color) - - -- 鏂囨湰缁樺埗鍖哄煙 - local textPadding = 8 - local textX = ax + textPadding - local textY = ay + (self.h - ctx:line_height(self.text_style)) // 2 - local maxTextWidth = self.w - textPadding * 2 - - -- 纭畾瑕佹樉绀虹殑鏂囨湰 - local displayText = self.text - local text_color = self.text_color - - if not displayText or displayText == "" then - displayText = self.placeholder - text_color = self.placeholder_color - elseif self.input_type == "password" then - displayText = string.rep("*", #self.text) - end - - -- 澶勭悊闀挎枃鏈粴鍔ㄦ樉绀 - local textWidth = ctx:text_width(displayText, self.text_style) - if textWidth > maxTextWidth then - -- 浣跨敤 fit_text_to_width 宸ュ叿鍑芥暟鎴柇鏂囨湰 - displayText = fit_text_to_width(displayText, maxTextWidth, self.text_style, { ellipsis = false }) - end - - -- 缁樺埗鏂囨湰 - if displayText and displayText ~= "" then - ctx:draw_text(displayText, textX, textY, text_color, self.text_style) - end -end - --- 浜嬩欢澶勭悊 -function input:handle_event(evt, x, y) - if not self.enabled then return false end - - local inside = self:contains_point(x or 0, y or 0) - - if evt == "TOUCH_DOWN" then - if inside then - self._pressed = true - self:invalidate() - return true - end - elseif evt == "SINGLE_TAP" then - if inside then - self._pressed = false - self:focus() - self:invalidate() - return true - end - return false - end - - return false -end - -ui.input = function(opts) - return input:new(opts) -end - --- 5.6 Keyboard -local keyboard = setmetatable({}, { __index = BaseWidget }) -keyboard.__index = keyboard - -function keyboard:new(opts) - opts = opts or {} - local o = BaseWidget.new(self, { - x = 0, - y = 0, - w = opts.width or 300, - h = opts.height or 450, - visible = false - }) - - -- 鍏宠仈鐨 Input 缁勪欢 - o.input = opts.input - - -- 鏄惁鍚敤鐐瑰嚮鍙樿壊鏁堟灉 - o.enable_click_effect = opts.enable_click_effect ~= false - - -- 閿洏甯冨眬鍙傛暟 - o.keySize = 90 - o.keyGap = 0 - - -- 杈撳叆妯″紡 - o.isNumberMode = false - o.isPinyin9KeyMode = false - - -- 瀛楁瘝閿洏鎸夐敭鏄犲皠 - o.letterMappings = { - { text = "ABC", chars = { "a", "b", "c", "A", "B", "C" }, type = "letters", keyId = 1 }, - { text = "DEF", chars = { "d", "e", "f", "D", "E", "F" }, type = "letters", keyId = 2 }, - { text = "GHI", chars = { "g", "h", "i", "G", "H", "I" }, type = "letters", keyId = 3 }, - { text = "JKL", chars = { "j", "k", "l", "J", "K", "L" }, type = "letters", keyId = 4 }, - { text = "MNO", chars = { "m", "n", "o", "M", "N", "O" }, type = "letters", keyId = 5 }, - { text = "PQRS", chars = { "p", "q", "r", "s", "P", "Q", "R", "S" }, type = "letters", keyId = 6 }, - { text = "TUV", chars = { "t", "u", "v", "T", "U", "V" }, type = "letters", keyId = 7 }, - { text = "WXYZ", chars = { "w", "x", "y", "z", "W", "X", "Y", "Z" }, type = "letters", keyId = 8 }, - { text = "绌烘牸", chars = { " " }, type = "space" }, - { text = "delete", chars = {}, type = "delete" }, - { text = "NUM", chars = {}, type = "num" }, - { text = "涓/EN", chars = {}, type = "lang" } - } - - -- 鏁板瓧閿洏鎸夐敭鏄犲皠 - o.numberMappings = { - { text = "1", chars = { "1" }, type = "number" }, - { text = "2", chars = { "2" }, type = "number" }, - { text = "3", chars = { "3" }, type = "number" }, - { text = "4", chars = { "4" }, type = "number" }, - { text = "5", chars = { "5" }, type = "number" }, - { text = "6", chars = { "6" }, type = "number" }, - { text = "7", chars = { "7" }, type = "number" }, - { text = "8", chars = { "8" }, type = "number" }, - { text = "9", chars = { "9" }, type = "number" }, - { text = "delete", chars = {}, type = "delete" }, - { text = "0", chars = { "0" }, type = "number" }, - { text = "EN", chars = {}, type = "letter" } - } - - -- 鏍规嵁妯″紡璁剧疆鎸夐敭鏄犲皠 - o.keyMappings = o.letterMappings - - -- 鎸夐敭甯冨眬 - o.keyLayout = {} - o:build_key_layout() - - -- 鍊欓夊瓧绗︾浉鍏崇姸鎬 - o.selectedKey = nil - o.currentCandidates = {} - o._pressedCandidateIndex = nil - - -- 9閿嫾闊宠緭鍏ユā寮忕浉鍏冲睘鎬 - o.keySequence = {} -- 褰撳墠鎸夐敭搴忓垪锛堝瓨鍌ㄦ寜閿甀D锛1-8锛 - o.syllableCandidates = {} -- 闊宠妭鍊欓夊垪琛 - o.selectedSyllableIndex = 1 -- 褰撳墠閫変腑鐨勯煶鑺傜储寮 - o.currentSyllable = "" -- 褰撳墠閫変腑鐨勯煶鑺傦紙宸茬‘璁わ級 - o.pinyinCandidates = {} -- 鍊欓夊瓧鍒楄〃锛圲TF-8瀛楃涓叉暟缁勶級 - o.selectedCandidateIndex = 1 -- 褰撳墠閫変腑鐨勫欓夊瓧绱㈠紩 - o.syllablePageIndex = 1 -- 闊宠妭鍒楄〃褰撳墠椤电储寮 - o.candidatePageIndex = 1 -- 鍊欓夊瓧鍒楄〃褰撳墠椤电储寮曪紙姣忛〉8涓欓夊瓧锛 - o.pinyinModule = nil -- pinyin妯″潡缂撳瓨 - - -- 鍊欓夊尯鏄剧ず鐘舵 - o.displayStartIndex = 1 -- 棰勮妗嗘樉绀虹殑璧峰瀛楃浣嶇疆 - o._pressedSyllableIndex = nil -- 褰撳墠鎸変笅鐨勯煶鑺傜储寮 - o._backButtonPressed = false -- 杩斿洖鎸夐挳鎸変笅鐘舵 - - return o -end - -function keyboard:build_key_layout() - local start_x = self.x + 30 -- 宸︿晶棰勭暀30px锛堢敤浜庢湭鏉ラ煶鑺傞夋嫨鍖猴級 - local start_y = self.y + 95 -- 椤堕儴鎺у埗鏍50px + 鍊欓夊尯50px - local keySize = self.keySize - local keyGap = self.keyGap - - -- 鏋勫缓3脳4鎸夐敭甯冨眬 - self.keyLayout = {} - local keyIndex = 1 - - for row = 0, 3 do - for col = 0, 2 do - if keyIndex <= #self.keyMappings then - local key = { - x = start_x + col * (keySize + keyGap), - y = start_y + row * (keySize + keyGap), - w = keySize, - h = keySize, - text = self.keyMappings[keyIndex].text, - chars = self.keyMappings[keyIndex].chars, - type = self.keyMappings[keyIndex].type, - keyId = self.keyMappings[keyIndex].keyId, -- 鐢ㄤ簬鎷奸煶杈撳叆 - pressed = false - } - table.insert(self.keyLayout, key) - keyIndex = keyIndex + 1 - end - end - end -end - -function keyboard:show() - -- 璁＄畻閿洏浣嶇疆锛堝睆骞曚腑涓嬪榻愬簳杈癸級 - local sw = render_state.viewport_w - local sh = render_state.viewport_h - self.x = (sw - self.w) // 2 -- 姘村钩灞呬腑 - self.y = sh - self.h -- 搴曢儴瀵归綈 - - -- 閲嶆柊鏋勫缓鎸夐敭甯冨眬 - self:build_key_layout() - - self.visible = true - self.enabled = true - - -- 閲嶇疆鐘舵 - self.selectedKey = nil - self.currentCandidates = {} - self.displayStartIndex = 1 - - -- 閲嶇疆鎷奸煶杈撳叆鐘舵 - self.keySequence = {} - self.syllableCandidates = {} - self.selectedSyllableIndex = 1 - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.syllablePageIndex = 1 - self.candidatePageIndex = 1 - self._pressedSyllableIndex = nil - self._pressedCandidateIndex = nil - - -- 娣诲姞鍒拌繍琛屾椂鏍圭粍浠跺垪琛紙椤跺眰鏄剧ず锛 - runtime.add(self) -end - -function keyboard:hide() - self.visible = false - self.enabled = false - - -- 浠庤繍琛屾椂鏍圭粍浠跺垪琛ㄧЩ闄 - runtime.remove(self) - - -- 閫氱煡 Input 缁勪欢澶卞幓鐒︾偣 - if self.input and self.input.focused then - self.input:blur() - end -end - -function keyboard:is_visible() - return self.visible -end - -function keyboard:set_input_type(inputType) - -- 鏍规嵁杈撳叆绫诲瀷鍒囨崲閿洏妯″紡 - if inputType == "number" then - self:switch_to_number_mode() - else - self:switch_to_letter_mode() - end -end - -function keyboard:switch_to_number_mode() - if not self.isNumberMode then - self.isNumberMode = true - self.isPinyin9KeyMode = false -- 鍒囨崲鍒版暟瀛楁ā寮忔椂鍏抽棴鎷奸煶妯″紡 - self.keyMappings = self.numberMappings - self:build_key_layout() - -- 娓呴櫎鍊欓夊瓧绗︾姸鎬 - self.selectedKey = nil - self.currentCandidates = {} - self._pressedCandidateIndex = nil - -- 娓呴櫎鎷奸煶杈撳叆鐘舵 - self.keySequence = {} - self.syllableCandidates = {} - self.currentSyllable = "" - self.pinyinCandidates = {} - self:invalidate() - end -end - -function keyboard:switch_to_letter_mode() - if self.isNumberMode then - self.isNumberMode = false - -- 鍒囨崲鍒板瓧姣嶆ā寮忔椂涓嶆竻闄ゆ嫾闊虫ā寮忥紙淇濇寔褰撳墠鐘舵侊級 - self.keyMappings = self.letterMappings - self:build_key_layout() - -- 娓呴櫎鍊欓夊瓧绗︾姸鎬 - self.selectedKey = nil - self.currentCandidates = {} - self._pressedCandidateIndex = nil - self:invalidate() - end -end - --- 鍒囨崲鍒9閿嫾闊虫ā寮 -function keyboard:switch_to_pinyin_9key_mode() - self.isPinyin9KeyMode = true - self.keySequence = {} - self.syllableCandidates = {} - self.selectedSyllableIndex = 1 - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.syllablePageIndex = 1 - self.candidatePageIndex = 1 - self._pressedSyllableIndex = nil - - -- 鍔犺浇pinyin妯″潡锛堟ā缁勮嚜甯︾殑鏍稿績搴擄紝涓嶉渶瑕乺equire锛 - if not self.pinyinModule then - self.pinyinModule = pinyin - if not self.pinyinModule then - log.warn("Keyboard", "pinyin妯″潡涓嶅彲鐢") - self.isPinyin9KeyMode = false - return false - end - end - - self:invalidate() - return true -end - --- 澶勭悊9閿緭鍏 -function keyboard:on_pinyin_9key_input(keyId) - -- keyId: 1-8 瀵瑰簲 ABC-WXYZ - if not self.isPinyin9KeyMode then - return - end - - -- 闄愬埗鎸夐敭搴忓垪鏈澶ч暱搴︿负5锛堜腑鏂囨渶澶5涓煶鑺傛嫾闊筹級 - if #self.keySequence >= 5 then - log.warn("Keyboard", "鎸夐敭搴忓垪宸茶揪鏈澶ч暱搴5") - return - end - - -- 濡傛灉宸茬粡鏈夐変腑鐨勯煶鑺傦紝鍏堟竻闄ゅ欓夊瓧鐘舵 - if self.currentSyllable ~= "" then - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.candidatePageIndex = 1 - end - - -- 杩藉姞鍒版寜閿簭鍒 - table.insert(self.keySequence, keyId) - - -- 鏌ヨ鍙兘鐨勯煶鑺傦紙杈撳叆绗竴涓寜閿悗鍗冲紑濮嬫樉绀猴級 - if self.pinyinModule and self.pinyinModule.querySyllables then - local syllables = self.pinyinModule.querySyllables(self.keySequence) - self.syllableCandidates = syllables or {} - self.selectedSyllableIndex = 1 - self.syllablePageIndex = 1 - log.info("Keyboard", "鎸夐敭搴忓垪:", table.concat(self.keySequence, ","), - "闊宠妭鏁:", #self.syllableCandidates) - else - self.syllableCandidates = {} - end - - self:invalidate() -end - --- 閫夋嫨闊宠妭 -function keyboard:select_syllable(syllable) - if not self.isPinyin9KeyMode or not syllable then - return false - end - - -- 纭閫変腑鐨勯煶鑺 - self.currentSyllable = syllable - - -- 鏌ヨ璇ラ煶鑺傚搴旂殑鍊欓夊瓧锛堜娇鐢╭ueryUtf8鐩存帴杩斿洖UTF-8瀛楃涓叉暟缁勶級 - if self.pinyinModule and self.pinyinModule.queryUtf8 then - local chars = self.pinyinModule.queryUtf8(syllable) - self.pinyinCandidates = chars or {} - self.selectedCandidateIndex = 1 - self.candidatePageIndex = 1 - log.info("Keyboard", "閫変腑闊宠妭:", syllable, "鍊欓夊瓧鏁:", #self.pinyinCandidates) - else - self.pinyinCandidates = {} - end - - -- 娓呯┖鎸夐敭搴忓垪锛堝噯澶囪緭鍏ヤ笅涓涓瓧锛 - self.keySequence = {} - self.syllableCandidates = {} - self.selectedSyllableIndex = 1 - self.syllablePageIndex = 1 - - self:invalidate() - return true -end - --- 閫夋嫨鍊欓夊瓧 -function keyboard:select_candidate(index) - if not self.isPinyin9KeyMode then - return false - end - - -- index 鏄浉瀵圭储寮曪紙1-8锛夛紝闇瑕佽绠楀疄闄呯储寮曪紙鑰冭檻鍒嗛〉锛 - local actualIndex = (self.candidatePageIndex - 1) * 8 + index - - if actualIndex >= 1 and actualIndex <= #self.pinyinCandidates then - local char = self.pinyinCandidates[actualIndex] -- 鐩存帴浣跨敤UTF-8瀛楃涓 - - -- 鎻掑叆鍒拌緭鍏ユ - if self.input then - self.input:insert_text(char) - end - - -- 閲嶇疆鐘舵侊紝鍑嗗杈撳叆涓嬩竴涓瓧 - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.candidatePageIndex = 1 - - self:invalidate() - return true - end - - return false -end - --- 鍒犻櫎閿鐞嗭紙9閿ā寮忥級 -function keyboard:on_pinyin_9key_delete() - if not self.isPinyin9KeyMode then - return - end - - -- 濡傛灉姝ｅ湪閫夋嫨闊宠妭锛堟湁鎸夐敭搴忓垪鏈‘璁わ級 - if #self.keySequence > 0 then - -- 鍒犻櫎鏈鍚庝竴涓寜閿紝骞舵牴鎹墿浣欐寜閿簭鍒楅噸鏂版煡璇㈤煶鑺 - table.remove(self.keySequence, #self.keySequence) - if #self.keySequence > 0 then - if self.pinyinModule and self.pinyinModule.querySyllables then - local syllables = self.pinyinModule.querySyllables(self.keySequence) - self.syllableCandidates = syllables or {} - self.selectedSyllableIndex = 1 - self.syllablePageIndex = 1 - else - self.syllableCandidates = {} - self.selectedSyllableIndex = 1 - self.syllablePageIndex = 1 - end - else - -- 娌℃湁鎸夐敭浜嗭紝娓呯┖闊宠妭鍊欓 - self.syllableCandidates = {} - self.selectedSyllableIndex = 1 - self.syllablePageIndex = 1 - end - log.info("Keyboard", "鍒犻櫎涓浣嶆寜閿紝褰撳墠搴忓垪:", table.concat(self.keySequence, ",")) - self:invalidate() - return - end - - -- 濡傛灉宸查変腑闊宠妭骞跺湪閫夋嫨鍊欓夋眽瀛楅樁娈碉紝鍒犻櫎搴旀竻绌洪煶鑺傚苟鍥炲埌鎸夐敭杈撳叆 - if self.currentSyllable ~= "" then - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.candidatePageIndex = 1 - log.info("Keyboard", "娓呯┖宸查夐煶鑺傦紝杩斿洖鎸夐敭杈撳叆闃舵") - self:invalidate() - return - else - -- 娌℃湁閫夋嫨闊宠妭锛屽垹闄よ緭鍏ユ涓殑鏈鍚庝竴涓瓧绗 - if self.input then - local currentText = self.input:get_text() - if currentText and #currentText > 0 then - -- 鎸 UTF-8 瀛楃鍒犻櫎鏈鍚庝竴涓瓧绗︼紝閬垮厤娈嬬暀鍗婁釜瀛楄妭瀵艰嚧 "锟" - local lastStart = 1 - local i = 1 - while i <= #currentText do - local _, charLen = get_utf8_char(currentText, i) - lastStart = i - i = i + math.max(charLen, 1) - end - local deleteLen = #currentText - lastStart + 1 - self.input:delete_text(lastStart, deleteLen) - end - end - end -end - --- 缁樺埗鏂规硶 -function keyboard:draw(ctx) - if not self.visible then return end - - local ax, ay = self:get_absolute_position() - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - - -- 缁樺埗閿洏鑳屾櫙 - ctx:fill_rect(ax, ay, self.w, self.h, bg_color ) - ctx:stroke_rect(ax, ay, self.w, self.h, border_color) - - -- 缁樺埗椤堕儴鎺у埗鏍忥紙杩斿洖鎸夐挳鍜岄瑙堝尯锛 - self:draw_top_bar(ctx, ax, ay) - - -- 缁樺埗鍊欓夊尯锛堥煶鑺傛垨鍊欓夊瓧锛 - if self.isPinyin9KeyMode then - -- 鏄剧ず鍊欓夊瓧閫夋嫨鍖猴紙濮嬬粓鏄剧ず锛 - self:draw_pinyin_candidates(ctx, ax, ay) - else - -- 鏄剧ず棰勮鍖猴紙鑻辨枃妯″紡锛 - self:draw_preview_area(ctx, ax, ay) - -- 缁樺埗鍊欓夊瓧绗﹀尯锛堣嫳鏂囨ā寮忥級 - self:draw_candidate_area(ctx, ax, ay) - end - - -- 缁樺埗宸︿晶闊宠妭閫夋嫨鍖猴紙9閿嫾闊虫ā寮忥級 - if self.isPinyin9KeyMode then - self:draw_left_syllable_panel(ctx, ax, ay) - end - - -- 缁樺埗鎸夐敭 - for i = 1, #self.keyLayout do - self:draw_key(ctx, self.keyLayout[i]) - end -end - -function keyboard:draw_top_bar(ctx, ax, ay) - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - local button_bg_color = bg_color - - -- 杩斿洖鎸夐挳 - local backBtnX = ax + 10 - local backBtnY = ay + 5 - local backBtnW = 60 - local backBtnH = 35 - -- 妫鏌ヨ繑鍥炴寜閽槸鍚﹁鎸変笅 - local backBtnbg_color = (self.enable_click_effect and self._backButtonPressed) and COLOR_GRAY or button_bg_color - ctx:fill_rect(backBtnX, backBtnY, backBtnW, backBtnH, backBtnbg_color ) - ctx:stroke_rect(backBtnX, backBtnY, backBtnW, backBtnH, border_color) - local back_text = "杩斿洖" - local back_style = { size = 12 } - ctx:draw_text_in_rect_centered(backBtnX, backBtnY, backBtnW, backBtnH, back_text, { - color = text_color, - style = back_style - }) - - -- 杈撳叆棰勮鍖 - if self.input then - local previewX = backBtnX + backBtnW + 10 -- 棰勮妗嗚捣濮嬩綅缃 - local previewW = self.w - 90 -- 棰勮妗嗗搴︼細300px - 90px = 210px - local previewText = self.input:get_text() - - -- 澶勭悊棰勮鏂囨湰鏄剧ず锛堜笂鏂逛粎棰勮宸茶緭鍏ョ殑姹夊瓧/鏂囨湰锛屼笉鍐嶆樉绀洪煶鑺傦級 - local displayText = previewText - if displayText == "" then - displayText = "杈撳叆棰勮" - else - local style = { size = 12 } - local textWidth = ctx:text_width(displayText, style) - local maxTextWidth = previewW - 20 -- 宸﹀彸鍚勭暀10鍍忕礌 - if textWidth > maxTextWidth then - displayText = fit_text_to_width(displayText, maxTextWidth, style, { ellipsis = false }) - end - end - - -- 杈撳叆棰勮鍖猴細鏈夎竟妗嗭紝楂35px - local previewAreaY = backBtnY - local previewAreaH = backBtnH - ctx:fill_rect(previewX, previewAreaY, previewW, previewAreaH, button_bg_color ) - ctx:stroke_rect(previewX, previewAreaY, previewW, previewAreaH, border_color) - -- 宸﹀榻愮粯鍒讹紝宸﹁竟璺10px - local previewtext_color = (previewText == "") and COLOR_GRAY or text_color - ctx:draw_text(displayText, previewX + 10, previewAreaY + (previewAreaH - ctx:line_height({ size = 12 })) // 2, - previewtext_color, { size = 12 }) - - -- 鏂板锛氶煶鑺傞瑙堝尯锛堜綅浜庨瑙堝尯涓嬫柟5px锛岄珮20px锛屾棤杈规锛 - if self.isPinyin9KeyMode then - local syllablePreviewY = previewAreaY + previewAreaH - local syllableText = "" - if #self.keySequence > 0 then - -- 鏄剧ず鎸夐敭搴忓垪锛堝锛歛bc+mno锛 - local keyToLetters = { - [1] = "abc", - [2] = "def", - [3] = "ghi", - [4] = "jkl", - [5] = "mno", - [6] = "pqrs", - [7] = "tuv", - [8] = "wxyz" - } - local keyPreview = {} - for _, keyId in ipairs(self.keySequence) do - table.insert(keyPreview, keyToLetters[keyId] or "") - end - syllableText = table.concat(keyPreview, "+") - elseif self.currentSyllable ~= "" then - -- 鏄剧ず宸查変腑鐨勯煶鑺 - syllableText = self.currentSyllable - end - if syllableText ~= "" then - ctx:draw_text(syllableText, previewX + 10, - syllablePreviewY + (20 - ctx:line_height({ size = 12 })) // 2, - text_color, { size = 12 }) - end - end - end -end - -function keyboard:draw_preview_area(ctx, ax, ay) - if not self.input then return end - - local previewY = ay + 5 -- 鍜岃繑鍥炴寜閿钩琛 - local previewHeight = 35 -- 鍜岃繑鍥炴寜閿珮搴︿竴鑷 - local previewX = ax + 80 -- 棰勮妗嗚捣濮嬩綅缃紙杩斿洖閿悗锛 - local previewW = self.w - 90 -- 棰勮妗嗗搴 - - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - - -- 缁樺埗棰勮鍖鸿儗鏅 - ctx:fill_rect(previewX, previewY, previewW, previewHeight, bg_color ) - ctx:stroke_rect(previewX, previewY, previewW, previewHeight, border_color) - - -- 缁樺埗棰勮鏂囨湰 - local previewText = self.input:get_text() or "" - if previewText == "" then - previewText = "杈撳叆棰勮" - text_color = COLOR_GRAY - end - - -- 澶勭悊闀挎枃鏈 - local previewStyle = { size = 12 } - local textWidth = ctx:text_width(previewText, previewStyle) - local maxTextWidth = previewW - 20 -- 宸﹀彸鍚勭暀10鍍忕礌 - if textWidth > maxTextWidth then - previewText = fit_text_to_width(previewText, maxTextWidth, previewStyle, { ellipsis = false }) - end - - local textHeight = ctx:line_height(previewStyle) - local textX = previewX + 10 - local textY = previewY + (previewHeight - textHeight) // 2 - ctx:draw_text(previewText, textX, textY, text_color, previewStyle) -end - -function keyboard:draw_key(ctx, key) - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - local presse_dbg_color = COLOR_GRAY - - local btnbg_color = (self.enable_click_effect and key.pressed) and presse_dbg_color or bg_color - - ctx:fill_rect(key.x, key.y, key.w, key.h, btnbg_color ) - ctx:stroke_rect(key.x, key.y, key.w, key.h, border_color) - - -- -- 缁樺埗鎸夐敭鏂囨湰 - local displayText = key.text - - local textStyle = { size = 12 } - local textWidth = ctx:text_width(displayText, textStyle) - local textHeight = ctx:line_height(textStyle) - local textX = key.x + (key.w - textWidth) // 2 - local textY = key.y + (key.h - textHeight) // 2 - ctx:draw_text(displayText, textX, textY, text_color, textStyle) -end - --- 浜嬩欢澶勭悊 -function keyboard:handle_event(evt, x, y) - if not self.visible or not self.enabled then - return false - end - - local inside = self:contains_point(x or 0, y or 0) - - -- 妫鏌ユ槸鍚︾偣鍑讳簡杩斿洖鎸夐挳 - local backBtnX = self.x + 10 - local backBtnY = self.y + 5 - local backBtnW = 60 - local backBtnH = 40 - if x >= backBtnX and x < backBtnX + backBtnW and - y >= backBtnY and y < backBtnY + backBtnH then - if evt == "TOUCH_DOWN" then - self._backButtonPressed = true - self:invalidate() - return true - elseif evt == "SINGLE_TAP" then - self._backButtonPressed = false - self:hide() - return true - elseif evt == "MOVE_X" or evt == "MOVE_Y" then - self._backButtonPressed = false - self:invalidate() - return true - end - end - - -- 澶勭悊鍊欓夊瓧宸﹀彸缈婚〉鎸夐敭锛9閿嫾闊虫ā寮忥級 - if self.isPinyin9KeyMode and #self.pinyinCandidates > 0 then - if self:handle_candidate_arrow_touch(evt, x, y) then - return true - end - end - - -- 澶勭悊鍊欓夊瓧閫夋嫨鍖鸿Е鎽革紙9閿嫾闊虫ā寮忥級 - if self.isPinyin9KeyMode and #self.pinyinCandidates > 0 then - if self:handle_candidate_panel_touch(evt, x, y) then - return true - end - end - - -- 澶勭悊闊宠妭閫夋嫨鍖鸿Е鎽革紙9閿嫾闊虫ā寮忥級 - if self.isPinyin9KeyMode and #self.syllableCandidates > 0 and self.currentSyllable == "" then - if self:handle_syllable_panel_touch(evt, x, y) then - return true - end - end - - -- 澶勭悊鍊欓夊瓧绗﹂夋嫨锛堣嫳鏂囨ā寮忥級 - if not self.isPinyin9KeyMode and #self.currentCandidates > 0 then - local candidateY = self.y + 50 - local candidateHeight = 50 - local candidateBtnSize = 30 - - for i = 1, 10 do - local btnX = self.x + (i - 1) * candidateBtnSize - local btnY = candidateY + (candidateHeight - candidateBtnSize) // 2 - - if i <= #self.currentCandidates and - x >= btnX and x < btnX + candidateBtnSize and - y >= btnY and y < btnY + candidateBtnSize then - if evt == "TOUCH_DOWN" then - self._pressedCandidateIndex = i - self:invalidate() - return true - elseif evt == "SINGLE_TAP" then - local char = self.currentCandidates[i] - self:on_candidate_selected(char) - return true - elseif evt == "MOVE_X" or evt == "MOVE_Y" then - if self._pressedCandidateIndex ~= i then - self._pressedCandidateIndex = nil - self:invalidate() - end - return true - end - end - end - end - - -- 澶勭悊鎸夐敭鐐瑰嚮 - if evt == "TOUCH_DOWN" and inside then - -- 妫鏌ユ槸鍚︾偣鍑讳簡鎸夐敭 - for i = 1, #self.keyLayout do - local key = self.keyLayout[i] - if x >= key.x and x < key.x + key.w and - y >= key.y and y < key.y + key.h then - key.pressed = true - self._capture = true - self:invalidate() - return true - end - end - return true - elseif evt == "SINGLE_TAP" and self._capture then - -- 澶勭悊鎸夐敭閲婃斁 - for i = 1, #self.keyLayout do - local key = self.keyLayout[i] - if key.pressed then - key.pressed = false - self:on_key_pressed(key) - self:invalidate() - break - end - end - - self._capture = false - return true - elseif (evt == "MOVE_X" or evt == "MOVE_Y") and self._capture then - -- 鏇存柊鎸夐敭鎸変笅鐘舵 - for i = 1, #self.keyLayout do - local key = self.keyLayout[i] - local wasPressed = key.pressed - key.pressed = (x >= key.x and x < key.x + key.w and - y >= key.y and y < key.y + key.h) - if wasPressed ~= key.pressed then - self:invalidate() - end - end - return true - end - - return false -end - --- 澶勭悊鎸夐敭鎸変笅 -function keyboard:on_key_pressed(key) - if not key then return end - - -- 鍒犻櫎閿鐞 - if key.type == "delete" then - -- 9閿嫾闊虫ā寮忎笅鐨勫垹闄ら敭澶勭悊 - if self.isPinyin9KeyMode then - self:on_pinyin_9key_delete() - return - end - - -- 娓呴櫎鍊欓夊瓧绗︾姸鎬 - self.selectedKey = nil - self.currentCandidates = {} - self._pressedCandidateIndex = nil - - if self.input then - local currentText = self.input:get_text() - if currentText and #currentText > 0 then - -- 鎸 UTF-8 瀛楃鍒犻櫎鏈鍚庝竴涓瓧绗 - local lastStart = 1 - local i = 1 - while i <= #currentText do - local _, charLen = get_utf8_char(currentText, i) - lastStart = i - i = i + math.max(charLen, 1) - end - local deleteLen = #currentText - lastStart + 1 - self.input:delete_text(lastStart, deleteLen) - end - end - self:invalidate() - return - end - - -- 鏁板瓧/瀛楁瘝妯″紡鍒囨崲 - if key.type == "num" then - self:switch_to_number_mode() - return - elseif key.type == "letter" then - self:switch_to_letter_mode() - return - end - - -- 9閿嫾闊虫ā寮忎笅鐨勫瓧姣嶉敭澶勭悊 - if self.isPinyin9KeyMode and key.type == "letters" and key.keyId then - self:on_pinyin_9key_input(key.keyId) - return - end - - - -- 9閿嫾闊虫ā寮忎笅鐨勭┖鏍奸敭澶勭悊 - if self.isPinyin9KeyMode and key.type == "space" then - if self.input then - self.input:insert_text(" ") - end - return - end - - -- 璇█鍒囨崲閿紙涓/EN锛 - if key.type == "lang" then - if self.isPinyin9KeyMode then - -- 鍏抽棴鎷奸煶妯″紡锛屽垏鎹㈠埌鑻辨枃妯″紡 - self.isPinyin9KeyMode = false - -- 娓呴櫎鎷奸煶杈撳叆鐘舵 - self.keySequence = {} - self.syllableCandidates = {} - self.currentSyllable = "" - self.pinyinCandidates = {} - self.selectedCandidateIndex = 1 - self.syllablePageIndex = 1 - self.candidatePageIndex = 1 - self._pressedSyllableIndex = nil - -- 濡傛灉褰撳墠鏄暟瀛楁ā寮忥紝闇瑕佸厛鍒囨崲鍒板瓧姣嶆ā寮 - if self.isNumberMode then - self:switch_to_letter_mode() - end - else - -- 鍒囨崲鍒版嫾闊虫ā寮 - -- 濡傛灉褰撳墠鏄暟瀛楁ā寮忥紝闇瑕佸厛鍒囨崲鍒板瓧姣嶆ā寮 - if self.isNumberMode then - self:switch_to_letter_mode() - end - -- 灏濊瘯鍒囨崲鍒版嫾闊虫ā寮 - local success = self:switch_to_pinyin_9key_mode() - if not success then - log.warn("Keyboard", "鍒囨崲鍒版嫾闊虫ā寮忓け璐ワ紝pinyin妯″潡涓嶅彲鐢") - end - end - self:invalidate() - return - end - - -- 鏁板瓧/瀛楁瘝妯″紡鍒囨崲 - if key.type == "num" then - self:switch_to_number_mode() - return - elseif key.type == "letter" then - self:switch_to_letter_mode() - return - end - - -- 鏅氭寜閿鐞嗭紙瀛楁瘝/鏁板瓧锛 - if key.chars and #key.chars > 0 then - -- 娓呴櫎涔嬪墠鐨勫欓夊瓧绗︾姸鎬 - self.selectedKey = nil - self.currentCandidates = {} - self._pressedCandidateIndex = nil - - -- 澶勭悊鏁板瓧鐩存帴杈撳叆 - if key.type == "number" then - local char = key.chars[1] - if self.input then - self.input:insert_text(char) - end - -- 澶勭悊绌烘牸閿 - elseif key.type == "space" then - if self.input then - self.input:insert_text(" ") - end - else - -- 瀛楁瘝閿細鏄剧ず鍊欓夊瓧绗︼紝璁╃敤鎴烽夋嫨 - self.selectedKey = key - self.currentCandidates = key.chars - self:invalidate() - end - end -end - --- 澶勭悊鍊欓夊瓧绗﹂夋嫨 -function keyboard:on_candidate_selected(char) - if char and char ~= "" then - if self.input then - self.input:insert_text(char) - end - end - -- 娓呴櫎鍊欓夌姸鎬佸拰鎸夐敭鐘舵 - self.selectedKey = nil - self.currentCandidates = {} - self._pressedCandidateIndex = nil - - -- 娓呴櫎鎵鏈夋寜閿姸鎬 - for i = 1, #self.keyLayout do - self.keyLayout[i].pressed = false - end - - self:invalidate() -end - --- 缁樺埗鍊欓夊瓧绗﹀尯 -function keyboard:draw_candidate_area(ctx, ax, ay) - local candidateY = ay + 50 -- 鍊欓夊尯Y鍧愭爣锛堥瑙堝尯涓嬫柟10px锛 - local candidateHeight = 50 - local candidateBtnSize = 30 - - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - local presse_dbg_color = COLOR_GRAY - - -- 鍊欓夋寜閿浐瀹10涓紝浠庡乏鍒板彸鎺掑垪 - for i = 1, 10 do - local btnX = ax + (i - 1) * candidateBtnSize - local btnY = candidateY + (candidateHeight - candidateBtnSize) // 2 - - -- 鏍规嵁鏄惁鏈夊欓夊瓧绗﹀喅瀹氭樉绀哄唴瀹 - if i <= #self.currentCandidates then - local char = self.currentCandidates[i] - -- 妫鏌ュ欓夋寜閿槸鍚﹁鎸変笅 - local isPressed = (self._pressedCandidateIndex == i) - local btnbg_color = (self.enable_click_effect and isPressed) and presse_dbg_color or bg_color - - ctx:fill_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, btnbg_color ) - ctx:stroke_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, border_color) - - -- 缁樺埗鍊欓夊瓧绗︽枃鏈 - local textStyle = { size = 12 } - local textWidth = ctx:text_width(char, textStyle) - local textHeight = ctx:line_height(textStyle) - local textX = btnX + (candidateBtnSize - textWidth) // 2 - local textY = btnY + (candidateBtnSize - textHeight) // 2 - ctx:draw_text(char, textX, textY, text_color, textStyle) - else - -- 娌℃湁鍊欓夊瓧绗︽椂鏄剧ず绌烘寜閽 - ctx:fill_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, bg_color ) - ctx:stroke_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, border_color) - end - end -end - --- 澶勭悊鍊欓夊瓧宸﹀彸缈婚〉鎸夐敭 -function keyboard:handle_candidate_arrow_touch(evt, x, y) - local candidateY = self.y + 50 - local candidateHeight = 50 - local candidateBtnSize = 30 - local arrowW = candidateBtnSize - - -- 宸︿晶缈婚〉鎸夐敭锛堚啇锛 - local leftArrowX = self.x - local leftArrowY = candidateY + (candidateHeight - candidateBtnSize) // 2 - if x >= leftArrowX and x < leftArrowX + arrowW and - y >= leftArrowY and y < leftArrowY + candidateBtnSize then - if evt == "SINGLE_TAP" then - if self.candidatePageIndex > 1 then - self.candidatePageIndex = self.candidatePageIndex - 1 - self.selectedCandidateIndex = (self.candidatePageIndex - 1) * 8 + 1 - self:invalidate() - end - return true - end - end - - -- 鍙充晶缈婚〉鎸夐敭锛堚啋锛 - local rightArrowX = self.x + self.w - arrowW - local rightArrowY = leftArrowY - if x >= rightArrowX and x < rightArrowX + arrowW and - y >= rightArrowY and y < rightArrowY + candidateBtnSize then - if evt == "SINGLE_TAP" then - local maxPage = math.ceil(#self.pinyinCandidates / 8) - if self.candidatePageIndex < maxPage then - self.candidatePageIndex = self.candidatePageIndex + 1 - self.selectedCandidateIndex = (self.candidatePageIndex - 1) * 8 + 1 - self:invalidate() - end - return true - end - end - - return false -end - --- 澶勭悊鍊欓夊瓧閫夋嫨鍖鸿Е鎽 -function keyboard:handle_candidate_panel_touch(evt, x, y) - local candidateY = self.y + 50 - local candidateHeight = 50 - local candidateBtnSize = 30 - local arrowW = candidateBtnSize - local candidatestart_x = self.x + arrowW - - for i = 1, 8 do - local idx = (self.candidatePageIndex - 1) * 8 + i - local btnX = candidatestart_x + (i - 1) * candidateBtnSize - local btnY = candidateY + (candidateHeight - candidateBtnSize) // 2 - - if idx <= #self.pinyinCandidates and - x >= btnX and x < btnX + candidateBtnSize and - y >= btnY and y < btnY + candidateBtnSize then - if evt == "TOUCH_DOWN" then - self._pressedCandidateIndex = idx - self:invalidate() - return true - elseif evt == "SINGLE_TAP" then - self:select_candidate(i) -- 浼犲叆鐩稿绱㈠紩锛1-8锛 - self._pressedCandidateIndex = nil - return true - elseif evt == "MOVE_X" or evt == "MOVE_Y" then - if self._pressedCandidateIndex ~= idx then - self._pressedCandidateIndex = nil - self:invalidate() - end - return true - end - end - end - - return false -end - --- 澶勭悊闊宠妭閫夋嫨鍖鸿Е鎽 -function keyboard:handle_syllable_panel_touch(evt, x, y) - local syllableBtnSize = 30 - local syllableAreaX = self.x - local syllableAreaY = self.y + 95 - local start_y = syllableAreaY - - -- 涓婁竴椤垫寜閽紙绗竴涓皬鏍煎瓙锛 - local topBtnY = start_y - if x >= syllableAreaX and x < syllableAreaX + syllableBtnSize and - y >= topBtnY and y < topBtnY + syllableBtnSize then - if evt == "SINGLE_TAP" then - if self.syllablePageIndex > 1 then - self.syllablePageIndex = self.syllablePageIndex - 1 - self.selectedSyllableIndex = (self.syllablePageIndex - 1) * 10 + 1 - self:invalidate() - end - return true - end - end - - -- 涓棿10涓煶鑺傛寜閽紙浠庣浜屼釜灏忔牸瀛愬紑濮嬶級 - local syllablestart_y = start_y + syllableBtnSize - for i = 1, 10 do - local idx = (self.syllablePageIndex - 1) * 10 + i - local btnY = syllablestart_y + (i - 1) * syllableBtnSize - - if idx <= #self.syllableCandidates and - x >= syllableAreaX and x < syllableAreaX + syllableBtnSize and - y >= btnY and y < btnY + syllableBtnSize then - if evt == "TOUCH_DOWN" then - self._pressedSyllableIndex = idx - self:invalidate() - return true - elseif evt == "SINGLE_TAP" then - local syllable = self.syllableCandidates[idx] - self.selectedSyllableIndex = idx - self:select_syllable(syllable) - self._pressedSyllableIndex = nil - return true - elseif evt == "MOVE_X" or evt == "MOVE_Y" then - if self._pressedSyllableIndex ~= idx then - self._pressedSyllableIndex = nil - self:invalidate() - end - return true - end - end - end - - -- 涓嬩竴椤垫寜閽紙绗12涓皬鏍煎瓙锛 - local bottomBtnY = start_y + 11 * syllableBtnSize - if x >= syllableAreaX and x < syllableAreaX + syllableBtnSize and - y >= bottomBtnY and y < bottomBtnY + syllableBtnSize then - if evt == "SINGLE_TAP" then - local maxPage = math.ceil(#self.syllableCandidates / 10) - if self.syllablePageIndex < maxPage then - self.syllablePageIndex = self.syllablePageIndex + 1 - self.selectedSyllableIndex = (self.syllablePageIndex - 1) * 10 + 1 - self:invalidate() - end - return true - end - end - - return false -end - --- 缁樺埗宸︿晶闊宠妭閫夋嫨鍖 -function keyboard:draw_left_syllable_panel(ctx, ax, ay) - local syllableBtnSize = 30 -- 姣忎釜闊宠妭鎸夐挳澶у皬锛30x30锛 - local syllableAreaX = ax -- 宸︿晶棰勭暀鍖哄煙X鍧愭爣 - local syllableAreaY = ay + 95 -- 浠庢寜閿尯鍩熶笂鏂瑰紑濮嬶紙涓庡ぇ鏍煎瓙瀵归綈锛 - - -- 澶ф牸瀛愰珮搴︽槸90px锛4涓ぇ鏍煎瓙鎬婚珮搴360px - -- 12涓皬鏍煎瓙锛屾瘡涓30px锛屾诲叡360px锛屾濂藉榻 - -- 姣3涓皬鏍煎瓙瀵归綈涓涓ぇ鏍煎瓙锛90px = 3 * 30px锛 - local keySize = 90 -- 澶ф牸瀛愰珮搴 - local totalHeight = 4 * keySize -- 4涓ぇ鏍煎瓙鐨勬婚珮搴 = 360px - - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - local selecte_dbg_color = COLOR_SKY_BLUE - local selected_text_color = COLOR_WHITE - local presse_dbg_color = COLOR_GRAY - - -- 12涓皬鏍煎瓙锛屾瘡涓30px锛屾诲叡360px锛屾濂界瓑浜4涓ぇ鏍煎瓙鐨勯珮搴 - local start_y = syllableAreaY - - -- 1. 鏈涓婇潰鐨勪笂涓椤靛垏鎹㈡寜閿紙鈫戯級- 绗竴涓ぇ鏍煎瓙鐨勭涓涓皬鏍煎瓙浣嶇疆 - local topBtnY = start_y - ctx:fill_rect(syllableAreaX, topBtnY, syllableBtnSize, syllableBtnSize, bg_color ) - ctx:stroke_rect(syllableAreaX, topBtnY, syllableBtnSize, syllableBtnSize, border_color) - -- 浣跨敤 draw_arrow_icon 缁樺埗绠ご鍥炬爣 - draw_arrow_icon(syllableAreaX, topBtnY, syllableBtnSize, syllableBtnSize, "up", text_color) - - -- 2. 涓棿10涓煶鑺傞夋嫨鎸夐敭 - -- 浠庣浜屼釜灏忔牸瀛愬紑濮嬶紝姣3涓皬鏍煎瓙瀵瑰簲涓涓ぇ鏍煎瓙 - -- 绱㈠紩1鏄笂涓椤碉紝绱㈠紩2-11鏄10涓煶鑺傦紝绱㈠紩12鏄笅涓椤 - local syllablestart_y = start_y + syllableBtnSize -- 浠庣浜屼釜灏忔牸瀛愬紑濮 - for i = 1, 10 do - local idx = (self.syllablePageIndex - 1) * 10 + i - local btnY = syllablestart_y + (i - 1) * syllableBtnSize - - if idx <= #self.syllableCandidates then - local syllable = self.syllableCandidates[idx] - local isSelected = (idx == self.selectedSyllableIndex) - local isPressed = (self._pressedSyllableIndex == idx) - local btnbg_color - if self.enable_click_effect and isPressed then - btnbg_color = presse_dbg_color - elseif isSelected then - btnbg_color = selecte_dbg_color - else - btnbg_color = bg_color - end - local btntext_color = (isSelected or (self.enable_click_effect and isPressed)) and selected_text_color or - text_color - - ctx:fill_rect(syllableAreaX, btnY, syllableBtnSize, syllableBtnSize, btnbg_color ) - ctx:stroke_rect(syllableAreaX, btnY, syllableBtnSize, syllableBtnSize, border_color) - ctx:draw_text_in_rect_centered(syllableAreaX, btnY, syllableBtnSize, syllableBtnSize, syllable, { - color = btntext_color, - style = { size = 10 } - }) - else - -- 绌烘寜閽 - ctx:fill_rect(syllableAreaX, btnY, syllableBtnSize, syllableBtnSize, bg_color ) - ctx:stroke_rect(syllableAreaX, btnY, syllableBtnSize, syllableBtnSize, border_color) - end - end - - -- 3. 鏈涓嬮潰鐨勪笅涓椤靛垏鎹㈡寜閿紙鈫擄級- 绗4涓ぇ鏍煎瓙鐨勭3涓皬鏍煎瓙浣嶇疆锛堟渶鍚庝竴涓級 - local bottomBtnY = start_y + 11 * syllableBtnSize -- 绗12涓皬鏍煎瓙锛堢储寮12锛 - ctx:fill_rect(syllableAreaX, bottomBtnY, syllableBtnSize, syllableBtnSize, bg_color ) - ctx:stroke_rect(syllableAreaX, bottomBtnY, syllableBtnSize, syllableBtnSize, border_color) - draw_arrow_icon(syllableAreaX, bottomBtnY, syllableBtnSize, syllableBtnSize, "down", text_color) -end - --- 缁樺埗鍊欓夊瓧閫夋嫨鍖 -function keyboard:draw_pinyin_candidates(ctx, ax, ay) - local candidateY = ay + 50 -- 鍊欓夊尯Y鍧愭爣 - local candidateHeight = 50 - -- 涓枃鍊欓夊甫宸﹀彸缈婚〉锛氬乏鍙冲悇鍗1鏍(30px)锛屼腑闂8鏍煎欓 - local candidateBtnSize = 30 -- 姣忎釜鍊欓夋寜閽ぇ灏忥紙30x30锛 - - local dark = (current_theme == "dark") - local bg_color = dark and COLOR_WIN11_DARK_BUTTON_BG or COLOR_WIN11_LIGHT_BUTTON_BG - local border_color = dark and COLOR_WIN11_DARK_BUTTON_BORDER or COLOR_WIN11_LIGHT_BUTTON_BORDER - local text_color = dark and COLOR_WHITE or COLOR_BLACK - local selecte_dbg_color = COLOR_SKY_BLUE - local selected_text_color = COLOR_WHITE - local presse_dbg_color = COLOR_GRAY - - -- 宸︿晶鍒嗛〉鎸夐敭锛堚啇锛 - local arrowW = candidateBtnSize - local leftArrowX = ax - local leftArrowY = candidateY + (candidateHeight - candidateBtnSize) // 2 - ctx:fill_rect(leftArrowX, leftArrowY, arrowW, candidateBtnSize, bg_color ) - ctx:stroke_rect(leftArrowX, leftArrowY, arrowW, candidateBtnSize, border_color) - draw_arrow_icon(leftArrowX, leftArrowY, arrowW, candidateBtnSize, "left", text_color) - - -- 鍙充晶鍒嗛〉鎸夐敭锛堚啋锛 - local rightArrowX = ax + self.w - arrowW - local rightArrowY = leftArrowY - ctx:fill_rect(rightArrowX, rightArrowY, arrowW, candidateBtnSize, bg_color ) - ctx:stroke_rect(rightArrowX, rightArrowY, arrowW, candidateBtnSize, border_color) - draw_arrow_icon(rightArrowX, rightArrowY, arrowW, candidateBtnSize, "right", text_color) - - -- 鍊欓夋寜閿浐瀹8涓紙灞呬腑鍖哄煙锛屼粠 ax + arrowW 寮濮嬶級 - local candidatestart_x = ax + arrowW - for i = 1, 8 do - local idx = (self.candidatePageIndex - 1) * 8 + i - local btnX = candidatestart_x + (i - 1) * candidateBtnSize - local btnY = candidateY + (candidateHeight - candidateBtnSize) // 2 - - if idx <= #self.pinyinCandidates then - local char = self.pinyinCandidates[idx] -- 鐩存帴浣跨敤UTF-8瀛楃涓 - local isSelected = (idx == self.selectedCandidateIndex) - local isPressed = (self._pressedCandidateIndex == idx) - local btnbg_color - if self.enable_click_effect and isPressed then - btnbg_color = presse_dbg_color - elseif isSelected then - btnbg_color = selecte_dbg_color - else - btnbg_color = bg_color - end - local btntext_color = (isSelected or (self.enable_click_effect and isPressed)) and selected_text_color or - text_color - - ctx:fill_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, btnbg_color ) - ctx:stroke_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, border_color) - - -- 浣跨敤瀛椾綋娓叉煋鍊欓夊瓧锛堜紭鍏堜娇鐢╤zfont锛屽鏋滀笉鍙敤鍒欓檷绾у埌鍏朵粬瀛椾綋鍚庣锛 - -- 閫氳繃 ctx:draw_text 缁熶竴鎺ュ彛锛屽瓧浣撳悗绔湪 ui.init() 涓厤缃 - local textStyle = { size = 12 } - ctx:draw_text_in_rect_centered(btnX, btnY, candidateBtnSize, candidateBtnSize, char, { - color = btntext_color, - style = textStyle - }) - else - -- 绌烘寜閽 - ctx:fill_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, bg_color ) - ctx:stroke_rect(btnX, btnY, candidateBtnSize, candidateBtnSize, border_color) - end - end -end - --- 缁樺埗闊宠妭鍊欓夊尯锛堟樉绀哄湪鍊欓夊瓧閫夋嫨鍖虹殑浣嶇疆锛屼絾鍐呭涓嶅悓锛 -function keyboard:draw_syllable_candidates(ctx, ax, ay) - -- 闊宠妭鍊欓夊尯鏆傛椂涓嶅崟鐙粯鍒讹紝鐢卞乏渚ч煶鑺傞夋嫨鍖哄鐞 - -- 杩欓噷鍙互棰勭暀锛屽鏋滈渶瑕佹樉绀洪煶鑺傞瑙堝彲浠ュ湪杩欓噷瀹炵幇 -end - -ui.keyboard = function(opts) - return keyboard:new(opts) -end - --- 5.7 MessageBox -local message_box = setmetatable({}, { __index = BaseWidget }) -message_box.__index = message_box - -function message_box:new(opts) - opts = opts or {} - opts.w = opts.width or opts.w or 280 - opts.h = opts.height or opts.h or 160 - opts.x = opts.x or 20 - opts.y = opts.y or 40 - local o = BaseWidget.new(self, opts) - o.title = opts.title or "Info" - o.message = opts.message or "" - o.word_wrap = opts.word_wrap ~= false - local dark = (current_theme == "dark") - o.border_color = opts.border_color or (dark and COLOR_WHITE or COLOR_BLACK) - o.text_color = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK) - o.bg_color = opts.bg_color or (dark and COLOR_WIN11_DARK_DIALOG_BG or COLOR_WIN11_LIGHT_DIALOG_BG) - o.buttons = opts.buttons or { "OK" } - o.on_result = opts.on_result - o.text_style = { size = opts.text_size or opts.size or 12 } - o._buttons = {} - o:_layout_buttons() - o:_layout_message() - return o -end - -function message_box:_layout_buttons() - self._buttons = {} - local count = #self.buttons - if count == 0 then return end - local btnW = 80 - local gap = 12 - local total = count * btnW + (count - 1) * gap - local start_x = (self.w - total) // 2 - local btnY = self.h - 12 - 36 - for i = 1, count do - local label = tostring(self.buttons[i]) - local btn = button:new({ x = start_x, y = btnY, w = btnW, h = 36, text = label }) - btn.on_click = function() - if self.on_result then - local ok, err = pcall(self.on_result, label, self) - if not ok then - log.warn("MessageBox", "on_result error", err) - end - end - self.visible = false - end - self:add(btn) - self._buttons[#self._buttons + 1] = btn - start_x = start_x + btnW + gap - end -end - -function message_box:_layout_message() - self._msgPadding = 10 - self._msgstart_y = 36 - local reserved = (#self.buttons > 0) and (12 + 36) or 10 - self._msgHeight = self.h - reserved - self._msgstart_y - self._msgWidth = self.w - self._msgPadding * 2 - if self.word_wrap then - self._messageLines = wrap_text_lines(self.message, self._msgWidth, self.text_style) - local lh = font_line_height(self.text_style) - self._maxLines = math.max(1, math.floor(self._msgHeight / lh)) - else - self._messageLines = nil - end -end - -function message_box:set_message(message) - self.message = tostring(message or "") - self:_layout_message() - self:invalidate() -end - -function message_box:set_title(title) - self.title = tostring(title or "") - self:invalidate() -end - -function message_box:show() - self.visible = true - self.enabled = true - self:invalidate() -end - -function message_box:hide() - self.visible = false - self:invalidate() -end - -function message_box:draw(ctx) - if not self.visible then return end - local ax, ay = self:get_absolute_position() - ctx:fill_rect(ax, ay, self.w, self.h, self.bg_color) - ctx:stroke_rect(ax, ay, self.w, self.h, self.border_color) - ctx:draw_text(self.title, ax + 10, ay + 8, self.text_color, self.text_style) - local style = self.text_style - local lh = ctx:line_height(style) - local start_y = ay + self._msgstart_y - if self.word_wrap then - local lines = self._messageLines or wrap_text_lines(self.message, self._msgWidth, style) - local limit = math.min(#lines, self._maxLines or #lines) - for i = 1, limit do - ctx:draw_text(lines[i], ax + self._msgPadding, start_y + (i - 1) * lh, self.text_color, style) - end - else - local text = fit_text_to_width(self.message, self._msgWidth, style, { ellipsis = true }) - ctx:draw_text(text, ax + self._msgPadding, start_y, self.text_color, style) - end -end - -function message_box:handle_event() - if not (self.visible and self.enabled) then return false end - return true -end - -ui.message_box = function(opts) - return message_box:new(opts) -end - --- 5.6 Picture -local picture = setmetatable({}, { __index = BaseWidget }) -picture.__index = picture - -function picture:new(opts) - opts = opts or {} - local o = BaseWidget.new(self, opts) - o.src = opts.src - o.sources = opts.sources - o.index = opts.index or 1 - o.autoplay = not not opts.autoplay - o.interval = opts.interval or 1000 - o._last_switch = now_ms() - o._imageCache = {} - o._timer_id = nil - if o.w == 0 then o.w = 80 end - if o.h == 0 then o.h = 80 end - -- 濡傛灉鍚敤鑷姩鎾斁锛屽惎鍔ㄥ畾鏃跺櫒 - if o.autoplay and o.sources and #o.sources > 1 then - o:_start_autoplay_timer() - end - return o -end - -function picture:set_sources(list) - self.sources = list - self.index = 1 - -- 濡傛灉鍚敤鑷姩鎾斁涓旀湁澶氫釜鍥剧墖锛岄噸鍚畾鏃跺櫒 - if self.autoplay and list and #list > 1 then - self:_stop_autoplay_timer() - self:_start_autoplay_timer() - elseif not list or #list <= 1 then - self:_stop_autoplay_timer() - end -end - -function picture:next() - if not self.sources or #self.sources == 0 then return end - self.index = (self.index % #self.sources) + 1 -end - -function picture:prev() - if not self.sources or #self.sources == 0 then return end - self.index = (self.index - 2) % #self.sources + 1 -end - -function picture:_start_autoplay_timer() - if self._timer_id then return end - if not (self.sources and #self.sources > 1) then return end - - -- 浣跨敤瀹氭椂鍣ㄥ畾鏈熻Е鍙戝垏鎹 - local function autoplay_tick() - if not self.autoplay or not self.visible then - self:_stop_autoplay_timer() - return - end - if not self.sources or #self.sources <= 1 then - self:_stop_autoplay_timer() - return - end - - local t = now_ms() - if (t - self._last_switch) >= self.interval then - self:next() - self._last_switch = t - self:invalidate() - end - end - - -- 灏濊瘯浣跨敤 sys.timerLoopStart锛堝鏋滃彲鐢級 - if sys and sys.timerLoopStart then - -- 浣跨敤杈冪煭鐨勬鏌ラ棿闅旓紙100ms锛夛紝纭繚鍙婃椂鍝嶅簲 - self._timer_id = sys.timerLoopStart(autoplay_tick, math.min(100, self.interval)) - else - -- 濡傛灉娌℃湁瀹氭椂鍣 API锛屽洖閫鍒板師鏉ョ殑鏂瑰紡锛堝湪 draw 涓鏌ワ級 - -- 杩欑鎯呭喌涓嬮渶瑕佺‘淇 ui.render() 琚畾鏈熻皟鐢 - self._timer_id = true -- 鏍囪涓哄凡鍚敤锛屼絾浣跨敤 draw() 涓殑閫昏緫 - end -end - -function picture:_stop_autoplay_timer() - if self._timer_id and sys and sys.timerStop then - sys.timerStop(self._timer_id) - end - self._timer_id = nil -end - -function picture:play() - self.autoplay = true - if not self._timer_id then - self:_start_autoplay_timer() - end -end - -function picture:pause() - self.autoplay = false - self:_stop_autoplay_timer() -end - -function picture:draw() - if not self.visible then return end - local ax, ay = self:get_absolute_position() - local path = self.src - if self.sources and #self.sources > 0 then - path = self.sources[self.index] - end - - if type(path) == "string" and path ~= "" then - -- 浼樺厛浣跨敤鍥剧墖缂撳瓨锛坙cd.image2raw + lcd.draw锛 - if lcd and lcd.image2raw and lcd.draw then - local zbuff = ui.image_cache.get_zbuff(path) - if zbuff then - -- 浣跨敤 zbuff 缁樺埗锛宭cd.draw 浼氳嚜鍔ㄤ娇鐢 zbuff 鍐呴儴鐨 width 鍜 height - lcd.draw(ax, ay, nil, nil, zbuff) - return - end - end - end - - -- 缁樺埗鍗犱綅绗 - draw_image_placeholder(ax, ay, self.w, self.h, COLOR_GRAY, COLOR_WHITE) -end - -function picture:handle_event() - return false -end - -ui.picture = function(opts) - return picture:new(opts) -end - --- 5.7 ProgressBar -local progress_bar = setmetatable({}, { __index = BaseWidget }) -progress_bar.__index = progress_bar - -function progress_bar:new(opts) - opts = opts or {} - opts.w = opts.width or opts.w or 200 - opts.h = opts.height or opts.h or 24 - local o = BaseWidget.new(self, opts) - o.progress = math.max(0, math.min(100, opts.progress or 0)) - o.show_percentage = opts.show_percentage ~= false - o.text = opts.text - o.text_style = { size = opts.text_size or opts.size or 12 } - local dark = (current_theme == "dark") - o.background_color = opts.background_color or (dark and COLOR_GRAY or 0xC618) - o.progress_color = opts.progress_color or (dark and COLOR_BLUE or COLOR_SKY_BLUE) - o.border_color = opts.border_color or (dark and COLOR_WHITE or 0x8410) - o.text_color = opts.text_color or (dark and COLOR_WHITE or COLOR_BLACK) - return o -end - -function progress_bar:get_progress() - return self.progress -end - -function progress_bar:set_progress(value) - self.progress = math.max(0, math.min(100, value)) - self:invalidate() -end - -function progress_bar:set_text(text) - self.text = tostring(text or "") - self:invalidate() -end - -function progress_bar:draw(ctx) - if not self.visible then return end - local ax, ay = self:get_absolute_position() - ctx:fill_rect(ax + 1, ay + 1, self.w - 2, self.h - 2, self.background_color) - ctx:stroke_rect(ax, ay, self.w, self.h, self.border_color) - local innerWidth = math.max(0, self.w - 2) - local fillWidth = math.floor(innerWidth * (self.progress / 100)) - if fillWidth > 0 then - ctx:fill_rect(ax + 1, ay + 1, fillWidth, self.h - 2, self.progress_color) - end - if self.show_percentage or self.text then - local label = self.text or (tostring(self.progress) .. "%") - draw_text_in_rect_centered(ax, ay, self.w, self.h, label, { - color = self.text_color, - style = self.text_style, - padding = 2 - }) - end -end - -function progress_bar:handle_event() - return false -end - -ui.progress_bar = function(opts) - return progress_bar:new(opts) -end - --- 5.8 Window -local function window_theme_color() - return (current_theme == "dark") and COLOR_BLACK or COLOR_WHITE -end - -local function window_snap_axis(self, axis, mode) - local sc = self._scroll - if not sc then return false end - local pageSize, contentSize, offsetField - if axis == "x" then - pageSize = sc.page_width or self.w - contentSize = sc.content_width or self.w - offsetField = "offset_x" - if not (sc.direction == "horizontal" or sc.direction == "both") then - return false - end - else - pageSize = sc.page_height or self.h - contentSize = sc.content_height or self.h - offsetField = "offset_y" - if not (sc.direction == "vertical" or sc.direction == "both") then - return false - end - end - if pageSize <= 0 then return false end - local pages = math.max(1, math.floor((contentSize + pageSize - 1) / pageSize)) - local current = sc[offsetField] or 0 - local cur = math.floor((-(current) + pageSize / 2) / pageSize) - if mode == "increment" then - cur = cur + 1 - elseif mode == "decrement" then - cur = cur - 1 - elseif type(mode) == "number" then - cur = mode - end - if cur < 0 then cur = 0 end - if cur > pages - 1 then cur = pages - 1 end - local target = -cur * pageSize - if target ~= current then - sc[offsetField] = target - self:invalidate() - return true - end - return false -end - -local window = setmetatable({}, { __index = BaseWidget }) -window.__index = window - -function window:new(opts) - opts = opts or {} - opts.x = opts.x or 0 - opts.y = opts.y or 0 - opts.w = opts.w or render_state.viewport_w - opts.h = opts.h or render_state.viewport_h - local o = BaseWidget.new(self, opts) - o.background_color = opts.background_color or window_theme_color() - o.background_image = opts.background_image - o._scroll = nil - if opts.scroll then - o:enable_scroll(opts.scroll) - end - return o -end - -function window:add(child) - child = BaseWidget.add(self, child) - child._parentWindow = self - return child -end - -function window:remove(child) - for i = #self.children, 1, -1 do - if self.children[i] == child then - table.remove(self.children, i) - if child then - if child.on_unmount then - pcall(child.on_unmount, child) - end - child.parent = nil - child._parentWindow = nil - end - self:invalidate() - return true - end - end - return false -end - -function window:clear() - for i = #self.children, 1, -1 do - local child = self.children[i] - table.remove(self.children, i) - if child then - if child.on_unmount then - pcall(child.on_unmount, child) - end - child.parent = nil - child._parentWindow = nil - end - end - self:invalidate() -end - -function window:set_background_color(color) - self.background_color = color - self.background_image = nil - self:invalidate() -end - -function window:set_background_image(path) - self.background_image = path - self:invalidate() -end - -function window:_scroll_bounds() - local sc = self._scroll - if not sc then return 0, 0, 0, 0 end - local cw = sc.content_width or self.w - local ch = sc.content_height or self.h - local minX = math.min(0, self.w - cw) - local maxX = 0 - local minY = math.min(0, self.h - ch) - local maxY = 0 - return minX, maxX, minY, maxY -end - -function window:_handle_scroll_gesture(evt, x, y) - local sc = self._scroll - if not sc or not sc.enabled then - return false - end - if evt == "TOUCH_DOWN" then - sc.active = self:contains_point(x, y) - sc.dragging = false - sc.start_x = x - sc.start_y = y - sc.base_offset_x = sc.offset_x - sc.base_offset_y = sc.offset_y - sc.snapped = false - return false - elseif evt == "MOVE_X" or evt == "MOVE_Y" then - if not sc.active then return false end - sc.dragging = true - local dx = x - (sc.start_x or x) - local dy = y - (sc.start_y or y) - local minX, maxX, minY, maxY = self:_scroll_bounds() - local changed = false - local snap_horizontal = sc.snap_to_page and (sc.direction == "horizontal" or sc.direction == "both") - local snap_vertical = sc.snap_to_page and (sc.direction == "vertical" or sc.direction == "both") - if sc.direction == "horizontal" or sc.direction == "both" then - if not snap_horizontal then - local nx = clamp((sc.base_offset_x or 0) + dx, minX, maxX) - if nx ~= sc.offset_x then - sc.offset_x = nx - changed = true - end - end - end - if sc.direction == "vertical" or sc.direction == "both" then - if not snap_vertical then - local ny = clamp((sc.base_offset_y or 0) + dy, minY, maxY) - if ny ~= sc.offset_y then - sc.offset_y = ny - changed = true - end - end - end - if changed then - self:invalidate() - end - return true - elseif evt == "SINGLE_TAP" or evt == "LONG_PRESS" then - local was_dragging = sc.dragging - sc.active = false - sc.dragging = false - if was_dragging then - if sc.snap_to_page then - window_snap_axis(self, "x") - window_snap_axis(self, "y") - end - return true - end - elseif evt == "SWIPE_LEFT" or evt == "SWIPE_RIGHT" then - if sc.snap_to_page and (sc.direction == "horizontal" or sc.direction == "both") then - local mode = (evt == "SWIPE_LEFT") and "increment" or "decrement" - window_snap_axis(self, "x", mode) - sc.active = false - sc.dragging = false - sc.snapped = true - return true - end - elseif evt == "SWIPE_UP" or evt == "SWIPE_DOWN" then - if sc.snap_to_page and (sc.direction == "vertical" or sc.direction == "both") then - local mode = (evt == "SWIPE_DOWN") and "increment" or "decrement" - window_snap_axis(self, "y", mode) - sc.active = false - sc.dragging = false - sc.snapped = true - return true - end - end - return false -end - -function window:enable_scroll(opts) - opts = opts or {} - self._scroll = { - enabled = true, - direction = opts.direction or "vertical", - content_width = opts.content_width or opts.contentWidth or self.w, - content_height = opts.content_height or opts.contentHeight or self.h, - offset_x = 0, - offset_y = 0, - start_x = 0, - start_y = 0, - base_offset_x = 0, - base_offset_y = 0, - active = false, - dragging = false, - page_width = opts.page_width or self.w, - page_height = opts.page_height or self.h, - snap_to_page = opts.snap_to_page or false, - snapped = false - } -end - -function window:set_content_size(w, h) - if not self._scroll then - self:enable_scroll({}) - end - if w then self._scroll.content_width = w end - if h then self._scroll.content_height = h end -end - --- 鍚敤瀛愰〉闈㈢鐞 -function window:enable_subpage_manager(opts) - opts = opts or {} - if not self._managed then - self._managed = { - pages = {}, - back_event_name = opts.back_event_name or "NAV.BACK", - on_back = opts.on_back - } - if sys and sys.subscribe then - sys.subscribe(self._managed.back_event_name, function() - if self._managed.on_back then - pcall(self._managed.on_back) - end - local anyVisible = false - for _, pg in pairs(self._managed.pages) do - if pg and pg.visible ~= false then - anyVisible = true - break - end - end - if not anyVisible then - self.visible = true - self.enabled = true - self:invalidate() - end - end) - end - end - return self -end - --- 閰嶇疆瀛愰〉闈㈠伐鍘 -function window:configure_subpages(factories) - if not self._managed then - self:enable_subpage_manager() - end - self._managed.factories = self._managed.factories or {} - for k, v in pairs(factories or {}) do - self._managed.factories[k] = v - end - return self -end - --- 鏄剧ず瀛愰〉闈 -function window:show_subpage(name, factory) - if not self._managed then - error("enable_subpage_manager must be called before show_subpage") - end - -- 闅愯棌鎵鏈夊叾浠栧瓙椤甸潰 - for key, pg in pairs(self._managed.pages) do - if pg and pg.visible ~= false then - pg.visible = false - pg.enabled = false - pg:invalidate() - end - end - -- 濡傛灉瀛愰〉闈笉瀛樺湪锛屽垯鍒涘缓 - if not self._managed.pages[name] then - local f = factory - if not f and self._managed.factories then - f = self._managed.factories[name] - end - if not f then - error("no factory for subpage '" .. tostring(name) .. "'") - end - self._managed.pages[name] = f() - self._managed.pages[name]._parentWindow = self - runtime.add(self._managed.pages[name]) - end - -- 闅愯棌褰撳墠绐楀彛锛屾樉绀哄瓙椤甸潰 - self.visible = false - self.enabled = false - self._managed.pages[name].visible = true - self._managed.pages[name].enabled = true - self:invalidate() - self._managed.pages[name]:invalidate() -end - --- 杩斿洖涓婄骇椤甸潰 -function window:back() - if self._parentWindow then - self.visible = false - self.enabled = false - self:invalidate() - local parent = self._parentWindow - local anyVisible = false - if parent._managed and parent._managed.pages then - for _, pg in pairs(parent._managed.pages) do - if pg and pg.visible ~= false then - anyVisible = true - break - end - end - end - if not anyVisible then - parent.visible = true - parent.enabled = true - parent:invalidate() - end - end -end - --- 鍏抽棴瀛愰〉闈 -function window:close_subpage(name, opts) - if not self._managed or not self._managed.pages then - return false - end - opts = opts or {} - local pg = self._managed.pages[name] - if not pg then - return false - end - pg.visible = false - pg.enabled = false - pg:invalidate() - if opts.destroy == true then - runtime.remove(pg) - self._managed.pages[name] = nil - if collectgarbage then - collectgarbage("collect") - end - end - -- 妫鏌ユ槸鍚﹁繕鏈夊叾浠栧彲瑙佺殑瀛愰〉闈 - local anyVisible = false - for _, p in pairs(self._managed.pages) do - if p and p.visible ~= false then - anyVisible = true - break - end - end - if not anyVisible then - self.visible = true - self.enabled = true - self:invalidate() - end - return true -end - -function window:draw(ctx) - local ax, ay = self:get_absolute_position() - if self.background_image and lcd then - if lcd.drawImage then - lcd.drawImage(ax, ay, self.background_image) - elseif lcd.showImage then - lcd.showImage(ax, ay, self.background_image) - else - ctx:fill_rect(ax, ay, self.w, self.h, self.background_color) - end - else - ctx:fill_rect(ax, ay, self.w, self.h, self.background_color) - end - for i = 1, #self.children do - local child = self.children[i] - if child and child.visible ~= false and child.draw then - child:draw(ctx) - end - end -end - -function window:dispatch_pointer(evt, x, y) - if not self.visible or not self.enabled then return false end - local inside = self:contains_point(x, y) or (self._scroll and self._scroll.dragging) - if not inside and evt ~= "MOVE_X" and evt ~= "MOVE_Y" then - return false - end - if self:_handle_scroll_gesture(evt, x, y) then - return true - end - for i = #self.children, 1, -1 do - if self.children[i]:dispatch_pointer(evt, x, y) then - return true - end - end - return false -end - -ui.window = function(opts) - return window:new(opts) -end - --- ================================ --- 6. 瀵瑰鎺ュ彛瀵煎嚭 --- ================================ - -function ui.sw_init(opts) - opts = opts or {} - if opts.theme == "light" or opts.theme == "dark" then - current_theme = opts.theme - end - runtime.bindInput() -end - -function ui.theme() - return current_theme -end - -function ui.add(widget) - return runtime.add(widget) -end - -function ui.remove(widget) - return runtime.remove(widget) -end - -function ui.clear(color) - ui.render.background(color or COLOR_BLACK) -end - --- 宸插簾闄わ細棰勮1.8.0鍒犻櫎 -function ui.renderFrame() - return nil -- 杩斿洖绌哄 -end - --- 宸插簾闄わ細棰勮1.8.0鍒犻櫎 -function ui.refresh() - return nil -- 杩斿洖绌哄 -end - -return ui \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exfotawifi.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exfotawifi.lua deleted file mode 100644 index e34c446..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exfotawifi.lua +++ /dev/null @@ -1,229 +0,0 @@ ---[[ -@module exfotawifi -@summary 鐢ㄤ簬Air8000/8000A/8000W鍨嬪彿妯＄粍鑷姩鍗囩骇WIFI -@version 1.0.3 -@date 2025.9.23 -@author 鎷撴瘏鎭 -@usage -娉細浣跨敤鏃跺湪鍒涘缓鐨勪竴涓猼ask澶勭悊鍑芥暟涓洿鎺ヨ皟鐢╡xfotawifi.request()鍗冲彲寮濮嬫墽琛學iFi鍗囩骇浠诲姟 -鍗囩骇瀹屾瘯鍚庢渶濂藉彇娑堣皟鐢紝闃叉鍚庢湡鐗堟湰鍗囩骇杩囬珮瀵艰嚧绋嬪簭浣跨敤涓嶇ǔ瀹 - --- 鐢ㄦ硶瀹炰緥 -local exfotawifi = require("exfotawifi") - -local function fota_wifi_task() - -- ...姝ゅ鐪佺暐寰堝浠ｇ爜 - - local result = exfotawifi.request() - if result then - log.info("exfotawifi", "鍗囩骇浠诲姟鎵ц鎴愬姛") - else - log.info("exfotawifi", "鍗囩骇浠诲姟鎵ц澶辫触") - end - - -- ...姝ゅ鐪佺暐寰堝浠ｇ爜 -end - --- 鍚姩WiFi鑷姩鏇存柊浠诲姟 -sys.taskInit(fota_wifi_task) -]] -local exfotawifi = {} -local is_request = false -- 鏍囪鏄惁姝ｅ湪鎵цrequest浠诲姟 -local fota_result = false -- 璁板綍fota浠诲姟鐨勬墽琛岀粨鏋 - --- 鍒ゆ柇鏄惁涓虹┖ -local function is_nil(s) - return s == nil or s == "" -end - --- 鍒ゆ柇json鏄惁鍚堟硶 -local function is_json(str) - local success, result = pcall(json.decode, str) - return success and type(result) == "table" -end - --- 瑙ｆ瀽鏈嶅姟鍣ㄥ搷搴旂殑json鏁版嵁 -local function parse_response(body) - if not body or body == "" then - log.error("exfotawifi", "杩斿洖鐨刡ody涓虹┖") - return nil - end - - local success, json_body = pcall(json.decode, body) - if success and type(json_body) == "table" then - log.info("exfotawifi", "瑙ｆ瀽鏈嶅姟鍣ㄥ搷搴旀垚鍔") - return json_body - else - log.error("exfotawifi", "瑙ｆ瀽鏈嶅姟鍣ㄥ搷搴斿け璐ワ紝body鍐呭:", body) - return nil - end -end - --- 鍒ゆ柇鏄惁闇瑕佸崌绾э紝杩斿洖true鎴杅alse -local function need_fota(version, server_version) - local version_num = tonumber(version) - local server_version_num = tonumber(server_version) - if version_num < server_version_num then - return true - end - return false -end - --- 涓嬭浇鍗囩骇鏂囦欢锛屾敮鎸佹柇鐐圭画浼 -local function download_file(url) - local download_dir = "/http_download/" - local result, reason = io.mkdir(download_dir) - if not result then - log.error("download_file","io.mkdir error", reason) - end - - local file_path = download_dir.."fotawifi.bin" - local downloaded_size = 0 - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦紝鑾峰彇宸蹭笅杞界殑澶у皬 - if io.exists(file_path) then - downloaded_size = io.fileSize(file_path) - log.info("exfotawifi", "妫娴嬪埌鏈畬鎴愮殑涓嬭浇锛屽凡涓嬭浇澶у皬:", downloaded_size) - end - - -- 璁剧疆璇锋眰澶达紝鏀寔鏂偣缁紶 - local headers = {} - if downloaded_size > 0 then - headers["Range"] = "bytes=" .. downloaded_size .. "-" - end - - local code, headers, body = http.request("GET", url, headers, nil, nil).wait() - if code == 200 or code == 206 then - -- 寮濮嬪啓鍏ユ枃浠 - local file_mode = downloaded_size > 0 and "a+" or "w+" - local file = io.open(file_path, file_mode) - if file then - file:seek("end", downloaded_size) - file:write(body) - file:close() - - -- 鍒ゆ柇鏂囦欢鏄惁涓嬭浇瀹屾暣 - local file_size = io.fileSize(file_path) - local content_length = tonumber(headers["content-length"] or headers["Content-Length"]) - if file_size >= (content_length or file_size) then - log.info("exfotawifi", "涓嬭浇鍗囩骇鏂囦欢鎴愬姛,鏂囦欢璺緞:", file_path) - return file_path - else - log.info("exfotawifi", "涓嬭浇涓...褰撳墠澶у皬:", file_size, "鐩爣澶у皬:", content_length) - end - else - log.error("exfotawifi", "鏃犳硶鍒涘缓鏂囦欢") - -- 鍒犻櫎涓嶅畬鏁寸殑鏂囦欢 - os.remove(file_path) - end - else - log.error("exfotawifi", "涓嬭浇澶辫触,鐘舵佺爜:", code) - -- 鍒犻櫎涓嶅畬鏁寸殑鏂囦欢 - if io.exists(file_path) then - os.remove(file_path) - end - end - return nil -end - --- 鎵ц鍗囩骇鎿嶄綔 -local function fota_start(file_path) - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if not io.exists(file_path) then - log.error("exfotawifi", "鍗囩骇鏂囦欢涓嶅瓨鍦") - return false - end - - -- 妫鏌ユ枃浠跺ぇ灏忔槸鍚﹁秴杩256K (256 * 1024 Bytes) - local file_size = io.fileSize(file_path) - if file_size < 256 * 1024 then - log.error("exfotawifi", "鍗囩骇鏂囦欢澶у皬涓嶈冻256K锛屾枃浠跺ぇ灏:", file_size) - return false - end - - -- 鎵цairlink.sfota鎿嶄綔 - local result = airlink.sfota(file_path) - if result then - log.info("exfotawifi", "鍗囩骇鎴愬姛") - -- 閲婃斁鏂囦欢鍗犵敤鐨勭┖闂 - -- 鍥犱负sfota鏄紓姝ユ墽琛岀殑锛屾墍浠ヨ繖閲屼笉鑳界敤os.remove()鍒犻櫎鏂囦欢 - file_path = nil - return true - else - log.error("exfotawifi", "鍗囩骇澶辫触") - os.remove(file_path) - return false - end -end - - -function exfotawifi.request() - local result, ip, adapter = sys.waitUntil("IP_READY", 30000) - if result then - log.info("exfotawifi", "寮濮嬫墽琛屽崌绾т换鍔") - - if is_request then - log.warn("exfotawifi", "鍗囩骇浠诲姟姝ｅ湪鎵ц涓紝璇峰嬁閲嶅璋冪敤") - return false - end - - is_request = true - fota_result = false - - -- 鏋勫缓璇锋眰URL - local url = "http://wififota.openluat.com/air8000/update.json" - local imei = is_nil(mobile.imei()) and "鏈煡imei" or mobile.imei() - local version = is_nil(airlink.sver()) and "鏈煡鐗堟湰" or airlink.sver() - local muid = is_nil(mobile.muid()) and "鏈煡muid" or mobile.muid() - local hw = is_nil(hmeta.hwver()) and "鏈煡纭欢鐗堟湰" or hmeta.hwver() - local coreversion = is_nil(rtos.version()) and "鏈煡4G鍥轰欢鐗堟湰" or rtos.version() - local model = is_nil(hmeta.model()) and "鏈煡4G璁惧鍨嬪彿" or hmeta.model() - local request_url = string.format("%s?imei=%s&version=%s&muid=%s&hw=%s&coreversion=%s&model=%s", url, imei, version, muid, hw, coreversion, model) - - log.info("exfotawifi", "姝ｅ湪璇锋眰鍗囩骇淇℃伅, URL:", request_url) - - -- 鍙戦丠TTP璇锋眰鑾峰彇鏈嶅姟鍣ㄥ搷搴 - local code, headers, body = http.request("GET", request_url, {}, nil, {timeout = 30000}).wait() - if code == 200 then - log.info("exfotawifi", "鑾峰彇鏈嶅姟鍣ㄥ搷搴旀垚鍔") - -- 鎵撳嵃杩斿洖鐨刡ody鍐呭 - -- log.info("exfotawifi", "body:", body) - -- 瑙ｆ瀽鏈嶅姟鍣ㄥ搷搴旂殑json鏁版嵁 - local response = parse_response(body) - if response then - -- 鑾峰彇鏈嶅姟鍣ㄨ繑鍥炵殑鐗堟湰鍙峰拰涓嬭浇閾炬帴 - local server_version = response.version - local download_url = response.url - - -- 鑾峰彇鏈湴鐗堟湰鍙 - local local_version = airlink.sver() - - -- 鍒ゆ柇鏄惁闇瑕佸崌绾 - if need_fota(local_version, server_version) then - log.info("exfotawifi", "闇瑕佸崌绾, 鏈湴鐗堟湰:", local_version, "鏈嶅姟鍣ㄧ増鏈:", server_version) - -- 涓嬭浇鍗囩骇鏂囦欢 - local file_path = download_file(download_url) - if file_path then - -- 寮濮嬪崌绾 - fota_result = fota_start(file_path) - end - else - log.info("exfotawifi", "褰撳墠宸叉槸鏈鏂癢IFI鍥轰欢") - fota_result = true - end - else - log.error("exfotawifi", "瑙ｆ瀽鏈嶅姟鍣ㄥ搷搴斿け璐") - end - else - log.error("exfotawifi", "鑾峰彇鏈嶅姟鍣ㄥ搷搴斿け璐,鐘舵佺爜:", code) - end - else - log.error("褰撳墠姝ｅ湪鍗囩骇WIFI&钃濈墮鍥轰欢锛岃鎻掑叆鍙互涓婄綉鐨凷IM鍗″苟閲嶆柊鍚姩") - end - - -- 閲婃斁璇锋眰鏍囪 - is_request = false - return fota_result -end - -return exfotawifi diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exgnss.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exgnss.lua deleted file mode 100644 index 9b43261..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exgnss.lua +++ /dev/null @@ -1,1029 +0,0 @@ ---[[ -@module exgnss -@summary exgnss鎵╁睍搴 -@version 1.0 -@date 2025.07.16 -@author 鏉庢簮榫 -@usage --- 鐢ㄦ硶瀹炰緥 --- 娉ㄦ剰锛歟xgnss.lua閫傜敤鐨勪骇鍝佽寖鍥达紝鍙兘鐢ㄤ簬鍚堝畽鍐呴儴闆嗘垚GNSS鍔熻兘鐨勪骇鍝侊紝鐩墠鏈堿ir780EGH锛孉ir8000绯诲垪 --- 鎻愰啋: 鏈簱杈撳嚭鐨勫潗鏍,鍧囦负 WGS84 鍧愭爣绯 --- 濡傞渶瑕佸湪鍥藉唴鍦板浘浣跨敤, 瑕佽浆鎹㈡垚瀵瑰簲鍦板浘鐨勫潗鏍囩郴, 渚嬪 GCJ02 BD09 --- 鐩稿叧閾炬帴: https://lbsyun.baidu.com/index.php?title=coordinate --- 鐩稿叧閾炬帴: https://www.openluat.com/GPS-Offset.html - ---鍏充簬exgnss鐨勪笁绉嶅簲鐢ㄥ満鏅細 -exgnss.DEFAULT: ---- exgnss搴旂敤妯″紡1. --- 鎵撳紑gnss鍚庯紝gnss瀹氫綅鎴愬姛鏃讹紝濡傛灉鏈夊洖璋冨嚱鏁帮紝浼氳皟鐢ㄥ洖璋冨嚱鏁 --- 浣跨敤姝ゅ簲鐢ㄦā寮忚皟鐢╡xgnss.open鎵撳紑鐨勨済nss搴旂敤鈥濓紝蹇呴』涓诲姩璋冪敤exgnss.close --- 鎴栬卐xgnss.close_all鎵嶈兘鍏抽棴姝も済nss搴旂敤鈥,涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 --- 閫氫織鐐硅灏辨槸涓鐩存墦寮锛岄櫎闈炶嚜宸辨墜鍔ㄥ叧闂帀 - -exgnss.TIMERORSUC: ---- exgnss搴旂敤妯″紡2. --- 鎵撳紑gnss鍚庯紝濡傛灉鍦╣nss寮鍚渶澶ф椂闀垮埌杈炬椂锛屾病鏈夊畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝 --- 浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- 鎵撳紑gnss鍚庯紝濡傛灉鍦╣nss寮鍚渶澶ф椂闀垮唴锛屽畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝 --- 浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- 鎵撳紑gnss鍚庯紝鍦ㄨ嚜鍔ㄥ叧闂鈥済nss搴旂敤鈥濆墠锛屽彲浠ヨ皟鐢╡xgnss.close鎴栬 --- exgnss.close_all涓诲姩鍏抽棴姝も済nss搴旂敤鈥濓紝涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 --- 閫氫織鐐硅灏辨槸璁剧疆瑙勫畾鏃堕棿鎵撳紑锛屽鏋滆瀹氭椂闂村唴瀹氫綅鎴愬姛灏变細鑷姩鍏抽棴姝ゅ簲鐢紝 --- 濡傛灉娌℃湁瀹氫綅鎴愬姛锛屾椂闂村埌浜嗕篃浼氳嚜鍔ㄥ叧闂搴旂敤 - -exgnss.TIMER: ---- exgnss搴旂敤妯″紡3. --- 鎵撳紑gnss鍚庯紝鍦╣nss寮鍚渶澶ф椂闀挎椂闂村埌杈炬椂锛屾棤璁烘槸鍚﹀畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝 --- 浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- 鎵撳紑gnss鍚庯紝鍦ㄨ嚜鍔ㄥ叧闂鈥済nss搴旂敤鈥濆墠锛屽彲浠ヨ皟鐢╡xgnss.close鎴栬卐xgnss.close_all --- 涓诲姩鍏抽棴姝も済nss搴旂敤鈥濓紝涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 --- 閫氫織鐐硅灏辨槸璁剧疆瑙勫畾鏃堕棿鎵撳紑锛屾棤璁烘槸鍚﹀畾浣嶆垚鍔燂紝鍒颁簡鏃堕棿閮戒細鑷姩鍏抽棴姝ゅ簲鐢紝 --- 鍜岀浜岀鐨勫尯鍒湪浜庡畾浣嶆垚鍔熶箣鍚庝笉浼氳嚜鍔ㄥ叧闂紝鍒版椂闂翠箣鍚庢墠浼氳嚜鍔ㄥ叧闂 - -exgnss=require("exgnss") - -local function mode1_cb(tag) - log.info("TAGmode1_cb+++++++++",tag) - log.info("nmea", "rmc", json.encode(exgnss.rmc(2))) -end - -local function mode2_cb(tag) - log.info("TAGmode2_cb+++++++++",tag) - log.info("nmea", "rmc", json.encode(exgnss.rmc(2))) -end - -local function mode3_cb(tag) - log.info("TAGmode3_cb+++++++++",tag) - log.info("nmea", "rmc", json.encode(exgnss.rmc(2))) -end - -local function gnss_fnc() - local gnssotps={ - gnssmode=1, --1涓哄崼鏄熷叏瀹氫綅锛2涓哄崟鍖楁枟 - agps_enable=true, --鏄惁浣跨敤AGPS锛屽紑鍚疉GPS鍚庡畾浣嶉熷害鏇村揩锛屼細璁块棶鏈嶅姟鍣ㄤ笅杞芥槦鍘嗭紝鏄熷巻鏃舵晥鎬т负鍖楁枟1灏忔椂锛孏PS4灏忔椂锛岄粯璁や笅杞芥槦鍘嗙殑鏃堕棿涓1灏忔椂锛屽嵆涓灏忔椂鍐呭彧浼氫笅杞戒竴娆 - debug=true, --鏄惁杈撳嚭璋冭瘯淇℃伅 - -- uart=2, --浣跨敤鐨勪覆鍙,780EGH鍜8000榛樿涓插彛2 - -- uartbaud=115200, --涓插彛娉㈢壒鐜囷紝780EGH鍜8000榛樿115200 - -- bind=1, --缁戝畾uart绔彛杩涜GNSS鏁版嵁璇诲彇锛屾槸鍚﹁缃覆鍙ｈ浆鍙戯紝鎸囧畾涓插彛鍙 - -- rtc=false --瀹氫綅鎴愬姛鍚庤嚜鍔ㄨ缃甊TC true寮鍚紝flase鍏抽棴 - ----鍥犱负GNSS浣跨敤杈呭姪瀹氫綅鐨勯昏緫锛屾槸妯″潡涓嬭浇鏄熷巻鏂囦欢锛岀劧鍚庢妸鏁版嵁鍙戦佺粰GNSS鑺墖锛 - ----鑺墖瑙ｆ瀽鏄熷巻鏂囦欢闇瑕10-30s锛岄粯璁NSS浼氬紑鍚20s锛岃閫昏緫濡傛灉涓嶆墽琛岋紝浼氬鑷翠笅涓娆NSS寮鍚畾浣嶆槸鍐峰惎鍔紝 - ----瀹氫綅閫熷害鎱紝澶ф35S宸﹀彸锛屾墍浠ラ粯璁ゅ紑鍚紝濡傛灉鍙互鎺ュ彈涓嬩竴娆″畾浣嶆槸鍐峰惎鍔紝鍙互鎶奱uto_open璁剧疆鎴恌alse - ----闇瑕佹敞鎰忕殑鏄儹鍚姩鍦ㄥ畾浣嶆垚鍔熶箣鍚庯紝闇瑕佸啀寮鍚3s宸﹀彸鎵嶈兘淇濊瘉鏈鐨勬槦鍘嗚幏鍙栧畬鎴愶紝濡傛灉瀵瑰畾浣嶉熷害鏈夎姹傦紝寤鸿杩欎箞澶勭悊 - -- auto_open=false - } - --璁剧疆gnss鍙傛暟 - exgnss.setup(gnssotps) - --寮鍚痝nss搴旂敤 - exgnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) - exgnss.open(exgnss.DEFAULT,{tag="MODE2",cb=mode2_cb}) - exgnss.open(exgnss.TIMERORSUC,{tag="MODE3",val=60,cb=mode3_cb}) - sys.wait(40000) - log.info("鍏抽棴涓涓猤nss搴旂敤锛岀劧鍚庢煡鐪嬩笅鎵鏈夊簲鐢ㄧ殑鐘舵") - --鍏抽棴涓涓猤nss搴旂敤 - exgnss.close(exgnss.TIMER,{tag="MODE1"}) - --鏌ヨ3涓猤nss搴旂敤鐘舵 - log.info("gnss搴旂敤鐘舵1",exgnss.is_active(exgnss.TIMER,{tag="MODE1"})) - log.info("gnss搴旂敤鐘舵2",exgnss.is_active(exgnss.DEFAULT,{tag="MODE2"})) - log.info("gnss搴旂敤鐘舵3",exgnss.is_active(exgnss.TIMERORSUC,{tag="MODE3"})) - sys.wait(10000) - --鍏抽棴鎵鏈塯nss搴旂敤 - exgnss.close_all() - --鏌ヨ3涓猤nss搴旂敤鐘舵 - log.info("gnss搴旂敤鐘舵1",exgnss.is_active(exgnss.TIMER,{tag="MODE1"})) - log.info("gnss搴旂敤鐘舵2",exgnss.is_active(exgnss.DEFAULT,{tag="MODE2"})) - log.info("gnss搴旂敤鐘舵3",exgnss.is_active(exgnss.TIMERORSUC,{tag="MODE3"})) - --鏌ヨ鏈鍚庝竴娆″畾浣嶇粨鏋 - local loc= exgnss.last_loc() - if loc then - log.info("lastloc", loc.lat,loc.lng) - end -end - -sys.taskInit(gnss_fnc) - - ---GNSS瀹氫綅鐘舵佺殑娑堟伅澶勭悊鍑芥暟锛 -local function gnss_state(event, ticks) - -- event鍙栧兼湁 - -- "FIXED"锛歴tring绫诲瀷 瀹氫綅鎴愬姛 - -- "LOSE"锛 string绫诲瀷 瀹氫綅涓㈠け - -- "CLOSE": string绫诲瀷 GNSS鍏抽棴锛屼粎閰嶅悎浣跨敤gnss.lua鏈夋晥 - - -- ticks number绫诲瀷 鏄簨浠跺彂鐢熺殑鏃堕棿,涓鑸彲浠ュ拷鐣 - log.info("exgnss", "state", event) -end -sys.subscribe("GNSS_STATE",gnss_state) - -]] -local exgnss = {} ---gnss寮鍚爣蹇楋紝true琛ㄧず寮鍚姸鎬侊紝false鎴栬卬il琛ㄧず鍏抽棴鐘舵 -local openFlag ---gnss瀹氫綅鏍囧織锛宼rue琛ㄧず锛屽叾浣欒〃绀烘湭瀹氫綅 -local fixFlag=nil - ---涓插彛閰嶇疆 -local uart_baudrate = 115200 -local uart_id = 2 - ---gnss 鐨勪覆鍙ｇ嚎绋嬫槸鍚﹀湪宸ヤ綔锛 -local taskFlag=false - -local agpsFlag=false - -local timeres=false - ---淇濆瓨缁忕含搴﹀埌鏂囦欢鍖 -local function save_loc(lat,lng) - if not lat or not lng then - if libgnss.isFix() then - local rmc = libgnss.getRmc(0) - if rmc then - lat, lng = rmc.lat, rmc.lng - end - end - end - if lat and lng then - -- log.info("寰呬繚瀛樼殑GPS浣嶇疆", lat, lng) - local locStr = string.format('{"lat":%.5f,"lng":%.5f}', lat, lng) - -- log.info("gnss", "淇濆瓨GPS浣嶇疆", locStr) - io.writeFile("/hxxtloc", locStr) - end - if timeres then - local now = os.time() - io.writeFile("/hxxt_tm", tostring(now)) - timeres=false - -- log.info("now", now) - end -end - -local tid -local timetid -local function timer_fnc() - timeres=true - local now = os.time() - io.writeFile("/hxxt_tm", tostring(now)) -end - -sys.subscribe("GNSS_STATE", function(event) - -- log.info("libagps","libagps is "..event) - if event == "FIXED" then - save_loc() - tid=sys.timerLoopStart(save_loc,600000) - timetid=sys.timerStart(timer_fnc,10000) - if exgnss.opts.rtc==true then - sys.publish("NTP_UPDATE") - end - elseif event == "LOSE" or event == "CLOSE" then - -- log.info("libagps","libagps is close") - sys.timerStop(tid) - sys.timerStop(timetid) - end -end) - ---agps鎿嶄綔锛岃仈缃戣闂湇鍔″櫒鑾峰彇鏄熷巻鏁版嵁 -local function agps() - local lat, lng - - --姝ら昏緫鍦╝gps瀹氫綅鎴愬姛涔嬪悗锛岃繕浼氱户缁紑鍚10s-15s锛 - --鍘熷洜鏄洜涓哄鏋滅涓娆″喎鍚姩涔嬪悗锛屽畾浣嶆垚鍔熶箣鍚庯紝 - --濡傛灉鐩存帴鍏抽棴gnss浼氬鑷磄nss鑺墖鐨勬槦鍘嗘病鏈夎В鏋愬畬姣曪紝浼氬奖鍝嶄笅涓娆＄殑瀹氫綅涓哄喎鍚姩 - --濡傛灉瀵瑰姛鑰楁湁闇姹傦紝闇瑕佸畾浣嶅揩锛屽彲浠ユ瘡娆￠兘浣跨敤agps锛屼笉闇瑕佽繖鍙ワ紝鐩存帴灞忚斀鎺夊嵆鍙 - --浠ｄ环鏄瘡娆″畾浣嶉兘浼氳繘琛屽熀绔欏畾浣嶏紝 - if exgnss.opts.auto_open~= false then - log.info("libagps","libagps is open") - exgnss.open(exgnss.TIMER,{tag="libagps",val=20}) - else - - end - -- 鍒ゆ柇鏄熷巻鏃堕棿鍜屼笅杞芥槦鍘 - local now = os.time() - local agps_time = tonumber(io.readFile("/hxxt_tm") or "0") or 0 - log.info("os.time",now) - log.info("agps_time",agps_time) - if now - agps_time > 3600 or io.fileSize("/hxxt.dat") < 1024 then - local url = exgnss.opts.url - if not exgnss.opts.url then - if exgnss.opts.gnssmode and 2 == exgnss.opts.gnssmode then - -- 鍗曞寳鏂 - url = "http://download.openluat.com/9501-xingli/HXXT_BDS_AGNSS_DATA.dat" - else - url = "http://download.openluat.com/9501-xingli/HXXT_GPS_BDS_AGNSS_DATA.dat" - end - end - local code = http.request("GET", url, nil, nil, {dst="/hxxt.dat"}).wait() - if code and code == 200 then - log.info("exgnss.opts", "涓嬭浇鏄熷巻鎴愬姛", url) - io.writeFile("/hxxt_tm", tostring(now)) - else - log.info("exgnss.opts", "涓嬭浇鏄熷巻澶辫触", code) - end - else - log.info("exgnss.opts", "鏄熷巻涓嶉渶瑕佹洿鏂", now - agps_time) - end - --杩涜鍩虹珯瀹氫綅锛岀粰鍒癵nss鑺墖涓涓ぇ姒傜殑浣嶇疆 - if mobile then - local lbsLoc2 = require("lbsLoc2") - lat, lng = lbsLoc2.request(5000) - -- local lat, lng, t = lbsLoc2.request(5000, "bs.openluat.com") - -- log.info("lbsLoc2", lat, lng) - if lat and lng then - lat = tonumber(lat) - lng = tonumber(lng) - log.info("lbsLoc2", lat, lng) - -- 杞崲鍗曚綅 - local lat_dd,lat_mm = math.modf(lat) - local lng_dd,lng_mm = math.modf(lng) - lat = lat_dd * 100 + lat_mm * 60 - lng = lng_dd * 100 + lng_mm * 60 - end - elseif wlan then - -- wlan.scan() - -- sys.waitUntil("WLAN_SCAN_DONE", 5000) - end - --鑾峰彇鍩虹珯瀹氫綅澶辫触鍒欎娇鐢ㄦ湰鍦颁箣鍓嶄繚瀛樼殑浣嶇疆 - if not lat then - -- 鑾峰彇鏈鍚庣殑鏈湴浣嶇疆 - local locStr = io.readFile("/hxxtloc") - if locStr then - local jdata = json.decode(locStr) - if jdata and jdata.lat then - lat = jdata.lat - lng = jdata.lng - end - end - end - local gps_uart_id = uart_id - - -- 鍐欏叆鏄熷巻 - local agps_data = io.readFile("/hxxt.dat") - if agps_data and #agps_data > 1024 then - log.info("exgnss.opts", "鍐欏叆鏄熷巻鏁版嵁", "闀垮害", #agps_data) - for offset=1,#agps_data,512 do - log.info("exgnss", "AGNSS", "write >>>", #agps_data:sub(offset, offset + 511)) - uart.write(gps_uart_id, agps_data:sub(offset, offset + 511)) - sys.wait(100) -- 绛100ms鍙嶈屾洿鎴愬姛 - end - -- uart.write(gps_uart_id, agps_data) - else - log.info("exgnss.opts", "娌℃湁鏄熷巻鏁版嵁") - return - end - -- "lat":23.4068813,"min":27,"valid":true,"day":27,"lng":113.2317505 - --濡傛灉娌℃湁缁忕含搴︾殑璇濓紝瀹氫綅鏃堕棿浼氬彉闀匡紝澶ф10-20s宸﹀彸 - if not lat or not lng then - -- lat, lng = 23.4068813, 113.2317505 - log.info("exgnss.opts", "娌℃湁GPS鍧愭爣", lat, lng) - return --鏆傛椂涓嶅啓鍏ュ弬鑰冧綅缃 - else - log.info("exgnss.opts", "鍐欏叆GPS鍧愭爣", lat, lng) - end - --鍐欏叆鏃堕棿 - local date = os.date("!*t") - if date.year > 2023 then - local str = string.format("$AIDTIME,%d,%d,%d,%d,%d,%d,000", date["year"], date["month"], date["day"], - date["hour"], date["min"], date["sec"]) - log.info("exgnss.opts", "鍙傝冩椂闂", str) - uart.write(gps_uart_id, str .. "\r\n") - sys.wait(20) - end - -- 鍐欏叆鍙傝冧綅缃 - local str = string.format("$AIDPOS,%.7f,%s,%.7f,%s,1.0\r\n", - lat > 0 and lat or (0 - lat), lat > 0 and 'N' or 'S', - lng > 0 and lng or (0 - lng), lng > 0 and 'E' or 'W') - log.info("exgnss.opts", "鍐欏叆AGPS鍙傝冧綅缃", str) - uart.write(gps_uart_id, str) - - -- 缁撴潫 - exgnss.opts.agps_tm = now - agpsFlag=true -end - ---鎵цagps鎿嶄綔鍒ゆ柇 -local function is_agps() - -- 濡傛灉涓嶆槸寮哄埗鍐欏叆AGPS淇℃伅, 鑰屼笖鏄凡缁忓畾浣嶆垚鍔熺殑鐘舵,閭ｅ氨娌″繀瑕佷簡 - if libgnss.isFix() then return end - -- 鍏堝垽鏂竴涓嬫椂闂 - while not socket.adapter(socket.dft()) do - log.warn("airlbs_multi_cells_wifi_func", "wait IP_READY", socket.dft()) - -- 鍦ㄦ澶勯樆濉炵瓑寰呴粯璁ょ綉鍗¤繛鎺ユ垚鍔熺殑娑堟伅"IP_READY" - -- 鎴栬呯瓑寰1绉掕秴鏃堕鍑洪樆濉炵瓑寰呯姸鎬; - -- 娉ㄦ剰锛氭澶勭殑1000姣瓒呮椂涓嶈淇敼鐨勬洿闀匡紱 - -- 鍥犱负褰撲娇鐢╡xnetif.set_priority_order閰嶇疆澶氫釜缃戝崱杩炴帴澶栫綉鐨勪紭鍏堢骇鏃讹紝浼氶殣寮忕殑淇敼榛樿浣跨敤鐨勭綉鍗 - -- 褰揺xnetif.set_priority_order鐨勮皟鐢ㄦ椂搴忓拰姝ゅ鐨剆ocket.adapter(socket.dft())鍒ゆ柇鏃跺簭鏈夊彲鑳戒笉鍖归厤 - -- 姝ゅ鐨1绉掞紝鑳藉淇濊瘉锛屽嵆浣挎椂搴忎笉鍖归厤锛屼篃鑳1绉掗挓閫鍑洪樆濉炵姸鎬侊紝鍐嶅幓鍒ゆ柇socket.adapter(socket.dft()) - local result=sys.waitUntil("IP_READY", 30000) - if result == false then - log.warn("gnss_agps", "wait IP_READY timeout") - return - end - end - if not exgnss.opts.agps_tm then - socket.sntp() - sys.waitUntil("NTP_UPDATE", 5000) - end - local now = os.time() - local agps_time = tonumber(io.readFile("/hxxt_tm") or "0") or 0 - -- if ((not exgnss.opts.agps_tm) and (now - agps_time > 300)) or now - agps_time > 3600 then - if not exgnss.opts.agps_tm or now - agps_time > 3600 then - -- 鎵цAGPS - log.info("exgnss.opts", "寮濮嬫墽琛孉GPS") - sys.taskInit(agps) - else - log.info("exgnss.opts", "鏆備笉闇瑕佸啓鍏GPS") - end -end - - ---鎵撳紑gnss锛屽唴閮ㄥ嚱鏁颁娇鐢紝涓嶆帹鑽愮粰鑴氭湰灞備娇鐢 -local function fnc_open() - if openFlag then return end - libgnss.clear() -- 娓呯┖鏁版嵁,鍏煎垵濮嬪寲 - uart.setup(uart_id, uart_baudrate) - if exgnss.opts.gnss_volgpio then - gpio.setup(exgnss.opts.gnss_volgpio,1) - else - pm.power(pm.GPS, true) - end - openFlag = true - if exgnss.opts.gnssmode==1 then - --榛樿鍏ㄥ紑鍚 - log.info("鍏ㄥ崼鏄熷紑鍚") - elseif exgnss.opts.gnssmode==2 then - --榛樿寮鍚崟鍖楁枟 - sys.timerStart(function() - uart.write(uart_id, "$CFGSYS,h10\r\n") - end,200) - log.info("鍗曞寳鏂楀紑鍚") - end - if exgnss.opts.debug==true then - log.info("debug寮鍚") - libgnss.debug(true) - end - if type(exgnss.opts.bind)=="number" then - log.info("缁戝畾bind浜嬩欢") - libgnss.bind(uart_id,exgnss.opts.bind) - else - libgnss.bind(uart_id) - end - if exgnss.opts.rtc==true then - log.info("rtc寮鍚") - libgnss.rtcAuto(true) - end - if exgnss.opts.agps_enable==true then - log.info("agps寮鍚") - sys.taskInit(is_agps) - end - --璁剧疆杈撳嚭VTG鍐呭 - sys.timerStart(function() - uart.write(uart_id,"$CFGMSG,0,5,1,1\r\n") - end,800) - --璁剧疆杈撳嚭ZDA鍐呭 - sys.timerStart(function() - uart.write(uart_id,"$CFGMSG,0,6,1,1\r\n") - end,900) - sys.publish("GNSS_STATE","OPEN") - log.info("exgnss._open") -end - ---鍏抽棴gnss锛屽唴閮ㄥ嚱鏁颁娇鐢紝涓嶆帹鑽愮粰鑴氭湰灞備娇鐢 -local function fnc_close() - if not openFlag then return end - save_loc() - if exgnss.opts.gnss_volgpio then - gpio.setup(exgnss.opts.gnss_volgpio,0) - else - pm.power(pm.GPS, false) - end - uart.close(uart_id) - openFlag = false - fixFlag = false - timeres=false - sys.publish("GNSS_STATE","CLOSE",fixFlag) - log.info("exgnss._close") - libgnss.clear() -end - - ---- gnss搴旂敤妯″紡1. --- --- 鎵撳紑gnss鍚庯紝gnss瀹氫綅鎴愬姛鏃讹紝濡傛灉鏈夊洖璋冨嚱鏁帮紝浼氳皟鐢ㄥ洖璋冨嚱鏁 --- --- 浣跨敤姝ゅ簲鐢ㄦā寮忚皟鐢╣nss.open鎵撳紑鐨勨済nss搴旂敤鈥濓紝蹇呴』涓诲姩璋冪敤gnss.close鎴栬単nss.close_all鎵嶈兘鍏抽棴姝も済nss搴旂敤鈥,涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 -exgnss.DEFAULT = 1 ---- gnss搴旂敤妯″紡2. --- --- 鎵撳紑gnss鍚庯紝濡傛灉鍦╣nss寮鍚渶澶ф椂闀垮埌杈炬椂锛屾病鏈夊畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- --- 鎵撳紑gnss鍚庯紝濡傛灉鍦╣nss寮鍚渶澶ф椂闀垮唴锛屽畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- --- 鎵撳紑gnss鍚庯紝鍦ㄨ嚜鍔ㄥ叧闂鈥済nss搴旂敤鈥濆墠锛屽彲浠ヨ皟鐢╣nss.close鎴栬単nss.close_all涓诲姩鍏抽棴姝も済nss搴旂敤鈥濓紝涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 -exgnss.TIMERORSUC = 2 ---- gnss搴旂敤妯″紡3. --- --- 鎵撳紑gnss鍚庯紝鍦╣nss寮鍚渶澶ф椂闀挎椂闂村埌杈炬椂锛屾棤璁烘槸鍚﹀畾浣嶆垚鍔燂紝濡傛灉鏈夊洖璋冨嚱鏁帮紝浼氳皟鐢ㄥ洖璋冨嚱鏁帮紝鐒跺悗鑷姩鍏抽棴姝も済nss搴旂敤鈥 --- --- 鎵撳紑gnss鍚庯紝鍦ㄨ嚜鍔ㄥ叧闂鈥済nss搴旂敤鈥濆墠锛屽彲浠ヨ皟鐢╣nss.close鎴栬単nss.close_all涓诲姩鍏抽棴姝も済nss搴旂敤鈥濓紝涓诲姩鍏抽棴鏃讹紝鍗充娇鏈夊洖璋冨嚱鏁帮紝涔熶笉浼氳皟鐢ㄥ洖璋冨嚱鏁 -exgnss.TIMER = 3 - ---鈥済nss搴旂敤鈥濊〃 -local tList = {} - ---[[ -鍑芥暟鍚嶏細delItem -鍔熻兘 锛氫粠鈥済nss搴旂敤鈥濊〃涓垹闄や竴椤光済nss搴旂敤鈥濓紝骞朵笉鏄湡姝ｇ殑鍒犻櫎锛屽彧鏄缃竴涓棤鏁堟爣蹇 -鍙傛暟 锛 - mode锛歡nss搴旂敤妯″紡 - para锛 - para.tag锛氣済nss搴旂敤鈥濇爣璁 - para.val锛歡nss寮鍚渶澶ф椂闀 - para.cb锛氬洖璋冨嚱鏁 -杩斿洖鍊硷細鏃 -]] -local function delItem(mode,para) - for i=1,#tList do - --鏍囧織鏈夋晥 骞朵笖 gnss搴旂敤妯″紡鐩稿悓 骞朵笖 鈥済nss搴旂敤鈥濇爣璁扮浉鍚 - if tList[i].flag and tList[i].mode==mode and tList[i].para.tag==para.tag then - --璁剧疆鏃犳晥鏍囧織 - tList[i].flag,tList[i].delay = false - break - end - end -end - - ---[[ -鍑芥暟鍚嶏細addItem -鍔熻兘 锛氭柊澧炰竴椤光済nss搴旂敤鈥濆埌鈥済nss搴旂敤鈥濊〃 -鍙傛暟 锛 - mode锛歡nss搴旂敤妯″紡 - para锛 - para.tag锛氣済nss搴旂敤鈥濇爣璁 - para.val锛歡nss寮鍚渶澶ф椂闀 - para.cb锛氬洖璋冨嚱鏁 -杩斿洖鍊硷細鏃 -]] -local function addItem(mode,para) - --鍒犻櫎鐩稿悓鐨勨済nss搴旂敤鈥 - delItem(mode,para) - local item,i,fnd = {flag=true, mode=mode, para=para} - --濡傛灉鏄疶IMERORSUC鎴栬匱IMER妯″紡锛屽垵濮嬪寲gnss宸ヤ綔鍓╀綑鏃堕棿 - if mode==exgnss.TIMERORSUC or mode==exgnss.TIMER then item.para.remain = para.val end - for i=1,#tList do - --濡傛灉瀛樺湪鏃犳晥鐨勨済nss搴旂敤鈥濋」锛岀洿鎺ヤ娇鐢ㄦ浣嶇疆 - if not tList[i].flag then - tList[i] = item - fnd = true - break - end - end - --鏂板涓椤 - if not fnd then table.insert(tList,item) end -end - ---閫鍑篏NSS瀹氭椂鍣 -local function existTimerItem() - for i=1,#tList do - if tList[i].flag and (tList[i].mode==exgnss.TIMERORSUC or tList[i].mode==exgnss.TIMER or tList[i].para.delay) then return true end - end -end - ---GNSS瀹氭椂鍣 -local function timerFnc() - for i=1,#tList do - if tList[i].flag then - log.info("exgnss.timerFnc@"..i,tList[i].mode,tList[i].para.tag,tList[i].para.val,tList[i].para.remain,tList[i].para.delay) - local rmn,dly,md,cb = tList[i].para.remain,tList[i].para.delay,tList[i].mode,tList[i].para.cb - - if rmn and rmn>0 then - tList[i].para.remain = rmn-1 - end - if dly and dly>0 then - tList[i].para.delay = dly-1 - end - rmn = tList[i].para.remain - - if libgnss.isFix() and md==exgnss.TIMER and rmn==0 and not tList[i].para.delay then - tList[i].para.delay = 1 - end - dly = tList[i].para.delay - if libgnss.isFix() then - if dly and dly==0 then - if cb then cb(tList[i].para.tag) end - if md == exgnss.DEFAULT then - tList[i].para.delay = nil - else - exgnss.close(md,tList[i].para) - end - end - else - if rmn and rmn == 0 then - if cb then cb(tList[i].para.tag) end - exgnss.close(md,tList[i].para) - end - end - end - end - if existTimerItem() then sys.timerStart(timerFnc,1000) end -end - ---[[ -鍑芥暟鍚嶏細statInd -鍔熻兘 锛氬鐞唃nss瀹氫綅鎴愬姛鐨勬秷鎭 -鍙傛暟 锛 - evt锛歡nss娑堟伅绫诲瀷 -杩斿洖鍊硷細鏃 -]] -local function statInd(evt) - --瀹氫綅鎴愬姛鐨勬秷鎭 - if evt == "FIXED" then - fixFlag = true - for i=1,#tList do - log.info("exgnss.statInd@"..i,tList[i].flag,tList[i].mode,tList[i].para.tag,tList[i].para.val,tList[i].para.remain,tList[i].para.delay,tList[i].para.cb) - if tList[i].flag then - if tList[i].mode ~= exgnss.TIMER then - tList[i].para.delay = 1 - if tList[i].mode == exgnss.DEFAULT then - if existTimerItem() then sys.timerStart(timerFnc,1000) end - end - end - end - end - end -end - - ---[[ -璁剧疆gnss瀹氫綅鍙傛暟 -@api exgnss.setup(opts) -@table opts gnss瀹氫綅鍙傛暟锛屽彲閫夊糶nssmode:瀹氫綅鍗槦妯″紡锛1涓哄崼鏄熷叏瀹氫綅锛2涓哄崟鍖楁枟锛岄粯璁や负鍗槦鍏ㄥ畾浣 -agps_enable:鏄惁鍚敤AGPS锛宼rue涓哄惎鐢紝false涓轰笉鍚敤锛岄粯璁や负false -debug:鏄惁杈撳嚭璋冭瘯淇℃伅鍒發uatools锛宼rue涓鸿緭鍑猴紝false涓轰笉杈撳嚭锛岄粯璁や负false -uart:GNSS涓插彛閰嶇疆锛780EGH鍜8000榛樿涓簎art2锛屽彲涓嶅～ -uartbaud:GNSS涓插彛娉㈢壒鐜囷紝780EGH鍜8000榛樿涓115200锛屽彲涓嶅～ -bind:缁戝畾uart绔彛杩涜GNSS鏁版嵁璇诲彇锛屾槸鍚﹁缃覆鍙ｈ浆鍙戯紝鎸囧畾涓插彛鍙凤紝涓嶉渶瑕佽浆鍙戝彲涓嶅～ -rtc:瀹氫綅鎴愬姛鍚庤嚜鍔ㄨ缃甊TC true寮鍚紝flase鍏抽棴锛岄粯璁や负flase锛屼笉闇瑕佸彲涓嶅～ -@return nil 鏃犺繑鍥炲 -@usage -local gnssotps={ - gnssmode=1, --1涓哄崼鏄熷叏瀹氫綅锛2涓哄崟鍖楁枟 - agps_enable=true, --鏄惁浣跨敤AGPS锛屽紑鍚疉GPS鍚庡畾浣嶉熷害鏇村揩锛屼細璁块棶鏈嶅姟鍣ㄤ笅杞芥槦鍘嗭紝鏄熷巻鏃舵晥鎬т负鍖楁枟1灏忔椂锛孏PS4灏忔椂锛岄粯璁や笅杞芥槦鍘嗙殑鏃堕棿涓1灏忔椂锛屽嵆涓灏忔椂鍐呭彧浼氫笅杞戒竴娆 - debug=true, --鏄惁杈撳嚭璋冭瘯淇℃伅 - -- uart=2, --浣跨敤鐨勪覆鍙,780EGH鍜8000榛樿涓插彛2 - -- uartbaud=115200, --涓插彛娉㈢壒鐜囷紝780EGH鍜8000榛樿115200 - -- bind=1, --缁戝畾uart绔彛杩涜GNSS鏁版嵁璇诲彇锛屾槸鍚﹁缃覆鍙ｈ浆鍙戯紝鎸囧畾涓插彛鍙 - -- rtc=false --瀹氫綅鎴愬姛鍚庤嚜鍔ㄨ缃甊TC true寮鍚紝flase鍏抽棴 - ----鍥犱负GNSS浣跨敤杈呭姪瀹氫綅鐨勯昏緫锛屾槸妯″潡涓嬭浇鏄熷巻鏂囦欢锛岀劧鍚庢妸鏁版嵁鍙戦佺粰GNSS鑺墖锛 - ----鑺墖瑙ｆ瀽鏄熷巻鏂囦欢闇瑕10-30s锛岄粯璁NSS浼氬紑鍚20s锛岃閫昏緫濡傛灉涓嶆墽琛岋紝浼氬鑷翠笅涓娆NSS寮鍚畾浣嶆槸鍐峰惎鍔紝 - ----瀹氫綅閫熷害鎱紝澶ф35S宸﹀彸锛屾墍浠ラ粯璁ゅ紑鍚紝濡傛灉鍙互鎺ュ彈涓嬩竴娆″畾浣嶆槸鍐峰惎鍔紝鍙互鎶奱uto_open璁剧疆鎴恌alse - ----闇瑕佹敞鎰忕殑鏄儹鍚姩鍦ㄥ畾浣嶆垚鍔熶箣鍚庯紝闇瑕佸啀寮鍚3s宸﹀彸鎵嶈兘淇濊瘉鏈鐨勬槦鍘嗚幏鍙栧畬鎴愶紝濡傛灉瀵瑰畾浣嶉熷害鏈夎姹傦紝寤鸿杩欎箞澶勭悊 - -- auto_open=false - } - exgnss.setup(gnssotps) -]] -function exgnss.setup(opts) - exgnss.opts=opts - if hmeta.model():find("780EGH") or hmeta.model():find("8000") then - uart_id=2 - uart_baudrate=115200 - else - if exgnss.opts.uart_id then - uart_id=exgnss.opts.uart_id - else - uart_id=2 - end - if exgnss.opts.uartbaud then - uart_baudrate=exgnss.opts.uartbaud - else - uart_baudrate=115200 - end - end -end - ---[[ -鎵撳紑涓涓済nss搴旂敤鈥 -@api exgnss.open(mode,para) -@number mode gnss搴旂敤妯″紡锛屾敮鎸乬nss.DEFAULT锛実nss.TIMERORSUC锛実nss.TIMER涓夌 -@param para table绫诲瀷锛実nss搴旂敤鍙傛暟,para.tag锛歴tring绫诲瀷锛実nss搴旂敤鏍囪,para.val锛歯umber绫诲瀷锛実nss搴旂敤寮鍚渶澶ф椂闀匡紝鍗曚綅锛氱锛宮ode鍙傛暟涓篻nss.TIMERORSUC鎴栬単nss.TIMER鏃讹紝姝ゅ兼墠鏈夋剰涔夛紱浣跨敤close鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟,para.cb锛歡nss搴旂敤缁撴潫鏃剁殑鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓簆ara.cb(para.tag)锛涗娇鐢╟lose鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟 -@return nil 鏃犺繑鍥炲 -@usage --- 鈥済nss搴旂敤鈥濓細鎸囩殑鏄娇鐢╣nss鍔熻兘鐨勪竴涓簲鐢 --- 渚嬪锛屽亣璁炬湁濡備笅3绉嶉渶姹傦紝瑕佹墦寮gnss锛屽垯涓鍏辨湁3涓済nss搴旂敤鈥濓細 --- 鈥済nss搴旂敤1鈥濓細姣忛殧1鍒嗛挓鎵撳紑涓娆nss --- 鈥済nss搴旂敤2鈥濓細璁惧鍙戠敓闇囧姩鏃舵墦寮gnss --- 鈥済nss搴旂敤3鈥濓細鏀跺埌涓鏉＄壒娈婄煭淇℃椂鎵撳紑gnss --- 鍙湁鎵鏈夆済nss搴旂敤鈥濋兘鍏抽棴浜嗭紝鎵嶄細鍘荤湡姝ｅ叧闂璯nss --- 姣忎釜鈥済nss搴旂敤鈥濇墦寮鎴栬呭叧闂璯nss鏃讹紝鏈澶氭湁4涓弬鏁帮紝鍏朵腑 gnss搴旂敤妯″紡鍜実nss搴旂敤鏍囪 鍏卞悓鍐冲畾浜嗕竴涓敮涓鐨勨済nss搴旂敤鈥濓細 --- 1銆乬nss搴旂敤妯″紡(蹇呴) --- 2銆乬nss搴旂敤鏍囪(蹇呴) --- 3銆乬nss寮鍚渶澶ф椂闀縖鍙塢 --- 4銆佸洖璋冨嚱鏁癧鍙塢 --- 渚嬪gnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) --- exgnss.TIMER涓篻nss搴旂敤妯″紡锛"MODE1"涓篻nss搴旂敤鏍囪锛60绉掍负gnss寮鍚渶澶ф椂闀匡紝mode1_cb涓哄洖璋冨嚱鏁 -exgnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) -exgnss.open(exgnss.DEFAULT,{tag="MODE2",cb=mode2_cb}) -exgnss.open(exgnss.TIMERORSUC,{tag="MODE3",val=60,cb=mode3_cb}) -]] -function exgnss.open(mode,para) - assert((para and type(para) == "table" and para.tag and type(para.tag) == "string"),"exgnss.open para invalid") - log.info("exgnss.open",mode,para.tag,para.val,para.cb) - --濡傛灉gnss瀹氫綅鎴愬姛 - if libgnss.isFix() then - if mode~=exgnss.TIMER then - --鎵ц鍥炶皟鍑芥暟 - if para.cb then para.cb(para.tag) end - if mode==exgnss.TIMERORSUC then return end - end - end - addItem(mode,para) - --鐪熸鍘绘墦寮gnss - fnc_open() - --鍚姩1绉掔殑瀹氭椂鍣 - if existTimerItem() and not sys.timerIsActive(timerFnc) then - sys.timerStart(timerFnc,1000) - end -end - - ---[[ -鍏抽棴涓涓済nss搴旂敤鈥濓紝鍙槸浠庨昏緫涓婂叧闂竴涓猤nss搴旂敤锛屽苟涓嶄竴瀹氱湡姝ｅ叧闂璯nss锛屾槸鏈夋墍鏈夌殑gnss搴旂敤閮藉浜庡叧闂姸鎬侊紝鎵嶄細鍘荤湡姝ｅ叧闂璯nss -@api exgnss.close() -@number mode gnss搴旂敤妯″紡锛屾敮鎸乬nss.DEFAULT锛実nss.TIMERORSUC锛実nss.TIMER涓夌 -@param para table绫诲瀷锛実nss搴旂敤鍙傛暟,para.tag锛歴tring绫诲瀷锛実nss搴旂敤鏍囪,para.val锛歯umber绫诲瀷锛実nss搴旂敤寮鍚渶澶ф椂闀匡紝鍗曚綅锛氱锛宮ode鍙傛暟涓篻nss.TIMERORSUC鎴栬単nss.TIMER鏃讹紝姝ゅ兼墠鏈夋剰涔夛紱浣跨敤close鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟,para.cb锛歡nss搴旂敤缁撴潫鏃剁殑鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓簆ara.cb(para.tag)锛涗娇鐢╟lose鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟 -@return nil 鏃犺繑鍥炲 -@usage -exgnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) -exgnss.close(exgnss.TIMER,{tag="MODE1"}) -]] -function exgnss.close(mode,para) - assert((para and type(para)=="table" and para.tag and type(para.tag)=="string"),"exgnss.close para invalid") - log.info("exgnss.close",mode,para.tag,para.val,para.cb) - --鍒犻櫎姝も済nss搴旂敤鈥 - delItem(mode,para) - local valid,i - for i=1,#tList do - if tList[i].flag then - valid = true - end - end - --濡傛灉娌℃湁涓涓済nss搴旂敤鈥濇湁鏁堬紝鍒欏叧闂璯nss - if not valid then fnc_close() end -end - ---[[ -鍏抽棴鎵鏈夆済nss搴旂敤鈥 -@api exgnss.close_all() -@return nil 鏃犺繑鍥炲 -@usage -exgnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) -exgnss.open(exgnss.DEFAULT,{tag="MODE2",cb=mode2_cb}) -exgnss.open(exgnss.TIMERORSUC,{tag="MODE3",val=60,cb=mode3_cb}) -exgnss.close_all() -]] -function exgnss.close_all() - for i=1,#tList do - if tList[i].flag and tList[i].para.cb then tList[i].para.cb(tList[i].para.tag) end - exgnss.close(tList[i].mode,tList[i].para) - end -end - ---[[ -鍒ゆ柇涓涓済nss搴旂敤鈥濇槸鍚﹀浜庢縺娲荤姸鎬 -@api exgnss.is_active(mode,para) -@number mode gnss搴旂敤妯″紡锛屾敮鎸乬nss.DEFAULT锛実nss.TIMERORSUC锛実nss.TIMER涓夌 -@param para table绫诲瀷锛実nss搴旂敤鍙傛暟,para.tag锛歴tring绫诲瀷锛実nss搴旂敤鏍囪,para.val锛歯umber绫诲瀷锛実nss搴旂敤寮鍚渶澶ф椂闀匡紝鍗曚綅锛氱锛宮ode鍙傛暟涓篻nss.TIMERORSUC鎴栬単nss.TIMER鏃讹紝姝ゅ兼墠鏈夋剰涔夛紱浣跨敤close鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟,para.cb锛歡nss搴旂敤缁撴潫鏃剁殑鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓簆ara.cb(para.tag)锛涗娇鐢╟lose鎺ュ彛鏃讹紝涓嶉渶瑕佷紶鍏ユ鍙傛暟,gnss搴旂敤妯″紡鍜実nss搴旂敤鏍囪鍞竴纭畾涓涓済nss搴旂敤鈥濓紝璋冪敤鏈帴鍙ｆ煡璇㈢姸鎬佹椂锛宮ode鍜宲ara.tag瑕佸拰gnss.open鎵撳紑涓涓済nss搴旂敤鈥濇椂浼犲叆鐨刴ode鍜宲ara.tag淇濇寔涓鑷 -@return bool result锛屽浜庢縺娲荤姸鎬佽繑鍥瀟rue锛屽惁鍒欒繑鍥瀗il -@usage -exgnss.open(exgnss.TIMER,{tag="MODE1",val=60,cb=mode1_cb}) -exgnss.open(exgnss.DEFAULT,{tag="MODE2",cb=mode2_cb}) -exgnss.open(exgnss.TIMERORSUC,{tag="MODE3",val=60,cb=mode3_cb}) -log.info("gnss搴旂敤鐘舵1",exgnss.is_active(exgnss.TIMER,{tag="MODE1"})) -log.info("gnss搴旂敤鐘舵2",exgnss.is_active(exgnss.DEFAULT,{tag="MODE2"})) -log.info("gnss搴旂敤鐘舵3",exgnss.is_active(exgnss.TIMERORSUC,{tag="MODE3"})) -]] -function exgnss.is_active(mode,para) - assert((para and type(para)=="table" and para.tag and type(para.tag)=="string"),"exgnss.is_active para invalid") - for i=1,#tList do - if tList[i].flag and tList[i].mode==mode and tList[i].para.tag==para.tag then return true end - end -end - -sys.subscribe("GNSS_STATE",statInd) - - ---[[ -褰撳墠鏄惁宸茬粡瀹氫綅鎴愬姛 -@api exgnss.is_fix() -@return boolean true/false锛屽畾浣嶆垚鍔熻繑鍥瀟rue锛屽惁鍒欒繑鍥瀎alse -@usage -log.info("nmea", "is_fix", exgnss.is_fix()) -]] -function exgnss.is_fix() - return libgnss.isFix() -end - - ---[[ -鑾峰彇number绫诲瀷鐨勪綅缃拰閫熷害淇℃伅 -@api exgnss.int_location(speed_type) -@number 閫熷害鍗曚綅,榛樿鏄痬/h, -0 - m/h 绫/灏忔椂, 榛樿鍊, 鏁村瀷 -1 - m/s 绫/绉, 娴偣鏁 -2 - km/h 鍗冪背/灏忔椂, 娴偣鏁 -3 - kn/h 鑻遍噷/灏忔椂, 娴偣鏁 -@return number lat鏁版嵁, 鏍煎紡涓 DDDDDDDDD锛岀ず渚嬶細343482649锛孌DDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢 -@return number lng鏁版嵁, 鏍煎紡涓 DDDDDDDDD锛岀ず渚嬶細1135039700锛孌DDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢 -@return number speed鏁版嵁, 鍗曚綅鏍规嵁speed_type鍐冲畾锛宮/h, m/s, km/h, kn/h -@usage ---DDDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢紝绀轰緥锛343482649瀵瑰簲鐨勫師濮嬪兼槸34.3482649 --- 璇ユ暟鎹槸閫氳繃RMC杞崲鐨勶紝濡傛灉鎯宠幏鍙栨洿璇︾粏鐨勫彲浠ョ敤exgnss.rmc(1) --- speed鏁版嵁榛樿 绫/灏忔椂锛岃繑鍥炲间緥濡傦細343482649 1135039700 390m/h -log.info("nmea", "loc", exgnss.int_location()) --- speed鏁版嵁绫/绉掞紝杩斿洖鍊间緥濡傦細343482649 1135039700 0.1085478m/s -log.info("nmea", "loc", exgnss.int_location(1)) --- speed鏁版嵁鍗冪背/灏忔椂锛岃繑鍥炲间緥濡傦細343482649 1135039700 0.3907720km/h -log.info("nmea", "loc", exgnss.int_location(2)) --- speed鏁版嵁鑻遍噷/灏忔椂锛岃繑鍥炲间緥濡傦細343482649 1135039700 0.2110000kn/h -log.info("nmea", "loc", exgnss.int_location(3)) -]] -function exgnss.int_location(speed_type) - return libgnss.getIntLocation(speed_type) -end - - ---[[ -鑾峰彇RMC鐨勪俊鎭紝缁忕含搴︼紝鏃堕棿锛岄熷害锛岃埅鍚戯紝瀹氫綅鏄惁鏈夋晥锛岀鍋忚 -@api exgnss.rmc(lnglat_mode) -@number 缁忕含搴︽暟鎹殑鏍煎紡, 0-ddmm.mmmmm鏍煎紡, 1-DDDDDDDDD鏍煎紡, 2-DD.DDDDDDD鏍煎紡, 3-鍘熷RMC瀛楃涓 -@return table/string rmc鏁版嵁 -@usage --- 瑙ｆ瀽nmea -log.info("nmea", "rmc", json.encode(exgnss.rmc(2))) --- 瀹炰緥杈撳嚭,鑾峰彇鍊肩殑瑙ｉ噴 --- { --- "course":344.9920044, // 鍦伴潰鑸悜锛屽崟浣嶄负搴︼紝浠庡寳鍚戣捣椤烘椂閽堣绠 --- "valid":true, // true瀹氫綅鎴愬姛,false瀹氫綅涓㈠け --- "lat":34.5804405, // 绾害, 姝ｆ暟涓哄寳绾, 璐熸暟涓哄崡绾 --- "lng":113.8399506, // 缁忓害, 姝ｆ暟涓轰笢缁, 璐熸暟涓鸿タ缁 --- "variation":0, // 纾佸亸瑙掞紝鍥哄畾涓0 --- "speed":0.2110000 // 鍦伴潰閫熷害, 鍗曚綅涓"鑺" --- "year":2023, // 骞翠唤 --- "month":1, // 鏈堜唤, 1-12 --- "day":5, // 鏈堜唤澶, 1-31 --- "hour":7, // 灏忔椂,0-23 --- "min":23, // 鍒嗛挓,0-59 --- "sec":20, // 绉,0-59 --- } ---妯″紡0绀轰緥锛 ---json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣嶏紝鏈ず渚嬩繚鐣5浣嶅皬鏁 -log.info("nmea", "rmc0", json.encode(exgnss.rmc(0),"5f")) -{"variation":0,"lat":3434.82666,"min":54,"valid":true,"day":17,"lng":11350.39746,"speed":0.21100,"year":2025,"month":7,"sec":30,"hour":11,"course":344.99200} ---妯″紡1绀轰緥锛 ---DDDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢 -log.info("nmea", "rmc1", json.encode(exgnss.rmc(1))) -{"variation":0,"lat":345804414,"min":54,"valid":true,"day":17,"lng":1138399500,"speed":0.2110000,"year":2025,"month":7,"sec":30,"hour":11,"course":344.9920044} ---妯″紡2绀轰緥锛 ---json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣 -log.info("nmea", "rmc2", json.encode(exgnss.rmc(2))) -{"variation":0,"lat":34.5804405,"min":54,"valid":true,"day":17,"lng":113.8399506,"speed":0.2110000,"year":2025,"month":7,"sec":30,"hour":11,"course":344.9920044} ---妯″紡3绀轰緥锛 -log.info("nmea", "rmc3", exgnss.rmc(3)) -$GNRMC,115430.000,A,3434.82649,N,11350.39700,E,0.211,344.992,170725,,,A,S*02\r -]] -function exgnss.rmc(lnglat_mode) - return libgnss.getRmc(lnglat_mode) -end - ---[[ -鑾峰彇鍘熷GSV淇℃伅 -@api exgnss.gsv() -@return table 鍘熷GSV鏁版嵁 -@usage --- 瑙ｆ瀽nmea -log.info("nmea", "gsv", json.encode(exgnss.gsv())) --- 瀹炰緥杈撳嚭 --- { --- "total_sats":24, // 鎬诲彲瑙佸崼鏄熸暟閲 --- "sats":[ --- { --- "snr":27, // 淇″櫔姣 --- "azimuth":278, // 鏂瑰悜瑙 --- "elevation":59, // 浠拌 --- "tp":0, // 0 - GPS, 1 - BD, 2 - GLONASS, 3 - Galileo, 4 - QZSS --- "nr":4 // 鍗槦缂栧彿 --- }, --- // 杩欓噷蹇界暐浜22涓崼鏄熺殑淇℃伅 --- { --- "snr":0, --- "azimuth":107, --- "elevation":19, --- "tp":1, --- "nr":31 --- } --- ] --- } -]] -function exgnss.gsv() - return libgnss.getGsv() -end - - ---[[ -鑾峰彇鍘熷GSA淇℃伅 -@api exgnss.gsa(data_mode) -@number 妯″紡锛岄粯璁や负0 -鎵鏈夊崼鏄熺郴缁熷叏閮ㄨ緭鍑哄湪涓璧凤紝1 - 姣忎釜鍗槦绯荤粺鍗曠嫭鍒嗗紑杈撳嚭 -@return table 鍘熷GSA鏁版嵁 -@usage --- 鑾峰彇 -log.info("nmea", "gsa", json.encode(exgnss.gsa())) --- 绀轰緥鏁版嵁(妯″紡0, 涔熷氨鏄粯璁ゆā寮) ---sysid:1涓篏PS锛4涓哄寳鏂楋紝2涓篏LONASS锛3涓篏alileo -{"pdop":1.1770000, 浣嶇疆绮惧害鍥犲瓙锛0.00 - 99.99锛屼笉瀹氫綅鏃跺间负 99.99 -"sats":[15,13,5,18,23,20,24,30,24,13,33,38,8,14,28,41,6,39,25,16,32,27], // 姝ｅ湪浣跨敤鐨勫崼鏄熺紪鍙 -"vdop":1.0160000, 鍨傜洿绮惧害鍥犲瓙锛0.00 - 99.99锛屼笉瀹氫綅鏃跺间负 99.99 -"hdop":0.5940000, // 姘村钩绮惧害鍥犲瓙锛0.00 - 99.99锛屼笉瀹氫綅鏃跺间负 99.99 -"sysid":1, // 鍗槦绯荤粺缂栧彿1涓篏PS锛4涓哄寳鏂楋紝2涓篏LONASS锛3涓篏alileo -"fix_type":3 // 瀹氫綅妯″紡, 1-鏈畾浣, 2-2D瀹氫綅, 3-3D瀹氫綅 -} - ---妯″紡1 -log.info("nmea", "gsa", json.encode(exgnss.gsa())) - -[{"pdop":1.1770000,"sats":[15,13,5,18,23,20,24],"vdop":1.0160000,"hdop":0.5940000,"sysid":1,"fix_type":3}, -{"pdop":1.1770000,"sats":[30,24,13,33,38,8,14,28,41,6,39,25],"vdop":1.0160000,"hdop":0.5940000,"sysid":4,"fix_type":3}, -{"pdop":1.1770000,"sats":[16,32,27],"vdop":1.0160000,"hdop":0.5940000,"sysid":4,"fix_type":3}, -{"pdop":1.1770000,"sats":{},"vdop":1.0160000,"hdop":0.5940000,"sysid":2,"fix_type":3}, -{"pdop":1.1770000,"sats":{},"vdop":1.0160000,"hdop":0.5940000,"sysid":3,"fix_type":3}] - -]] - -function exgnss.gsa(data_mode) - return libgnss.getGsa(data_mode) -end - - ---[[ -鑾峰彇VTG閫熷害淇℃伅 -@api exgnss.vtg(data_mode) -@number 鍙, 3-鍘熷瀛楃涓, 涓嶄紶鎴栬呬紶鍏朵粬鍊, 鍒欒繑鍥炴诞鐐瑰 -@return table/string 鍘熷VTG鏁版嵁 -@usage --- 瑙ｆ瀽nmea -log.info("nmea", "vtg", json.encode(exgnss.vtg())) --- 绀轰緥 -{ - "speed_knots":0, // 閫熷害, 鑻遍噷/灏忔椂 - "true_track_degrees":0, // 鐪熷寳鏂瑰悜瑙 - "magnetic_track_degrees":0, // 纾佸寳鏂瑰悜瑙 - "speed_kph":0 // 閫熷害, 鍗冪背/灏忔椂 -} - ---妯″紡3 -log.info("nmea", "vtg", exgnss.vtg(3)) --- 杩斿洖鍊硷細$GNVTG,0.000,T,,M,0.000,N,0.000,K,A*13\r --- 鎻愰啋: 鍦ㄩ熷害<5km/h鏃, 涓嶄細杩斿洖鏂瑰悜瑙 -]] -function exgnss.vtg(data_mode) - return libgnss.getVtg(data_mode) -end - ---鑾峰彇鍘熷ZDA鏃堕棿鍜屾棩鏈熶俊鎭 ---[[ -鑾峰彇鍘熷ZDA鏃堕棿鍜屾棩鏈熶俊鎭 -@api exgnss.zda() -@return table 鍘熷zda鏁版嵁 -@usage -log.info("nmea", "zda", json.encode(exgnss.zda())) --- 瀹炰緥杈撳嚭 --- { --- "minute_offset":0, // 鏈湴鏃跺尯鐨勫垎閽, 涓鑸浐瀹氳緭鍑0 --- "hour_offset":0, // 鏈湴鏃跺尯鐨勫皬鏃, 涓鑸浐瀹氳緭鍑0 --- "year":2023 // UTC 骞达紝鍥涗綅鏁板瓧 --- "month":1, // UTC 鏈堬紝涓や綅锛01 ~ 12 --- "day":5, // UTC 鏃ワ紝涓や綅鏁板瓧锛01 ~ 31 --- "hour":7, // 灏忔椂 --- "min":50, // 鍒 --- "sec":14, // 绉 --- } -]] -function exgnss.zda() - return libgnss.getZda() -end - ---[[ -鑾峰彇GGA鏁版嵁 -@api exgnss.gga(lnglat_mode) -@number 缁忕含搴︽暟鎹殑鏍煎紡, 0-ddmm.mmmmm鏍煎紡, 1-DDDDDDDDD鏍煎紡, 2-DD.DDDDDDD鏍煎紡, 3-鍘熷GGA瀛楃涓 -@return table GGA鏁版嵁, 鑻ュ涓嶅瓨鍦ㄤ細杩斿洖nil -@usage -local gga = exgnss.gga(2) -log.info("GGA", json.encode(gga, "11g")) ---瀹炰緥杈撳嚭,鑾峰彇鍊肩殑瑙ｉ噴: --- { --- "dgps_age":0, // 宸垎鏍℃鏃跺欢锛屽崟浣嶄负绉 --- "fix_quality":1, // 瀹氫綅鐘舵佹爣璇 0 - 鏃犳晥,1 - 鍗曠偣瀹氫綅,2 - 宸垎瀹氫綅 --- "satellites_tracked":14, // 鍙備笌瀹氫綅鐨勫崼鏄熸暟閲 --- "altitude":0.255, // 娴峰钩闈㈠垎绂诲害, 鎴栬呮垚涓烘捣鎷, 鍗曚綅鏄背, --- "hdop":0.0335, // 姘村钩绮惧害鍥犲瓙锛0.00 - 99.99锛屼笉瀹氫綅鏃跺间负 99.99 --- "longitude":113.231, // 缁忓害, 姝ｆ暟涓轰笢缁, 璐熸暟涓鸿タ缁 --- "latitude":23.4067, // 绾害, 姝ｆ暟涓哄寳绾, 璐熸暟涓哄崡绾 --- "height":0 // 妞悆楂橈紝鍥哄畾杈撳嚭 1 浣嶅皬鏁 --- } -妯″紡0绀轰緥锛 -json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣嶏紝鏈ず渚嬩繚鐣5浣嶅皬鏁 -local gga = exgnss.gga(0) -if gga then - log.info("GGA0", json.encode(gga, "5f")) -end -{"longitude":11419.19531,"dgps_age":0,"altitude":86.40000,"hdop":0.59400,"height":-13.70000,"fix_quality":1,"satellites_tracked":22,"latitude":3447.86914} -妯″紡1绀轰緥锛 -DDDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢 -local gga1 = exgnss.gga(1) -if gga1 then - log.info("GGA1", json.encode(gga1)) -end -{"longitude":1143199103,"dgps_age":0,"altitude":86.4000015,"hdop":0.5940000,"height":-13.6999998,"fix_quality":1,"satellites_tracked":22,"latitude":347978178} -妯″紡2绀轰緥锛 -json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣 -local gga2 = exgnss.gga(2) -if gga2 then - log.info("GGA2", json.encode(gga2)) -end -{"longitude":114.3199081,"dgps_age":0,"altitude":86.4000015,"hdop":0.5940000,"height":-13.6999998,"fix_quality":1,"satellites_tracked":22,"latitude":34.7978172} -妯″紡3绀轰緥锛 -local gga3 = exgnss.gga(3) -if gga3 then - log.info("GGA3", gga3) -end -$GNGGA,131241.000,3434.81372,N,11350.39930,E,1,05,4.924,165.5,M,-15.2,M,,*6D\r -]] -function exgnss.gga(lnglat_mode) - return libgnss.getGga(lnglat_mode) -end - ---[[ -鑾峰彇GLL鏁版嵁 -@api exgnss.gll(data_mode) -@number 缁忕含搴︽暟鎹殑鏍煎紡, 0-ddmm.mmmmm鏍煎紡, 1-DDDDDDDDD鏍煎紡, 2-DD.DDDDDDD鏍煎紡 -@return table GLL鏁版嵁, 鑻ュ涓嶅瓨鍦ㄤ細杩斿洖nil -@usage -local gll = exgnss.gll(2) -if gll then - log.info("GLL", json.encode(gll, "11g")) -end --- 瀹炰緥鏁版嵁,鑾峰彇鍊肩殑瑙ｉ噴: --- { --- "status":"A", // 瀹氫綅鐘舵, A鏈夋晥, B鏃犳晥 --- "mode":"A", // 瀹氫綅妯″紡, V鏃犳晥, A鍗曠偣瑙, D宸垎瑙 --- "sec":20, // 绉, UTC鏃堕棿涓哄噯 --- "min":23, // 鍒嗛挓, UTC鏃堕棿涓哄噯 --- "hour":7, // 灏忔椂, UTC鏃堕棿涓哄噯 --- "longitude":113.231, // 缁忓害, 姝ｆ暟涓轰笢缁, 璐熸暟涓鸿タ缁 --- "latitude":23.4067, // 绾害, 姝ｆ暟涓哄寳绾, 璐熸暟涓哄崡绾 --- "us":0 // 寰鏁, 閫氬父涓0 --- } ---妯″紡0绀轰緥锛 ---json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣嶏紝鏈ず渚嬩繚鐣5浣嶅皬鏁 -local gll = exgnss.gll(0) -if gll then - log.info("GLL0", json.encode(gll, "5f")) -end -{"longitude":11419.19531,"sec":14,"min":32,"mode":"A","hour":6,"us":0,"status":"A","latitude":3447.86914} ---妯″紡1绀轰緥锛 ---DDDDDDDDD鏍煎紡鏄敱DD.DDDDDDD*10000000杞崲鑰屾潵锛岀洰鐨勬槸浣滀负鏁存暟锛屾柟渚挎煇浜涘満鏅娇鐢 -local gll1 = exgnss.gll(1) -if gll1 then - log.info("GLL1", json.encode(gll1)) -end -{"longitude":1143199103,"sec":14,"min":32,"mode":"A","hour":6,"us":0,"status":"A","latitude":347978178} -妯″紡2绀轰緥锛 ---json.encode榛樿杈撳嚭"7f"鏍煎紡淇濈暀7浣嶅皬鏁帮紝鍙互鏍规嵁鑷繁闇瑕佺殑鏍煎紡璋冩暣灏忔暟浣 -local gll2 = exgnss.gll(2) -if gll2 then - log.info("GLL2", json.encode(gll2)) -end -{"longitude":114.3199081,"sec":14,"min":32,"mode":"A","hour":6,"us":0,"status":"A","latitude":34.7978172} -]] -function exgnss.gll(data_mode) - return libgnss.getGll(data_mode) -end ---[[ -鑾峰彇鏈鍚庣殑缁忕含搴︽暟鎹 -@api exgnss.last_loc() -@return table 缁忕含搴︽暟鎹紝琛ㄩ噷闈㈢殑鍐呭锛歿lat=ddmm.mmmmm0000,lng=ddmm.mmmmm0000},杩斿洖nil琛ㄧず娌℃湁鏁版嵁锛屾鏁版嵁鍦ㄥ畾浣嶆垚鍔燂紝鍏抽棴gps鏃讹紝浼氳嚜鍔ㄤ繚瀛樺埌鏂囦欢绯荤粺涓紝瀹氫綅鎴愬姛涔嬪悗姣10鍒嗛挓濡傛灉杩樺浜庡畾浣嶆垚鍔熺姸鎬佷細鏇存柊 -@usage -local loc= exgnss.last_loc() -if loc then - log.info("lastloc", loc.lat,loc.lng) -end -鏃ュ織杈撳嚭鍐呭绀轰緥锛 -3447.8679200000 11419.196290000 -]] -function exgnss.last_loc() - local locStr = io.readFile("/hxxtloc") - if locStr then - local jdata = json.decode(locStr) - return jdata - end -end -return exgnss \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exlcd.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exlcd.lua deleted file mode 100644 index 3d15f89..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exlcd.lua +++ /dev/null @@ -1,327 +0,0 @@ --- exlcd.lua ---[[ -@module exlcd -@summary LCD鏄剧ず鎷撳睍搴 -@version 1.0.5 -@date 2025.12.23 -@author 姹熻 -@usage -鏈枃浠朵负LCD鏄剧ず鎷撳睍搴擄紝鏍稿績涓氬姟閫昏緫涓猴細 -1銆佸垵濮嬪寲LCD鏄剧ず灞忥紝鏀寔澶氱鏄剧ず鑺墖 -2銆佺鐞嗗睆骞曡儗鍏変寒搴﹀強寮鍏崇姸鎬 -3銆佹彁渚涘睆骞曠姸鎬佺鐞嗗姛鑳 -4銆佹敮鎸佹牴鎹甽cd_model鑷姩閰嶇疆鍙傛暟 - -鏈枃浠剁殑瀵瑰鎺ュ彛鏈6涓細 -1銆乪xlcd.init(param)锛歀CD鍒濆鍖栧嚱鏁 -2銆乪xlcd.set_bl(level)锛氳缃儗鍏変寒搴︽帴鍙ｏ紝level涓轰寒搴︾骇鍒(0-100) -3銆乪xlcd.get_bl()锛氬綋鍓嶈缃儗鍏変寒搴︾骇鍒煡璇 -4銆乪xlcd.sleep()锛氬睆骞曚紤鐪 -5銆乪xlcd.wakeup()锛氬睆骞曞敜閱 -6銆乪xlcd.get_sleep()锛氫紤鐪犵姸鎬佹煡璇 -]] - -local exlcd = {} - --- 灞忓箷鐘舵佺鐞嗚〃 -local screen_state = { - last_brightness = 100, -- 榛樿浜害100% - backlight_on = true, -- 鑳屽厜榛樿寮鍚 - lcd_config = nil -- 瀛樺偍LCD閰嶇疆 -} - --- 棰勫畾涔夊睆骞曢厤缃〃 -local predefined_configs = { - Air780EHM_LCD_4 = { - lcd_model = "Air780EHM_LCD_4", - pin_vcc = 24, - pin_rst = 36, - pin_pwr = 25, - pin_pwm = 2, - port = lcd.HWID_0, - direction = 3, - w = 480, - h = 320, - xoffset = 0, - yoffset = 0, - sleepcmd = 0X10, - wakecmd = 0X11, - }, - - AirLCD_1000 = { - lcd_model = "AirLCD_1000", - pin_vcc = 29, - pin_rst = 36, - pin_pwr = 30, - pin_pwm = 1, - port = lcd.HWID_0, - direction = 0, - w = 320, - h = 480, - xoffset = 0, - yoffset = 0, - sleepcmd = 0X10, - wakecmd = 0X11, - }, - - AirLCD_1010 = { - lcd_model = "AirLCD_1010", - pin_vcc = 141, - pin_rst = 36, - pin_pwr = 1, - pin_pwm = 0, - port = lcd.HWID_0, - direction = 0, - w = 320, - h = 480, - xoffset = 0, - yoffset = 0, - sleepcmd = 0X10, - wakecmd = 0X11, - }, - - AirLCD_1020 = { - lcd_model = "AirLCD_1020", - pin_pwr = 8, - pin_pwm = 0, - port = lcd.RGB, - direction = 0, - w = 800, - h = 480, - xoffset = 0, - yoffset = 0, - } -} - ---[[ -鍒濆鍖朙CD鏄剧ず灞 -@api exlcd.init(param) -@table param LCD閰嶇疆鍙傛暟锛屽弬鑰冨簱鐨勮鏄庡強demo鐢ㄦ硶 -@return bool 鍒濆鍖栨垚鍔熻繑鍥瀟rue锛屽け璐ヨ繑鍥瀎alse -@usage --- 浣跨敤棰勫畾涔夐厤缃垵濮嬪寲 -exlcd.init({lcd_model = "Air780EHM_LCD_4"}) - --- 鑷畾涔夊弬鏁板垵濮嬪寲 -exlcd.init({ - lcd_model = "st7796", - port = lcd.HWID_0, - pin_rst = 36, - pin_pwr = 25, - pin_pwm = 2, - w = 480, - h = 320, - direction = 0 -}) -]] -function exlcd.init(param) - if type(param) ~= "table" then - log.error("exlcd", "鍙傛暟蹇呴』涓鸿〃") - return false - end - - -- 妫鏌ュ繀瑕佸弬鏁 - if not param.lcd_model then - log.error("exlcd", "缂哄皯蹇呰鍙傛暟: lcd_model") - return false - end - - local config = {} - - -- 鏍规嵁lcd_model閫夋嫨閰嶇疆绛栫暐 - if param.lcd_model == "Air780EHM_LCD_4" then - -- Air780EHM_LCD_4: 鍙娇鐢╨cd_model锛屽叾浠栧弬鏁板浐瀹 - config = predefined_configs.Air780EHM_LCD_4 - log.info("exlcd", "浣跨敤Air780EHM_LCD_4鍥哄畾閰嶇疆") - elseif predefined_configs[param.lcd_model] then - -- 鍏朵粬棰勫畾涔夊瀷鍙: 浣跨敤棰勫畾涔夐厤缃綔涓哄熀纭锛屼紶鍏ュ弬鏁拌鐩栭瀹氫箟閰嶇疆 - config = {} - - -- 澶嶅埗棰勫畾涔夐厤缃 - for k, v in pairs(predefined_configs[param.lcd_model]) do - config[k] = v - end - - -- 鐢ㄤ紶鍏ュ弬鏁拌鐩栭瀹氫箟閰嶇疆 - for k, v in pairs(param) do - if k ~= "lcd_model" or v ~= param.lcd_model then -- 閬垮厤閲嶅璁剧疆lcd_model - config[k] = v - end - end - - log.info("exlcd", "浣跨敤" .. param.lcd_model .. "鍩虹閰嶇疆锛屼紶鍏ュ弬鏁板凡瑕嗙洊") - else - -- 鏈煡鍨嬪彿: 鐩存帴浣跨敤浼犲叆鍙傛暟 - config = param - log.info("exlcd", "浣跨敤浼犲叆鍙傛暟閰嶇疆") - end - - -- LCD鍨嬪彿鏄犲皠琛 - local lcd_models = { - AirLCD_1000 = "st7796", - Air780EHM_LCD_4 = "st7796", - AirLCD_1010 = "st7796", - AirLCD_1020 = "h050iwv" - } - - -- 纭畾LCD鍨嬪彿 - local lcd_model = lcd_models[config.lcd_model] or config.lcd_model - - -- 瀛樺偍LCD閰嶇疆渚涘叾浠栧嚱鏁颁娇鐢 - screen_state.lcd_config = { - pin_pwr = config.pin_pwr, - pin_pwm = config.pin_pwm, - model = lcd_model, - lcd_model = config.lcd_model - } - - -- 璁剧疆鐢垫簮寮曡剼 (鍙) - if config.pin_vcc then - gpio.setup(config.pin_vcc, 1, gpio.PULLUP) - gpio.set(config.pin_vcc, 1) - end - - -- 璁剧疆鑳屽厜鐢垫簮寮曡剼 (鍙) - if config.pin_pwr then - gpio.setup(config.pin_pwr, 1, gpio.PULLUP) - gpio.set(config.pin_pwr, 1) -- 榛樿寮鍚儗鍏 - end - - -- 璁剧疆PWM鑳屽厜寮曡剼 (鍙) - if config.pin_pwm then - pwm.setup(config.pin_pwm, 1000, screen_state.last_brightness) - pwm.open(config.pin_pwm, 1000, screen_state.last_brightness) - end - - -- 灞忓箷鍒濆鍖 (spi_dev鍜宨nit_in_service涓哄彲閫夊弬鏁) - local lcd_init = lcd.init( - lcd_model, - config, - config.spi_dev and config.spi_dev or nil, - config.init_in_service and config.init_in_service or nil - ) - log.info("exlcd", "LCD鍒濆鍖", lcd_init) - - -- 鑷畾涔夊垵濮嬪寲瀹屾垚纭 - if lcd_model == "custom" then - lcd.user_done() - end - return lcd_init -end - ---[[ -璁剧疆鑳屽厜浜害 -@api exlcd.set_bl(level) -@number level 浜害绾у埆锛0-100锛0琛ㄧず鍏抽棴鑳屽厜 -@return bool 璁剧疆鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage --- 璁剧疆50%浜害 -exlcd.set_bl(50) - --- 鍏抽棴鑳屽厜 -exlcd.set_bl(0) -]] - -function exlcd.set_bl(level) - -- 妫鏌WM閰嶇疆 - if not screen_state.lcd_config.pin_pwm then - log.error("exlcd", "PWM閰嶇疆涓嶅瓨鍦紝鏃犳硶璋冭妭鑳屽厜") - return false - end - - -- 纭繚GPIO宸插叧闂 - if screen_state.lcd_config.pin_pwr then - gpio.close(screen_state.lcd_config.pin_pwr) - end - - -- 璁剧疆骞跺紑鍚疨WM - pwm.stop(screen_state.lcd_config.pin_pwm) - pwm.close(screen_state.lcd_config.pin_pwm) - pwm.setup(screen_state.lcd_config.pin_pwm, 1000, 100) - pwm.open(screen_state.lcd_config.pin_pwm, 1000, level) - screen_state.last_brightness = level - screen_state.backlight_on = (level > 0) - log.info("exlcd", "鑳屽厜璁剧疆涓", level, "%") - return true -end - ---[[ -鑾峰彇褰撳墠鑳屽厜浜害 -@api exlcd.get_bl() -@return number 褰撳墠鑳屽厜浜害绾у埆(0-100) -@usage -local brightness = exlcd.get_bl() -log.info("褰撳墠鑳屽厜浜害", brightness) -]] -function exlcd.get_bl() - return screen_state.last_brightness -end - ---[[ -灞忓箷杩涘叆浼戠湢鐘舵 -@api exlcd.sleep() -@usage -exlcd.sleep() -]] -function exlcd.sleep() - if not screen_state.is_sleeping then - -- 鍏抽棴PWM鑳屽厜 (濡傛灉閰嶇疆浜) - if screen_state.lcd_config and screen_state.lcd_config.pin_pwm then - pwm.close(screen_state.lcd_config.pin_pwm) - end - - -- 鍏抽棴鑳屽厜鐢垫簮 (濡傛灉閰嶇疆浜) - if screen_state.lcd_config and screen_state.lcd_config.pin_pwr then - gpio.setup(screen_state.lcd_config.pin_pwr, 1, gpio.PULLUP) - gpio.set(screen_state.lcd_config.pin_pwr, 0) - end - - -- 鎵цLCD鐫＄湢 - lcd.sleep() - screen_state.is_sleeping = true - log.info("exlcd", "LCD杩涘叆浼戠湢鐘舵") - end -end - ---[[ -灞忓箷浠庝紤鐪犵姸鎬佸敜閱 -@api exlcd.wakeup() -@usage -exlcd.wakeup() -]] -function exlcd.wakeup() - if screen_state.is_sleeping then - -- 寮鍚儗鍏夌數婧 (濡傛灉閰嶇疆浜) - if screen_state.lcd_config and screen_state.lcd_config.pin_pwr then - gpio.set(screen_state.lcd_config.pin_pwr, 1) - end - - -- 鍞ら啋LCD - lcd.wakeup() - sys.wait(100) -- 绛夊緟100ms绋冲畾 - - -- 鎭㈠鑳屽厜璁剧疆 (濡傛灉閰嶇疆浜哖WM寮曡剼) - if screen_state.lcd_config and screen_state.lcd_config.pin_pwm then - pwm.setup(screen_state.lcd_config.pin_pwm, 1000, screen_state.last_brightness) - pwm.open(screen_state.lcd_config.pin_pwm, 1000, screen_state.last_brightness) - end - - screen_state.is_sleeping = false - log.info("exlcd", "LCD鍞ら啋") - end -end - ---[[ -鑾峰彇灞忓箷浼戠湢鐘舵 -@api exlcd.get_sleep() -@return bool true琛ㄧず灞忓箷澶勪簬浼戠湢鐘舵侊紝false琛ㄧず灞忓箷澶勪簬宸ヤ綔鐘舵 -@usage -if exlcd.get_sleep() then - log.info("灞忓箷澶勪簬浼戠湢鐘舵") -end -]] -function exlcd.get_sleep() - return screen_state.is_sleeping -end - -return exlcd \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus.lua deleted file mode 100644 index a295849..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus.lua +++ /dev/null @@ -1,387 +0,0 @@ ---[[ -@module exmodbus -@summary exmodbus 鎺у埗Modbus RTU/ASCII/TCP涓荤珯/浠庣珯閫氫俊 -@version 1.0 -@date 2025. -@author 椹ⅵ闃 -@usage -鏈枃浠剁殑瀵瑰鎺ュ彛鏈 5 涓細 -1銆乪xmodbus.create(config)锛氬垱寤 modbus 涓荤珯/浠庣珯锛屾敮鎸 RTU銆丄SCII銆乀CP 涓夌閫氫俊妯″紡 -2銆乵odbus:read(config)锛氫富绔欏悜浠庣珯鍙戣捣璇诲彇璇锋眰锛堜粎閫傜敤浜 RTU銆丄SCII銆乀CP 涓荤珯妯″紡锛 -3銆乵odbus:write(config)锛氫富绔欏悜浠庣珯鍙戣捣鍐欏叆璇锋眰锛堜粎閫傜敤浜 RTU銆丄SCII銆乀CP 涓荤珯妯″紡锛 -4銆乵odbus:destroy()锛氶攢姣 modbus 涓荤珯/浠庣珯瀹炰緥瀵硅薄 -5銆乵odbus:on(callback)锛氫粠绔欐敞鍐屽洖璋冩帴鍙ｏ紝鐢ㄤ簬澶勭悊涓荤珯鍙戣捣鐨勮姹傦紙浠呴傜敤浜 RTU銆丄SCII銆乀CP 浠庣珯妯″紡锛 -]] -local exmodbus = {} - --- 瀹氫箟閫氫俊妯″紡甯搁噺 -exmodbus.RTU_MASTER = 0 -- RTU 涓荤珯妯″紡 -exmodbus.RTU_SLAVE = 1 -- RTU 浠庣珯妯″紡 -exmodbus.ASCII_MASTER = 2 -- ASCII 涓荤珯妯″紡 -exmodbus.ASCII_SLAVE = 3 -- ASCII 浠庣珯妯″紡 -exmodbus.TCP_MASTER = 4 -- TCP 涓荤珯妯″紡 -exmodbus.TCP_SLAVE = 5 -- TCP 浠庣珯妯″紡 - --- 瀹氫箟鏁版嵁绫诲瀷甯搁噺 -exmodbus.COIL_STATUS = 0 -- 绾垮湀鐘舵 -exmodbus.INPUT_STATUS = 1 -- 绂绘暎杈撳叆鐘舵 -exmodbus.HOLDING_REGISTER = 4 -- 淇濇寔瀵勫瓨鍣 -exmodbus.INPUT_REGISTER = 3 -- 杈撳叆瀵勫瓨鍣 - --- 瀹氫箟鎿嶄綔绫诲瀷甯搁噺 -exmodbus.READ_COILS = 0x01 -- 璇荤嚎鍦堢姸鎬 -exmodbus.READ_DISCRETE_INPUTS = 0x02 -- 璇荤鏁ｈ緭鍏ョ姸鎬 -exmodbus.READ_HOLDING_REGISTERS = 0x03 -- 璇讳繚鎸佸瘎瀛樺櫒 -exmodbus.READ_INPUT_REGISTERS = 0x04 -- 璇昏緭鍏ュ瘎瀛樺櫒 -exmodbus.WRITE_SINGLE_COIL = 0x05 -- 鍐欏崟涓嚎鍦堢姸鎬 -exmodbus.WRITE_SINGLE_HOLDING_REGISTER = 0x06 -- 鍐欏崟涓繚鎸佸瘎瀛樺櫒 -exmodbus.WRITE_MULTIPLE_HOLDING_REGISTERS = 0x10 -- 鍐欏涓繚鎸佸瘎瀛樺櫒 -exmodbus.WRITE_MULTIPLE_COILS = 0x0F -- 鍐欏涓嚎鍦堢姸鎬 - --- 瀹氫箟鍝嶅簲缁撴灉甯搁噺 -exmodbus.STATUS_SUCCESS = 0 -- 鏀跺埌鍝嶅簲鏁版嵁涓旀暟鎹湁鏁 -exmodbus.STATUS_DATA_INVALID = 1 -- 鏀跺埌鍝嶅簲鏁版嵁浣嗘暟鎹崯鍧/鏍￠獙澶辫触 -exmodbus.STATUS_EXCEPTION = 2 -- 鏀跺埌鏍囧噯寮傚父鍝嶅簲鐮 -exmodbus.STATUS_TIMEOUT = 3 -- 瓒呮椂鏈敹鍒板搷搴 -exmodbus.STATUS_PARAM_INVALID = 4 -- 璇锋眰鍙傛暟涓嶆纭 - --- 寮傚父鍝嶅簲鐮佸父閲 -exmodbus.ILLEGAL_FUNCTION = 0x01 -- 涓嶆敮鎸佽姹傜殑鍔熻兘鐮 -exmodbus.ILLEGAL_DATA_ADDRESS = 0x02 -- 璇锋眰鐨勬暟鎹湴鍧鏃犳晥鎴栬秴鍑鸿寖鍥 -exmodbus.ILLEGAL_DATA_VALUE = 0x03 -- 璇锋眰鐨勬暟鎹兼棤鏁 -exmodbus.SLAVE_DEVICE_FAILURE = 0x04 -- 浠庣珯鍦ㄦ墽琛屾搷浣滄椂鍙戠敓鍐呴儴閿欒 -exmodbus.ACKNOWLEDGE = 0x05 -- 璇锋眰宸叉帴鍙楋紝浣嗛渶瑕侀暱鏃堕棿澶勭悊 -exmodbus.SLAVE_DEVICE_BUSY = 0x06 -- 浠庣珯姝ｅ繖锛屾棤娉曞鐞嗚姹 -exmodbus.NEGATIVE_ACKNOWLEDGE = 0x07 -- 鏃犳硶鎵ц缂栫▼鍔熻兘 -exmodbus.MEMORY_PARITY_ERROR = 0x08 -- 鍐呭瓨濂囧伓鏍￠獙閿欒 -exmodbus.GATEWAY_PATH_UNAVAILABLE = 0x0A -- 缃戝叧璺緞涓嶅彲鐢 -exmodbus.GATEWAY_TARGET_NO_RESPONSE = 0x0B -- 缃戝叧鐩爣璁惧鏃犲搷搴 - --- 鍏ㄥ眬闃熷垪涓庤皟搴﹀櫒锛 -local request_queue = {} -local next_request_id = 1 -local scheduler_started = false - --- 鐢熸垚鍞竴璇锋眰 ID锛 -local function gen_request_id() - local id = next_request_id - next_request_id = next_request_id + 1 - -- 纭繚璇锋眰 ID 鍦 32 浣嶆湁绗﹀彿鏁存暟鑼冨洿鍐咃紱 - if next_request_id == 0x7FFFFFFF then next_request_id = 1 end - return id -end - --- 澶勭悊闃熷垪涓殑璇锋眰锛 -local function process_request_queue() - while true do - if #request_queue > 0 then - local req = table.remove(request_queue, 1) - local instance = req.instance - local config = req.config - local is_read = req.is_read - local req_id = req.request_id - - local result - if is_read then - result = instance:read_internal(config) - else - result = instance:write_internal(config) - end - - sys.publish("exmodbus/resp/" .. req_id, result) - else - sys.waitUntil("start_scheduler") - end - end -end - --- 鍚姩璋冨害鍣紱 -local function start_scheduler() - if scheduler_started then return end - scheduler_started = true - sys.taskInit(process_request_queue) -end - --- 鍏ラ槦璇锋眰骞剁瓑寰呭搷搴旓紱锛堝唴閮ㄤ娇鐢級 -function exmodbus.enqueue_request(instance, config, is_read) - -- 鐢熸垚鍞竴璇锋眰 ID锛 - local req_id = gen_request_id() - - -- 妫鏌ラ槦鍒楁槸鍚︿负绌猴紱 - -- 濡傛灉涓虹┖锛屽厛鍏ラ槦锛岀劧鍚庡彂甯冧富棰樺憡鐭ヨ皟搴﹀櫒寮濮嬪鐞嗭紱 - -- 濡傛灉涓嶄负绌猴紝鍒欑洿鎺ュ叆闃燂紝涓嶇敤鍛婄煡璋冨害鍣紱 - if #request_queue == 0 then - -- 鍏ラ槦璇锋眰锛 - table.insert(request_queue, { - instance = instance, - config = config, - is_read = is_read, - request_id = req_id - }) - - sys.publish("start_scheduler") - else - -- 鍏ラ槦璇锋眰锛 - table.insert(request_queue, { - instance = instance, - config = config, - is_read = is_read, - request_id = req_id - }) - end - - -- 鍚姩璋冨害鍣紱 - start_scheduler() - local ok, result = sys.waitUntil("exmodbus/resp/" .. req_id) - - return result -end - ---[[ -鍒涘缓涓涓柊鐨勫疄渚嬶紱 -@api exmodbus.create(config) -@param config table 閰嶇疆鍙傛暟琛紝鍖呭惈浠ヤ笅瀛楁锛 - mode number 閫氫俊妯″紡锛屽繀椤绘槸 exmodbus 妯″潡瀹氫箟鐨勫父閲忥紙濡 exmodbus.RTU_MASTER锛 - uart_id number 涓插彛 ID锛寀art0 鍐 0锛寀art1 鍐 1锛屼互姝ょ被鎺 - baud_rate number 娉㈢壒鐜 - data_bits number 鏁版嵁浣 - stop_bits number 鍋滄浣 - parity_bits number 鏍￠獙浣 - byte_order number 瀛楄妭椤哄簭 - rs485_dir_gpio number RS485 鏂瑰悜杞崲 GPIO 寮曡剼 - rs485_dir_rx_level number RS485 鎺ユ敹鏂瑰悜鐢靛钩 - adapter number 缃戝崱 ID - ip_address string 鏈嶅姟鍣 IP 鍦板潃 - port number 鏈嶅姟鍣ㄧ鍙ｅ彿 - is_udp boolean 鏄惁浣跨敤 UDP 鍗忚 - is_tls boolean 鏄惁浣跨敤鍔犲瘑浼犺緭 - keep_idle number 杩炴帴绌洪棽澶氶暱鏃堕棿鍚庯紝寮濮嬪彂閫佺涓涓 keepalive 鎺㈤拡鎶ユ枃锛屽崟浣嶏細绉 - keep_interval number 鍙戦佺涓涓帰閽堝悗锛屽鏋滄病鏀跺埌 ACK 鍥炲锛岄棿闅斿涔呭啀鍙戦佷笅涓涓帰閽堬紝鍗曚綅锛氱 - keep_cnt number 鎬诲叡鍙戦佸灏戞鎺㈤拡鍚庯紝濡傛灉渚濈劧娌℃湁鍥炲锛屽垯鍒ゆ柇杩炴帴宸叉柇寮 - server_cert string TCP 妯″紡涓嬬殑鏈嶅姟鍣 CA 璇佷功鏁版嵁锛孶DP 妯″紡涓嬬殑 PSK - client_cert string TCP 妯″紡涓嬬殑瀹㈡埛绔瘉涔︽暟鎹紝UDP 妯″紡涓嬬殑 PSK-ID - client_key string TCP 妯″紡涓嬬殑瀹㈡埛绔閽ュ姞瀵嗘暟鎹 - client_password string TCP 妯″紡涓嬬殑瀹㈡埛绔閽ュ彛浠ゆ暟鎹 -@return table/nil 鎴愬姛鏃惰繑鍥炲疄渚嬪璞★紝澶辫触鏃惰繑鍥 nil -@usage -RTU/ASCII 閫氫俊妯″紡锛 -local config = { - mode = exmodbus.RTU_MASTER, -- 閫氫俊妯″紡锛歊TU 涓荤珯 - uart_id = 1, -- 涓插彛 ID锛歶art1 - baud_rate = 115200, -- 娉㈢壒鐜囷細115200 - data_bits = 8, -- 鏁版嵁浣嶏細8 - stop_bits = 1, -- 鍋滄浣嶏細1 - parity_bits = uart.None, -- 鏍￠獙浣嶏細鏃犳牎楠 - byte_order = uart.LSB, -- 瀛楄妭椤哄簭锛氬皬绔簭 - rs485_dir_gpio = 23, -- RS485 鏂瑰悜杞崲 GPIO 寮曡剼 - rs485_dir_rx_level = 0 -- RS485 鎺ユ敹鏂瑰悜鐢靛钩锛0 涓轰綆鐢靛钩锛1 涓洪珮鐢靛钩 -} -local rtu_master = exmodbus.create(config) - -TCP 閫氫俊妯″紡锛 -local config = { - mode = exmodbus.TCP_MASTER, -- 閫氫俊妯″紡锛歍CP 涓荤珯 - adapter = socket.LWIP_ETH, -- 缃戝崱 ID锛歀wIP 鍗忚鏍堢殑浠ュお缃戝崱 - ip_address = "192.168.1.100", -- 鏈嶅姟鍣 IP 鍦板潃锛192.168.1.100锛堜富绔欙細鏈嶅姟鍣 IP锛涗粠绔欙細鏈湴 IP锛屼粠绔欏彲浠ヤ笉鐢ㄥ～姝ゅ弬鏁帮級 - port = 502, -- 鏈嶅姟鍣ㄧ鍙ｅ彿锛502锛堜富绔欙細鏈嶅姟鍣ㄧ鍙ｏ紱浠庣珯锛氭湰鍦扮鍙ｏ級 - is_udp = false, -- 鏄惁浣跨敤 UDP 鍗忚锛氫笉浣跨敤 UDP 鍗忚锛宖alse/nil 琛ㄧず浣跨敤 TCP 鍗忚 - is_tls = false, -- 鏄惁浣跨敤鍔犲瘑浼犺緭锛氫笉浣跨敤鍔犲瘑浼犺緭锛宖alse/nil 琛ㄧず涓嶄娇鐢ㄥ姞瀵 - keep_idle = 300, -- 杩炴帴绌洪棽澶氶暱鏃堕棿鍚庯紝寮濮嬪彂閫佺涓涓 keepalive 鎺㈤拡鎶ユ枃锛300 绉 - keep_interval = 10, -- 鍙戦佺涓涓帰閽堝悗锛屽鏋滄病鏀跺埌 ACK 鍥炲锛岄棿闅斿涔呭啀鍙戦佷笅涓涓帰閽堬細10 绉 - keep_cnt = 3, -- 鎬诲叡鍙戦佸灏戞鎺㈤拡鍚庯紝濡傛灉渚濈劧娌℃湁鍥炲锛屽垯鍒ゆ柇杩炴帴宸叉柇寮锛3 娆 - server_cert = nil, -- TCP 妯″紡涓嬬殑鏈嶅姟鍣 CA 璇佷功鏁版嵁锛孶DP 妯″紡涓嬬殑 PSK锛氬鏋滃鎴风涓嶉渶瑕侀獙璇佹湇鍔″櫒璇佷功锛屽垯璁句负 nil 鎴栫┖鐫 - client_cert = nil, -- TCP 妯″紡涓嬬殑瀹㈡埛绔瘉涔︽暟鎹紝UDP 妯″紡涓嬬殑 PSK-ID锛氬鏋滄湇鍔″櫒涓嶉渶瑕侀獙璇佸鎴风璇佷功锛屽垯璁句负 nil 鎴栫┖鐫 - client_key = nil, -- TCP 妯″紡涓嬬殑瀹㈡埛绔閽ュ姞瀵嗘暟鎹細濡傛灉鏈嶅姟鍣ㄤ笉闇瑕侀獙璇佸鎴风绉侀挜锛屽垯璁句负 nil 鎴栫┖鐫 - client_password = nil -- TCP 妯″紡涓嬬殑瀹㈡埛绔閽ュ彛浠ゆ暟鎹細濡傛灉鏈嶅姟鍣ㄤ笉闇瑕侀獙璇佸鎴风绉侀挜鍙ｄ护锛屽垯璁句负 nil 鎴栫┖鐫 -} -local tcp_master = exmodbus.create(config) ---]] -function exmodbus.create(config) - -- 妫鏌ラ厤缃弬鏁版槸鍚︽湁鏁堬紱 - if not config or type(config) ~= "table" then - log.error("exmodbus", "閰嶇疆蹇呴』鏄〃鏍肩被鍨") - return false - end - - -- 鏍规嵁閫氫俊妯″紡鍔犺浇瀵瑰簲鐨勬ā鍧楋紱 - if config.mode == exmodbus.RTU_MASTER or config.mode == exmodbus.RTU_SLAVE or - config.mode == exmodbus.ASCII_MASTER or config.mode == exmodbus.ASCII_SLAVE then - local result, mod = pcall(require, "exmodbus_rtu_ascii") - if not result then - log.error("exmodbus", "鍔犺浇 RTU/ASCII 妯″潡澶辫触") - return false - end - return mod.create(config, exmodbus, gen_request_id) - elseif config.mode == exmodbus.TCP_MASTER or config.mode == exmodbus.TCP_SLAVE then - local result, mod = pcall(require, "exmodbus_tcp") - if not result then - log.error("exmodbus", "鍔犺浇 TCP 妯″潡澶辫触") - return false - end - return mod.create(config, exmodbus, gen_request_id) - else - log.error("exmodbus", "閫氫俊妯″紡涓嶆敮鎸") - return false - end -end - ---[[ -涓荤珯鍚戜粠绔欏彂閫佽鍙栬姹傦紙浠呴傜敤浜 RTU銆丄SCII銆乀CP 涓荤珯妯″紡锛 -@api modbus:read(config) -@param config table 閰嶇疆鍙傛暟琛紝鍖呭惈浠ヤ笅瀛楁锛 - slave_id number 浠庣珯 ID - reg_type number 瀵勫瓨鍣ㄧ被鍨 - start_addr number 瀵勫瓨鍣ㄨ捣濮嬪湴鍧 - reg_count number 瀵勫瓨鍣ㄦ暟閲 - raw_request string 鍘熷璇锋眰甯 - timeout number 瓒呮椂鏃堕棿锛屽崟浣嶏細姣 -@return table 鍖呭惈浠ヤ笅瀛楁锛 - status number 鍝嶅簲缁撴灉鐘舵佺爜锛屽弬鑰 exmodbus 妯″潡瀹氫箟鐨勫父閲忥紙濡 exmodbus.STATUS_SUCCESS锛 - execption_code number 寮傚父鐮侊紝浠呭湪 status 涓 exmodbus.STATUS_EXCEPTION 鏃舵湁鏁 - data table 瀵勫瓨鍣ㄦ暟鍊硷紝浠呭湪 status 涓 exmodbus.STATUS_SUCCESS 鏃舵湁鏁堬紝鍖呭惈浠ヤ笅瀛楁 - [start_addr] number 瀵勫瓨鍣ㄦ暟鍊硷紝绱㈠紩涓哄瘎瀛樺櫒鍦板潃锛屽间负瀵勫瓨鍣ㄦ暟鍊 - ... - raw_response string 鍘熷鍝嶅簲甯 -@usage -鐢ㄦ埛鍦ㄤ紶鍏 config 鍙傛暟鏃讹紝鏈 鍘熷甯 鍜 瀛楁鍙傛暟 涓ょ鏂瑰紡 -1. 鍘熷甯ф柟寮 -local read_config = { - raw_request = "010300000002C40B", -- 鍘熷璇锋眰甯э細01 03 00 00 00 02 C4 0B锛堣鍙栦繚鎸佸瘎瀛樺櫒 0x0000 寮濮嬬殑 2 涓瘎瀛樺櫒锛 - timeout = 1000 -- 瓒呮椂鏃堕棿锛1000 姣 -} -local result = modbus:read(read_config) -if result.status == exmodbus.STATUS_SUCCESS then - log.info("exmodbus_test", "璇诲彇鎴愬姛锛屽師濮嬪搷搴斿抚: ", table.concat(result.raw_response, ", ")) -elseif result.status == exmodbus.STATUS_TIMEOUT then - log.error("exmodbus_test", "璇诲彇璇锋眰瓒呮椂") -else - log.error("exmodbus_test", "璇诲彇澶辫触") -end - -2. 瀛楁鍙傛暟鏂瑰紡 -local read_config = { - slave_id = 1, -- 浠庣珯 ID锛1 - reg_type = exmodbus.HOLDING_REGISTER, -- 瀵勫瓨鍣ㄧ被鍨嬶細淇濇寔瀵勫瓨鍣 - start_addr = 0x0000, -- 瀵勫瓨鍣ㄨ捣濮嬪湴鍧锛0 - reg_count = 0x0002, -- 瀵勫瓨鍣ㄦ暟閲忥細2 - timeout = 1000 -- 瓒呮椂鏃堕棿锛1000 姣 -} - -local result = modbus:read(read_config) --- 鏍规嵁杩斿洖鐘舵佸鐞嗙粨鏋 -if result.status == exmodbus.STATUS_SUCCESS then - -- 鏁版嵁瑙ｆ瀽锛 - log.info("exmodbus_test", "鎴愬姛璇诲彇鍒颁粠绔 1 淇濇寔瀵勫瓨鍣 0-2 鐨勫硷紝瀵勫瓨鍣 0 鏁板硷細", result.data[result.start_addr], - "锛屽瘎瀛樺櫒 1 鏁板硷細", result.data[result.start_addr + 1]) -elseif result.status == exmodbus.STATUS_DATA_INVALID then - log.info("exmodbus_test", "鏀跺埌浠庣珯 1 鐨勫搷搴旀暟鎹絾鏁版嵁鎹熷潖/鏍￠獙澶辫触") -elseif result.status == exmodbus.STATUS_EXCEPTION then - log.info("exmodbus_test", "鏀跺埌浠庣珯 1 鐨 modbus 鏍囧噯寮傚父鍝嶅簲锛屽紓甯哥爜涓", result.execption_code) -elseif result.status == exmodbus.STATUS_TIMEOUT then - log.info("exmodbus_test", "鏈敹鍒颁粠绔 1 鐨勫搷搴旓紙瓒呮椂锛") -end ---]] --- 璇ユ帴鍙ｅ湪鍚勪釜瀛愭枃浠朵腑锛屾澶勪粎鐢ㄤ綔娉ㄩ噴 --- function modbus:read(config) end - - ---[[ -涓荤珯鍚戜粠绔欏彂閫佸啓鍏ヨ姹傦紙浠呴傜敤浜 RTU銆丄SCII銆乀CP 涓荤珯妯″紡锛 -@api modbus:write(config) -@param config table 閰嶇疆鍙傛暟琛紝鍖呭惈浠ヤ笅瀛楁锛 - slave_id number 浠庣珯 ID - reg_type number 瀵勫瓨鍣ㄧ被鍨 - start_addr number 瀵勫瓨鍣ㄨ捣濮嬪湴鍧 - reg_count number 瀵勫瓨鍣ㄦ暟閲 - data table 瀵勫瓨鍣ㄦ暟鍊硷紝鍖呭惈浠ヤ笅瀛楁锛 - [start_addr] number 瀵勫瓨鍣ㄦ暟鍊硷紝绱㈠紩涓哄瘎瀛樺櫒鍦板潃锛屽间负瀵勫瓨鍣ㄦ暟鍊 - ... - force_multiple boolean 鏄惁寮哄埗浣跨敤鍐欏涓姛鑳界爜杩涜鍐欏叆鍗曚釜瀵勫瓨鍣ㄦ搷浣 - raw_request string 鍘熷璇锋眰甯 - timeout number 瓒呮椂鏃堕棿锛屽崟浣嶏細姣 -@return table 鍖呭惈浠ヤ笅瀛楁锛 - status number 鍝嶅簲缁撴灉鐘舵佺爜锛屽弬鑰 exmodbus 妯″潡瀹氫箟鐨勫父閲忥紙濡 exmodbus.STATUS_SUCCESS锛 - execption_code number 寮傚父鐮侊紝浠呭湪 status 涓 exmodbus.STATUS_EXCEPTION 鏃舵湁鏁 - raw_response string 鍘熷鍝嶅簲甯 -@usage -鐢ㄦ埛鍦ㄤ紶鍏 config 鍙傛暟鏃讹紝鏈 鍘熷甯 鍜 瀛楁鍙傛暟 涓ょ鏂瑰紡 -1. 鍘熷甯ф柟寮 -local write_config = { - raw_request = "011000000002007B01592471", -- 鍘熷璇锋眰甯э細01 10 00 00 00 02 00 7B 01 59 24 71锛堝啓鍏ヤ繚鎸佸瘎瀛樺櫒 0x0000 寮濮嬬殑 2 涓瘎瀛樺櫒锛屽间负 0x007B 鍜 0x0159锛 - timeout = 1000 -- 瓒呮椂鏃堕棿锛1000 姣 -} -local result = modbus:write(write_config) -if result.status == exmodbus.STATUS_SUCCESS then - log.info("exmodbus_test", "鍐欏叆鎴愬姛锛屽師濮嬪搷搴斿抚: ", table.concat(result.raw_response, ", ")) -elseif result.status == exmodbus.STATUS_TIMEOUT then - log.error("exmodbus_test", "鍐欏叆璇锋眰瓒呮椂") -else - log.error("exmodbus_test", "鍐欏叆澶辫触") -end - -2. 瀛楁鍙傛暟鏂瑰紡 -local write_config = { - slave_id = 1, -- 浠庣珯 ID锛1 - reg_type = exmodbus.HOLDING_REGISTER, -- 瀵勫瓨鍣ㄧ被鍨嬶細淇濇寔瀵勫瓨鍣 - start_addr = 0x0000, -- 瀵勫瓨鍣ㄨ捣濮嬪湴鍧锛0 - reg_count = 0x0002, -- 瀵勫瓨鍣ㄦ暟閲忥細2 - data = { - [0x0000] = 0x007B, -- 瀵勫瓨鍣 0 鏁板硷細0x007B - [0x0001] = 0x0159, -- 瀵勫瓨鍣 1 鏁板硷細0x0159 - }, - timeout = 1000 -- 瓒呮椂鏃堕棿锛1000 姣 -} - -local result = modbus:write(write_config) --- 鏍规嵁杩斿洖鐘舵佸鐞嗙粨鏋 -if result.status == exmodbus.STATUS_SUCCESS then - log.info("exmodbus_test", "鎴愬姛鍐欏叆浠庣珯 1 淇濇寔瀵勫瓨鍣 0-2 鐨勫") -elseif result.status == exmodbus.STATUS_DATA_INVALID then - log.info("exmodbus_test", "鏀跺埌浠庣珯 1 鐨勫搷搴旀暟鎹絾鏁版嵁鎹熷潖/鏍￠獙澶辫触") -elseif result.status == exmodbus.STATUS_EXCEPTION then - log.info("exmodbus_test", "鏀跺埌浠庣珯 1 鐨 modbus 鏍囧噯寮傚父鍝嶅簲锛屽紓甯哥爜涓", result.execption_code) -elseif result.status == exmodbus.STATUS_TIMEOUT then - log.info("exmodbus_test", "鏈敹鍒颁粠绔 1 鐨勫搷搴旓紙瓒呮椂锛") -end ---]] --- 璇ユ帴鍙ｅ湪鍚勪釜瀛愭枃浠朵腑锛屾澶勪粎鐢ㄤ綔娉ㄩ噴 --- function modbus:write(config) end - - ---[[ -閿姣 modbus 涓荤珯/浠庣珯瀹炰緥瀵硅薄 -@api modbus:destroy() -@return nil -@usage -modbus:destroy() ---]] --- 璇ユ帴鍙ｅ湪鍚勪釜瀛愭枃浠朵腑锛屾澶勪粎鐢ㄤ綔娉ㄩ噴 --- function modbus:destroy() end - - ---[[ -浠庣珯娉ㄥ唽鍥炶皟鎺ュ彛锛岀敤浜庡鐞嗕富绔欏彂璧风殑璇锋眰锛堜粎閫傜敤浜 RTU銆丄SCII銆乀CP 浠庣珯妯″紡锛 -@api modbus:on(callback) -@param callback function 鍥炶皟鍑芥暟锛屾牸寮忎负锛 - function callback(request) - -- 鐢ㄦ埛浠ｇ爜 - end - 璇ュ洖璋冨嚱鏁版帴鏀 requset 涓涓弬鏁帮紝璇ュ弬鏁颁负 table 绫诲瀷锛屽寘鍚互涓嬪瓧娈碉細 - slave_id number 浠庣珯 ID - func_code number 鍔熻兘鐮 - reg_type number 瀵勫瓨鍣ㄧ被鍨 - start_addr number 瀵勫瓨鍣ㄨ捣濮嬪湴鍧 - reg_count number 瀵勫瓨鍣ㄦ暟閲 - data table 瀵勫瓨鍣ㄦ暟鍊硷紝鍖呭惈浠ヤ笅瀛楁锛 - [start_addr] number 瀵勫瓨鍣ㄦ暟鍊硷紝绱㈠紩涓哄瘎瀛樺櫒鍦板潃锛屽间负瀵勫瓨鍣ㄦ暟鍊 - ... -@return nil -@usage -function callback(request) - -- 鐢ㄦ埛澶勭悊浠ｇ爜 -end ---]] --- 璇ユ帴鍙ｅ湪鍚勪釜瀛愭枃浠朵腑锛屾澶勪粎鐢ㄤ綔娉ㄩ噴 --- modbus:on(callback) - -return exmodbus diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_rtu_ascii.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_rtu_ascii.lua deleted file mode 100644 index 3441a03..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_rtu_ascii.lua +++ /dev/null @@ -1,1071 +0,0 @@ --- 瀹氫箟绫荤粨鏋勶紱 -local modbus = {} -- 瀹氫箟 modbus 瀹炰緥鐨勫厓琛紱 -modbus.__index = modbus -- 瀹氫箟 modbus 瀹炰緥鐨勭储寮曞厓鏂规硶锛岀敤浜庤闂疄渚嬬殑灞炴э紱 -modbus.__metatable = "instance is protected" -- 瀹氫箟 modbus 瀹炰緥鐨勫厓琛紝闃叉澶栭儴淇敼锛 - --- 妯″潡绾у彉閲忥細渚濊禆娉ㄥ叆鐨勫紩鐢紱 -local exmodbus_ref -- 涓绘ā鍧楀紩鐢紝鐢ㄤ簬璁块棶enqueue_request绛夋牳蹇冨姛鑳斤紱 -local gen_id_func -- ID鐢熸垚鍑芥暟寮曠敤锛岀敤浜庣敓鎴愬敮涓璇锋眰ID锛 - --- 鍒涘缓 modbus 瀹炰緥鐨勬瀯閫犲嚱鏁帮紱 -function modbus:new(config) - local obj = { - mode = config.mode, -- 閫氫俊妯″紡 - uart_id = config.uart_id, -- 涓插彛 ID - baud_rate = config.baud_rate, -- 娉㈢壒鐜 - data_bits = config.data_bits, -- 鏁版嵁浣 - stop_bits = config.stop_bits, -- 鍋滄浣 - parity_bits = config.parity_bits, -- 鏍￠獙浣 - byte_order = config.byte_order, -- 瀛楄妭搴 - rs485_dir_gpio = config.rs485_dir_gpio, -- RS485 鏂瑰悜鎺у埗 GPIO 寮曡剼 - rs485_dir_rx_level = config.rs485_dir_rx_level, -- RS485 鏂瑰悜鎺у埗鎺ユ敹鐢靛钩 - } - - -- 涓插彛鏄惁宸插垵濮嬪寲锛 - obj.uart_initialized = false - -- 褰撳墠绛夊緟鐨勪富棰橈紱 - obj.current_wait_request_id = nil - -- 浠庣珯璇锋眰澶勭悊鍥炶皟鍑芥暟锛 - obj.slaveHandler = nil - - -- 璁剧疆鍘熻〃锛 - setmetatable(obj, modbus) - -- 杩斿洖瀹炰緥锛 - return obj -end - --- 瑙ｆ瀽 Modbus RTU 璇锋眰甯э紙浠庣珯浣跨敤锛夛紱 -local function parse_rtu_request(frame) - -- 鏍￠獙璇锋眰甯ч暱搴︽槸鍚﹁嚦灏戜负 4 瀛楄妭锛堝寘鍚粠绔欏湴鍧銆佸姛鑳界爜鍜 CRC锛夛紱 - local frame_len = #frame - if frame_len < 4 then - return nil - end - - -- 浠呮牎楠 CRC锛堟牸寮忓熀纭鏍￠獙锛夛紱 - local calc_crc = crypto.crc16_modbus(frame:sub(1, -3)) - local recv_crc = string.byte(frame, -2) + bit.lshift(string.byte(frame, -1), 8) - if calc_crc ~= recv_crc then - -- log.warn("exmodbus", "璇锋眰甯 CRC 鏍￠獙澶辫触") - return nil - end - - -- 鎻愬彇浠庣珯鍦板潃鍜屽姛鑳界爜锛 - local slave_id = string.byte(frame, 1) - local func_code = string.byte(frame, 2) - - -- 鎵鏈夊瓧娈靛敖鍙兘鎻愬彇锛屽嵆浣垮煎彲鑳介潪娉曪紱 - local request_data = { - slave_id = slave_id, - func_code = func_code, - reg_type = nil, - start_addr = nil, - reg_count = nil, - data = {}, - } - - -- 璇昏姹傚拰鍗曞啓璇锋眰锛 - -- 鏍￠獙璇锋眰甯ч暱搴︽槸鍚︿负 8 瀛楄妭锛堝寘鍚粠绔欏湴鍧銆佸姛鑳界爜銆佽捣濮嬪湴鍧銆佸瘎瀛樺櫒鏁伴噺/瀵勫瓨鍣ㄥ煎拰 CRC锛夛紱 - if frame_len == 8 then - request_data.start_addr = bit.lshift(string.byte(frame, 3), 8) + string.byte(frame, 4) - request_data.reg_count = bit.lshift(string.byte(frame, 5), 8) + string.byte(frame, 6) - - -- 鍐欏崟涓嚎鍦堬紱 - if func_code == exmodbus_ref.WRITE_SINGLE_COIL then - local coil_val = bit.lshift(string.byte(frame, 5), 8) + string.byte(frame, 6) - request_data.reg_count = 1 - request_data.data[request_data.start_addr] = (coil_val == 0xFF00) and 1 or 0 - -- 鍐欏崟涓繚鎸佸瘎瀛樺櫒锛 - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - local reg_val = bit.lshift(string.byte(frame, 5), 8) + string.byte(frame, 6) - request_data.reg_count = 1 - request_data.data[request_data.start_addr] = reg_val - end - -- 澶氬啓璇锋眰锛 - -- 鏍￠獙璇锋眰甯ч暱搴︽槸鍚﹁嚦灏戜负 9 瀛楄妭锛堝寘鍚粠绔欏湴鍧銆佸姛鑳界爜銆佽捣濮嬪湴鍧銆佸瘎瀛樺櫒鏁伴噺銆佸瓧鑺傛暟閲忋佹暟鎹拰 CRC锛夛紱 - elseif frame_len >= 9 then - request_data.start_addr = bit.lshift(string.byte(frame, 3), 8) + string.byte(frame, 4) - request_data.reg_count = bit.lshift(string.byte(frame, 5), 8) + string.byte(frame, 6) - - -- 鍐欏涓嚎鍦堬紱 - if func_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - for i = 0, request_data.reg_count - 1 do - local byte_idx = 8 + math.floor(i / 8) - if byte_idx > frame_len - 2 then break end -- 闃叉瓒婄晫锛 - local bit_idx = i % 8 - local byte_val = string.byte(frame, byte_idx) - local bit_val = bit.band(byte_val, bit.lshift(1, bit_idx)) ~= 0 and 1 or 0 - request_data.data[request_data.start_addr + i] = bit_val - end - -- 鍐欏涓繚鎸佸瘎瀛樺櫒锛 - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - for i = 0, request_data.reg_count - 1 do - local pos = 8 + i * 2 - if pos + 1 > frame_len - 2 then break end -- 闃叉瓒婄晫锛 - local val = bit.lshift(string.byte(frame, pos), 8) + string.byte(frame, pos + 1) - request_data.data[request_data.start_addr + i] = val - end - end - end - - -- 瀵逛簬璇昏姹傦紝data 涓 nil锛岀敱鐢ㄦ埛澶勭悊璇婚昏緫锛 - if not request_data.data and ( - func_code == exmodbus_ref.READ_COILS or - func_code == exmodbus_ref.READ_DISCRETE_INPUTS or - func_code == exmodbus_ref.READ_HOLDING_REGISTERS or - func_code == exmodbus_ref.READ_INPUT_REGISTERS - ) then - request_data.data = nil -- request_data.data 淇濇寔 nil锛岀敱鐢ㄦ埛澶勭悊璇婚昏緫锛 - end - - return request_data -end - --- 鏋勫缓 Modbus RTU 鍝嶅簲甯э紙浠庣珯浣跨敤锛夛紱 -local function build_rtu_response(request, user_return) - local slave_id = request.slave_id - local func_code = request.func_code - - -- 鐢ㄦ埛杩斿洖寮傚父鐮 -> 寮傚父鍝嶅簲锛 - if type(user_return) == "number" then - local exception_code = user_return - local frame = string.char(slave_id, bit.bor(func_code, 0x80), exception_code) - local crc = crypto.crc16_modbus(frame) - return frame .. string.char(crc & 0xFF, (crc >> 8) & 0xFF) - end - - -- 鐢ㄦ埛杩斿洖琛 -> 姝ｅ父鍝嶅簲锛 - if type(user_return) ~= "table" then - log.error("exmodbus", "浠庣珯鍥炶皟蹇呴』杩斿洖 table 鎴 number锛屽疄闄呯被鍨: ", type(user_return)) - return nil - end - - local data_bytes = "" - - -- 澶勭悊璇荤嚎鍦堝拰璇荤鏁ｈ緭鍏ュ搷搴旓紱 - if func_code == exmodbus_ref.READ_COILS or func_code == exmodbus_ref.READ_DISCRETE_INPUTS then - local reg_count = request.reg_count - - -- 鏍￠獙 reg_count 鏄惁鏈夋晥锛 - if not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 reg_count 鏃犳晥") - return nil - end - - local byte_count = math.ceil(reg_count / 8) - local values = {} - - for i = 0, reg_count - 1 do - local addr = request.start_addr + i - local bit_val = user_return[addr] - if bit_val == nil then - log.error("exmodbus", "璇荤嚎鍦/绂绘暎杈撳叆鍥炶皟鏈繑鍥炲湴鍧 ", addr, " 鐨勬暟鎹") - return nil - end - if bit_val ~= 0 and bit_val ~= 1 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0 鎴 1锛屽疄闄: ", bit_val) - return nil - end - - local byte_idx = math.floor(i / 8) - if not values[byte_idx] then values[byte_idx] = 0 end - if bit_val == 1 then - values[byte_idx] = bit.bor(values[byte_idx], bit.lshift(1, i % 8)) - end - end - - data_bytes = string.char(byte_count) - for i = 0, byte_count - 1 do - data_bytes = data_bytes .. string.char(values[i] or 0) - end - -- 澶勭悊璇讳繚鎸佸瘎瀛樺櫒鍜岃杈撳叆瀵勫瓨鍣ㄥ搷搴旓紱 - elseif func_code == exmodbus_ref.READ_HOLDING_REGISTERS or func_code == exmodbus_ref.READ_INPUT_REGISTERS then - local reg_count = request.reg_count - -- 鏍￠獙 reg_count 鏄惁鏈夋晥锛 - if not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 reg_count 鏃犳晥") - return nil - end - - local values = "" - for i = 0, reg_count - 1 do - local addr = request.start_addr + i - local val = user_return[addr] - if val == nil then - log.error("exmodbus", "璇讳繚鎸佸瘎瀛樺櫒/杈撳叆瀵勫瓨鍣ㄥ洖璋冩湭杩斿洖鍦板潃 ", addr, " 鐨勬暟鎹") - return nil - end - if type(val) ~= "number" or val ~= math.floor(val) or val < 0 or val > 65535 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0~65535 鐨勬暣鏁帮紝瀹為檯: ", val) - return nil - end - values = values .. string.char((val >> 8) & 0xFF, val & 0xFF) - end - data_bytes = string.char(#values) .. values - -- 澶勭悊鍐欏崟涓嚎鍦堝搷搴旓紱 - elseif func_code == exmodbus_ref.WRITE_SINGLE_COIL then - local addr = request.start_addr - -- 鏍￠獙 start_addr 鏄惁鏈夋晥锛 - if addr == nil then - log.error("exmodbus", "璇锋眰涓 start_addr 鏃犳晥") - return nil - end - local coil_val = (request.data and request.data[addr]) or 0 - local resp_val = (coil_val ~= 0) and 0xFF00 or 0x0000 - data_bytes = string.char( - (addr >> 8) & 0xFF, addr & 0xFF, - (resp_val >> 8) & 0xFF, resp_val & 0xFF - ) - -- 澶勭悊鍐欏崟涓繚鎸佸瘎瀛樺櫒鍝嶅簲锛 - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - local addr = request.start_addr - -- 鏍￠獙 start_addr 鏄惁鏈夋晥锛 - if addr == nil then - log.error("exmodbus", "璇锋眰涓 start_addr 鏃犳晥") - return nil - end - local reg_val = (request.data and request.data[addr]) or 0 - -- 鏍￠獙 reg_val 鏄惁鏈夋晥锛 - if type(reg_val) ~= "number" or reg_val ~= math.floor(reg_val) or reg_val < 0 or reg_val > 65535 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0~65535 鐨勬暣鏁帮紝瀹為檯: ", reg_val) - return nil - end - data_bytes = string.char( - (addr >> 8) & 0xFF, addr & 0xFF, - (reg_val >> 8) & 0xFF, reg_val & 0xFF - ) - -- 澶勭悊鍐欏涓嚎鍦/淇濇寔瀵勫瓨鍣ㄥ搷搴旓紱 - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_COILS or func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - local start_addr = request.start_addr - local reg_count = request.reg_count - -- 鏍￠獙 start_addr 鍜 reg_count 鏄惁鏈夋晥锛 - if not start_addr or not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 start_addr 鎴 reg_count 鏃犳晥") - return nil - end - data_bytes = string.char( - (start_addr >> 8) & 0xFF, start_addr & 0xFF, - (reg_count >> 8) & 0xFF, reg_count & 0xFF - ) - -- 澶勭悊鏈煡鍔熻兘鐮侊紝瑙嗕负閿欒锛 - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮侊紝涓旀湭杩斿洖寮傚父鐮: ", func_code) - return nil - end - - local frame = string.char(slave_id, func_code) .. data_bytes - local crc = crypto.crc16_modbus(frame) - return frame .. string.char(crc & 0xFF, (crc >> 8) & 0xFF) -end - --- 鍒濆鍖栦覆鍙ｏ紱 -local function init_uart(instance) - -- 妫鏌ヤ覆鍙ｆ槸鍚﹀凡琚垵濮嬪寲锛 - if instance.uart_initialized then - log.warn("exmodbus", "涓插彛 ", instance.uart_id, " 宸茬粡鍒濆鍖栵紝鏃犻渶閲嶅鍒濆鍖") - return true - end - - -- 閰嶇疆涓插彛鍙傛暟锛屽苟寮鍚覆鍙ｅ姛鑳斤紱 - local result = uart.setup( - instance.uart_id, -- 涓插彛 ID - instance.baud_rate, -- 娉㈢壒鐜 - instance.data_bits, -- 鏁版嵁浣 - instance.stop_bits, -- 鍋滄浣 - instance.parity_bits, -- 鏍￠獙浣 - instance.byte_order, -- 瀛楄妭搴 - nil, -- 缂撳啿鍖哄ぇ灏 - instance.rs485_dir_gpio, -- RS485 鏂瑰悜鎺у埗 GPIO 寮曡剼 - instance.rs485_dir_rx_level -- RS485 鏂瑰悜鎺у埗鎺ユ敹鐢靛钩 - ) - -- 妫鏌ヤ覆鍙ｆ槸鍚﹀垵濮嬪寲鎴愬姛锛 - -- 鎴愬姛鏃惰繑鍥 0锛屽叾浠栬繑鍥炲艰〃绀哄け璐ワ紱 - if result ~= 0 then - log.error("exmodbus", "涓插彛 ", instance.uart_id, " 鍒濆鍖栧け璐") - return false - end - - -- 瀹氫箟鍙戦佸畬鎴愬洖璋冨嚱鏁帮紱 - -- 褰撲覆鍙ｅ彂閫佸畬鎴愭椂锛屽彂甯冧竴涓富棰橈紝閫氱煡鍏朵粬浠诲姟锛 - local function on_sent(uart_id) - sys.publish("exmodbus/sent/" .. uart_id, true) - end - - -- 瀹氫箟鎺ユ敹瀹屾垚鍥炶皟鍑芥暟锛 - -- 褰撲覆鍙ｆ帴鏀跺畬鎴愭椂锛屽鎺ユ敹鏁版嵁杩涜澶勭悊锛 - -- 澶勭悊鎴愬姛鏃讹紝鍙戝竷涓涓富棰橈紝閫氱煡鍏朵粬浠诲姟锛 - -- 澶勭悊澶辫触鏃讹紝涓嶅仛浠讳綍澶勭悊锛 - local function on_receive(uart_id, data_len) - local data = uart.read(uart_id, data_len) - if not data or #data == 0 then return end - - -- 澶勭悊 RTU 涓荤珯妯″紡涓嬬殑鎺ユ敹鏁版嵁锛 - if instance.mode == exmodbus_ref.RTU_MASTER then - -- 鏍￠獙绛夊緟涓婚鏄惁瀛樺湪锛 - if instance.current_wait_request_id then - -- 鍙戝竷涓婚锛岄氱煡鍏朵粬浠诲姟锛 - sys.publish("exmodbus/rtu_resp/" .. instance.current_wait_request_id, data) - -- 鍙戝竷鍚庯紝娓呴櫎绛夊緟涓婚锛 - instance.current_wait_request_id = nil - return - end - -- 澶勭悊 RTU 浠庣珯妯″紡涓嬬殑鎺ユ敹鏁版嵁锛 - elseif instance.mode == exmodbus_ref.RTU_SLAVE then - -- 瑙ｆ瀽 RTU 璇锋眰甯э紱 - local request = parse_rtu_request(data) - if request then - -- 骞挎挱鍦板潃锛0锛変笉鍝嶅簲锛 - if request.slave_id == 0 then - -- 璋冪敤鍥炶皟浠ュ厑璁哥敤鎴疯褰曟垨澶勭悊骞挎挱鍛戒护锛堝鍐欏瘎瀛樺櫒锛夛紱 - if instance.slaveHandler then - instance.slaveHandler(request) - -- 娉ㄦ剰锛氬嵆浣垮洖璋冭繑鍥炴暟鎹紝涔熶笉鍙戦佸搷搴旓紱 - end - -- 骞挎挱璇锋眰澶勭悊瀹屾瘯锛屼笉鍥炲锛 - return - end - if instance.slaveHandler then - local user_return = instance.slaveHandler(request) - local response_frame = build_rtu_response(request, user_return) - if response_frame then - uart.write(uart_id, response_frame) - else - log.error("exmodbus", "鏋勫缓鍝嶅簲甯уけ璐ワ紝浠庣珯鍦板潃:", request.slave_id) - end - else - log.warn("exmodbus", "鏀跺埌涓荤珯璇锋眰锛屼絾鏈敞鍐屽洖璋冨嚱鏁") - end - else - log.debug("exmodbus", "鏃犳晥 RTU 璇锋眰甯э紙CRC 鎴栨牸寮忛敊璇級") - end - return - end - end - - -- 娉ㄥ唽鍙戦佸畬鎴愬拰鎺ユ敹瀹屾垚鍥炶皟鍑芥暟锛 - uart.on(instance.uart_id, "sent", on_sent) - uart.on(instance.uart_id, "receive", on_receive) - - -- 鍒濆鍖栨垚鍔燂紝璁剧疆鏍囧織浣嶄负 true锛 - instance.uart_initialized = true - log.info("exmodbus", "涓插彛 " .. instance.uart_id .. " 鍒濆鍖栨垚鍔燂紝娉㈢壒鐜 " .. instance.baud_rate) - return true -end - --- 鍒涘缓涓涓柊鐨勫疄渚嬶紱 -local function create(config, exmodbus, gen_request_id) - exmodbus_ref = exmodbus - gen_id_func = gen_request_id - - -- 鍒涘缓涓涓柊鐨勫疄渚嬶紱 - local instance = modbus:new(config) - -- 妫鏌ュ疄渚嬫槸鍚﹀垱寤烘垚鍔燂紱 - if not instance then - log.error("exmodbus", "鍒涘缓 Modbus 瀹炰緥澶辫触") - return false - end - - -- 鍒濆鍖栦覆鍙ｏ紱 - local result = init_uart(instance) - -- 妫鏌ヤ覆鍙ｅ垵濮嬪寲缁撴灉锛 - if not result then - -- 閿姣佸凡鍒涘缓鐨勫疄渚嬶紝閲婃斁璧勬簮锛 - instance:destroy() - return false - end - - -- 杩斿洖瀹炰緥锛 - return instance -end - --- 閿姣佸凡鍒涘缓鐨勫疄渚嬶紝閲婃斁璧勬簮锛 -function modbus:destroy() - -- 妫鏌ュ疄渚嬫槸鍚﹀凡琚攢姣侊紱 - if not self then - log.error("exmodbus", "瀹炰緥瀵硅薄宸茶閿姣侊紝鏃犻渶閲嶅閿姣") - return - end - - -- 鍏抽棴涓插彛锛 - if self.uart_initialized then - uart.close(self.uart_id) - uart.on(self.uart_id, "sent", nil) - uart.on(self.uart_id, "receive", nil) - end - - -- 閲婃斁GPIO璧勬簮锛 - if self.rs485_dir_gpio then - gpio.close(self.rs485_dir_gpio) - end - - -- 閿姣佸凡鍒涘缓鐨勫疄渚嬶紱 - setmetatable(self, nil) - - log.info("exmodbus", "瀹炰緥瀵硅薄宸查攢姣") -end - --- 鏋勫缓 Modbus RTU 甯х殑鍑芥暟锛屾敮鎸佽鍙栧拰鍐欏叆鎿嶄綔锛涳紙涓荤珯浣跨敤锛 -local function build_rtu_frame(opt_type, config) - -- 鍙傛暟楠岃瘉锛 - if not config or type(config) ~= "table" then - log.error("exmodbus", "閰嶇疆蹇呴』鏄〃鏍肩被鍨") - return false - end - - -- 楠岃瘉蹇呰鍙傛暟锛 - if not config.slave_id then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: slave_id") - return false - end - - if not config.reg_type then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: reg_type") - return false - end - - if not config.start_addr then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: start_addr") - return false - end - - if not config.reg_count then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: reg_count") - return false - end - - if opt_type == "write" then - if not config.data then - log.error("exmodbus", "缂哄皯鍐欏叆璇锋眰蹇呰鍙傛暟: data") - return false - end - end - - -- 鍙傛暟鑼冨洿楠岃瘉锛 - if type(config.slave_id) ~= "number" or config.slave_id < 1 or config.slave_id > 247 then - log.error("exmodbus", "浠庣珯鍦板潃蹇呴』鍦 1-247 鑼冨洿鍐") - return false - end - - if type(config.start_addr) ~= "number" or config.start_addr < 0 or config.start_addr > 65535 then - log.error("exmodbus", "璧峰鍦板潃蹇呴』鍦 0-65535 鑼冨洿鍐") - return false - end - - if config.reg_type ~= exmodbus_ref.COIL_STATUS and config.reg_type ~= exmodbus_ref.INPUT_STATUS and - config.reg_type ~= exmodbus_ref.HOLDING_REGISTER and config.reg_type ~= exmodbus_ref.INPUT_REGISTER then - log.error("exmodbus", "鏃犳晥鐨勫瘎瀛樺櫒绫诲瀷: " .. tostring(config.reg_type)) - return false - end - - -- 鏍规嵁鎿嶄綔绫诲瀷鍜屽瘎瀛樺櫒绫诲瀷纭畾鍔熻兘鐮侊紱 - local function_code - if opt_type == "write" then - -- 鏍￠獙姣忎竴涓湴鍧鏄惁鏈夋暟鎹紝涓旀暟鎹槸鍚︿负鏁板瓧绫诲瀷锛 - for i = 0, config.reg_count - 1 do - local addr = config.start_addr + i - if config.data[addr] == nil then - log.error("exmodbus", "缂哄皯瀵勫瓨鍣ㄦ暟鎹", "address:", addr) - return false - end - if type(config.data[addr]) ~= "number" then - log.error("exmodbus", "瀵勫瓨鍣ㄦ暟鎹繀椤绘槸鏁板瓧绫诲瀷", "address:", addr) - return false - end - end - - -- 鍒ゆ柇鏄惁寮哄埗浣跨敤鍐欏涓姛鑳界爜锛 - local use_multiple = config.force_multiple - - if config.reg_count == 1 then - -- 鍐欏叆鍗曚釜绾垮湀鎴栧崟涓繚鎸佸瘎瀛樺櫒锛 - if not use_multiple then -- 浣跨敤鍐欏崟涓姛鑳界爜锛 - if config.reg_type == exmodbus_ref.COIL_STATUS then - function_code = exmodbus_ref.WRITE_SINGLE_COIL - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - function_code = exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER - end - else -- 浣跨敤鍐欏涓姛鑳界爜锛 - if config.reg_type == exmodbus_ref.COIL_STATUS then - function_code = exmodbus_ref.WRITE_MULTIPLE_COILS - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - function_code = exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS - end - end - elseif config.reg_count > 1 then - -- 鍐欏叆澶氫釜绾垮湀鎴栧瘎瀛樺櫒锛 - if config.reg_type == exmodbus_ref.COIL_STATUS then - function_code = exmodbus_ref.WRITE_MULTIPLE_COILS - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - function_code = exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS - end - end - elseif opt_type == "read" then - -- 璇荤嚎鍦堢姸鎬侊紱 - if config.reg_type == exmodbus_ref.COIL_STATUS then - function_code = exmodbus_ref.READ_COILS - -- 璇荤鏁ｈ緭鍏ョ姸鎬侊紱 - elseif config.reg_type == exmodbus_ref.INPUT_STATUS then - function_code = exmodbus_ref.READ_DISCRETE_INPUTS - -- 璇讳繚鎸佸瘎瀛樺櫒锛 - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - function_code = exmodbus_ref.READ_HOLDING_REGISTERS - -- 璇昏緭鍏ュ瘎瀛樺櫒锛 - elseif config.reg_type == exmodbus_ref.INPUT_REGISTER then - function_code = exmodbus_ref.READ_INPUT_REGISTERS - end - end - - local data_bytes - -- 鍔熻兘鐮 0x01 鍜 0x02锛氳鍙栫嚎鍦堢姸鎬佸拰绂绘暎杈撳叆鐘舵侊紱 - if function_code == exmodbus_ref.READ_COILS or function_code == exmodbus_ref.READ_DISCRETE_INPUTS then - -- 楠岃瘉鏁伴噺鑼冨洿锛 - if config.reg_count < 1 or config.reg_count > 2000 then - log.error("exmodbus", "绾垮湀/绂绘暎杈撳叆璇诲彇鏁伴噺瓒呭嚭鑼冨洿: " .. config.reg_count .. " (鑼冨洿: 1-2000)") - return false - end - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鏁伴噺锛夛紙澶х搴忥級锛 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF - ) - - -- 鍔熻兘鐮 0x03 鍜 0x04锛氳鍙栦繚鎸佸瘎瀛樺櫒鍜岃緭鍏ュ瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.READ_HOLDING_REGISTERS or function_code == exmodbus_ref.READ_INPUT_REGISTERS then - -- 楠岃瘉鏁伴噺鑼冨洿锛 - if config.reg_count < 1 or config.reg_count > 125 then - log.error("exmodbus", "瀵勫瓨鍣ㄨ鍙栨暟閲忚秴鍑鸿寖鍥: " .. config.reg_count .. " (鑼冨洿: 1-125)") - return false - end - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鏁伴噺锛夛紙瀛楄妭搴忎负澶х搴忥級锛 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF - ) - - -- 鍔熻兘鐮 0x05锛氬啓鍏ュ崟涓嚎鍦堬紱 - elseif function_code == exmodbus_ref.WRITE_SINGLE_COIL then - -- 鍐欏叆鍗曚釜绾垮湀锛屽煎繀椤绘槸 0xFF00 (ON) 鎴 0x0000 (OFF)锛 - local value = config.data[config.start_addr] ~= 0 and 0xFF00 or 0x0000 - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鍊硷級锛堝瓧鑺傚簭涓哄ぇ绔簭锛夛紱 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (value >> 8) & 0xFF, value & 0xFF - ) - - -- 鍔熻兘鐮 0x06锛氬啓鍏ュ崟涓繚鎸佸瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - -- 鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣紱 - local value = config.data[config.start_addr] - - -- 楠岃瘉瀵勫瓨鍣ㄥ艰寖鍥达紙16 浣嶆棤绗﹀彿鏁存暟锛夛紱 - if value < 0 or value > 65535 or value ~= math.floor(value) then - log.error("exmodbus", "瀵勫瓨鍣ㄥ煎繀椤绘槸 0~65535 鑼冨洿鍐呯殑鏁存暟锛屽疄闄呭: ", value) - return false - end - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鍊硷級锛堝瓧鑺傚簭涓哄ぇ绔簭锛夛紱 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (value >> 8) & 0xFF, value & 0xFF - ) - - -- 鍔熻兘鐮 0x0F锛氬啓鍏ュ涓嚎鍦堬紱 - elseif function_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - -- 楠岃瘉鏁伴噺鑼冨洿锛 - if config.reg_count < 1 or config.reg_count > 1968 then - log.error("exmodbus", "绾垮湀鍐欏叆鏁伴噺瓒呭嚭鑼冨洿: " .. config.reg_count .. " (鑼冨洿: 1-1968)") - return false - end - - -- 璁＄畻瀛楄妭鏁帮紱 - local byte_count = math.ceil(config.reg_count / 8) - local values_bytes = "" - - -- 鏋勫缓绾垮湀鏁版嵁锛堝瓧鑺傚簭涓哄ぇ绔簭锛夛紱 - for i = 0, byte_count - 1 do - local byte_value = 0 - -- 閬嶅巻褰撳墠瀛楄妭鐨 8 涓綅锛 - for j = 0, 7 do - local bit_index = i * 8 + j -- 璁＄畻褰撳墠姣旂壒鍦ㄦ暣涓嚎鍦堝簭鍒椾腑鐨勫叏灞绱㈠紩锛堜粠 0 寮濮嬶級锛 - -- 妫鏌ュ綋鍓嶆瘮鐗规槸鍚﹀湪鏈夋晥鑼冨洿鍐咃紱 - if bit_index < config.reg_count then - local addr = config.start_addr + bit_index -- 鏍规嵁璧峰鍦板潃鍜屽叏灞绱㈠紩璁＄畻瀹為檯鐨勭嚎鍦堝湴鍧锛 - local bit_val = config.data[addr] -- 鑾峰彇褰撳墠绾垮湀鐨勭姸鎬佸硷紙0 鎴 1锛夛紱 - if bit_val ~= nil and bit_val ~= 0 then - byte_value = byte_value | (1 << j) -- 濡傛灉鐘舵佷负 1锛屽垯灏嗗綋鍓嶄綅璁剧疆涓 1锛 - end - end - end - values_bytes = values_bytes .. string.char(byte_value) - end - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鏁伴噺 + 瀛楄妭鏁 + 绾垮湀鏁版嵁锛夛紙瀛楄妭搴忎负澶х搴忥級锛 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF, - byte_count - ) .. values_bytes - - -- 鍔熻兘鐮 0x10锛氬啓鍏ュ涓繚鎸佸瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - -- 楠岃瘉鏁伴噺鑼冨洿锛 - if config.reg_count < 1 or config.reg_count > 123 then - log.error("exmodbus", "瀵勫瓨鍣ㄥ啓鍏ユ暟閲忚秴鍑鸿寖鍥: " .. config.reg_count .. " (鑼冨洿: 1-123)") - return false - end - - -- 璁＄畻瀛楄妭鏁帮紱 - local byte_count = config.reg_count * 2 - local values_bytes = "" - - -- 鏋勫缓瀵勫瓨鍣ㄦ暟鎹紙瀛楄妭搴忎负澶х搴忥級锛 - for i = 0, config.reg_count - 1 do - local addr = config.start_addr + i - local value = config.data[addr] - values_bytes = values_bytes .. string.char( - (value >> 8) & 0xFF, value & 0xFF - ) - end - - -- 鏋勫缓鏁版嵁閮ㄥ垎锛堣捣濮嬪湴鍧 + 鏁伴噺 + 瀛楄妭鏁 + 瀵勫瓨鍣ㄦ暟鎹級锛堝瓧鑺傚簭涓哄ぇ绔簭锛夛紱 - data_bytes = string.char( - (config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF, - (config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF, - byte_count - ) .. values_bytes - - -- 鏈煡鍔熻兘鐮侊紱 - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮佹瀯寤: " .. function_code) - return false - end - - -- 鏋勫缓 Modbus RTU 甯э紙浠庣珯鍦板潃 + 鍔熻兘鐮 + 鏁版嵁锛夛紱 - local frame = string.char(config.slave_id, function_code) .. data_bytes - - -- 璁＄畻 CRC16 鏍￠獙骞舵坊鍔犲埌甯ф湯灏撅紙灏忕搴忥級锛 - local crc = crypto.crc16_modbus(frame) - frame = frame .. string.char(crc & 0xFF, (crc >> 8) & 0xFF) - - return frame, function_code -end - --- 鍙戦 Modbus 璇锋眰骞剁瓑寰呭搷搴旓紱 -local function sendRequest_waitResponse(instance, request_frame, config) - -- 鐢熸垚鍞竴璇锋眰ID锛 - local req_id = gen_id_func() - instance.current_wait_request_id = req_id - - -- 鎵ц鍙戦佽姹傦紱 - uart.write(instance.uart_id, request_frame) - - -- 绛夊緟鍙戦佸畬鎴愶紱 - local sent_ok = sys.waitUntil("exmodbus/sent/" .. instance.uart_id, 200) - if not sent_ok then - log.error("exmodbus", "鏁版嵁鍙戦佸け璐") - instance.current_wait_request_id = nil - return false, nil - end - - -- -- 鏄剧ず鍙戦佺殑HEX鏁版嵁锛 - -- local hex_str = "" - -- for i = 1, #request_frame do - -- hex_str = hex_str .. string.format("%02X ", string.byte(request_frame, i)) - -- end - -- log.info("exmodbus", "鍙戦佽姹傚懡浠ゆ垚鍔, HEX: " .. hex_str:sub(1, -2)) - - -- 绛夊緟鎺ユ敹鍝嶅簲锛 - local ok, response = sys.waitUntil("exmodbus/rtu_resp/" .. req_id, config.timeout or 1000) - - -- 娓呴櫎褰撳墠绛夊緟鐨勮姹侷D锛 - instance.current_wait_request_id = nil - - -- 鏄剧ず鎺ユ敹鐨凥EX鏁版嵁锛 - if ok then - -- hex_str = "" - -- for i = 1, #response do - -- hex_str = hex_str .. string.format("%02X ", string.byte(response, i)) - -- end - -- log.info("exmodbus", "鎺ユ敹鍝嶅簲鎴愬姛, HEX: " .. hex_str:sub(1, -2)) - return true, response - else - -- log.error("exmodbus", "鎺ユ敹鍝嶅簲澶辫触鎴栬秴鏃") - return false, nil - end -end - --- 瑙ｆ瀽 Modbus RTU 鍝嶅簲鎶ユ枃锛堜富绔欎娇鐢級锛 -local function parse_rtu_response(response, config, function_code) - -- 瀹氫箟杩斿洖鏁版嵁缁撴瀯锛 - local return_data = { - status = false, - execption_code = nil, - data = {}, - } - - -- 楠岃瘉鍝嶅簲鏄惁涓虹┖锛 - if not response or #response == 0 then - log.error("exmodbus", "鍝嶅簲鎶ユ枃涓虹┖") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 楠岃瘉鍝嶅簲闀垮害锛堟渶灏忛暱搴︼細浠庣珯鍦板潃 + 鍔熻兘鐮 + CRC = 4 瀛楄妭锛夛紱 - if not response or #response < 4 then - log.error("exmodbus", "鍝嶅簲鎶ユ枃闀垮害涓嶈冻") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鎻愬彇鍝嶅簲涓殑瀛楁锛 - local actual_slave_id = string.byte(response, 1) - local actual_function_code = string.byte(response, 2) - local response_length = #response - - -- 楠岃瘉浠庣珯鍦板潃鏄惁鍖归厤锛 - if actual_slave_id ~= config.slave_id then - log.error("exmodbus", "浠庣珯鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.slave_id, "瀹為檯:", actual_slave_id) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 妫鏌ユ槸鍚︿负寮傚父鍝嶅簲锛堝姛鑳界爜鏈楂樹綅涓 1锛夛紱 - if bit.band(actual_function_code, 0x80) ~= 0 then - -- 寮傚父鍝嶅簲鏍煎紡锛氫粠绔欏湴鍧(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 寮傚父鐮(1 瀛楄妭) + CRC(2 瀛楄妭)锛 - if response_length ~= 5 then - log.error("exmodbus", "寮傚父鍝嶅簲鎶ユ枃闀垮害涓嶆纭紝鏈熸湜: 5 瀛楄妭锛屽疄闄:", response_length, "瀛楄妭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鎻愬彇寮傚父鐮侊紙绗 3 瀛楄妭锛夛紱 - local exception_code = string.byte(response, 3) - log.error("exmodbus", "鎺ユ敹鍒 Modbus 寮傚父鍝嶅簲锛屽姛鑳界爜:", actual_function_code, "寮傚父鐮:", exception_code) - - return_data.status = exmodbus_ref.STATUS_EXCEPTION - return_data.execption_code = exception_code - return return_data - end - - -- 楠岃瘉鍔熻兘鐮佹槸鍚﹀尮閰嶏紱 - if actual_function_code ~= function_code then - log.error("exmodbus", "鍔熻兘鐮佷笉鍖归厤锛屾湡鏈:", function_code, "瀹為檯:", actual_function_code) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鏍规嵁涓嶅悓鐨勫姛鑳界爜瑙ｆ瀽鏁版嵁锛 - local parsed_data = {} - - -- 鍔熻兘鐮 0x01 鍜 0x02锛氳鍙栫嚎鍦堢姸鎬佸拰绂绘暎杈撳叆鐘舵侊紱 - if function_code == exmodbus_ref.READ_COILS or function_code == exmodbus_ref.READ_DISCRETE_INPUTS then - -- 鎻愬彇鏁版嵁閮ㄥ垎锛堜笉鍖呮嫭CRC锛夛紱 - local data_length = string.byte(response, 3) - local data_start_pos = 4 - local data_end_pos = response_length - 2 -- 鍑忓幓CRC闀垮害 - - -- 楠岃瘉鏁版嵁闀垮害鏄惁姝ｇ‘锛 - -- 娉ㄦ剰锛氳繖閲屽彧楠岃瘉鍝嶅簲鎶ユ枃涓０鏄庣殑鏁版嵁闀垮害涓庡疄闄呮暟鎹暱搴︽槸鍚︿竴鑷达紱 - if data_end_pos - data_start_pos + 1 ~= data_length then - log.error("exmodbus", "鏁版嵁闀垮害涓嶅尮閰嶏紝鏈熸湜:", data_length, "瀹為檯:", data_end_pos - data_start_pos + 1) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 楠岃瘉瀛楄妭鏁版槸鍚﹁冻澶熻〃绀烘寚瀹氭暟閲忕殑浣嶏紱 - local expected_bytes = math.ceil(config.reg_count / 8) - if data_length < expected_bytes then - log.error("exmodbus", "鏁版嵁瀛楄妭鏁颁笉瓒筹紝鏃犳硶琛ㄧず鎵鏈変綅") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽浣嶆暟鎹紱 - for i = 0, config.reg_count - 1 do - local modbus_addr = config.start_addr + i -- 璁＄畻褰撳墠浣嶅搴旂殑 Modbus 鍦板潃锛 - local byte_pos = data_start_pos + math.floor(i / 8) -- 璁＄畻褰撳墠浣嶅搴旂殑瀛楄妭浣嶇疆锛 - local bit_pos = i % 8 -- 璁＄畻褰撳墠浣嶅搴旂殑浣嶄綅缃紱 - local byte_value = string.byte(response, byte_pos) - parsed_data[modbus_addr] = bit.band(byte_value, bit.lshift(1, bit_pos)) ~= 0 and 1 or 0 - end - - -- 鍔熻兘鐮 0x03 鍜 0x04锛氳鍙栦繚鎸佸瘎瀛樺櫒鍜岃緭鍏ュ瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.READ_HOLDING_REGISTERS or function_code == exmodbus_ref.READ_INPUT_REGISTERS then - -- 鎻愬彇鏁版嵁閮ㄥ垎锛堜笉鍖呮嫭CRC锛夛紱 - local data_length = string.byte(response, 3) - local data_start_pos = 4 - local data_end_pos = response_length - 2 -- 鍑忓幓CRC闀垮害 - - -- 楠岃瘉鏁版嵁闀垮害鏄惁姝ｇ‘锛 - if data_end_pos - data_start_pos + 1 ~= data_length then - log.error("exmodbus", "鏁版嵁闀垮害涓嶅尮閰嶏紝鏈熸湜:", data_length, "瀹為檯:", data_end_pos - data_start_pos + 1) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 楠岃瘉瀛楄妭鏁版槸鍚﹁冻澶熻〃绀烘寚瀹氭暟閲忕殑瀵勫瓨鍣紱 - local expected_bytes = config.reg_count * 2 - if data_length < expected_bytes then - log.error("exmodbus", "鏁版嵁瀛楄妭鏁颁笉瓒筹紝鏃犳硶琛ㄧず鎵鏈夊瘎瀛樺櫒") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽瀵勫瓨鍣ㄦ暟鎹紙澶х搴忥級锛 - for i = 0, config.reg_count - 1 do - local modbus_addr = config.start_addr + i -- 璁＄畻褰撳墠瀵勫瓨鍣ㄥ搴旂殑 Modbus 鍦板潃锛 - local reg_pos = data_start_pos + i * 2 -- 璁＄畻褰撳墠瀵勫瓨鍣ㄥ搴旂殑瀛楄妭浣嶇疆锛 - parsed_data[modbus_addr] = bit.lshift(string.byte(response, reg_pos), 8) + string.byte(response, reg_pos + 1) - end - - -- 鍔熻兘鐮 0x05锛氬啓鍏ュ崟涓嚎鍦堬紱 - elseif function_code == exmodbus_ref.WRITE_SINGLE_COIL then - -- 鍐欏叆鍗曚釜绾垮湀鍝嶅簲鏍煎紡锛氫粠绔欏湴鍧(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 绾垮湀鍦板潃(2 瀛楄妭) + 绾垮湀鍊(2 瀛楄妭) + CRC(2 瀛楄妭)锛 - if response_length ~= 8 then - log.error("exmodbus", "鍐欏叆鍗曚釜绾垮湀鍝嶅簲鎶ユ枃闀垮害涓嶆纭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽绾垮湀鍦板潃鍜屽硷紱 - local coil_addr = bit.lshift(string.byte(response, 3), 8) + string.byte(response, 4) - local coil_value = bit.lshift(string.byte(response, 5), 8) + string.byte(response, 6) - - -- 楠岃瘉鍦板潃鏄惁鍖归厤璇锋眰锛 - if config.start_addr and coil_addr ~= config.start_addr then - log.error("exmodbus", "绾垮湀鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", coil_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 绾垮湀鍊煎簲璇ユ槸 0x0000(OFF) 鎴 0xFF00(ON)锛 - local normalized_value = (coil_value == 0x0000) and 0 or 1 - parsed_data[coil_addr] = normalized_value - - -- 鍔熻兘鐮 0x06锛氬啓鍏ュ崟涓繚鎸佸瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - -- 鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀牸寮忥細浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 瀵勫瓨鍣ㄥ湴鍧(2 瀛楄妭) + 瀵勫瓨鍣ㄥ(2 瀛楄妭) + CRC(2 瀛楄妭)锛 - if response_length ~= 8 then - log.error("exmodbus", "鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀姤鏂囬暱搴︿笉姝ｇ‘") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽瀵勫瓨鍣ㄥ湴鍧鍜屽硷紱 - local reg_addr = bit.lshift(string.byte(response, 3), 8) + string.byte(response, 4) - local reg_value = bit.lshift(string.byte(response, 5), 8) + string.byte(response, 6) - - -- 楠岃瘉鍦板潃鏄惁鍖归厤璇锋眰锛 - if config.start_addr and reg_addr ~= config.start_addr then - log.error("exmodbus", "鍗曚釜淇濇寔瀵勫瓨鍣ㄥ湴鍧涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", reg_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - parsed_data[reg_addr] = reg_value - - -- 鍔熻兘鐮 0x0F锛氬啓鍏ュ涓嚎鍦堬紱 - elseif function_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - -- 鍐欏叆澶氫釜绾垮湀鍝嶅簲鏍煎紡锛氫粠绔欏湴鍧(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 璧峰鍦板潃(2 瀛楄妭) + 绾垮湀鏁伴噺(2 瀛楄妭) + CRC(2 瀛楄妭)锛 - if response_length ~= 8 then - log.error("exmodbus", "鍐欏叆澶氫釜绾垮湀鍝嶅簲鎶ユ枃闀垮害涓嶆纭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽璧峰鍦板潃鍜岀嚎鍦堟暟閲忥紱 - local start_addr = bit.lshift(string.byte(response, 3), 8) + string.byte(response, 4) - local coil_count = bit.lshift(string.byte(response, 5), 8) + string.byte(response, 6) - - -- 楠岃瘉鍦板潃鍜屾暟閲忔槸鍚﹀尮閰嶈姹傦紱 - if config.start_addr and start_addr ~= config.start_addr then - log.error("exmodbus", "绾垮湀璧峰鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", start_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - if config.reg_count and coil_count ~= config.reg_count then - log.error("exmodbus", "绾垮湀鏁伴噺涓嶅尮閰嶏紝鏈熸湜:", config.reg_count, "瀹為檯:", coil_count) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鍦ㄨ繑鍥炴暟鎹腑璁板綍鎿嶄綔鎴愬姛鐨勮捣濮嬪湴鍧鍜屾暟閲忥紱 - parsed_data.start_addr = start_addr - parsed_data.count = coil_count - - -- 鍔熻兘鐮 0x10锛氬啓鍏ュ涓繚鎸佸瘎瀛樺櫒锛 - elseif function_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - -- 鍐欏叆澶氫釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀牸寮忥細浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 璧峰鍦板潃(2 瀛楄妭) + 瀵勫瓨鍣ㄦ暟閲(2 瀛楄妭) + CRC(2 瀛楄妭)锛 - if response_length ~= 8 then - log.error("exmodbus", "鍐欏叆澶氫釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀姤鏂囬暱搴︿笉姝ｇ‘") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽璧峰鍦板潃鍜屽瘎瀛樺櫒鏁伴噺锛 - local start_addr = bit.lshift(string.byte(response, 3), 8) + string.byte(response, 4) - local reg_count = bit.lshift(string.byte(response, 5), 8) + string.byte(response, 6) - - -- 楠岃瘉鍦板潃鍜屾暟閲忔槸鍚﹀尮閰嶈姹傦紱 - if config.start_addr and start_addr ~= config.start_addr then - log.error("exmodbus", "瀵勫瓨鍣ㄨ捣濮嬪湴鍧涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", start_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - if config.reg_count and reg_count ~= config.reg_count then - log.error("exmodbus", "瀵勫瓨鍣ㄦ暟閲忎笉鍖归厤锛屾湡鏈:", config.reg_count, "瀹為檯:", reg_count) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鍦ㄨ繑鍥炴暟鎹腑璁板綍鎿嶄綔鎴愬姛鐨勮捣濮嬪湴鍧鍜屾暟閲忥紱 - parsed_data.start_addr = start_addr - parsed_data.count = reg_count - - -- 鏈煡鍔熻兘鐮侊紱 - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮佽В鏋:", function_code) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鎴愬姛瑙ｆ瀽鍝嶅簲鏁版嵁锛 - -- log.info("exmodbus", "鍝嶅簲瑙ｆ瀽鎴愬姛锛屽姛鑳界爜:", function_code, "鏁版嵁:", json.encode(parsed_data)) - return_data.status = exmodbus_ref.STATUS_SUCCESS - return_data.data = parsed_data - return return_data -end - --- 涓荤珯璇诲彇璇锋眰鍑芥暟锛涳紙鍐呴儴浣跨敤锛 -function modbus:read_internal(config) - -- 澶勭悊鍝嶅簲缁撴灉锛 - local parsed_data = {} - - -- 妫鏌ラ氫俊妯″紡鏄惁鏈夋晥锛 - if self.mode == exmodbus_ref.RTU_MASTER then - - -- 妫鏌ユ槸鍚﹀悓鏃舵寚瀹氫簡 slave_id 鍜 raw_request锛 - if config.slave_id and config.raw_request then - log.error("exmodbus", "绂佹鍚屾椂鎸囧畾 slave_id 鍜 raw_request") - return false - end - - -- 鐢ㄦ埛浼犲叆瀛楁寮忚姹傚抚锛 - if config.slave_id then - -- 鏋勫缓 Modbus RTU 甯э紱 - local request_frame, function_code = build_rtu_frame("read", config) - if not request_frame then - parsed_data.status = exmodbus_ref.STATUS_DATA_INVALID - return parsed_data - end - - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, request_frame, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 瑙ｆ瀽鍝嶅簲鏁版嵁锛 - parsed_data = parse_rtu_response(response, config, function_code) - end - - -- 鐢ㄦ埛浼犲叆鍘熷璇锋眰甯э紱 - elseif config.raw_request then - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, config.raw_request, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 鐩存帴杩斿洖鍝嶅簲缁撴灉鍜屽師濮嬪搷搴旀暟鎹紱 - parsed_data.status = exmodbus_ref.STATUS_SUCCESS - parsed_data.raw_response = response - end - end - - return parsed_data - else - log.error("exmodbus", "閫氫俊妯″紡涓嶆敮鎸") - return false - end -end - --- 涓荤珯鍐欏叆璇锋眰鐨勫嚱鏁帮紱 -function modbus:write_internal(config) - - -- 澶勭悊鍝嶅簲缁撴灉锛 - local parsed_data = {} - - -- 妫鏌ラ氫俊妯″紡鏄惁鏈夋晥锛 - if self.mode == exmodbus_ref.RTU_MASTER then - - -- 妫鏌ユ槸鍚﹀悓鏃舵寚瀹氫簡 slave_id 鍜 raw_request锛 - if config.slave_id and config.raw_request then - log.error("exmodbus", "绂佹鍚屾椂鎸囧畾 slave_id 鍜 raw_request") - return false - end - - -- 鐢ㄦ埛浼犲叆瀛楁寮忚姹傚抚锛 - if config.slave_id then - -- 鏋勫缓 Modbus RTU 甯э紱 - local request_frame, function_code = build_rtu_frame("write", config) - if not request_frame then - parsed_data.status = exmodbus_ref.STATUS_DATA_INVALID - return parsed_data - end - - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, request_frame, config) - if not result then - -- log.error("exmodbus", "鎺ユ敹鍝嶅簲澶辫触鎴栬秴鏃") - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 瑙ｆ瀽鍝嶅簲鏁版嵁锛 - parsed_data = parse_rtu_response(response, config, function_code) - end - - -- 鐢ㄦ埛浼犲叆鍘熷璇锋眰甯э紱 - elseif config.raw_request then - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, config.raw_request, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 鐩存帴杩斿洖鍝嶅簲缁撴灉鍜屽師濮嬪搷搴旀暟鎹紱 - parsed_data.status = exmodbus_ref.STATUS_SUCCESS - parsed_data.raw_response = response - end - end - - return parsed_data - else - log.error("exmodbus", "閫氫俊妯″紡涓嶆敮鎸") - return false - end -end - --- 涓荤珯璇诲彇璇锋眰鐨勫嚱鏁帮紱 -function modbus:read(config) - return exmodbus_ref.enqueue_request(self, config, true) -end - --- 涓荤珯鍐欏叆璇锋眰鐨勫嚱鏁帮紱 -function modbus:write(config) - return exmodbus_ref.enqueue_request(self, config, false) -end - --- 娉ㄥ唽浠庣珯璇锋眰澶勭悊鍥炶皟鍑芥暟锛 -function modbus:on(callback) - if type(callback) ~= "function" then - log.error("exmodbus", "on(callback) 鐨勫弬鏁板繀椤绘槸涓涓嚱鏁") - return false - end - self.slaveHandler = callback - log.info("exmodbus", "宸叉敞鍐屼粠绔欒姹傚鐞嗗洖璋冨嚱鏁") - return true -end - -return { create = create } diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_tcp.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_tcp.lua deleted file mode 100644 index 6a39361..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmodbus_tcp.lua +++ /dev/null @@ -1,1247 +0,0 @@ --- 瀹氫箟绫荤粨鏋勶紱 -local modbus = {} -- 瀹氫箟 modbus 瀹炰緥鐨勫厓琛紱 -modbus.__index = modbus -- 瀹氫箟 modbus 瀹炰緥鐨勭储寮曞厓鏂规硶锛岀敤浜庤闂疄渚嬬殑灞炴э紱 -modbus.__metatable = "instance is protected" -- 瀹氫箟 modbus 瀹炰緥鐨勫厓琛紝闃叉澶栭儴淇敼锛 - --- 妯″潡绾у彉閲忥細渚濊禆娉ㄥ叆鐨勫紩鐢紱 -local exmodbus_ref -- 涓绘ā鍧楀紩鐢紝鐢ㄤ簬璁块棶enqueue_request绛夋牳蹇冨姛鑳斤紱 -local gen_id_func -- ID鐢熸垚鍑芥暟寮曠敤锛岀敤浜庣敓鎴愬敮涓璇锋眰ID锛 - --- Modbus TCP 鍗忚澶撮暱搴 -local MODBUS_TCP_HEADER_LEN = 7 - -local libnet = require "libnet" - --- 鍒涘缓 modbus 瀹炰緥鐨勬瀯閫犲嚱鏁帮紱 -function modbus:new(config, TASK_NAME) - local obj = { - mode = config.mode, -- 閫氫俊妯″紡 - adapter = config.adapter, -- 缃戠粶閫傞厤鍣 - ip_address = config.ip_address, -- IP 鍦板潃 - port = config.port, -- 绔彛鍙 - is_udp = config.is_udp, -- 鏄惁浣跨敤 UDP 鍗忚 - is_tls = config.is_tls, -- 鏄惁浣跨敤 TLS 鍔犲瘑 - keep_idle = config.keep_idle, -- 杩炴帴绌洪棽澶氶暱鏃堕棿鍚庯紝寮濮嬪彂閫佺涓涓 keepalive 鎺㈤拡鎶ユ枃锛堢锛 - keep_interval = config.keep_interval, -- 鍙戦佺涓涓帰閽堝悗锛屽鏋滄病鏀跺埌 ACK 鍥炲锛岄棿闅斿涔呭啀鍙戦佷笅涓涓帰閽堬紙绉掞級 - keep_cnt = config.keep_cnt, -- 鎬诲叡鍙戦佸灏戞鎺㈤拡鍚庯紝濡傛灉渚濈劧娌℃湁鍥炲锛屽垯鍒ゅ畾杩炴帴宸叉柇寮 - server_cert = config.server_cert, -- TCP妯″紡涓嬬殑鏈嶅姟鍣╟a璇佷功鏁版嵁锛孶DP妯″紡涓嬬殑PSK - client_cert = config.client_cert, -- TCP妯″紡涓嬬殑瀹㈡埛绔瘉涔︽暟鎹紝UDP妯″紡涓嬬殑PSK-ID - client_key = config.client_key, -- TCP妯″紡涓嬬殑瀹㈡埛绔閽ュ姞瀵嗘暟鎹 - client_password = config.client_password, -- TCP妯″紡涓嬬殑瀹㈡埛绔閽ュ彛浠ゆ暟鎹 - } - - -- 杩炴帴鐘舵 - obj.is_connected = false - -- 浠庣珯璇锋眰澶勭悊鍥炶皟鍑芥暟锛 - obj.slaveHandler = nil - -- 浠诲姟鍚嶇О - obj.TASK_NAME = TASK_NAME - -- 鎺ユ敹鏁版嵁缂撳啿鍖 - obj.recv_buff = nil - -- 鍙戦佽姹傞槦鍒 - obj.send_queue = {} - -- 褰撳墠绛夊緟鍝嶅簲鐨勪簨鍔D - obj.pending_transaction = nil - - -- 璁剧疆鍘熻〃锛 - setmetatable(obj, modbus) - -- 杩斿洖瀹炰緥锛 - return obj -end - --- 鏋勫缓 Modbus TCP 璇锋眰甯э紙涓荤珯浣跨敤锛 -local function build_tcp_frame(request_type, config) - -- 鍙傛暟楠岃瘉 - if not config or type(config) ~= "table" then - log.error("exmodbus", "閰嶇疆蹇呴』鏄〃鏍肩被鍨") - return false - end - - -- 楠岃瘉蹇呰鍙傛暟 - if not config.slave_id then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: slave_id") - return false - end - - if not config.reg_type then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: reg_type") - return false - end - - if not config.start_addr then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: start_addr") - return false - end - - if not config.reg_count then - log.error("exmodbus", "缂哄皯蹇呰鍙傛暟: reg_count") - return false - end - - if request_type == "write" then - if not config.data then - log.error("exmodbus", "缂哄皯鍐欏叆璇锋眰蹇呰鍙傛暟: data") - return false - end - end - - -- 鍙傛暟鑼冨洿楠岃瘉 - if type(config.slave_id) ~= "number" or config.slave_id < 1 or config.slave_id > 247 then - log.error("exmodbus", "浠庣珯鍦板潃蹇呴』鍦 1-247 鑼冨洿鍐") - return false - end - - if type(config.start_addr) ~= "number" or config.start_addr < 0 or config.start_addr > 65535 then - log.error("exmodbus", "璧峰鍦板潃蹇呴』鍦 0-65535 鑼冨洿鍐") - return false - end - - if config.reg_type ~= exmodbus_ref.COIL_STATUS and config.reg_type ~= exmodbus_ref.INPUT_STATUS and - config.reg_type ~= exmodbus_ref.HOLDING_REGISTER and config.reg_type ~= exmodbus_ref.INPUT_REGISTER then - log.error("exmodbus", "鏃犳晥鐨勫瘎瀛樺櫒绫诲瀷: " .. tostring(config.reg_type)) - return false - end - - -- 鏍规嵁鎿嶄綔绫诲瀷鍜屽瘎瀛樺櫒绫诲瀷纭畾鍔熻兘鐮 - local func_code - local data = "" - - if request_type == "read" then - -- 璇昏姹 - if config.reg_type == exmodbus_ref.COIL_STATUS then - func_code = exmodbus_ref.READ_COILS - if config.reg_count < 1 or config.reg_count > 2000 then - log.error("exmodbus", "绾垮湀璇诲彇鏁伴噺瓒呭嚭鑼冨洿: " .. config.reg_count .. " (鑼冨洿: 1-2000)") - return false - end - elseif config.reg_type == exmodbus_ref.INPUT_STATUS then - func_code = exmodbus_ref.READ_DISCRETE_INPUTS - if config.reg_count < 1 or config.reg_count > 2000 then - log.error("exmodbus", "绂绘暎杈撳叆璇诲彇鏁伴噺瓒呭嚭鑼冨洿: " .. config.reg_count .. " (鑼冨洿: 1-2000)") - return false - end - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - func_code = exmodbus_ref.READ_HOLDING_REGISTERS - if config.reg_count < 1 or config.reg_count > 125 then - log.error("exmodbus", "淇濇寔瀵勫瓨鍣ㄨ鍙栨暟閲忚秴鍑鸿寖鍥: " .. config.reg_count .. " (鑼冨洿: 1-125)") - return false - end - elseif config.reg_type == exmodbus_ref.INPUT_REGISTER then - func_code = exmodbus_ref.READ_INPUT_REGISTERS - if config.reg_count < 1 or config.reg_count > 125 then - log.error("exmodbus", "杈撳叆瀵勫瓨鍣ㄨ鍙栨暟閲忚秴鍑鸿寖鍥: " .. config.reg_count .. " (鑼冨洿: 1-125)") - return false - end - end - - data = string.char(config.slave_id, func_code) .. - string.char((config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF) .. - string.char((config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF) - else - -- 鍐欒姹 - -- 鏍￠獙姣忎竴涓湴鍧鏄惁鏈夋暟鎹紝涓旀暟鎹槸鍚︿负鏁板瓧绫诲瀷 - for i = 0, config.reg_count - 1 do - local addr = config.start_addr + i - if config.data[addr] == nil then - log.error("exmodbus", "缂哄皯瀵勫瓨鍣ㄦ暟鎹", "address:", addr) - return false - end - if type(config.data[addr]) ~= "number" then - log.error("exmodbus", "瀵勫瓨鍣ㄦ暟鎹繀椤绘槸鏁板瓧绫诲瀷", "address:", addr) - return false - end - end - - -- 鍒ゆ柇鏄惁寮哄埗浣跨敤鍐欏涓姛鑳界爜 - local use_multiple = config.force_multiple - - if config.reg_type == exmodbus_ref.COIL_STATUS then - if config.reg_count == 1 then - if not use_multiple then - func_code = exmodbus_ref.WRITE_SINGLE_COIL - else - func_code = exmodbus_ref.WRITE_MULTIPLE_COILS - end - else - func_code = exmodbus_ref.WRITE_MULTIPLE_COILS - if config.reg_count < 1 or config.reg_count > 1968 then - log.error("exmodbus", "绾垮湀鍐欏叆鏁伴噺瓒呭嚭鑼冨洿: " .. config.reg_count .. " (鑼冨洿: 1-1968)") - return false - end - end - elseif config.reg_type == exmodbus_ref.HOLDING_REGISTER then - if config.reg_count == 1 then - if not use_multiple then - func_code = exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER - else - func_code = exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS - end - else - func_code = exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS - if config.reg_count < 1 or config.reg_count > 123 then - log.error("exmodbus", "瀵勫瓨鍣ㄥ啓鍏ユ暟閲忚秴鍑鸿寖鍥: " .. config.reg_count .. " (鑼冨洿: 1-123)") - return false - end - end - else - log.error("exmodbus", "涓嶆敮鎸佺殑瀵勫瓨鍣ㄧ被鍨") - return nil - end - - -- 鏋勫缓鍐欐暟鎹 - if func_code == exmodbus_ref.WRITE_SINGLE_COIL then - -- 鍐欏叆鍗曚釜绾垮湀锛屽煎繀椤绘槸 0xFF00 (ON) 鎴 0x0000 (OFF) - local value = config.data[config.start_addr] ~= 0 and 0xFF00 or 0x0000 - data = string.char(config.slave_id, func_code) .. - string.char((config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF) .. - string.char((value >> 8) & 0xFF, value & 0xFF) - - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - -- 鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣 - local value = config.data[config.start_addr] - if value < 0 or value > 65535 or value ~= math.floor(value) then - log.error("exmodbus", "瀵勫瓨鍣ㄥ煎繀椤绘槸 0~65535 鑼冨洿鍐呯殑鏁存暟锛屽疄闄呭: ", value) - return false - end - data = string.char(config.slave_id, func_code) .. - string.char((config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF) .. - string.char((value >> 8) & 0xFF, value & 0xFF) - - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - -- 鍐欏叆澶氫釜绾垮湀 - local byte_count = math.ceil(config.reg_count / 8) - local values_bytes = "" - - -- 鏋勫缓绾垮湀鏁版嵁锛堝瓧鑺傚簭涓哄ぇ绔簭锛 - for i = 0, byte_count - 1 do - local byte_value = 0 - -- 閬嶅巻褰撳墠瀛楄妭鐨 8 涓綅 - for j = 0, 7 do - local bit_index = i * 8 + j - -- 妫鏌ュ綋鍓嶆瘮鐗规槸鍚﹀湪鏈夋晥鑼冨洿鍐 - if bit_index < config.reg_count then - local addr = config.start_addr + bit_index - local bit_val = config.data[addr] - if bit_val ~= nil and bit_val ~= 0 then - byte_value = byte_value | (1 << j) - end - end - end - values_bytes = values_bytes .. string.char(byte_value) - end - - data = string.char(config.slave_id, func_code) .. - string.char((config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF) .. - string.char((config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF) .. - string.char(byte_count) .. values_bytes - - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - -- 鍐欏叆澶氫釜淇濇寔瀵勫瓨鍣 - local byte_count = config.reg_count * 2 - local values_bytes = "" - - -- 鏋勫缓瀵勫瓨鍣ㄦ暟鎹紙瀛楄妭搴忎负澶х搴忥級 - for i = 0, config.reg_count - 1 do - local addr = config.start_addr + i - local value = config.data[addr] - if value < 0 or value > 65535 or value ~= math.floor(value) then - log.error("exmodbus", "瀵勫瓨鍣ㄥ煎繀椤绘槸 0~65535 鑼冨洿鍐呯殑鏁存暟锛屽湴鍧:", addr, "鍊:", value) - return false - end - values_bytes = values_bytes .. string.char((value >> 8) & 0xFF, value & 0xFF) - end - - data = string.char(config.slave_id, func_code) .. - string.char((config.start_addr >> 8) & 0xFF, config.start_addr & 0xFF) .. - string.char((config.reg_count >> 8) & 0xFF, config.reg_count & 0xFF) .. - string.char(byte_count) .. values_bytes - end - end - - -- 鏋勫缓瀹屾暣鐨 TCP 璇锋眰甯 - local transaction_id = gen_id_func() % 0x10000 - local length = #data -- 闀垮害鍖呭惈浠庣珯ID - local frame = string.pack(">H", transaction_id) .. -- 浜嬪姟 ID - string.pack(">H", 0) .. -- 鍗忚 ID - string.pack(">H", length) .. -- 闀垮害 - data -- 浠庣珯ID + PDU鏁版嵁 - - return frame, func_code, transaction_id -end - --- 瑙ｆ瀽 Modbus TCP 鍝嶅簲甯э紙涓荤珯浣跨敤锛 -local function parse_tcp_response(response, config, expected_func_code, expected_transaction_id) - -- 瀹氫箟杩斿洖鏁版嵁缁撴瀯锛 - local return_data = { - status = false, - execption_code = nil, - data = {}, - } - - -- 妫鏌ュ搷搴旀槸鍚︿负绌 - if not response or #response == 0 then - log.error("exmodbus", "鍝嶅簲鎶ユ枃涓虹┖") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 妫鏌ュ搷搴斿抚闀垮害 - if #response < MODBUS_TCP_HEADER_LEN + 1 then - log.error("exmodbus", "鍝嶅簲甯ч暱搴︿笉瓒") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽 MBAP 澶 - local transaction_id = string.unpack(">H", response, 1) - local protocol_id = string.unpack(">H", response, 3) - local length = string.unpack(">H", response, 5) - local slave_id = string.unpack("B", response, 7) - - -- 妫鏌ヤ簨鍔 ID 鏄惁鍖归厤 - if transaction_id ~= expected_transaction_id then - log.error("exmodbus", "浜嬪姟ID涓嶅尮閰") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 妫鏌ュ崗璁 ID - if protocol_id ~= 0 then - log.error("exmodbus", "鏃犳晥鐨勫崗璁甀D") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 妫鏌ユ暟鎹暱搴 - if #response ~= 6 + length then - log.error("exmodbus", "鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 妫鏌ヤ粠绔橧D鏄惁鍖归厤 - if slave_id ~= config.slave_id then - log.error("exmodbus", "浠庣珯鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.slave_id, "瀹為檯:", slave_id) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽鍔熻兘鐮 - local func_code = string.unpack("B", response, 8) - local response_length = #response - - -- 妫鏌ュ紓甯稿搷搴 - if bit.band(func_code, 0x80) ~= 0 then - -- 妫鏌ュ紓甯稿搷搴旀姤鏂囬暱搴︽槸鍚︽纭 - if response_length ~= 9 then - log.error("exmodbus", "寮傚父鍝嶅簲鎶ユ枃闀垮害涓嶆纭紝鏈熸湜: 9 瀛楄妭锛屽疄闄:", response_length, "瀛楄妭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鎻愬彇寮傚父鐮 - local exception_code = string.unpack("B", response, 9) - log.error("exmodbus", "鎺ユ敹鍒 Modbus 寮傚父鍝嶅簲锛屽姛鑳界爜:", func_code, "寮傚父鐮:", exception_code) - - return_data.status = exmodbus_ref.STATUS_EXCEPTION - return_data.execption_code = exception_code - return return_data - end - - -- 妫鏌ュ姛鑳界爜鏄惁鍖归厤 - if func_code ~= expected_func_code then - log.error("exmodbus", "鍔熻兘鐮佷笉鍖归厤锛屾湡鏈:", expected_func_code, "瀹為檯:", func_code) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - - -- 鏍规嵁涓嶅悓鐨勫姛鑳界爜瑙ｆ瀽鏁版嵁 - local parsed_data = {} - - -- 鍔熻兘鐮 0x01 鍜 0x02锛氳鍙栫嚎鍦堢姸鎬佸拰绂绘暎杈撳叆鐘舵 - if func_code == exmodbus_ref.READ_COILS or func_code == exmodbus_ref.READ_DISCRETE_INPUTS then - -- 鎻愬彇鏁版嵁閮ㄥ垎 - local byte_count = string.unpack("B", response, 9) - local data_start_pos = 10 - local data_end_pos = response_length - - -- 楠岃瘉鏁版嵁闀垮害鏄惁姝ｇ‘ - if data_end_pos - data_start_pos + 1 ~= byte_count then - log.error("exmodbus", "鏁版嵁闀垮害涓嶅尮閰嶏紝鏈熸湜:", byte_count, "瀹為檯:", data_end_pos - data_start_pos + 1) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 楠岃瘉瀛楄妭鏁版槸鍚﹁冻澶熻〃绀烘寚瀹氭暟閲忕殑浣 - local expected_bytes = math.ceil(config.reg_count / 8) - if byte_count < expected_bytes then - log.error("exmodbus", "鏁版嵁瀛楄妭鏁颁笉瓒筹紝鏃犳硶琛ㄧず鎵鏈変綅") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽浣嶆暟鎹 - for i = 0, config.reg_count - 1 do - local modbus_addr = config.start_addr + i -- 璁＄畻褰撳墠浣嶅搴旂殑 Modbus 鍦板潃 - local byte_pos = data_start_pos + math.floor(i / 8) -- 璁＄畻褰撳墠浣嶅搴旂殑瀛楄妭浣嶇疆 - local bit_pos = i % 8 -- 璁＄畻褰撳墠浣嶅搴旂殑浣嶄綅缃 - local byte_value = string.unpack("B", response, byte_pos) - parsed_data[modbus_addr] = bit.band(byte_value, bit.lshift(1, bit_pos)) ~= 0 and 1 or 0 - end - - -- 鍔熻兘鐮 0x03 鍜 0x04锛氳鍙栦繚鎸佸瘎瀛樺櫒鍜岃緭鍏ュ瘎瀛樺櫒 - elseif func_code == exmodbus_ref.READ_HOLDING_REGISTERS or func_code == exmodbus_ref.READ_INPUT_REGISTERS then - -- 鎻愬彇鏁版嵁閮ㄥ垎 - local byte_count = string.unpack("B", response, 9) - local data_start_pos = 10 - local data_end_pos = response_length - - -- 楠岃瘉鏁版嵁闀垮害鏄惁姝ｇ‘ - if data_end_pos - data_start_pos + 1 ~= byte_count then - log.error("exmodbus", "鏁版嵁闀垮害涓嶅尮閰嶏紝鏈熸湜:", byte_count, "瀹為檯:", data_end_pos - data_start_pos + 1) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 楠岃瘉瀛楄妭鏁版槸鍚﹁冻澶熻〃绀烘寚瀹氭暟閲忕殑瀵勫瓨鍣 - local expected_bytes = config.reg_count * 2 - if byte_count < expected_bytes then - log.error("exmodbus", "鏁版嵁瀛楄妭鏁颁笉瓒筹紝鏃犳硶琛ㄧず鎵鏈夊瘎瀛樺櫒") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽瀵勫瓨鍣ㄦ暟鎹紙澶х搴忥級 - for i = 0, config.reg_count - 1 do - local modbus_addr = config.start_addr + i -- 璁＄畻褰撳墠瀵勫瓨鍣ㄥ搴旂殑 Modbus 鍦板潃 - local reg_pos = data_start_pos + i * 2 -- 璁＄畻褰撳墠瀵勫瓨鍣ㄥ搴旂殑瀛楄妭浣嶇疆 - parsed_data[modbus_addr] = bit.lshift(string.unpack("B", response, reg_pos), 8) + string.unpack("B", response, reg_pos + 1) - end - - -- 鍔熻兘鐮 0x05锛氬啓鍏ュ崟涓嚎鍦 - elseif func_code == exmodbus_ref.WRITE_SINGLE_COIL then - -- 鍐欏叆鍗曚釜绾垮湀鍝嶅簲鏍煎紡锛氫簨鍔D(2 瀛楄妭) + 鍗忚ID(2 瀛楄妭) + 闀垮害(2 瀛楄妭) + 浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 绾垮湀鍦板潃(2 瀛楄妭) + 绾垮湀鍊(2 瀛楄妭) - if response_length ~= 12 then - log.error("exmodbus", "鍐欏叆鍗曚釜绾垮湀鍝嶅簲鎶ユ枃闀垮害涓嶆纭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽绾垮湀鍦板潃鍜屽 - local coil_addr = string.unpack(">H", response, 9) - local coil_value = string.unpack(">H", response, 11) - - -- 楠岃瘉鍦板潃鏄惁鍖归厤璇锋眰 - if config.start_addr and coil_addr ~= config.start_addr then - log.error("exmodbus", "绾垮湀鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", coil_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 绾垮湀鍊煎簲璇ユ槸 0x0000(OFF) 鎴 0xFF00(ON) - local normalized_value = (coil_value == 0x0000) and 0 or 1 - parsed_data[coil_addr] = normalized_value - - -- 鍔熻兘鐮 0x06锛氬啓鍏ュ崟涓繚鎸佸瘎瀛樺櫒 - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - -- 鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀牸寮忥細浜嬪姟ID(2 瀛楄妭) + 鍗忚ID(2 瀛楄妭) + 闀垮害(2 瀛楄妭) + 浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 瀵勫瓨鍣ㄥ湴鍧(2 瀛楄妭) + 瀵勫瓨鍣ㄥ(2 瀛楄妭) - if response_length ~= 12 then - log.error("exmodbus", "鍐欏叆鍗曚釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀姤鏂囬暱搴︿笉姝ｇ‘") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽瀵勫瓨鍣ㄥ湴鍧鍜屽 - local reg_addr = string.unpack(">H", response, 9) - local reg_value = string.unpack(">H", response, 11) - - -- 楠岃瘉鍦板潃鏄惁鍖归厤璇锋眰 - if config.start_addr and reg_addr ~= config.start_addr then - log.error("exmodbus", "鍗曚釜淇濇寔瀵勫瓨鍣ㄥ湴鍧涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", reg_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - parsed_data[reg_addr] = reg_value - - -- 鍔熻兘鐮 0x0F锛氬啓鍏ュ涓嚎鍦 - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - -- 鍐欏叆澶氫釜绾垮湀鍝嶅簲鏍煎紡锛氫簨鍔D(2 瀛楄妭) + 鍗忚ID(2 瀛楄妭) + 闀垮害(2 瀛楄妭) + 浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 璧峰鍦板潃(2 瀛楄妭) + 绾垮湀鏁伴噺(2 瀛楄妭) - if response_length ~= 12 then - log.error("exmodbus", "鍐欏叆澶氫釜绾垮湀鍝嶅簲鎶ユ枃闀垮害涓嶆纭") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽璧峰鍦板潃鍜岀嚎鍦堟暟閲 - local start_addr = string.unpack(">H", response, 9) - local coil_count = string.unpack(">H", response, 11) - - -- 楠岃瘉鍦板潃鍜屾暟閲忔槸鍚﹀尮閰嶈姹 - if config.start_addr and start_addr ~= config.start_addr then - log.error("exmodbus", "绾垮湀璧峰鍦板潃涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", start_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - if config.reg_count and coil_count ~= config.reg_count then - log.error("exmodbus", "绾垮湀鏁伴噺涓嶅尮閰嶏紝鏈熸湜:", config.reg_count, "瀹為檯:", coil_count) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鍦ㄨ繑鍥炴暟鎹腑璁板綍鎿嶄綔鎴愬姛鐨勮捣濮嬪湴鍧鍜屾暟閲 - parsed_data.start_addr = start_addr - parsed_data.count = coil_count - - -- 鍔熻兘鐮 0x10锛氬啓鍏ュ涓繚鎸佸瘎瀛樺櫒 - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - -- 鍐欏叆澶氫釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀牸寮忥細浜嬪姟ID(2 瀛楄妭) + 鍗忚ID(2 瀛楄妭) + 闀垮害(2 瀛楄妭) + 浠庣珯鍦板潃(1 瀛楄妭) + 鍔熻兘鐮(1 瀛楄妭) + 璧峰鍦板潃(2 瀛楄妭) + 瀵勫瓨鍣ㄦ暟閲(2 瀛楄妭) - if response_length ~= 12 then - log.error("exmodbus", "鍐欏叆澶氫釜淇濇寔瀵勫瓨鍣ㄥ搷搴旀姤鏂囬暱搴︿笉姝ｇ‘") - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 瑙ｆ瀽璧峰鍦板潃鍜屽瘎瀛樺櫒鏁伴噺 - local start_addr = string.unpack(">H", response, 9) - local reg_count = string.unpack(">H", response, 11) - - -- 楠岃瘉鍦板潃鍜屾暟閲忔槸鍚﹀尮閰嶈姹 - if config.start_addr and start_addr ~= config.start_addr then - log.error("exmodbus", "瀵勫瓨鍣ㄨ捣濮嬪湴鍧涓嶅尮閰嶏紝鏈熸湜:", config.start_addr, "瀹為檯:", start_addr) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - if config.reg_count and reg_count ~= config.reg_count then - log.error("exmodbus", "瀵勫瓨鍣ㄦ暟閲忎笉鍖归厤锛屾湡鏈:", config.reg_count, "瀹為檯:", reg_count) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鍦ㄨ繑鍥炴暟鎹腑璁板綍鎿嶄綔鎴愬姛鐨勮捣濮嬪湴鍧鍜屾暟閲 - parsed_data.start_addr = start_addr - parsed_data.count = reg_count - - -- 鏈煡鍔熻兘鐮 - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮佽В鏋:", func_code) - return_data.status = exmodbus_ref.STATUS_DATA_INVALID - return return_data - end - - -- 鎴愬姛瑙ｆ瀽鍝嶅簲鏁版嵁 - return_data.data = parsed_data - return_data.status = exmodbus_ref.STATUS_SUCCESS - - return return_data -end - --- TCP 涓荤珯鍙戦佽姹傚苟绛夊緟鍝嶅簲 -local function sendRequest_waitResponse(instance, request_frame, config) - -- 妫鏌ヨ繛鎺ョ姸鎬 - if not instance.is_connected or not instance.socket_client then - log.error("exmodbus", "TCP 杩炴帴鏈缓绔嬫垨宸叉柇寮锛屾棤娉曞彂閫佽姹") - return false - end - - -- 浠庤姹傚抚涓彁鍙栦簨鍔D鍜屽姛鑳界爜 - local transaction_id = string.unpack(">H", request_frame, 1) - local function_code = string.unpack("B", request_frame, 8) - - -- 鍒涘缓璇锋眰淇℃伅骞舵坊鍔犲埌鍙戦侀槦鍒 - local request_info = { - request_frame = request_frame, - function_code = function_code, - transaction_id = transaction_id, - config = config - } - - table.insert(instance.send_queue, request_info) - - -- log.info("exmodbus", "璇锋眰宸叉坊鍔犲埌鍙戦侀槦鍒", transaction_id) - - sys.sendMsg(instance.TASK_NAME, socket.EVENT, 0) - - -- 绛夊緟鍝嶅簲 - local _, response_data = sys.waitUntil("exmodbus/tcp_resp/" .. transaction_id, - config.timeout or 5000) - - if not response_data then - log.error("exmodbus", "绛夊緟鍝嶅簲瓒呮椂") - return false, nil - end - - return true, response_data -end - --- TCP 涓荤珯鎺ユ敹鏁版嵁澶勭悊鍑芥暟 -local function tcp_master_receiver(instance) - if instance.recv_buff == nil then - instance.recv_buff = zbuff.create(1024) - end - - while true do - local succ, param = socket.rx(instance.socket_client, instance.recv_buff) - - if not succ then - log.info("exmodbus", "璇诲彇鏁版嵁澶辫触") - return false - end - - if instance.recv_buff:used() > 0 then - local data = instance.recv_buff:query() - sys.publish("exmodbus/tcp_resp/" .. instance.current_transaction_id, data) - -- log.info("exmodbus", "璇诲彇鏁版嵁鎴愬姛") - instance.recv_buff:del() - else - break - end - end - - return true -end - --- TCP 涓荤珯鍙戦佹暟鎹鐞嗗嚱鏁 -local function tcp_master_sender(instance) - -- 妫鏌ュ彂閫侀槦鍒椾腑鏄惁鏈夎姹 - while #instance.send_queue > 0 do - -- 鍙栧嚭闃熷垪涓殑绗竴涓姹 - local request_info = table.remove(instance.send_queue, 1) - local request_frame = request_info.request_frame - local function_code = request_info.function_code - local transaction_id = request_info.transaction_id - local config = request_info.config - - -- 璁剧疆褰撳墠浜嬪姟淇℃伅 - instance.current_transaction_id = transaction_id - - -- 鍙戦佽姹 - local result, buff_full = libnet.tx(instance.TASK_NAME, 15000, instance.socket_client, request_frame) - if not result then - log.error("exmodbus", "鍙戦佽姹傚け璐") - return true - end - - if buff_full then - log.error("exmodbus", "缂撳啿鍖哄凡婊★紝灏嗚姹傞噸鏂版斁鍥為槦鍒楅槦棣") - -- 灏嗚姹傞噸鏂版斁鍥為槦鍒楅槦棣 - table.insert(instance.send_queue, 1, request_info) - end - end - - return true -end - --- TCP 涓荤珯涓讳换鍔″嚱鏁 -local function tcp_master_main_task_func(instance) - local result, param - - while true do - -- 鍒涘缓 socket 瀹㈡埛绔 - instance.socket_client = socket.create(instance.adapter, instance.TASK_NAME) - if not instance.socket_client then - log.error("exmodbus", "鍒涘缓 socket 瀹㈡埛绔け璐") - goto EXCEPTION_PROC - end - - -- 閰嶇疆 socket - result = socket.config(instance.socket_client) - if not result then - log.error("exmodbus", "閰嶇疆 socket 澶辫触") - goto EXCEPTION_PROC - end - - -- 杩炴帴鏈嶅姟鍣 - result = libnet.connect(instance.TASK_NAME, 15000, instance.socket_client, instance.ip_address, instance.port) - if not result then - log.error("exmodbus", "杩炴帴鏈嶅姟鍣ㄥけ璐") - goto EXCEPTION_PROC - end - - log.info("exmodbus", "杩炴帴鏈嶅姟鍣ㄦ垚鍔") - instance.is_connected = true - - -- 涓诲惊鐜 - while true do - -- 澶勭悊鎺ユ敹鏁版嵁 - if not tcp_master_receiver(instance) then - log.info("exmodbus", "鎺ユ敹鏁版嵁澶勭悊澶辫触") - break - end - - -- 澶勭悊鍙戦佹暟鎹 - if not tcp_master_sender(instance) then - log.info("exmodbus", "鍙戦佹暟鎹鐞嗗け璐") - break - end - - -- 绛夊緟浜嬩欢 - result, param = libnet.wait(instance.TASK_NAME, 0, instance.socket_client) - if not result then - log.info("exmodbus", "杩炴帴鏂紑") - break - end - end - - -- 寮傚父澶勭悊 - ::EXCEPTION_PROC:: - - -- 鍏抽棴杩炴帴 - if instance.socket_client then - libnet.close(instance.TASK_NAME, 5000, instance.socket_client) - socket.release(instance.socket_client) - instance.socket_client = nil - instance.is_connected = false - end - - -- 绛夊緟 5 绉掑悗閲嶈瘯 - sys.wait(5000) - end -end - --- 瑙ｆ瀽 TCP 璇锋眰甯э紙浠庣珯浣跨敤锛 -local function parse_tcp_request(data) - -- 妫鏌ヨ姹傚抚闀垮害锛岃嚦灏戝寘鍚 MBAP 澶村拰鍔熻兘鐮 - if #data < MODBUS_TCP_HEADER_LEN + 1 then - log.error("exmodbus", "璇锋眰甯ч暱搴︿笉瓒") - return nil, "璇锋眰甯ч暱搴︿笉瓒" - end - - -- 瑙ｆ瀽 MBAP 澶达紙浜嬪姟鏍囪瘑绗(2)銆佸崗璁爣璇嗙(2)銆佹暟鎹暱搴(2)銆佷粠绔欏湴鍧(1)锛 - local transaction_id = string.unpack(">H", data, 1) - local protocol_id = string.unpack(">H", data, 3) - local length = string.unpack(">H", data, 5) - local slave_id = string.unpack("B", data, 7) - - -- 妫鏌ユ暟鎹暱搴︽槸鍚︿笌瀹為檯闀垮害鍖归厤 - if #data ~= 6 + length then - log.error("exmodbus", "鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤") - return nil, "鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤" - end - - -- 妫鏌ュ崗璁 ID锛圡odbus TCP 鍗忚 ID 蹇呴』涓 0锛 - if protocol_id ~= 0 then - log.error("exmodbus", "鏃犳晥鐨勫崗璁 ID") - return nil, "鏃犳晥鐨勫崗璁 ID" - end - - -- 瑙ｆ瀽鍔熻兘鐮 - local func_code = string.unpack("B", data, 8) - local request = { - transaction_id = transaction_id, - protocol_id = protocol_id, - length = length, - slave_id = slave_id, - func_code = func_code, - reg_type = nil, - start_addr = nil, - reg_count = nil, - data = {}, - } - - -- 鏍规嵁鍔熻兘鐮佽В鏋愯姹傚唴瀹 - if func_code == exmodbus_ref.READ_COILS or func_code == exmodbus_ref.READ_DISCRETE_INPUTS then - -- 璇荤嚎鍦堟垨绂绘暎杈撳叆 - request.reg_type = func_code == exmodbus_ref.READ_COILS and exmodbus_ref.COIL_STATUS or exmodbus_ref.DISCRETE_INPUT_STATUS - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = string.unpack(">H", data, 11) - elseif func_code == exmodbus_ref.READ_HOLDING_REGISTERS or func_code == exmodbus_ref.READ_INPUT_REGISTERS then - -- 璇讳繚鎸佸瘎瀛樺櫒鎴栬緭鍏ュ瘎瀛樺櫒 - request.reg_type = func_code == exmodbus_ref.READ_HOLDING_REGISTERS and exmodbus_ref.HOLDING_REGISTER or exmodbus_ref.INPUT_REGISTER - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = string.unpack(">H", data, 11) - elseif func_code == exmodbus_ref.WRITE_SINGLE_COIL then - -- 鍐欏崟涓嚎鍦 - request.reg_type = exmodbus_ref.COIL_STATUS - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = 1 - local value = string.unpack(">H", data, 11) - request.data = { [request.start_addr] = value == 0xFF00 and 1 or 0 } - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - -- 鍐欏崟涓瘎瀛樺櫒 - request.reg_type = exmodbus_ref.HOLDING_REGISTER - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = 1 - local value = string.unpack(">H", data, 11) - request.data = { [request.start_addr] = value } - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_COILS then - -- 鍐欏涓嚎鍦 - request.reg_type = exmodbus_ref.COIL_STATUS - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = string.unpack(">H", data, 11) - -- local byte_count = string.unpack("B", data, 13) - request.data = {} - for i = 0, request.reg_count - 1 do - local byte_pos = 13 + 1 + math.floor(i / 8) - local bit_pos = i % 8 - local byte_value = string.unpack("B", data, byte_pos) - local bit_value = bit.band(byte_value, bit.lshift(1, bit_pos)) > 0 and 1 or 0 - request.data[request.start_addr + i] = bit_value - end - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - -- 鍐欏涓瘎瀛樺櫒 - request.reg_type = exmodbus_ref.HOLDING_REGISTER - request.start_addr = string.unpack(">H", data, 9) - request.reg_count = string.unpack(">H", data, 11) - -- local byte_count = string.unpack("B", data, 13) - request.data = {} - for i = 0, request.reg_count - 1 do - local value = string.unpack(">H", data, 13 + 1 + i * 2) - request.data[request.start_addr + i] = value - end - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮:", func_code) - end - - return request -end - --- 鏋勫缓 Modbus TCP 鍝嶅簲甯э紙浠庣珯浣跨敤锛夛紱 -local function build_tcp_response(request, user_return) - local slave_id = request.slave_id - local func_code = request.func_code - - -- 鐢ㄦ埛杩斿洖寮傚父鐮 -> 寮傚父鍝嶅簲锛 - if type(user_return) == "number" then - local exception_code = user_return - local response_payload = string.char(slave_id, bit.bor(func_code, 0x80), exception_code) - - -- 鏋勫缓瀹屾暣鐨 TCP 鍝嶅簲甯 - local length = #response_payload - local response = string.pack(">H", request.transaction_id) .. -- 浜嬪姟 ID - string.pack(">H", 0) .. -- 鍗忚 ID - string.pack(">H", length) .. -- 闀垮害 - response_payload - - return response - end - - -- 鐢ㄦ埛杩斿洖琛 -> 姝ｅ父鍝嶅簲锛 - if type(user_return) ~= "table" then - log.error("exmodbus", "浠庣珯鍥炶皟蹇呴』杩斿洖 table 鎴 number锛屽疄闄呯被鍨: ", type(user_return)) - return nil - end - - local response_payload = "" - - -- 澶勭悊璇荤嚎鍦堝拰璇荤鏁ｈ緭鍏ュ搷搴旓紱 - if func_code == exmodbus_ref.READ_COILS or func_code == exmodbus_ref.READ_DISCRETE_INPUTS then - local reg_count = request.reg_count - - -- 鏍￠獙 reg_count 鏄惁鏈夋晥锛 - if not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 reg_count 鏃犳晥") - return nil - end - - local byte_count = math.ceil(reg_count / 8) - local values = {} - - for i = 0, reg_count - 1 do - local addr = request.start_addr + i - local bit_val = user_return[addr] - if bit_val == nil then - log.error("exmodbus", "璇荤嚎鍦/绂绘暎杈撳叆鍥炶皟鏈繑鍥炲湴鍧 ", addr, " 鐨勬暟鎹") - return nil - end - if bit_val ~= 0 and bit_val ~= 1 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0 鎴 1锛屽疄闄: ", bit_val) - return nil - end - - local byte_idx = math.floor(i / 8) - if not values[byte_idx] then values[byte_idx] = 0 end - if bit_val == 1 then - values[byte_idx] = bit.bor(values[byte_idx], bit.lshift(1, i % 8)) - end - end - - response_payload = string.char(slave_id, func_code, byte_count) - for i = 0, byte_count - 1 do - response_payload = response_payload .. string.char(values[i] or 0) - end - -- 澶勭悊璇讳繚鎸佸瘎瀛樺櫒鍜岃杈撳叆瀵勫瓨鍣ㄥ搷搴旓紱 - elseif func_code == exmodbus_ref.READ_HOLDING_REGISTERS or func_code == exmodbus_ref.READ_INPUT_REGISTERS then - local reg_count = request.reg_count - -- 鏍￠獙 reg_count 鏄惁鏈夋晥锛 - if not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 reg_count 鏃犳晥") - return nil - end - - local values = "" - for i = 0, reg_count - 1 do - local addr = request.start_addr + i - local val = user_return[addr] - if val == nil then - log.error("exmodbus", "璇讳繚鎸佸瘎瀛樺櫒/杈撳叆瀵勫瓨鍣ㄥ洖璋冩湭杩斿洖鍦板潃 ", addr, " 鐨勬暟鎹") - return nil - end - if type(val) ~= "number" or val ~= math.floor(val) or val < 0 or val > 65535 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0~65535 鐨勬暣鏁帮紝瀹為檯: ", val) - return nil - end - values = values .. string.char((val >> 8) & 0xFF, val & 0xFF) - end - response_payload = string.char(slave_id, func_code, #values) .. values - -- 澶勭悊鍐欏崟涓嚎鍦堝搷搴旓紱 - elseif func_code == exmodbus_ref.WRITE_SINGLE_COIL then - local addr = request.start_addr - -- 鏍￠獙 start_addr 鏄惁鏈夋晥锛 - if addr == nil then - log.error("exmodbus", "璇锋眰涓 start_addr 鏃犳晥") - return nil - end - local coil_val = (request.data and request.data[addr]) or 0 - local resp_val = (coil_val ~= 0) and 0xFF00 or 0x0000 - response_payload = string.char(slave_id, func_code) .. - string.char((addr >> 8) & 0xFF, addr & 0xFF, - (resp_val >> 8) & 0xFF, resp_val & 0xFF) - -- 澶勭悊鍐欏崟涓繚鎸佸瘎瀛樺櫒鍝嶅簲锛 - elseif func_code == exmodbus_ref.WRITE_SINGLE_HOLDING_REGISTER then - local addr = request.start_addr - -- 鏍￠獙 start_addr 鏄惁鏈夋晥锛 - if addr == nil then - log.error("exmodbus", "璇锋眰涓 start_addr 鏃犳晥") - return nil - end - local reg_val = (request.data and request.data[addr]) or 0 - -- 鏍￠獙 reg_val 鏄惁鏈夋晥锛 - if type(reg_val) ~= "number" or reg_val ~= math.floor(reg_val) or reg_val < 0 or reg_val > 65535 then - log.error("exmodbus", "鍦板潃 ", addr, " 鐨勫煎繀椤讳负 0~65535 鐨勬暣鏁帮紝瀹為檯: ", reg_val) - return nil - end - response_payload = string.char(slave_id, func_code) .. - string.char((addr >> 8) & 0xFF, addr & 0xFF, - (reg_val >> 8) & 0xFF, reg_val & 0xFF) - -- 澶勭悊鍐欏涓嚎鍦/淇濇寔瀵勫瓨鍣ㄥ搷搴旓紱 - elseif func_code == exmodbus_ref.WRITE_MULTIPLE_COILS or func_code == exmodbus_ref.WRITE_MULTIPLE_HOLDING_REGISTERS then - local start_addr = request.start_addr - local reg_count = request.reg_count - -- 鏍￠獙 start_addr 鍜 reg_count 鏄惁鏈夋晥锛 - if not start_addr or not reg_count or reg_count <= 0 then - log.error("exmodbus", "璇锋眰涓 start_addr 鎴 reg_count 鏃犳晥") - return nil - end - response_payload = string.char(slave_id, func_code) .. - string.char((start_addr >> 8) & 0xFF, start_addr & 0xFF, - (reg_count >> 8) & 0xFF, reg_count & 0xFF) - -- 澶勭悊鏈煡鍔熻兘鐮侊紝瑙嗕负閿欒锛 - else - log.error("exmodbus", "涓嶆敮鎸佺殑鍔熻兘鐮侊紝涓旀湭杩斿洖寮傚父鐮: ", func_code) - return nil - end - - -- 鏋勫缓瀹屾暣鐨 TCP 鍝嶅簲甯 - local length = #response_payload -- 闀垮害鍖呭惈浠庣珯ID - local response = string.pack(">H", request.transaction_id) .. -- 浜嬪姟 ID - string.pack(">H", 0) .. -- 鍗忚 ID - string.pack(">H", length) .. -- 闀垮害锛堝寘鍚粠绔橧D锛 - response_payload -- 浠庣珯ID + PDU鏁版嵁 - - return response -end - --- TCP 浠庣珯鎺ユ敹鏁版嵁澶勭悊鍑芥暟锛 -local function tcp_receiver(netc, instance) - -- 濡傛灉鏁版嵁鎺ユ敹缂撳啿鍖鸿繕娌℃湁鐢宠杩囩┖闂达紝鍒欏厛鐢宠鍐呭瓨绌洪棿 - if instance.recv_buff == nil then - instance.recv_buff = zbuff.create(1024) - end - - -- 寰幆浠庡唴鏍哥殑缂撳啿鍖鸿鍙栨帴鏀跺埌鐨勬暟鎹 - while true do - -- 浠庡唴鏍哥殑缂撳啿鍖轰腑璇诲彇鏁版嵁鍒 instance.recv_buff 涓 - local succ, param = socket.rx(netc, instance.recv_buff) - - -- 璇诲彇鏁版嵁澶辫触 - if not succ then - log.info("exmodbus", "璇诲彇鏁版嵁澶辫触锛屽凡鎺ユ敹鏁版嵁闀垮害", param) - return false - end - - -- 濡傛灉璇诲彇鍒颁簡鏁版嵁 - if instance.recv_buff:used() > 0 then - -- log.info("exmodbus", "宸叉帴鏀舵暟鎹暱搴", instance.recv_buff:used()) - - -- 璇诲彇鏁版嵁 - local data = instance.recv_buff:query() - - -- 瑙ｆ瀽 TCP 璇锋眰甯 - local request, err = parse_tcp_request(data) - if request then - -- 骞挎挱鍦板潃锛0锛変笉鍝嶅簲锛 - if request.slave_id == 0 then - -- 璋冪敤鍥炶皟浠ュ厑璁哥敤鎴疯褰曟垨澶勭悊骞挎挱鍛戒护锛堝鍐欏瘎瀛樺櫒锛夛紱 - if instance.slaveHandler then - instance.slaveHandler(request) - -- 娉ㄦ剰锛氬嵆浣垮洖璋冭繑鍥炴暟鎹紝涔熶笉鍙戦佸搷搴旓紱 - end - -- 骞挎挱璇锋眰澶勭悊瀹屾瘯锛屾竻闄ゅ搴旂殑鎶ユ枃鏁版嵁 - local expected_len = request.length + MODBUS_TCP_HEADER_LEN - 1 - instance.recv_buff:del(0, expected_len) - -- log.info("exmodbus", "骞挎挱璇锋眰澶勭悊瀹屾瘯锛屾竻闄ゆ姤鏂囬暱搴:", expected_len) - -- 骞挎挱璇锋眰澶勭悊瀹屾瘯锛屼笉鍥炲锛 - break - end - if instance.slaveHandler then - local user_return = instance.slaveHandler(request) - local response = build_tcp_response(request, user_return) - if response then - libnet.tx(instance.TASK_NAME, 0, netc, response) - sys.sendMsg(instance.TASK_NAME, socket.EVENT, 0) - else - log.error("exmodbus", "鏋勫缓鍝嶅簲甯уけ璐ワ紝浠庣珯鍦板潃:", request.slave_id) - end - - -- 娓呴櫎褰撳墠璇锋眰鏁版嵁 - local expected_len = request.length + MODBUS_TCP_HEADER_LEN - 1 - instance.recv_buff:del(0, expected_len) - -- log.info("exmodbus", "璇锋眰澶勭悊瀹屾瘯锛屾竻闄ゆ姤鏂囬暱搴:", expected_len) - else - log.warn("exmodbus", "鏀跺埌涓荤珯璇锋眰锛屼絾鏈敞鍐屽洖璋冨嚱鏁") - -- 娓呴櫎褰撳墠璇锋眰鏁版嵁 - local expected_len = request.length + MODBUS_TCP_HEADER_LEN - 1 - instance.recv_buff:del(0, expected_len) - log.info("exmodbus", "娓呴櫎鎶ユ枃闀垮害:", expected_len) - end - else - if err == "璇锋眰甯ч暱搴︿笉瓒" then - -- 璇锋眰甯ч暱搴︿笉瓒筹紝绛夊緟鏇村鏁版嵁 - -- log.info("exmodbus", "璇锋眰甯ч暱搴︿笉瓒筹紝绛夊緟鏇村鏁版嵁") - break - elseif err == "鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤" then - -- 鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤锛屾竻绌虹紦鍐插尯 - -- log.warn("exmodbus", "鏁版嵁闀垮害涓庡疄闄呴暱搴︿笉鍖归厤锛屾竻绌虹紦鍐插尯") - instance.recv_buff:del() - break - elseif err == "鍗忚 ID 閿欒" then - -- 鍗忚 ID 閿欒锛屾竻绌虹紦鍐插尯 - -- log.warn("exmodbus", "鍗忚 ID 閿欒锛屾竻绌虹紦鍐插尯") - instance.recv_buff:del() - break - end - end - else - -- 娌℃湁鏁版嵁鍙 - break - end - end - - return true -end - -local function tcp_slave_main_task_func(instance) - local netc = nil - local result, param - - while true do - -- 鍒涘缓 TCP 鏈嶅姟鍣 - netc = socket.create(instance.adapter, instance.TASK_NAME) - if not netc then - log.error("exmodbus", "鍒涘缓 TCP 鏈嶅姟鍣ㄥけ璐") - goto EXCEPTION_PROC - end - - -- 閰嶇疆鏈嶅姟鍣 - result = socket.config(netc, instance.port) - if not result then - log.error("exmodbus", "閰嶇疆 TCP 鏈嶅姟鍣ㄥけ璐") - goto EXCEPTION_PROC - end - - -- 鐩戝惉绔彛 - result = libnet.listen(instance.TASK_NAME, 0, netc) - if not result then - log.error("exmodbus", "鐩戝惉绔彛澶辫触") - goto EXCEPTION_PROC - end - - log.info("exmodbus", "TCP 浠庣珯宸插惎鍔紝鐩戝惉绔彛:", instance.port) - - -- 澶勭悊杩炴帴鍜屾暟鎹 - while true do - -- 澶勭悊鎺ユ敹鏁版嵁 - if not tcp_receiver(netc, instance) then - log.info("exmodbus", "鎺ユ敹鏁版嵁澶勭悊澶辫触") - break - end - - -- 绛夊緟浜嬩欢 - result, param = libnet.wait(instance.TASK_NAME, 0, netc) - if not result then - log.info("exmodbus", "瀹㈡埛绔柇寮杩炴帴") - break - end - end - - -- 寮傚父澶勭悊 - ::EXCEPTION_PROC:: - - -- 鍏抽棴杩炴帴 - if netc then - libnet.close(instance.TASK_NAME, 5000, netc) - socket.release(netc) - netc = nil - end - - -- 绛夊緟 5 绉掑悗閲嶈瘯 - sys.wait(5000) - end -end - --- 鍒涘缓涓涓柊鐨勫疄渚嬶紱 -local function create(config, exmodbus, gen_request_id) - exmodbus_ref = exmodbus - gen_id_func = gen_request_id - local TASK_NAME = "exmodbus_tcp_task_"..gen_id_func() - - -- 鍒涘缓涓涓柊鐨勫疄渚嬶紱 - local instance = modbus:new(config, TASK_NAME) - -- 妫鏌ュ疄渚嬫槸鍚﹀垱寤烘垚鍔燂紱 - if not instance then - log.error("exmodbus", "鍒涘缓 Modbus 瀹炰緥澶辫触") - return false - end - - -- 鏍规嵁妯″紡鍚姩涓嶅悓鐨勪换鍔 - if config.mode == exmodbus_ref.TCP_MASTER then - -- 鍚姩涓荤珯浠诲姟 - sys.taskInitEx(tcp_master_main_task_func, TASK_NAME, nil, instance) - log.info("exmodbus", "TCP 涓荤珯浠诲姟宸插惎鍔") - elseif config.mode == exmodbus_ref.TCP_SLAVE then - -- 鍚姩浠庣珯浠诲姟 - sys.taskInitEx(tcp_slave_main_task_func, TASK_NAME, nil, instance) - log.info("exmodbus", "TCP 浠庣珯浠诲姟宸插惎鍔") - else - log.error("exmodbus", "涓嶆敮鎸佺殑 TCP 妯″紡") - return false - end - - -- 杩斿洖瀹炰緥锛 - return instance -end - -function modbus:destroy() - -- 鍋滄浠诲姟 - sys.taskDel(self.TASK_NAME) - -- 閲婃斁缂撳啿鍖 - if self.recv_buff then - self.recv_buff:free() - self.recv_buff = nil - end -end - --- 鍐呴儴璇诲嚱鏁 -function modbus:read_internal(config) - -- 澶勭悊鍝嶅簲缁撴灉锛 - local parsed_data = {} - - -- 妫鏌ユ槸鍚﹀悓鏃舵寚瀹氫簡 slave_id 鍜 raw_request - if config.slave_id and config.raw_request then - log.error("exmodbus", "绂佹鍚屾椂鎸囧畾 slave_id 鍜 raw_request") - - parsed_data.status = exmodbus_ref.STATUS_PARAM_INVALID - return parsed_data - end - - if config.slave_id then - local request_frame, function_code, transaction_id = build_tcp_frame("read", config) - if not request_frame then - log.error("exmodbus", "鏋勫缓 TCP 璇诲彇璇锋眰澶辫触") - parsed_data.status = exmodbus_ref.STATUS_PARAM_INVALID - return parsed_data - end - - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, request_frame, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 瑙ｆ瀽鍝嶅簲鏁版嵁锛 - parsed_data = parse_tcp_response(response, config, function_code, transaction_id) - end - elseif config.raw_request then - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, config.raw_request, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 鐩存帴杩斿洖鍝嶅簲缁撴灉鍜屽師濮嬪搷搴旀暟鎹紱 - parsed_data.status = exmodbus_ref.STATUS_SUCCESS - parsed_data.raw_response = response - end - end - - return parsed_data -end - --- 涓荤珯鍐欏叆璇锋眰鐨勫嚱鏁帮紱 -function modbus:write_internal(config) - -- 澶勭悊鍝嶅簲缁撴灉锛 - local parsed_data = {} - - -- 妫鏌ユ槸鍚﹀悓鏃舵寚瀹氫簡 slave_id 鍜 raw_request - if config.slave_id and config.raw_request then - log.error("exmodbus", "绂佹鍚屾椂鎸囧畾 slave_id 鍜 raw_request") - - parsed_data.status = exmodbus_ref.STATUS_PARAM_INVALID - return parsed_data - end - - if config.slave_id then - local request_frame, function_code, transaction_id = build_tcp_frame("write", config) - if not request_frame then - log.error("exmodbus", "鏋勫缓 TCP 鍐欏叆璇锋眰澶辫触") - parsed_data.status = exmodbus_ref.STATUS_PARAM_INVALID - return parsed_data - end - - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, request_frame, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 瑙ｆ瀽鍝嶅簲鏁版嵁锛 - parsed_data = parse_tcp_response(response, config, function_code, transaction_id) - end - elseif config.raw_request then - -- 鍙戦佽姹傚苟绛夊緟鍝嶅簲锛 - local result, response = sendRequest_waitResponse(self, config.raw_request, config) - if not result then - parsed_data.status = exmodbus_ref.STATUS_TIMEOUT - else - -- 鐩存帴杩斿洖鍝嶅簲缁撴灉鍜屽師濮嬪搷搴旀暟鎹紱 - parsed_data.status = exmodbus_ref.STATUS_SUCCESS - parsed_data.raw_response = response - end - end - - return parsed_data -end - --- 璇诲嚱鏁帮紙涓荤珯浣跨敤锛 -function modbus:read(config) - return exmodbus_ref.enqueue_request(self, config, true) -end - --- 鍐欏嚱鏁帮紙涓荤珯浣跨敤锛 -function modbus:write(config) - return exmodbus_ref.enqueue_request(self, config, false) -end - --- 娉ㄥ唽浠庣珯璇锋眰澶勭悊鍥炶皟鍑芥暟锛 -function modbus:on(callback) - if type(callback) ~= "function" then - log.error("exmodbus", "on(callback) 鐨勫弬鏁板繀椤绘槸涓涓嚱鏁") - return false - end - self.slaveHandler = callback - log.info("exmodbus", "宸叉敞鍐屼粠绔欒姹傚鐞嗗洖璋冨嚱鏁") - return true -end - -return { create = create } \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmtn.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmtn.lua deleted file mode 100644 index f74273c..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exmtn.lua +++ /dev/null @@ -1,789 +0,0 @@ ---[[ -@module exmtn -@summary 杩愮淮鏃ュ織鎵╁睍搴擄紝璐熻矗鏃ュ織鐨勬寔涔呭寲瀛樺偍 -@version 1.0 -@date 2025.12.9 -@author zengeshuai -@usage -exmtn.init(1, 0) -- 鍒濆鍖栵紝1涓潡锛岀紦瀛樺啓鍏 -exmtn.log("info", "tag", "message", 123) -- 杈撳嚭杩愮淮鏃ュ織 -]] - -local exmtn = {} - --- 甯搁噺瀹氫箟 -local LOG_MTN_CACHE_SIZE = 4096 -local LOG_MTN_FILE_COUNT = 4 -local LOG_MTN_CONFIG_FILE = "/exmtn.trc" -local LOG_MTN_DEFAULT_BLOCKS_DIVISOR = 40 -local LOG_MTN_ADD_WRITE_THRESHOLD = 256 -local LOG_MTN_CONFIG_VERSION = 1 - --- 鍐欏叆鏂瑰紡甯搁噺 -exmtn.CACHE_WRITE = 0 -exmtn.ADD_WRITE = 1 - --- 鍐呴儴鐘舵 -local ctx = { - inited = false, - enabled = false, - cur_index = 1, -- 1-4 - block_size = 4096, -- 榛樿鍧楀ぇ灏 - blocks_per_file = 1, -- 姣忔枃浠跺潡鏁 - file_limit = 4096, -- 姣忔枃浠跺ぇ灏忛檺鍒 - write_way = 0, -- 0=缂撳瓨鍐欏叆, 1=鐩存帴杩藉姞 - cache = "", -- 缂撳瓨缂撳啿鍖 - cache_used = 0, -- 缂撳瓨宸蹭娇鐢ㄥ瓧鑺傛暟 -} - --- 閲嶇疆缂撳瓨 -local function reset_cache() - ctx.cache = "" - ctx.cache_used = 0 -end - --- 鑾峰彇褰撳墠鏂囦欢璺緞 -local function get_file_path(index) - return string.format("/hzmtn%d.trc", index or ctx.cur_index) -end - --- 鑾峰彇褰撳墠鏂囦欢澶у皬 -local function get_current_file_size() - local path = get_file_path() - local file = io.open(path, "rb") - if not file then - return 0 - end - local size = file:seek("end") - file:close() - -- file:seek("end") 杩斿洖鏂囦欢澶у皬锛屽鏋滃け璐ヨ繑鍥 nil - if size and size > 0 then - return size - end - return 0 -end - --- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 -local function file_exists(path) - local file = io.open(path, "rb") - if file then - file:close() - return true - end - return false -end - --- 妫鏌ユ墍鏈夋棩蹇楁枃浠舵槸鍚﹀瓨鍦 -local function files_exist() - for i = 1, LOG_MTN_FILE_COUNT do - local path = get_file_path(i) - if file_exists(path) then - return true - end - end - return false -end - --- 鍒犻櫎鎵鏈夋棩蹇楁枃浠 -local function remove_files() - for i = 1, LOG_MTN_FILE_COUNT do - local path = get_file_path(i) - os.remove(path) - end -end - --- 鍒涘缓绌烘枃浠 -local function create_files() - for i = 1, LOG_MTN_FILE_COUNT do - local path = get_file_path(i) - local file = io.open(path, "wb") - if file then - file:close() - end - end -end - --- 璇诲彇閰嶇疆鏂囦欢 -local function load_config() - local file = io.open(LOG_MTN_CONFIG_FILE, "rb") - if not file then - return nil -- 鏂囦欢涓嶅瓨鍦紝杩斿洖 nil - end - - local content = file:read("*a") - file:close() - - if not content or #content == 0 then - return nil -- 鏂囦欢涓虹┖ - end - - -- 瑙ｆ瀽閰嶇疆锛氭牸寮忎负 "VERSION=1\nINDEX=2\nBLOCKS=10\nWRITE_WAY=0\n" - local config = {} - for line in content:gmatch("[^\r\n]+") do - -- 绉婚櫎棣栧熬绌虹櫧瀛楃 - line = line:match("^%s*(.-)%s*$") or line - local key, value = line:match("([^=]+)=(.+)") - if key and value then - -- 绉婚櫎 key 鍜 value 鐨勯灏剧┖鐧藉瓧绗 - key = key:match("^%s*(.-)%s*$") or key - value = value:match("^%s*(.-)%s*$") or value - local num_value = tonumber(value) - if num_value then - config[key] = num_value - else - config[key] = value - end - end - end - - -- 楠岃瘉鐗堟湰鍙 - if config.VERSION ~= LOG_MTN_CONFIG_VERSION then - return nil -- 鐗堟湰涓嶅尮閰 - end - - return config -end - --- 淇濆瓨閰嶇疆鏂囦欢 -local function save_config(index, blocks, write_way) - local content = string.format("VERSION=%d\nINDEX=%d\nBLOCKS=%d\nWRITE_WAY=%d\n", - LOG_MTN_CONFIG_VERSION, index, blocks, write_way) - - local file = io.open(LOG_MTN_CONFIG_FILE, "wb") - if not file then - log.warn("exmtn", "鏃犳硶鎵撳紑閰嶇疆鏂囦欢: " .. LOG_MTN_CONFIG_FILE) - return false - end - - local ok = file:write(content) - file:close() - - if not ok then - log.warn("exmtn", "鍐欏叆閰嶇疆鏂囦欢澶辫触: " .. LOG_MTN_CONFIG_FILE) - return false - end - - return true -end - --- 鏇存柊绱㈠紩锛堝悓鏃朵繚瀛樺畬鏁撮厤缃級 -local function update_index(index) - return save_config(index, ctx.blocks_per_file, ctx.write_way) -end - --- 鏍煎紡鍖栨椂闂存埑 --- 杩斿洖鏍煎紡: [2025-11-05 15:06:49.947][00000027.994] -local function format_timestamp() - -- 鑾峰彇绯荤粺杩愯鏃堕棿锛堟绉掞級 - local ticks_ms = 0 - if mcu and mcu.ticks then - local ticks = mcu.ticks() - if ticks then - ticks_ms = ticks - end - end - - -- 鑾峰彇褰撳墠鏃ユ湡鏃堕棿 - local date_time_str = "" - local ms = 0 - - if os and os.date then - -- 鑾峰彇褰撳墠鏃ユ湡鏃堕棿瀛楃涓: 2025-11-05 15:06:49 - local dt = os.date("%Y-%m-%d %H:%M:%S") - if dt then - -- 璁＄畻姣锛氫娇鐢ㄧ郴缁熻繍琛屾椂闂寸殑姣閮ㄥ垎 - -- 濡傛灉 RTC 宸茶缃紝鏃堕棿浼氭洿鍑嗙‘ - ms = ticks_ms % 1000 - date_time_str = string.format("%s.%03d", dt, ms) - end - end - - -- 濡傛灉鏃犳硶鑾峰彇鏃ユ湡鏃堕棿锛屼娇鐢ㄩ粯璁ゆ牸寮 - if date_time_str == "" then - date_time_str = "1970-01-01 00:00:00.000" - end - - -- 璁＄畻绯荤粺杩愯鏃堕棿锛堢.姣锛 - local uptime_sec = math.floor(ticks_ms / 1000) - local uptime_ms = ticks_ms % 1000 - - -- 鏍煎紡鍖栬繍琛屾椂闂撮儴鍒: 00000027.994锛堝浐瀹氬搴︼紝9浣嶆暣鏁+3浣嶅皬鏁帮級 - local uptime_str = string.format("%09d.%03d", uptime_sec, uptime_ms) - - -- 杩斿洖瀹屾暣鏃堕棿鎴 - return string.format("[%s][%s]", date_time_str, uptime_str) -end - --- 鏍煎紡鍖栬皟璇曚俊鎭 -local function format_debug_info(level, include_level) - local info = debug.getinfo(2, "Sl") - if not info or not info.source then - return nil - end - - local src = info.source - -- 璺宠繃绗竴涓瓧绗︼紙@ 鎴 =锛 - if src:sub(1, 1) == "@" or src:sub(1, 1) == "=" then - src = src:sub(2) - end - - local line = info.currentline or 0 - if line > 64 * 1024 then - line = 0 - end - - if include_level and level then - return string.format("%s/%s:%d", level, src, line) - else - return string.format("%s:%d", src, line) - end -end - --- 鏍煎紡鍖栨秷鎭紙涓 log.info/warn/error 鏍煎紡涓鑷达紝浣嗘坊鍔犳椂闂存埑鍓嶇紑锛 -local function format_message(level, tag, ...) - local argc = select("#", ...) - - -- 鑾峰彇 log.style 閰嶇疆 - local log_style = 0 - if log and log.style then - log_style = log.style() or 0 - end - - -- 鏍规嵁绾у埆纭畾鏃ュ織鏍囪瘑 - local level_char = "I" -- 榛樿 info - if level == "warn" then - level_char = "W" - elseif level == "error" then - level_char = "E" - end - - local msg = "" - local dbg_info_with_level = format_debug_info(level_char, true) - local dbg_info_only = format_debug_info(nil, false) - - if log_style == 0 then - -- LOG_STYLE_NORMAL: "I/user.tag arg1 arg2 ...\n" - msg = string.format("%s/user.%s", level_char, tag) - for i = 1, argc do - local arg = select(i, ...) - msg = msg .. " " .. tostring(arg) - end - elseif log_style == 1 then - -- LOG_STYLE_DEBUG_INFO: "I/file.lua:123 tag arg1 arg2 ...\n" - if dbg_info_with_level then - msg = dbg_info_with_level - else - msg = level_char - end - msg = msg .. " " .. tag - for i = 1, argc do - local arg = select(i, ...) - msg = msg .. " " .. tostring(arg) - end - else - -- LOG_STYLE_FULL: "I/user.tag file.lua:123 arg1 arg2 ...\n" - msg = string.format("%s/user.%s", level_char, tag) - if dbg_info_only then - msg = msg .. " " .. dbg_info_only - end - for i = 1, argc do - local arg = select(i, ...) - msg = msg .. " " .. tostring(arg) - end - end - - msg = msg .. "\n" - - -- 娣诲姞鏃堕棿鎴冲墠缂 - local timestamp = format_timestamp() - return timestamp .. " " .. msg -end - --- 鍒锋柊缂撳瓨鍒版枃浠 -local function flush_cache() - if ctx.cache_used == 0 then - return true - end - - local path = get_file_path() - local file = io.open(path, "ab") - if not file then - log.warn("exmtn", "鏃犳硶鎵撳紑鏂囦欢: " .. path) - return false - end - - -- file:write 杩斿洖 true/false 鎴 nil锛屼笉杩斿洖瀛楄妭鏁 - local ok = file:write(ctx.cache) - file:close() - - if not ok then - log.warn("exmtn", "鍐欏叆鏂囦欢澶辫触: " .. path) - return false - end - - reset_cache() - return true -end - --- 鐩存帴鍐欏叆鏂囦欢锛圓DD_WRITE 妯″紡锛 -local function direct_write(data) - local path = get_file_path() - local file = io.open(path, "ab") - if not file then - log.warn("exmtn", "鏃犳硶鎵撳紑鏂囦欢: " .. path) - return false - end - - -- file:write 杩斿洖 true/false 鎴 nil锛屼笉杩斿洖瀛楄妭鏁 - local ok = file:write(data) - file:close() - - if not ok then - log.warn("exmtn", "鍐欏叆鏂囦欢澶辫触: " .. path) - return false - end - - return true -end - --- 灏嗘暟鎹拷鍔犲埌缂撳瓨鎴栫洿鎺ュ啓鍏 -local function buffer_append(data) - if not data or #data == 0 then - return true - end - - local len = #data - - -- ADD_WRITE 妯″紡锛氱洿鎺ュ啓鍏ユ枃浠 - if ctx.write_way == exmtn.ADD_WRITE then - -- 灏忔暟鎹厛缂撳瓨锛岀疮绉埌闃堝煎啀鍐欏叆 - if len < LOG_MTN_ADD_WRITE_THRESHOLD then - if ctx.cache_used + len > LOG_MTN_CACHE_SIZE then - if not flush_cache() then - return false - end - end - ctx.cache = ctx.cache .. data - ctx.cache_used = ctx.cache_used + len - -- 濡傛灉绱Н鍒伴槇鍊硷紝绔嬪嵆鍐欏叆 - if ctx.cache_used >= LOG_MTN_ADD_WRITE_THRESHOLD then - return flush_cache() - end - return true - end - -- 澶ф暟鎹洿鎺ュ啓鍏 - return direct_write(data) - end - - -- CACHE_WRITE 妯″紡锛氬師鏈夐昏緫 - if len > LOG_MTN_CACHE_SIZE then - -- 鍏堝埛鏂扮紦瀛 - if not flush_cache() then - return false - end - -- 澶ф暟鎹洿鎺ュ啓鍏 - return direct_write(data) - end - - -- 妫鏌ョ紦瀛樻槸鍚﹁冻澶 - if ctx.cache_used + len > LOG_MTN_CACHE_SIZE then - if not flush_cache() then - return false - end - end - - ctx.cache = ctx.cache .. data - ctx.cache_used = ctx.cache_used + len - return true -end - --- 鍐欏叆鏃ュ織鍒版枃浠 -local function write_to_file(msg) - if not ctx.enabled then - return true -- 鏈惎鐢ㄦ椂杩斿洖鎴愬姛锛屼笉鍐欏叆 - end - - local len = #msg - - -- CACHE_WRITE 妯″紡 - if ctx.write_way == exmtn.CACHE_WRITE then - -- 妫鏌ユ枃浠跺ぇ灏 + 缂撳瓨澶у皬 + 褰撳墠鏁版嵁鏄惁浼氳秴杩囬檺鍒 - -- 濡傛灉浼氳秴杩囷紝鍏堝埛鏂扮紦瀛 - if ctx.cache_used > 0 then - local file_sz = get_current_file_size() - if file_sz + ctx.cache_used + len > ctx.file_limit then - -- 鍏堝埛鏂扮紦瀛 - if not flush_cache() then - return false - end - -- 閲嶆柊鑾峰彇鏂囦欢澶у皬 - file_sz = get_current_file_size() - -- 妫鏌ユ枃浠舵槸鍚﹀凡婊 - if file_sz >= ctx.file_limit then - -- 鏂囦欢宸叉弧锛屽垏鎹㈠埌涓嬩竴涓枃浠 - ctx.cur_index = (ctx.cur_index % LOG_MTN_FILE_COUNT) + 1 - local path = get_file_path() - local file = io.open(path, "wb") - if file then - file:close() - end - if not update_index(ctx.cur_index) then - log.warn("exmtn", "鏇存柊绱㈠紩澶辫触") - return false - end - reset_cache() - end - end - else - -- 缂撳瓨涓虹┖锛屾鏌ユ枃浠跺ぇ灏 - local file_sz = get_current_file_size() - if file_sz + len > ctx.file_limit then - -- 鏂囦欢宸叉弧锛屽垏鎹㈠埌涓嬩竴涓枃浠 - ctx.cur_index = (ctx.cur_index % LOG_MTN_FILE_COUNT) + 1 - local path = get_file_path() - local file = io.open(path, "wb") - if file then - file:close() - end - if not update_index(ctx.cur_index) then - log.warn("exmtn", "鏇存柊绱㈠紩澶辫触") - return false - end - reset_cache() - end - end - - -- 濡傛灉鍔犲叆杩欐潯鏁版嵁鍚庣紦瀛樹細婊★紝鍏堝埛鏂扮紦瀛 - if ctx.cache_used + len > LOG_MTN_CACHE_SIZE then - if not flush_cache() then - return false - end - - -- 鍒锋柊鍚庡啀娆℃鏌ユ枃浠跺ぇ灏 - local file_sz = get_current_file_size() - if file_sz >= ctx.file_limit then - -- 鏂囦欢宸叉弧锛屽垏鎹㈠埌涓嬩竴涓枃浠 - ctx.cur_index = (ctx.cur_index % LOG_MTN_FILE_COUNT) + 1 - local path = get_file_path() - local file = io.open(path, "wb") - if file then - file:close() - end - if not update_index(ctx.cur_index) then - log.warn("exmtn", "鏇存柊绱㈠紩澶辫触") - return false - end - reset_cache() - end - end - - -- 鍔犲叆缂撳瓨 - return buffer_append(msg) - else - -- ADD_WRITE 妯″紡锛氬厛鍒锋柊缂撳瓨锛岀‘淇濇枃浠跺ぇ灏忓噯纭 - if ctx.cache_used > 0 then - if not flush_cache() then - return false - end - end - - -- 鑾峰彇褰撳墠鏂囦欢澶у皬 - local file_sz = get_current_file_size() - - -- 妫鏌ュ綋鍓嶆枃浠舵槸鍚﹀凡鍐欐弧 - if file_sz >= ctx.file_limit then - -- 鏂囦欢宸叉弧锛屽垏鎹㈠埌涓嬩竴涓枃浠 - ctx.cur_index = (ctx.cur_index % LOG_MTN_FILE_COUNT) + 1 - local path = get_file_path() - local file = io.open(path, "wb") - if file then - file:close() - end - if not update_index(ctx.cur_index) then - log.warn("exmtn", "鏇存柊绱㈠紩澶辫触") - return false - end - reset_cache() - end - - -- 妫鏌ュ綋鍓嶆暟鎹槸鍚﹁兘鏀惧叆褰撳墠鏂囦欢 - if file_sz + len > ctx.file_limit then - -- 褰撳墠鏁版嵁鏀句笉涓嬶紝鍒囨崲鍒颁笅涓涓枃浠 - ctx.cur_index = (ctx.cur_index % LOG_MTN_FILE_COUNT) + 1 - local path = get_file_path() - local file = io.open(path, "wb") - if file then - file:close() - end - if not update_index(ctx.cur_index) then - log.warn("exmtn", "鏇存柊绱㈠紩澶辫触") - return false - end - reset_cache() - end - - -- 鍔犲叆缂撳瓨鎴栫洿鎺ュ啓鍏ワ紙buffer_append 浼氭牴鎹ぇ灏忓喅瀹氾級 - return buffer_append(msg) - end -end - ---[[ -鍒濆鍖栬繍缁存棩蹇 -@api exmtn.init(blocks, write_way) -@int blocks 姣忎釜鏂囦欢鐨勫潡鏁帮紝0琛ㄧず绂佺敤锛屾鏁存暟琛ㄧず鍧楁暟閲 -@int write_way 鍐欏叆鏂瑰紡锛屽彲閫夊弬鏁般俥xmtn.CACHE_WRITE(0)琛ㄧず缂撳瓨鍐欏叆锛宔xmtn.ADD_WRITE(1)琛ㄧず鐩存帴杩藉姞鍐欏叆锛岄粯璁や负exmtn.CACHE_WRITE -@return boolean 鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage -exmtn.init(1, exmtn.CACHE_WRITE) -- 鍒濆鍖栵紝1涓潡锛岀紦瀛樺啓鍏 -]] -function exmtn.init(blocks, write_way) - -- 鍙傛暟鏍￠獙 - if blocks == nil then - blocks = 0 - end - blocks = math.floor(blocks) - if blocks < 0 then - log.warn("exmtn", "鏃犳晥鐨勫潡鏁") - return false - end - - write_way = write_way or exmtn.CACHE_WRITE - if write_way ~= exmtn.CACHE_WRITE and write_way ~= exmtn.ADD_WRITE then - write_way = exmtn.CACHE_WRITE - end - - -- 濡傛灉绂佺敤 - if blocks == 0 then - reset_cache() - remove_files() - ctx.enabled = false - ctx.cur_index = 1 - -- 鍒犻櫎閰嶇疆鏂囦欢 - os.remove(LOG_MTN_CONFIG_FILE) - ctx.inited = true - return true - end - - -- 璇诲彇鏂囦欢绯荤粺淇℃伅 - if not ctx.inited then - ctx.block_size = 4096 - ctx.blocks_per_file = 1 - - -- 灏濊瘯鑾峰彇鏂囦欢绯荤粺淇℃伅锛堥渶瑕 fs 妯″潡鏀寔锛 - -- fs.fsstat 杩斿洖: success, total_blocks, used_blocks, block_size, fs_type - if fs and fs.fsstat then - local success, total_blocks, used_blocks, block_size, fs_type = fs.fsstat("/") - if success and block_size and block_size > 0 then - ctx.block_size = block_size - if total_blocks and total_blocks > 0 then - local def_blocks = math.floor(total_blocks / LOG_MTN_DEFAULT_BLOCKS_DIVISOR) - if def_blocks > 0 then - ctx.blocks_per_file = def_blocks - end - end - end - end - end - - -- 璇诲彇閰嶇疆鏂囦欢锛堜粎鍦ㄩ娆″垵濮嬪寲鏃惰鍙栵級 - if not ctx.inited then - local config = load_config() - if config then - -- 璇诲彇绱㈠紩 - if config.INDEX and config.INDEX >= 1 and config.INDEX <= LOG_MTN_FILE_COUNT then - ctx.cur_index = config.INDEX - end - - -- 璇诲彇鍧楁暟閰嶇疆 - if config.BLOCKS and config.BLOCKS > 0 then - ctx.blocks_per_file = config.BLOCKS - end - - -- 璇诲彇鍐欏叆鏂瑰紡閰嶇疆 - if config.WRITE_WAY == 0 or config.WRITE_WAY == 1 then - ctx.write_way = config.WRITE_WAY - end - - log.info("exmtn", "璇诲彇绱㈠紩", ctx.cur_index) - log.info("exmtn", "璇诲彇鍧楁暟閰嶇疆", ctx.blocks_per_file) - log.info("exmtn", "璇诲彇鍐欏叆鏂瑰紡閰嶇疆", ctx.write_way) - end - end - - -- 妫鏌ラ厤缃槸鍚﹀彉鍖 - -- 濡傛灉宸插垵濮嬪寲锛屾瘮杈冨綋鍓嶉厤缃拰鏂伴厤缃紱濡傛灉鏈垵濮嬪寲锛屼笉闇瑕佸垽鏂紙棣栨鍒濆鍖栨绘槸"鍙樺寲"鐨勶級 - local config_changed = false - if ctx.inited then - -- 宸插垵濮嬪寲锛氭瘮杈冨綋鍓嶉厤缃拰鏂颁紶鍏ョ殑閰嶇疆 - config_changed = (ctx.blocks_per_file ~= blocks) or (ctx.write_way ~= write_way) - end - -- 鏈垵濮嬪寲锛歝onfig_changed 淇濇寔涓 false锛屽洜涓洪娆″垵濮嬪寲涓嶇畻"鍙樺寲" - - log.info("exmtn", "閰嶇疆鍙樺寲", config_changed) - -- 鏇存柊閰嶇疆 - ctx.blocks_per_file = blocks - ctx.write_way = write_way - ctx.file_limit = ctx.block_size * ctx.blocks_per_file - if ctx.file_limit == 0 then - ctx.file_limit = LOG_MTN_CACHE_SIZE - end - - -- 澶勭悊鏂囦欢鐨勪笁绉嶆儏鍐 - if config_changed then - -- 鎯呭喌1锛氶厤缃彉鍖栵紝娓呯┖鏂囦欢 - log.info("exmtn", "閰嶇疆鍙樺寲锛屾竻绌烘枃浠") - reset_cache() - remove_files() - create_files() - ctx.cur_index = 1 - elseif files_exist() then - -- 鎯呭喌2锛氶厤缃病鏈夊彉鍖栵紝鏂囦欢瀛樺湪锛屾牴鎹厤缃枃浠朵腑淇濆瓨鐨勬枃浠舵寚閽堢户缁啓 - log.info("exmtn", "閰嶇疆鏈彉鍖栵紝鏂囦欢瀛樺湪锛岀户缁啓鍏") - -- ctx.cur_index 宸茬粡浠庨厤缃枃浠惰鍙栵紙濡傛灉鏄娆″垵濮嬪寲锛夋垨淇濇寔褰撳墠鍊硷紙濡傛灉宸插垵濮嬪寲锛夛紝涓嶉渶瑕侀噸缃 - else - -- 鎯呭喌3锛氶厤缃病鏈夊彉鍖栵紝鏂囦欢涓嶅瓨鍦紝鍒涘缓鏂囦欢 - log.info("exmtn", "閰嶇疆鏈彉鍖栵紝鏂囦欢涓嶅瓨鍦紝鍒涘缓鏂囦欢") - create_files() - -- ctx.cur_index 宸茬粡浠庨厤缃枃浠惰鍙栵紙濡傛灉鏄娆″垵濮嬪寲锛夋垨淇濇寔褰撳墠鍊硷紙濡傛灉宸插垵濮嬪寲锛夛紝涓嶉渶瑕侀噸缃 - end - - -- 淇濆瓨閰嶇疆鍒版枃浠 - if not save_config(ctx.cur_index, blocks, write_way) then - log.warn("exmtn", "淇濆瓨閰嶇疆澶辫触") - return false - end - - ctx.enabled = true - ctx.inited = true - - -- 鎵撳嵃鍒濆鍖栦俊鎭 - if blocks > 0 then - local total_size = ctx.file_limit * LOG_MTN_FILE_COUNT - local file_size_mb = ctx.file_limit / (1024 * 1024) - local total_size_mb = total_size / (1024 * 1024) - local file_size_kb = ctx.file_limit / 1024 - local total_size_kb = total_size / 1024 - - if ctx.file_limit >= 1024 * 1024 then - log.info("exmtn", string.format("鍒濆鍖栨垚鍔: 姣忎釜鏂囦欢 %.2f MB (%d 鍧 脳 %d 瀛楄妭), 鎬荤┖闂 %.2f MB (%d 涓枃浠)", - file_size_mb, ctx.blocks_per_file, ctx.block_size, total_size_mb, LOG_MTN_FILE_COUNT)) - elseif ctx.file_limit >= 1024 then - log.info("exmtn", string.format("鍒濆鍖栨垚鍔: 姣忎釜鏂囦欢 %.2f KB (%d 鍧 脳 %d 瀛楄妭), 鎬荤┖闂 %.2f KB (%d 涓枃浠)", - file_size_kb, ctx.blocks_per_file, ctx.block_size, total_size_kb, LOG_MTN_FILE_COUNT)) - else - log.info("exmtn", string.format("鍒濆鍖栨垚鍔: 姣忎釜鏂囦欢 %d 瀛楄妭 (%d 鍧 脳 %d 瀛楄妭), 鎬荤┖闂 %d 瀛楄妭 (%d 涓枃浠)", - ctx.file_limit, ctx.blocks_per_file, ctx.block_size, total_size, LOG_MTN_FILE_COUNT)) - end - end - - return true -end - ---[[ -杈撳嚭杩愮淮鏃ュ織骞跺啓鍏ユ枃浠 -@api exmtn.log(level, tag, ...) -@string level 鏃ュ織绾у埆锛屽繀椤绘槸 "info", "warn", 鎴 "error" -@string tag 鏃ュ織鏍囪瘑锛屽繀椤绘槸瀛楃涓 -@... 闇鎵撳嵃鐨勫弬鏁 -@return boolean 鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage -exmtn.log("info", "message", 123) -exmtn.log("warn", "message", 456) -exmtn.log("error", "message", 789) -]] -function exmtn.log(level, tag, ...) - if not level or type(level) ~= "string" then - log.warn("exmtn", "level 蹇呴』鏄瓧绗︿覆") - return false - end - - if not tag or type(tag) ~= "string" then - log.warn("exmtn", "tag 蹇呴』鏄瓧绗︿覆") - return false - end - - -- 鏍规嵁绾у埆璋冪敤瀵瑰簲鐨勫簳灞傚嚱鏁帮紙浼氳鏃ュ織绾у埆杩囨护锛 - if level == "info" then - log.info(tag, ...) - elseif level == "warn" then - log.warn(tag, ...) - elseif level == "error" then - log.error(tag, ...) - else - log.warn("exmtn", "level 蹇呴』鏄 'info', 'warn' 鎴 'error'") - return false - end - - -- 鏍煎紡鍖栨秷鎭紙鐢ㄤ簬鏂囦欢鍐欏叆锛 - local msg = format_message(level, tag, ...) - if not msg then - log.warn("exmtn", "鏍煎紡鍖栨秷鎭け璐") - return false - end - - -- 鍐欏叆鏂囦欢锛堜笉鍙楁棩蹇楃骇鍒奖鍝嶏級 - return write_to_file(msg) -end - ---[[ -鑾峰彇褰撳墠閰嶇疆 -@api exmtn.get_config() -@return table|nil 閰嶇疆淇℃伅锛屽け璐ヨ繑鍥瀗il -@usage -local config = exmtn.get_config() -if config then - log.info("exmtn", "blocks:", config.blocks, "write_way:", config.write_way) -end -]] -function exmtn.get_config() - if not ctx.inited then - return nil - end - return { - enabled = ctx.enabled, - cur_index = ctx.cur_index, - block_size = ctx.block_size, - blocks_per_file = ctx.blocks_per_file, - file_limit = ctx.file_limit, - write_way = ctx.write_way, - } -end - ---[[ -娓呴櫎鎵鏈夎繍缁存棩蹇楁枃浠 -@api exmtn.clear() -@return boolean 鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage -local ok = exmtn.clear() -if ok then - log.info("exmtn", "鏃ュ織鏂囦欢宸叉竻闄") -end -]] -function exmtn.clear() - -- 濡傛灉宸插垵濮嬪寲锛屽厛鍒锋柊缂撳瓨锛堢‘淇濇暟鎹笉涓㈠け锛 - if ctx.inited and ctx.cache_used > 0 then - if not flush_cache() then - return false - end - end - - -- 鍒犻櫎鎵鏈夋棩蹇楁枃浠 - remove_files() - - -- 閲嶆柊鍒涘缓绌烘枃浠 - create_files() - - -- 閲嶇疆绱㈠紩涓1 - ctx.cur_index = 1 - - -- 鏇存柊閰嶇疆鏂囦欢 - if not save_config(1, ctx.blocks_per_file, ctx.write_way) then - return false - end - - log.info("exmtn", "杩愮淮鏃ュ織鏂囦欢宸叉竻闄") - return true -end - -return exmtn - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exnetif.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exnetif.lua deleted file mode 100644 index fe3a12c..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exnetif.lua +++ /dev/null @@ -1,1135 +0,0 @@ ---[[ -@module exnetif -@summary exnetif 鎺у埗缃戠粶浼樺厛绾э紙浠ュお缃->WIFI->4G锛夋牴鎹紭鍏堢骇閫夋嫨涓婄綉鐨勭綉鍗°傜畝鍖栧紑鍚缃戣瀺鍚堢殑鎿嶄綔锛4G浣滀负鏁版嵁鍑哄彛缁橶IFI,浠ュお缃戣澶囦笂缃戯紝浠ュお缃戜綔涓烘暟鎹嚭鍙ｇ粰WIFI,Air8000涓婄綉锛學IFI浣滀负鏁版嵁鍑哄彛缁橝ir8000,浠ュお缃戜笂缃戙 -@version 1.0 -@date 2025.06.26 -@author wjq -@usage -鏈枃浠剁殑瀵瑰鎺ュ彛鏈5涓細 -1銆乪xnetif.set_priority_order(networkConfigs)锛氳缃綉缁滀紭鍏堢骇椤哄簭骞跺垵濮嬪寲瀵瑰簲缃戠粶(闇瑕佸湪task涓皟鐢) -2銆乪xnetif.notify_status(cb_fnc)锛氳缃綉缁滅姸鎬佸彉鍖栧洖璋冨嚱鏁 -3銆乪xnetif.setproxy(adapter, main_adapter,other_configs)锛氶厤缃綉缁滀唬鐞嗗疄鐜板缃戣瀺鍚(闇瑕佸湪task涓皟鐢) -4銆乪xnetif.check_network_status(interval),妫娴嬮棿闅旀椂闂磎s(閫夊～)锛屼笉濉椂鍙娴嬩竴娆★紝濉啓鍚庡皢鏍规嵁闂撮殧鏃堕棿寰幆妫娴嬶紝浼氭彁楂樻ā鍧楀姛鑰 -5銆乪xnetif.close(type, adapter)锛氬叧闂寚瀹氱綉鍗,鍐呮牳鍥轰欢鐗堟湰鍙烽渶>=2020 -]] -local exnetif = {} - -dnsproxy = require("dnsproxy") -dhcpsrv = require("dhcpsrv") -httpdns = require("httpdns") --- 璁剧疆pingip -local wifi_ping_ip -local eth_ping_ip --- 灞鍩熺綉妯″紡 -local local_network_mode --- 鏄惁闇瑕侀氳繃ping鏉ユ祴璇曠綉缁滅殑杩為氭 -local need_ping = true --- 浣跨敤鍗曠綉鍗℃ā寮 -local single_network_mode = false --- 鏄惁鑷姩鍏抽棴闈炲綋鍓嶇綉鍗ocket杩炴帴 -local auto_socket_switch = true --- ping妫娴嬮棿闅旀椂闂 -local ping_time = 10000 --- 杩炴帴鐘舵 -local connection_states = { - DISCONNECTED = 0, - CONNECTING = 1, - CONNECTED = 2, - OPENED = 3, - SINGLE_NETWORK = 4, - STOPED = 5 -} - --- 鐘舵佸洖璋冨嚱鏁 -local states_cbfnc = function(net_type) -end --- 褰撳墠浼樺厛绾 -local current_priority = {socket.LWIP_ETH, socket.LWIP_STA, socket.LWIP_GP} --- 杩炴帴鐘舵 -local available = { - [socket.LWIP_STA] = connection_states.DISCONNECTED, - [socket.LWIP_ETH] = connection_states.DISCONNECTED, - [socket.LWIP_GP] = connection_states.DISCONNECTED, - [socket.LWIP_USER1] = connection_states.DISCONNECTED -} --- 褰撳墠浣跨敤鐨勭綉鍗 -local current_active = nil - --- 缃戠粶绫诲瀷杞瓧绗︿覆 -local function type_to_string(net_type) - local type_map = { - [socket.LWIP_STA] = "WiFi", - [socket.LWIP_ETH] = "Ethernet", - [socket.LWIP_GP] = "4G", - [socket.LWIP_USER1] = "8101SPIETH" - } - return type_map[net_type] or "Unknown" -end - --- 淇濆瓨浠ュお缃戠綉鍗″弬鏁帮紝鐢ㄤ簬鍏抽棴spi鍜屼緵鐢典娇鑳 -local eth_cfg = { - [socket.LWIP_ETH] = {}, - [socket.LWIP_USER1] = {} -} - --- 璁㈤槄socket杩炴帴鐘舵佸彉鍖栦簨浠讹紝socket鍑虹幇寮傚父鏃朵慨鏀圭綉鍗＄姸鎬 -local function socket_state_detection(adapter) - if netdrv.on then - log.info("netdrv", "璁㈤槄socket杩炴帴鐘舵佸彉鍖栦簨浠", type_to_string(adapter)) - -- 璁㈤槄socket杩炴帴鐘舵佸彉鍖栦簨浠 - netdrv.on(adapter, netdrv.EVT_SOCKET, function(id, event, params) - if event == "timeout" or event == "error" then - if available[adapter] == connection_states.CONNECTED then - available[adapter] = connection_states.CONNECTING - end - end - -- log.info("netdrv", "socket event", id, event, json.encode(params or {})) - -- if params then - -- -- params閲屼細鏈塺emote_ip, remote_port绛変俊鎭, 鍙寜闇鑾峰彇 - -- local remote_ip = params.remote_ip - -- local remote_port = params.remote_port - -- local domain_name = params.domain_name - -- log.info("netdrv", "socket event", "remote_ip", remote_ip, "remote_port", remote_port, "domain_name", domain_name) - -- end - end) - end -end - --- 鐘舵佹洿鏀瑰悗閲嶆柊璁剧疆榛樿缃戝崱 -local function apply_priority() - local usable = false - -- 鏌ユ壘浼樺厛绾ф渶楂樼殑鍙敤缃戠粶 - for _, net_type in ipairs(current_priority) do - -- log.info("缃戝崱椤哄簭",type_to_string(net_type),available[net_type]) - if available[net_type] == connection_states.CONNECTED then - usable = true - -- 璁剧疆浼樺厛绾ч珮鐨勭綉鍗 - if current_active ~= net_type then - log.info("璁剧疆缃戝崱", type_to_string(net_type)) - states_cbfnc(type_to_string(net_type), net_type) -- 榛樿缃戝崱鏀瑰彉鐨勫洖璋冨嚱鏁 - socket.dft(net_type) - if auto_socket_switch and socket.close_all then - socket.close_all(current_active) - end - current_active = net_type - end - break - end - end - - -- 浠庡瓨鍦ㄥ彲鐢ㄧ綉鍗″埌娌℃湁鍙敤缃戝崱锛屾墠閫氱煡鍥炶皟 - if usable == false and current_active ~= nil then - -- 閬垮厤閲嶅閫氱煡 - current_active = nil - states_cbfnc(nil, -1) - end -end - --- httpdns鍩熷悕瑙ｆ瀽娴嬭瘯 -local function http_dnstest(adaptertest) - local ip = httpdns.ali("baidu.com", { - adapter = adaptertest, - timeout = 3000 - }) - if ip ~= nil then - available[adaptertest] = connection_states.CONNECTED - log.info(type_to_string(adaptertest) .. "缃戝崱httpdns鍩熷悕瑙ｆ瀽鎴愬姛") - else - log.info(type_to_string(adaptertest) .. "缃戝崱httpdns鍩熷悕瑙ｆ瀽澶辫触") - end - log.info("httpdns", "baidu.com", ip) -end --- ping鎿嶄綔 -local function ping_request(adaptertest) - log.info("dns_request", type_to_string(adaptertest), need_ping) - if need_ping then - if adaptertest == socket.LWIP_ETH or adaptertest == socket.LWIP_USER1 then - if eth_ping_ip == nil then - http_dnstest(adaptertest) - else - icmp.setup(adaptertest) - icmp.ping(adaptertest, eth_ping_ip) - end - end - if adaptertest == socket.LWIP_STA then - if wifi_ping_ip == nil then - http_dnstest(adaptertest) - else - icmp.setup(adaptertest) - icmp.ping(adaptertest, wifi_ping_ip) - end - end - if adaptertest == socket.LWIP_GP then - if eth_ping_ip ~= nil then - icmp.setup(adaptertest) - icmp.ping(adaptertest, eth_ping_ip) - elseif wifi_ping_ip ~= nil then - icmp.setup(adaptertest) - icmp.ping(adaptertest, wifi_ping_ip) - else - http_dnstest(adaptertest) - end - end - else - log.info(type_to_string(adaptertest) .. "閰嶇疆浜嗕笉闇瑕乸ing锛岀洿鎺ュ垏鎹负CONNECTED鐘舵") - available[adaptertest] = connection_states.CONNECTED - end - apply_priority() -end --- 缃戝崱涓婄嚎鍥炶皟鍑芥暟 -local function ip_ready_handle(ip, adapter) - local _, _, gw = socket.localIP(adapter) - log.info("ip_ready_handle", ip, type_to_string(adapter), "state", available[adapter], "gw", gw) - if local_network_mode then - if adapter == socket.LWIP_ETH or adapter == socket.LWIP_USER1 then - eth_ping_ip = gw - elseif adapter == socket.LWIP_STA then - wifi_ping_ip = gw - end - end - log.info("eth_ping_ip", eth_ping_ip, "wifi_ping_ip", wifi_ping_ip) - -- 闇瑕乸ing鎿嶄綔锛宲ing閫氬悗璁や负缃戠粶鍙敤 - if available[adapter] == connection_states.OPENED then - available[adapter] = connection_states.CONNECTING - end - -- ping_request(adapter) -end --- 缃戝崱涓嬬嚎鍥炶皟鍑芥暟 -local function ip_lose_handle(adapter) - log.info("ip_lose_handle", type_to_string(adapter)) - if available[adapter] == connection_states.CONNECTING or available[adapter] == connection_states.CONNECTED then - available[adapter] = connection_states.OPENED - end - if current_active == adapter then - log.info(type_to_string(adapter) .. " 澶辨晥锛屽垏鎹㈠埌鍏朵粬缃戠粶") - apply_priority() - end -end - -local interval_time = nil - ---[[ -瀵规甯哥姸鎬佺殑缃戝崱杩涜ping娴嬭瘯 -@api exnetif.check_network_status(interval), -@int 妫娴嬮棿闅旀椂闂磎s(閫夊～)锛屼笉濉椂鍙娴嬩竴娆★紝濉啓鍚庡皢鏍规嵁闂撮殧鏃堕棿寰幆妫娴嬶紝浼氭彁楂樻ā鍧楀姛鑰 -]] -function exnetif.check_network_status(interval) - if interval ~= nil then - interval_time = interval - end - for _, net_type in ipairs(current_priority) do - if available[net_type] == connection_states.CONNECTED then - available[net_type] = connection_states.CONNECTING - end - end -end - --- 鎵撳紑浠ュお缃慦an鍔熻兘 -local function setup_eth(config) - if config.local_network_mode then - local_network_mode = true - end - if config.need_ping ~= nil then - need_ping = config.need_ping - end - if config.auto_socket_switch ~= nil then - auto_socket_switch = config.auto_socket_switch - -- log.info("璁剧疆鑷姩鍏抽棴闈炲綋鍓嶇綉鍗ocket杩炴帴", auto_socket_switch) - end - eth_ping_ip = config.ping_ip - if type(config.ping_time) == "number" then - ping_time = config.ping_time - end - log.info("鍒濆鍖栦互澶綉") - if not single_network_mode then - available[socket.LWIP_ETH] = connection_states.OPENED - else - available[socket.LWIP_ETH] = connection_states.SINGLE_NETWORK - end - -- 鎵撳紑CH390渚涚數 - if config.pwrpin then - gpio.setup(config.pwrpin, 1, gpio.PULLUP) - end - -- sys.wait(100) -- 绛夊緟浠ュお缃戞ā鍧椾笂鐢电ǔ瀹 - if config.tp == nil then - log.info("8101浠ュお缃") - if netdrv.setup(socket.LWIP_ETH) == false then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if config.pwrpin then - gpio.close(config.pwrpin) - end - return false - end - else - log.info("config.opts.spi", config.opts.spi, ",config.type", config.tp) - -- 閰嶇疆SPI鍜屽垵濮嬪寲缃戠粶椹卞姩 - local result = spi.setup(config.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负0锛岃〃绀烘墦寮鎴愬姛 - log.info("main", "spi open error", result) - if config.pwrpin then - gpio.close(config.pwrpin) - end - return false - end - -- 鍒濆鍖栨寚瀹歯etdrv璁惧, - -- socket.LWIP_ETH 缃戠粶閫傞厤鍣ㄧ紪鍙 - -- netdrv.CH390澶栨寕CH390 - -- SPI ID 1, 鐗囬 GPIO12 - if netdrv.setup(socket.LWIP_ETH, config.tp, config.opts) == false then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if config.pwrpin then - gpio.close(config.pwrpin) - end - return false - end - end - if config.static_ip then - sys.wait(1000) -- 绛夊緟浠ュお缃戞ā鍧楀垵濮嬪寲瀹屾垚,鍘绘帀浼氬鑷翠互澶綉鍒濆鍖栧け璐 - log.info("netdrv", "鑷畾涔変互澶綉IP鍦板潃", config.static_ip.ipv4) - log.info("闈欐乮p", - netdrv.ipv4(socket.LWIP_ETH, config.static_ip.ipv4, config.static_ip.mark, config.static_ip.gw)) - else - netdrv.dhcp(socket.LWIP_ETH, true) - end - log.info("浠ュお缃戝垵濮嬪寲瀹屾垚") - socket_state_detection(socket.LWIP_ETH) - return true -end - --- 鎵撳紑8101spi浠ュお缃慦an鍔熻兘 -local function setup_eth_user1(config) - if config.local_network_mode then - local_network_mode = true - end - if config.need_ping ~= nil then - need_ping = config.need_ping - end - if config.auto_socket_switch ~= nil then - auto_socket_switch = config.auto_socket_switch - -- log.info("璁剧疆鑷姩鍏抽棴闈炲綋鍓嶇綉鍗ocket杩炴帴", auto_socket_switch) - end - eth_ping_ip = config.ping_ip - if type(config.ping_time) == "number" then - ping_time = config.ping_time - end - log.info("鍒濆鍖栦互澶綉") - if not single_network_mode then - available[socket.LWIP_USER1] = connection_states.OPENED - else - available[socket.LWIP_USER1] = connection_states.SINGLE_NETWORK - end - -- 鎵撳紑CH390渚涚數 - if config.pwrpin then - gpio.setup(config.pwrpin, 1, gpio.PULLUP) - end - -- sys.wait(100)-- 绛夊緟浠ュお缃戞ā鍧椾笂鐢电ǔ瀹 - log.info("config.opts.spi", config.opts.spi, ",config.type", config.tp) - -- 閰嶇疆SPI鍜屽垵濮嬪寲缃戠粶椹卞姩 - local result = spi.setup(config.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负0锛岃〃绀烘墦寮鎴愬姛 - log.info("main", "spi open error", result) - if config.pwrpin then - gpio.close(config.pwrpin) - end - return false - end - -- 鍒濆鍖栨寚瀹歯etdrv璁惧, - -- socket.LWIP_ETH 缃戠粶閫傞厤鍣ㄧ紪鍙 - -- netdrv.CH390澶栨寕CH390 - -- SPI ID 1, 鐗囬 GPIO12 - if netdrv.setup(socket.LWIP_USER1, config.tp, config.opts) == false then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if config.pwrpin then - gpio.close(config.pwrpin) - end - return false - end - if config.static_ip then - sys.wait(1000) -- 绛夊緟浠ュお缃戞ā鍧楀垵濮嬪寲瀹屾垚,鍘绘帀浼氬鑷翠互澶綉鍒濆鍖栧け璐 - log.info("netdrv", "鑷畾涔変互澶綉IP鍦板潃", config.static_ip.ipv4) - log.info("闈欐乮p", - netdrv.ipv4(socket.LWIP_USER1, config.static_ip.ipv4, config.static_ip.mark, config.static_ip.gw)) - else - netdrv.dhcp(socket.LWIP_USER1, true) - end - - log.info("浠ュお缃戝垵濮嬪寲瀹屾垚") - socket_state_detection(socket.LWIP_USER1) - return true -end - --- 杩炴帴wifi(STA妯″紡) -local function set_wifi_info(config) - if config.local_network_mode then - local_network_mode = true - end - if config.need_ping ~= nil then - need_ping = config.need_ping - end - if config.auto_socket_switch ~= nil then - auto_socket_switch = config.auto_socket_switch - -- log.info("璁剧疆鑷姩鍏抽棴闈炲綋鍓嶇綉鍗ocket杩炴帴", auto_socket_switch) - end - wifi_ping_ip = config.ping_ip - if type(config.ping_time) == "number" then - ping_time = config.ping_time - end - log.info("WiFi鍚嶇О:", config.ssid) - log.info("瀵嗙爜 :", config.password) - log.info("ping_ip :", config.ping_ip) - wlan.init() - if not single_network_mode then - available[socket.LWIP_STA] = connection_states.OPENED - else - available[socket.LWIP_STA] = connection_states.SINGLE_NETWORK - end - -- 灏濊瘯杩炴帴Wi-Fi锛屽苟澶勭悊鍙兘鍑虹幇鐨勯敊璇 - local success = wlan.connect(config.ssid, config.password) - if not success then - log.error("WiFi杩炴帴澶辫触") - return false - end - log.info("WiFi STA鍒濆鍖栧畬鎴") - socket_state_detection(socket.LWIP_STA) - return true -end - --- 浠ュお缃戝浜巗top鐘舵侊紝閲嶅惎浠ュお缃 -local function eth_net_restart(adapter) - log.info("浠ュお缃戝浜巗top鐘舵侊紝閲嶅惎涓") - if not single_network_mode then - available[adapter] = connection_states.OPENED - else - available[adapter] = connection_states.SINGLE_NETWORK - end - -- 鎵撳紑CH390渚涚數 - if eth_cfg[adapter].pwrpin then - log.info("鎵撳紑浠ュお缃戜緵鐢靛紩鑴:", eth_cfg[adapter].pwrpin) - gpio.setup(eth_cfg[adapter].pwrpin, 1, gpio.PULLUP) - end - -- sys.wait(100) -- 绛夊緟浠ュお缃戞ā鍧椾笂鐢电ǔ瀹 - if eth_cfg[adapter].tp == nil then - log.info("8101浠ュお缃") - else - log.info("config.opts.spi", eth_cfg[adapter].opts.spi, ",config.type", eth_cfg[adapter].tp) - -- 閰嶇疆SPI鍜屽垵濮嬪寲缃戠粶椹卞姩 - local result = spi.setup(eth_cfg[adapter].opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负0锛岃〃绀烘墦寮鎴愬姛 - log.info("main", "spi open error", result) - if eth_cfg[adapter].pwrpin then - gpio.close(eth_cfg[adapter].pwrpin) - end - return false - end - end - netdrv.ctrl(adapter, netdrv.CTRL_UPDOWN, 1) -end - --- ping娴嬭瘯寰幆 -local function ping_test_loop() - while true do - for _, net_type in ipairs(current_priority) do - -- log.info("缃戝崱椤哄簭",type_to_string(net_type),available[net_type]) - if available[net_type] == connection_states.CONNECTING then - log.info(type_to_string(net_type) .. "缃戝崱寮濮婸ING") - ping_request(net_type) - sys.wait(ping_time) - end - end - sys.wait(1000) -- 閬垮厤姝诲惊鐜 - end -end - --- 姝ｅ父鐘舵佺綉鍗＄殑妫娴嬩换鍔 -local function normal_network_test() - while true do - if interval_time ~= nil then - sys.wait(interval_time) - exnetif.check_network_status() - end - sys.wait(1000) -- 閬垮厤姝诲惊鐜 - end -end - --- PING缁撴灉澶勭悊鍑芥暟 -local function ping_res(id, time, dst) - log.info("ping", id, time, dst) - log.info(type_to_string(id) .. "缃戝崱PING娴嬭瘯鎴愬姛") - available[id] = connection_states.CONNECTED - apply_priority() -end - ---[[ -璁剧疆缃戠粶浼樺厛绾э紝鐩稿簲缃戝崱鑾峰彇鍒癷p涓旂綉缁滄甯歌涓虹綉鍗″彲鐢紝涓㈠けip瑙嗕负缃戝崱涓嶅彲鐢.(闇瑕佸湪task涓皟鐢) -@api exnetif.set_priority_order(new_priority) -@table 缃戠粶浼樺厛绾у垪琛,浼樺厛绾т粠楂樺埌浣庡搴攖able涓殑绗竴涓弬鏁板埌鏈鍚庝竴涓弬鏁 -@return boolean 鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage -澶氱綉浼樺厛绾фā寮忥細 -exnetif.set_priority_order({ - { -- 鏈楂樹紭鍏堢骇缃戠粶 - WIFI = { -- WiFi閰嶇疆 - ssid = "your_ssid", -- WiFi鍚嶇О(string) - password = "your_pwd", -- WiFi瀵嗙爜(string) - need_ping = true, -- 鏄惁闇瑕侀氳繃ping鏉ユ祴璇曠綉缁滅殑杩為氭 - -- 鍦ㄦ病鏈塸ing娴嬭瘯鐜鐨勯」鐩腑锛岄渶瑕佸皢杩欎釜鍙傛暟璁剧疆涓篺alse锛岃〃绀轰笉闇瑕乸ing娴嬭瘯缃戠粶杩為氾紝 - -- 浠呮牴鎹甀P READY娑堟伅锛堝嵆鑾峰彇鍒颁簡ip鍦板潃锛夋潵鍒ゆ柇缃戠粶鐜鍑嗗灏辩华锛屾槸鍚︾綉缁滆繛閫氭у垯鏃犳硶淇濊瘉 - -- 濡傛灉娌℃湁璁剧疆姝ゅ弬鏁帮紝榛樿涓簍rue - -- 鍦ㄦ湁ping娴嬭瘯鐜鐨勯」鐩腑锛屽缓璁笉瑕佸皢杩欎釜鍙傛暟璁剧疆涓簍rue - local_network_mode = true,-- 灞鍩熺綉妯″紡(閫夊～鍙傛暟)锛岃缃负true鏃讹紝exnetif浼氳嚜鍔ㄥ皢ping_ip璁剧疆涓虹綉鍗＄殑缃戝叧ip銆 - -- 鐢ㄦ埛涓嶉渶瑕佷紶鍏ing_ip鍙傛暟锛屽嵆浣夸紶鍏ヤ簡锛屼篃鏃犳晥銆 - -- 杩欎釜妯″紡鐨勪娇鐢ㄥ満鏅紝浠呴傜敤浜庡眬鍩熺綉鐜锛涘彲浠ヨ闂缃戞椂锛屼笉瑕佷娇鐢 - ping_ip = "112.125.89.8", -- 杩為氭ф娴婭P(閫夊～鍙傛暟),榛樿浣跨敤httpdns鑾峰彇baidu.com鐨刬p浣滀负鍒ゆ柇鏉′欢锛 - -- 娉細濡傛灉濉啓ip锛屽垯ping閫氫綔涓哄垽鏂綉缁滄槸鍚﹀彲鐢ㄧ殑鏉′欢锛 - -- 鎵浠ラ渶瑕佹牴鎹綉缁滅幆澧冨～鍐欏唴缃戞垨鑰呭缃慽p, - -- 濉啓澶栫綉ip鐨勮瘽瑕佷繚璇佸缃慽p濮嬬粓鍙敤锛 - -- 濉啓灞鍩熺綉ip鐨勮瘽瑕佺‘淇濈浉搴攊p鍥哄畾涓旇兘澶熻ping閫 - ping_time = 10000 -- 濉啓ping_ip涓旀湭ping閫氭椂鐨勬娴嬮棿闅(ms, 鍙夛紝榛樿涓10绉) - -- 瀹氭椂ping灏嗕細褰卞搷妯″潡鍔熻楋紝浣跨敤浣庡姛鑰楁ā寮忕殑璇濆彲浠ラ傚綋寤惰繜闂撮殧鏃堕棿 - } - }, - { -- 娆′紭鍏堢骇缃戠粶 - ETHERNET = { -- 浠ュお缃戦厤缃 - pwrpin = 140, -- 渚涚數浣胯兘寮曡剼(number) - need_ping = true, -- 鏄惁闇瑕侀氳繃ping鏉ユ祴璇曠綉缁滅殑杩為氭 - -- 鍦ㄦ病鏈塸ing娴嬭瘯鐜鐨勯」鐩腑锛岄渶瑕佸皢杩欎釜鍙傛暟璁剧疆涓篺alse锛岃〃绀轰笉闇瑕乸ing娴嬭瘯缃戠粶杩為氾紝 - -- 浠呮牴鎹甀P READY娑堟伅锛堝嵆鑾峰彇鍒颁簡ip鍦板潃锛夋潵鍒ゆ柇缃戠粶鐜鍑嗗灏辩华锛屾槸鍚︾綉缁滆繛閫氭у垯鏃犳硶淇濊瘉 - -- 濡傛灉娌℃湁璁剧疆姝ゅ弬鏁帮紝榛樿涓簍rue - -- 鍦ㄦ湁ping娴嬭瘯鐜鐨勯」鐩腑锛屽缓璁笉瑕佸皢杩欎釜鍙傛暟璁剧疆涓簍rue - local_network_mode = true, -- 灞鍩熺綉妯″紡(閫夊～鍙傛暟)锛岃缃负true鏃讹紝exnetif浼氳嚜鍔ㄥ皢ping_ip璁剧疆涓虹綉鍗＄殑缃戝叧ip銆 - -- 鐢ㄦ埛涓嶉渶瑕佷紶鍏ing_ip鍙傛暟锛屽嵆浣夸紶鍏ヤ簡锛屼篃鏃犳晥銆 - -- 杩欎釜妯″紡鐨勪娇鐢ㄥ満鏅紝浠呴傜敤浜庡眬鍩熺綉鐜锛涘彲浠ヨ闂缃戞椂锛屼笉瑕佷娇鐢 - ping_ip = "112.125.89.8", -- 杩為氭ф娴婭P(閫夊～鍙傛暟),榛樿浣跨敤httpdns鑾峰彇baidu.com鐨刬p浣滀负鍒ゆ柇鏉′欢锛 - -- 娉細濡傛灉濉啓ip锛屽垯ping閫氫綔涓哄垽鏂綉缁滄槸鍚﹀彲鐢ㄧ殑鏉′欢锛 - -- 鎵浠ラ渶瑕佹牴鎹綉缁滅幆澧冨～鍐欏唴缃戞垨鑰呭缃慽p, - -- 濉啓澶栫綉ip鐨勮瘽瑕佷繚璇佸缃慽p濮嬬粓鍙敤锛 - -- 濉啓灞鍩熺綉ip鐨勮瘽瑕佺‘淇濈浉搴攊p鍥哄畾涓旇兘澶熻ping閫 - ping_time = 10000, -- 濉啓ping_ip涓旀湭ping閫氭椂鐨勬娴嬮棿闅(ms, 鍙,榛樿涓10绉) - -- 瀹氭椂ping灏嗕細褰卞搷妯″潡鍔熻楋紝浣跨敤浣庡姛鑰楁ā寮忕殑璇濆彲浠ラ傚綋寤惰繜闂撮殧鏃堕棿 - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = { spi = 1, cs = 12 }, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - static_ip = { -- 闈欐乮p閰嶇疆(閫夊～鍙傛暟)锛屼笉濉啓鍒欎娇鐢╠hcp鑾峰彇ip - ipv4 = "192.168.5.100", -- ip鍦板潃(string) - mark = "255.255.255.0", -- 瀛愮綉鎺╃爜(string) - gw = "192.168.5.1" -- 缃戝叧鍦板潃(string) - } - } - }, - { -- 鏈浣庝紭鍏堢骇缃戠粶 - LWIP_GP = true -- 鍚敤4G缃戠粶 - } -}) -鍗曠綉缁滄ā寮忥細 --- 鍗曠綉缁滄ā寮忎笅鍙娇鐢╓IFI缃戠粶 - exnetif.set_priority_order({ - { -- 鍗曠綉缁滐紝鎵撳紑wifi - WIFI = { -- WiFi閰嶇疆 - ssid = "test", -- WiFi鍚嶇О(string) - password = "HZ88888888", -- WiFi瀵嗙爜(string) - } - } - }) --- Air8000绯诲垪鍜780EXX绯诲垪鍗曠綉缁滄ā寮忎笅鍙娇鐢⊿PI浠ュお缃戠綉缁 - exnetif.set_priority_order({ - { - ETHERNET = { -- 浠ュお缃戦厤缃 - pwrpin = 140, -- 渚涚數浣胯兘寮曡剼(number) - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = {spi = 1, cs = 12}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - } - } - }) --- Air8101鍗曠綉缁滄ā寮忎笅鍙娇鐢⊿PI浠ュお缃戠綉缁 - exnetif.set_priority_order({ - { - ETHUSER1 = { -- 浠ュお缃戦厤缃 - pwrpin = 13, -- 渚涚數浣胯兘寮曡剼(number) - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = {spi = 0, cs = 15}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - static_ip = { -- 闈欐乮p閰嶇疆(閫夊～鍙傛暟)锛屼笉濉啓鍒欎娇鐢╠hcp鑾峰彇ip - ipv4 = "192.168.5.100", -- ip鍦板潃(string) - mark = "255.255.255.0", -- 瀛愮綉鎺╃爜(string) - gw = "192.168.5.1" -- 缃戝叧鍦板潃(string) - } - } - } - }) --- 鍗曠綉缁滄ā寮忎笅鍙娇鐢≧MII浠ュお缃戠綉缁 - exnetif.set_priority_order({ - { - ETHERNET = { -- 浠ュお缃戦厤缃 - pwrpin = 13, -- 渚涚數浣胯兘寮曡剼(number) - } - } - }) --- 4G鍗曠綉妯″紡涓嬶紝涓嶉渶瑕乺equire "exnetif"锛屽噺灏戜笉蹇呰鐨勫姛鑳芥ā鍧楀姞杞 -]] -function exnetif.set_priority_order(networkConfigs) - -- 鍒ゆ柇琛ㄤ腑鏁版嵁涓暟 - if #networkConfigs < 1 then - log.error("缃戠粶閰嶇疆涓虹┖") - return false - end - if #networkConfigs == 1 then - single_network_mode = true - end - - if not single_network_mode then - -- CONNECTING鐨勭綉鍗￠渶瑕佸畾鏃秔ing - sys.taskInit(ping_test_loop) - - -- 寰幆ping妫娴嬫甯哥綉鍗＄殑浠诲姟锛岄粯璁や笉鍚敤 - sys.taskInit(normal_network_test) - - sys.subscribe("PING_RESULT", ping_res) - -- 璁㈤槄缃戠粶鐘舵佸彉鍖栫殑娑堟伅 - sys.subscribe("IP_READY", ip_ready_handle) - sys.subscribe("IP_LOSE", ip_lose_handle) - - end - - local new_priority = {} - -- 鍙湁鍏抽棴鐘舵佺殑缃戝崱闇瑕佸垵濮嬪寲 - for _, config in ipairs(networkConfigs) do - if type(config.WIFI) == "table" then - if available[socket.LWIP_STA] == connection_states.DISCONNECTED then - -- 寮鍚痺ifi - local res = set_wifi_info(config.WIFI) - if res == false then - log.error("wifi杩炴帴澶辫触") - return false - end - else - log.info("wifi涓嶆槸鍏抽棴鐘舵侊紝璺宠繃鍒濆鍖") - end - table.insert(new_priority, socket.LWIP_STA) - end - if type(config.ETHUSER1) == "table" then - eth_cfg[socket.LWIP_USER1] = config.ETHUSER1 - if available[socket.LWIP_USER1] == connection_states.DISCONNECTED then - -- 寮鍚互澶綉 - local res = setup_eth_user1(config.ETHUSER1) - if res == false then - log.error("浠ュお缃戞墦寮澶辫触") - return false - end - elseif available[socket.LWIP_USER1] == connection_states.STOPED then - eth_net_restart(socket.LWIP_USER1) - else - log.info("8101spi浠ュお缃戜笉鏄叧闂姸鎬侊紝璺宠繃鍒濆鍖") - end - table.insert(new_priority, socket.LWIP_USER1) - end - if type(config.ETHERNET) == "table" then - eth_cfg[socket.LWIP_ETH] = config.ETHERNET - if available[socket.LWIP_ETH] == connection_states.DISCONNECTED then - -- 寮鍚互澶綉 - local res = setup_eth(config.ETHERNET) - if res == false then - log.error("浠ュお缃戞墦寮澶辫触") - return false - end - elseif available[socket.LWIP_ETH] == connection_states.STOPED then - eth_net_restart(socket.LWIP_ETH) - else - log.info("浠ュお缃戜笉鏄叧闂姸鎬侊紝璺宠繃鍒濆鍖") - end - table.insert(new_priority, socket.LWIP_ETH) - end - if config.LWIP_GP then - -- 閫鍑洪琛屾ā寮 - mobile.flymode(nil, false) - -- 寮鍚4G - table.insert(new_priority, socket.LWIP_GP) - available[socket.LWIP_GP] = connection_states.CONNECTING - if config.auto_socket_switch ~= nil then - auto_socket_switch = config.auto_socket_switch - -- log.info("璁剧疆鑷姩鍏抽棴闈炲綋鍓嶇綉鍗ocket杩炴帴", auto_socket_switch) - end - end - end - - -- 璁剧疆鏂颁紭鍏堢骇 - current_priority = new_priority - -- 姝ゅ鎸夌収鐢ㄦ埛鏈熸湜鐨勯厤缃紝鍏堣缃紭鍏堢骇鏈楂樼殑榛樿缃戝崱 - -- 闃叉鍑虹幇浠ヤ笅闂锛 - -- 渚嬪Air8000鍐呮牳鍥轰欢杩愯璧锋潵涔嬪悗锛岄粯璁ょ綉鍗℃槸socket.LWIP_GP锛屽鏋滅敤鎴疯皟鐢╡xnetif.set_priority_order鎺ュ彛閰嶇疆鏈楂樹紭鍏堢骇缃戝崱涓簊ocket.LWIP_ETH - -- 鍦╯ocket.LWIP_ETH缃戝崱鍑嗗灏辩华涔嬪墠锛宻ocket.LWIP_GP鍙兘宸茬粡鍑嗗灏辩华锛屾鏃堕粯璁ょ綉鍗′粛鐒舵槸socket.LWIP_GP锛 - -- 鑰岀綉缁滃簲鐢ㄥ眰锛堜緥濡俿ocket锛宮qtt绛夛級鏈夊叧鐨刣emo锛屾垜浠紪鍐欐椂锛屼笉鍏冲績鍏蜂綋缃戝崱锛岀洿鎺ヤ娇鐢ㄩ粯璁ょ綉鍗★紙杩欐牱绗﹀悎姝ｅ父閫昏緫锛夛紱 - -- 灏卞彲鑳戒細鍑虹幇鈥滅綉缁滃簲鐢ㄥ湪杩欐鏃堕棿鍐呯洿鎺ヤ娇鐢╯ocket.LWIP_GP锛岃屼笉鏄敤鎴锋湡鏈涚殑缃戝崱socket.LWIP_ETH鏉ヤ笂缃戔濈殑闂锛 - socket.dft(new_priority[1]) - apply_priority() - - return true -end - ---[[ -璁剧疆缃戠粶鐘舵佸彉鍖栧洖璋冨嚱鏁般傝Е鍙戞潯浠讹細缃戝崱鍒囨崲鎴栬呮墍鏈夌綉鍗￠兘鏂綉銆傚洖璋冨嚱鏁扮殑杈撳叆鍙傛暟: 1. 褰撴湁鍙敤缃戠粶鐨勬椂鍊欙紝杩斿洖褰撳墠浣跨敤缃戝崱銆佺綉鍗d锛2. 褰撴病鏈夊彲鐢ㄧ綉缁滅殑鏃跺欙紝杩斿洖 nil銆-1 銆 -@api exnetif.notify_status(cb_fnc) -@function 鍥炶皟鍑芥暟 -@usage - exnetif.notify_status(function(net_type,adapter) - log.info("鍙互浣跨敤浼樺厛绾ф洿楂樼殑缃戠粶:", net_type,adapter) - end) -]] -function exnetif.notify_status(cb_fnc) - log.info("notify_status", type(cb_fnc)) - if type(cb_fnc) ~= "function" then - log.error("notify_status璁剧疆閿欒锛岃浼犲叆涓涓嚱鏁") - return - end - states_cbfnc = cb_fnc -end - ---[[ -璁剧疆澶氱綉铻嶅悎妯″紡锛屼緥濡4G浣滀负鏁版嵁鍑哄彛缁橶IFI鎴栦互澶綉璁惧涓婄綉(闇瑕佸湪task涓皟鐢) -@api exnetif.setproxy(adapter, main_adapter,other_configs) -@adapter 闇瑕佷娇鐢ㄧ綉缁滅殑缃戝崱锛屼緥濡俿ocket.LWIP_ETH -@adapter 鎻愪緵缃戠粶鐨勭綉鍗★紝渚嬪socket.LWIP_GP -@table 鍏朵粬璁剧疆鍙傛暟(閫夊～鍙傛暟)锛 -@usage - 鍏稿瀷搴旂敤锛 - -- 浠ュお缃慦AN鎻愪緵缃戠粶鍏朵粬璁惧杩炴帴浠ュお缃慙AN鍙ｄ笂缃 - exnetif.setproxy(socket.LWIP_ETH, socket.LWIP_USER1, { - ethpower_en = 20,-- 浠ュお缃戞ā鍧楃殑pwrpin寮曡剼(gpio缂栧彿) - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = {spi = 0, cs = 8}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - main_adapter = { - ethpower_en = 21,-- 浠ュお缃戞ā鍧楃殑pwrpin寮曡剼(gpio缂栧彿) - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = {spi = 1, cs = 12} - } - }) then - -- wifi_sta鎻愪緵缃戠粶寮鍚痺ifi_ap鐑偣渚涜澶囦笂缃 - exnetif.setproxy(socket.LWIP_AP, socket.LWIP_STA, { - ssid = "test2", -- AP鐑偣鍚嶇О(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - password = "HZ88888888", -- AP鐑偣瀵嗙爜(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - ap_opts = { -- AP妯″紡涓嬮厤缃」(閫夊～鍙傛暟) - hidden = false, -- 鏄惁闅愯棌SSID, 榛樿false,涓嶉殣钘 - max_conn = 4 }, -- 鏈澶у鎴风鏁伴噺, 榛樿4 - channel = 6, -- AP寤虹珛鐨勯氶亾, 榛樿6 - main_adapter = { - ssid = "test", -- 鎻愪緵缃戠粶鐨勭綉鍗″紑鍚弬鏁 - password = "HZ88888888" - } - }) - -- 4G鎻愪緵缃戠粶寮鍚痺ifi_ap鐑偣渚涜澶囦笂缃,鍏朵粬璁惧杩炴帴浠ュお缃慙AN鍙ｄ笂缃 - exnetif.setproxy(socket.LWIP_AP, socket.LWIP_GP, { - ssid = "Hotspot", -- WiFi鍚嶇О(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - password = "password123", -- WiFi瀵嗙爜(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - adapter_addr = "192.168.5.1", -- adapter缃戝崱鐨刬p鍦板潃(閫夊～),闇瑕佽嚜瀹氫箟ip鍜岀綉鍏砳p鏃跺～鍐 - adapter_gw= { 192, 168, 5, 1 }, -- adapter缃戝崱鐨勭綉鍏冲湴鍧(閫夊～),闇瑕佽嚜瀹氫箟ip鍜岀綉鍏砳p鏃跺～鍐 - ap_opts={ -- AP妯″紡涓嬮厤缃」(閫夊～鍙傛暟) - hidden = false, -- 鏄惁闅愯棌SSID, 榛樿false,涓嶉殣钘 - max_conn = 4 }, -- 鏈澶у鎴风鏁伴噺, 榛樿4 - channel=6 -- AP寤虹珛鐨勯氶亾, 榛樿6 - }) - exnetif.setproxy(socket.LWIP_ETH, socket.LWIP_GP, { - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = { spi = 1, cs = 12}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - ethpower_en = 140, -- 浠ュお缃戞ā鍧楃殑pwrpin寮曡剼(gpio缂栧彿) - adapter_addr = "192.168.5.1", -- adapter缃戝崱鐨刬p鍦板潃(閫夊～),闇瑕佽嚜瀹氫箟ip鍜岀綉鍏砳p鏃跺～鍐 - adapter_gw= { 192, 168, 5, 1 }, -- adapter缃戝崱鐨勭綉鍏冲湴鍧(閫夊～),闇瑕佽嚜瀹氫箟ip鍜岀綉鍏砳p鏃跺～鍐 - }) - -- 浠ュお缃戞彁渚涚綉缁滀緵WiFi璁惧涓婄綉 - exnetif.setproxy(socket.LWIP_AP, socket.LWIP_ETH, { - ssid = "Hotspot", -- WiFi鍚嶇О(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - password = "password123", -- WiFi瀵嗙爜(string)锛岀綉鍗″寘鍚玾ifi鏃跺～鍐 - main_adapter={ - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = { spi = 1, cs = 12}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - ethpower_en = 140, -- 浠ュお缃戞ā鍧楃殑pwrpin寮曡剼(gpio缂栧彿) - } - }) - -- WIFI鎻愪緵缃戠粶渚涗互澶綉璁惧涓婄綉 - exnetif.setproxy(socket.LWIP_ETH, socket.LWIP_STA, { - tp = netdrv.CH390, -- 缃戝崱鑺墖鍨嬪彿(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - opts = { spi = 1, cs = 12}, -- 澶栨寕鏂瑰紡,闇瑕侀澶栫殑鍙傛暟(閫夊～鍙傛暟)锛屼粎spi鏂瑰紡澶栨寕浠ュお缃戞椂闇瑕佸～鍐欍 - ethpower_en = 140, -- 浠ュお缃戞ā鍧楃殑pwrpin寮曡剼(gpio缂栧彿) - main_adapter = { - ssid = "test", -- 鎻愪緵缃戠粶鐨勭綉鍗″紑鍚弬鏁 - password = "HZ88888888" - } - }) -]] -function exnetif.setproxy(adapter, main_adapter, other_configs) - if main_adapter == socket.LWIP_ETH and available[socket.LWIP_ETH] == connection_states.DISCONNECTED then - -- 鎵撳紑WAN鍔熻兘 - log.info("ch390", "鎵撳紑LDO渚涚數", other_configs.main_adapter.ethpower_en) - available[socket.LWIP_ETH] = connection_states.OPENED - -- 鎵撳紑CH390渚涚數 - if other_configs.main_adapter.ethpower_en then - gpio.setup(other_configs.main_adapter.ethpower_en, 1, gpio.PULLUP) - end - -- sys.wait(100) -- 绛夊緟浠ュお缃戞ā鍧椾笂鐢电ǔ瀹 - if other_configs.main_adapter.tp == nil then - log.info("8101浠ュお缃") - if netdrv.setup(socket.LWIP_ETH) == false then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - else - log.info("config.opts.spi", other_configs.main_adapter.opts.spi, ",config.type", - other_configs.main_adapter.tp) - -- 閰嶇疆SPI鍜屽垵濮嬪寲缃戠粶椹卞姩 - local result = spi.setup(other_configs.main_adapter.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负0锛岃〃绀烘墦寮鎴愬姛 - log.info("main", "spi open error", result) - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - -- 鍒濆鍖栨寚瀹歯etdrv璁惧, - local success = - netdrv.setup(socket.LWIP_ETH, other_configs.main_adapter.tp, other_configs.main_adapter.opts) - if not success then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - end - netdrv.dhcp(socket.LWIP_ETH, true) - local count = 1 - while 1 do - local ip = netdrv.ipv4(socket.LWIP_ETH) - if ip and ip ~= "0.0.0.0" then - break - end - if count > 600 then - log.error("浠ュお缃戣繛鎺ヨ秴鏃讹紝璇锋鏌ラ厤缃") - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - sys.wait(100) - count = count + 1 - end - elseif main_adapter == socket.LWIP_USER1 and available[socket.LWIP_USER1] == connection_states.DISCONNECTED then - log.info("鍒濆鍖栦互澶綉") - -- 鎵撳紑CH390渚涚數 - if other_configs.main_adapter.ethpower_en then - gpio.setup(other_configs.main_adapter.ethpower_en, 1, gpio.PULLUP) - end - -- sys.wait(100) -- 绛夊緟浠ュお缃戞ā鍧椾笂鐢电ǔ瀹 - log.info("config.opts.spi", other_configs.main_adapter.opts.spi, ",config.type", other_configs.main_adapter.tp) - available[socket.LWIP_USER1] = connection_states.OPENED - -- 閰嶇疆SPI鍜屽垵濮嬪寲缃戠粶椹卞姩 - local result = spi.setup(other_configs.main_adapter.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负0锛岃〃绀烘墦寮鎴愬姛 - log.info("main", "spi open error", result) - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - -- 鍒濆鍖栨寚瀹歯etdrv璁惧, - -- socket.LWIP_ETH 缃戠粶閫傞厤鍣ㄧ紪鍙 - -- netdrv.CH390澶栨寕CH390 - -- SPI ID 1, 鐗囬 GPIO12 - if netdrv.setup(socket.LWIP_USER1, other_configs.main_adapter.tp, other_configs.main_adapter.opts) == false then - log.error("浠ュお缃戝垵濮嬪寲澶辫触") - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - netdrv.dhcp(socket.LWIP_USER1, true) - log.info("浠ュお缃戝垵濮嬪寲瀹屾垚") - local count = 1 - while 1 do - local ip = netdrv.ipv4(socket.LWIP_USER1) - if ip and ip ~= "0.0.0.0" then - break - end - if count > 600 then - log.error("浠ュお缃戣繛鎺ヨ秴鏃讹紝璇锋鏌ラ厤缃") - if other_configs.main_adapter.ethpower_en then - gpio.close(other_configs.main_adapter.ethpower_en) - end - return false - end - sys.wait(100) - count = count + 1 - end - elseif main_adapter == socket.LWIP_STA and available[socket.LWIP_STA] == connection_states.DISCONNECTED then - -- 鎵撳紑STA鍔熻兘锛岃缃贩鍚堟ā寮 - wlan.init() - wlan.setMode(wlan.APSTA) - available[socket.LWIP_STA] = connection_states.OPENED - -- 灏濊瘯杩炴帴Wi-Fi锛屽苟澶勭悊鍙兘鍑虹幇鐨勯敊璇 - wlan.connect(other_configs.main_adapter.ssid, other_configs.main_adapter.password) - -- 绛夊緟鑾峰彇IP鍦板潃 - local count = 1 - while 1 do - local ip = netdrv.ipv4(socket.LWIP_STA) - if ip and ip ~= "0.0.0.0" then - log.info("WiFi STA宸茶繛鎺ワ紝IP:", ip) - break - end - if count > 600 then - log.error("WiFi STA杩炴帴瓒呮椂锛岃妫鏌ラ厤缃") - return false - end - sys.wait(100) - count = count + 1 - end - log.info("WiFi STA鍒濆鍖栧畬鎴") - end - - if adapter == socket.LWIP_ETH then - log.info("ch390", "鎵撳紑LDO渚涚數", other_configs.ethpower_en) - if other_configs.ethpower_en then - gpio.setup(other_configs.ethpower_en, 1, gpio.PULLUP) - end - -- 鎵撳紑LAN鍔熻兘 - -- 閰嶇疆 SPI 鍙傛暟锛孉ir8000 浣跨敤 SPI 鎺ュ彛涓庝互澶綉妯″潡杩涜閫氫俊銆 - if other_configs.tp then - log.info("netdrv spi鎸傝浇浠ュお缃", "鍒濆鍖朙AN鍔熻兘") - local result = spi.setup(other_configs.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负 0锛岃〃绀烘墦寮鎴愬姛 - log.error("main", "spi open error", result) - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - end - -- 鍒濆鍖栦互澶綉锛孉ir8000 鎸囧畾浣跨敤 CH390 鑺墖銆 - log.info("netdrv", "鍒濆鍖栦互澶綉", other_configs.tp, other_configs.opts) - if netdrv.setup(socket.LWIP_ETH, other_configs.tp, other_configs.opts) == false then - log.error("鍒濆鍖栦互澶綉澶辫触") - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - sys.wait(1000) -- 绛夊緟浠ュお缃戞ā鍧楀垵濮嬪寲瀹屾垚,鍘绘帀浼氬鑷翠互澶綉鍒濆鍖栧け璐 - -- 璁剧疆浠ュお缃戠殑 IP 鍦板潃銆佸瓙缃戞帺鐮併佺綉鍏冲湴鍧 - log.info("netdrv", "鑷畾涔変互澶綉IP鍦板潃", other_configs.adapter_addr, "缃戝叧鍦板潃", - other_configs.adapter_gw) - netdrv.ipv4(socket.LWIP_ETH, other_configs.adapter_addr or "192.168.5.1", "255.255.255.0", "0.0.0.0") - -- 鑾峰彇浠ュお缃戠綉缁滅姸鎬侊紝杩炴帴鍚庤繑鍥 true锛屽惁鍒欒繑鍥 false锛屽鏋滀笉瀛樺湪灏辫繑鍥 nil銆 - local count = 1 - while netdrv.ready(socket.LWIP_ETH) ~= true do - if count > 600 then - log.error("浠ュお缃戣繛鎺ヨ秴鏃讹紝璇锋鏌ラ厤缃") - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - count = count + 1 - -- log.info("netdrv", "绛夊緟浠ュお缃戝氨缁") -- 鑻ヤ互澶綉璁惧娌℃湁杩炰笂锛屽彲鎵撳紑姝ゅ娉ㄩ噴鎺掓煡銆 - sys.wait(100) - end - log.info("netdrv", "浠ュお缃戝氨缁") - -- 鍒涘缓 DHCP 鏈嶅姟鍣紝涓鸿繛鎺ュ埌浠ュお缃戠殑璁惧鍒嗛厤 IP 鍦板潃銆 - log.info("netdrv", "鍒涘缓dhcp鏈嶅姟鍣, 渚涗互澶綉浣跨敤") - if other_configs.adapter_gw then - dhcpsrv.create({ - adapter = socket.LWIP_ETH, - gw = other_configs.adapter_gw - }) - else - dhcpsrv.create({ - adapter = socket.LWIP_ETH, - gw = {192, 168, 5, 1} - }) - end - -- 鍒涘缓 DNS 浠ｇ悊鏈嶅姟锛屼娇寰椾互澶綉鎺ュ彛涓婄殑璁惧鍙互閫氳繃 4G 缃戠粶璁块棶浜掕仈缃戙 - log.info("netdrv", "鍒涘缓dns浠ｇ悊鏈嶅姟, 渚涗互澶綉浣跨敤") - elseif adapter == socket.LWIP_AP then - wlan.setMode(wlan.APSTA) - -- 鎵撳紑AP鍔熻兘锛岃缃贩鍚堟ā寮 - log.info("鎵цAP鍒涘缓鎿嶄綔", airlink.ready(), "姝ｅ父鍚?") - wlan.createAP(other_configs.ssid, other_configs.password, other_configs.adapter_addr or "192.168.4.1", - "255.255.255.0", other_configs.channel, other_configs.ap_opts) - -- 璁剧疆 AP 鐨 IP 鍦板潃銆佸瓙缃戞帺鐮併佺綉鍏冲湴鍧 - netdrv.ipv4(socket.LWIP_AP, other_configs.adapter_addr or "192.168.4.1", "255.255.255.0", "0.0.0.0") - -- 鑾峰彇 WiFi AP 缃戠粶鐘舵侊紝杩炴帴鍚庤繑鍥 true锛屽惁鍒欒繑鍥 false锛屽鏋滀笉瀛樺湪灏辫繑鍥 nil銆 - log.info("netdrv", "绛夊緟AP灏辩华") - local count = 1 - while netdrv.ready(socket.LWIP_AP) ~= true do - -- log.info("netdrv", "绛夊緟AP灏辩华") - if count > 600 then - log.error("AP鍒涘缓瓒呮椂锛岃妫鏌ラ厤缃") - return false - end - sys.wait(100) - count = count + 1 - end - -- 鍒涘缓 DHCP 鏈嶅姟鍣紝涓鸿繛鎺ュ埌 WiFi AP 鐨勮澶囧垎閰 IP 鍦板潃銆 - log.info("netdrv", "鍒涘缓dhcp鏈嶅姟鍣, 渚汚P浣跨敤") - if other_configs.adapter_gw then - dhcpsrv.create({ - adapter = socket.LWIP_AP, - gw = other_configs.adapter_gw - }) - else - dhcpsrv.create({ - adapter = socket.LWIP_AP - }) - end - elseif adapter == socket.LWIP_USER1 then - log.info("ch390", "鎵撳紑LDO渚涚數", other_configs.ethpower_en) - if other_configs.ethpower_en then - gpio.setup(other_configs.ethpower_en, 1, gpio.PULLUP) - end - -- 鎵撳紑LAN鍔熻兘 - -- 閰嶇疆 SPI 鍙傛暟锛孉ir8101 浣跨敤 SPI 鎺ュ彛涓庝互澶綉妯″潡杩涜閫氫俊銆 - log.info("netdrv spi鎸傝浇浠ュお缃", "鍒濆鍖朙AN鍔熻兘") - local result = spi.setup(other_configs.opts.spi, -- spi id - nil, 0, -- CPHA - 0, -- CPOL - 8, -- 鏁版嵁瀹藉害 - 25600000 -- ,--娉㈢壒鐜 - ) - log.info("main", "open spi", result) - if result ~= 0 then -- 杩斿洖鍊间负 0锛岃〃绀烘墦寮鎴愬姛 - log.error("main", "spi open error", result) - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - -- 鍒濆鍖栦互澶綉锛孉ir8000 鎸囧畾浣跨敤 CH390 鑺墖銆 - log.info("netdrv", "鍒濆鍖栦互澶綉", other_configs.tp, other_configs.opts) - if netdrv.setup(socket.LWIP_USER1, other_configs.tp, other_configs.opts) == false then - log.error("鍒濆鍖栦互澶綉澶辫触") - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - sys.wait(1000) -- 绛夊緟浠ュお缃戞ā鍧楀垵濮嬪寲瀹屾垚,鍘绘帀浼氬鑷翠互澶綉鍒濆鍖栧け璐 - -- 璁剧疆浠ュお缃戠殑 IP 鍦板潃銆佸瓙缃戞帺鐮併佺綉鍏冲湴鍧 - log.info("netdrv", "鑷畾涔変互澶綉IP鍦板潃", other_configs.adapter_addr, "缃戝叧鍦板潃", - other_configs.adapter_gw) - netdrv.ipv4(socket.LWIP_USER1, other_configs.adapter_addr or "192.168.5.1", "255.255.255.0", "0.0.0.0") - -- 鑾峰彇浠ュお缃戠綉缁滅姸鎬侊紝杩炴帴鍚庤繑鍥 true锛屽惁鍒欒繑鍥 false锛屽鏋滀笉瀛樺湪灏辫繑鍥 nil銆 - local count = 1 - while netdrv.ready(socket.LWIP_USER1) ~= true do - if count > 600 then - log.error("浠ュお缃戣繛鎺ヨ秴鏃讹紝璇锋鏌ラ厤缃") - if other_configs.ethpower_en then - gpio.close(other_configs.ethpower_en) - end - return false - end - count = count + 1 - -- log.info("netdrv", "绛夊緟浠ュお缃戝氨缁") -- 鑻ヤ互澶綉璁惧娌℃湁杩炰笂锛屽彲鎵撳紑姝ゅ娉ㄩ噴鎺掓煡銆 - sys.wait(100) - end - log.info("netdrv", "浠ュお缃戝氨缁") - -- 鍒涘缓 DHCP 鏈嶅姟鍣紝涓鸿繛鎺ュ埌浠ュお缃戠殑璁惧鍒嗛厤 IP 鍦板潃銆 - log.info("netdrv", "鍒涘缓dhcp鏈嶅姟鍣, 渚涗互澶綉浣跨敤") - if other_configs.adapter_gw then - dhcpsrv.create({ - adapter = socket.LWIP_USER1, - gw = other_configs.adapter_gw - }) - else - dhcpsrv.create({ - adapter = socket.LWIP_USER1, - gw = {192, 168, 5, 1} - }) - end - -- 鍒涘缓 DNS 浠ｇ悊鏈嶅姟锛屼娇寰椾互澶綉鎺ュ彛涓婄殑璁惧鍙互閫氳繃 4G 缃戠粶璁块棶浜掕仈缃戙 - log.info("netdrv", "鍒涘缓dns浠ｇ悊鏈嶅姟, 渚涗互澶綉浣跨敤") - end - - dnsproxy.setup(adapter, main_adapter) - netdrv.napt(main_adapter) - return true -end - ---[[ -鍏抽棴缃戝崱鍔熻兘銆(鍐呮牳鍥轰欢鐗堟湰鍙烽渶>=2020) -@api exnetif.close(type,adapter) -@param type boolean 鏄惁涓哄缃戣瀺鍚 -@param adapter number 闇瑕佸叧闂殑缃戝崱 -@return boolean 鎿嶄綔缁撴灉 -@usage - exnetif.close(true) --鍏抽棴澶氱綉铻嶅悎鍔熻兘 - exnetif.close(false,socket.LWIP_ETH) --鍏抽棴浼樺厛绾т腑鐨勪互澶綉缃戝崱 -]] -function exnetif.close(type, adapter) - if type == true then - -- TODO: 鐩墠dhcpsrv鎵╁睍搴擄紝dnsproxy鎵╁睍搴撳拰napt娌℃湁鍏抽棴鎺ュ彛 - else - if adapter == nil then - log.error("璇锋寚瀹氶渶瑕佸叧闂殑缃戝崱") - return false - end - -- 澶勭悊鍏抽棴鎿嶄綔锛屼互澶綉鍏抽棴spi鍜屼緵鐢典娇鑳姐俉LAN閮ㄥ垎AP鍙互鍏抽棴锛孲TA鍙互鏂紑杩炴帴銆4G鐨勮瘽灏辨槸杩涘嚭椋炶妯″紡銆傚苟璁剧疆缃戝崱涓哄叧闂姸鎬併 - available[adapter] = connection_states.DISCONNECTED - if adapter == socket.LWIP_AP then - wlan.stopAP() - elseif adapter == socket.LWIP_ETH or adapter == socket.LWIP_USER1 then - if netdrv.CTRL_UPDOWN == nil then - log.error("褰撳墠鍥轰欢涓嶆敮鎸佸叧闂帴鍙,璇蜂娇鐢ㄦ渶鏂板浐浠舵祴璇") - return false - end - if eth_cfg[adapter] and eth_cfg[adapter].pwrpin then - gpio.set(eth_cfg[adapter].pwrpin, 0) - gpio.close(eth_cfg[adapter].pwrpin) - end - -- 鍏抽棴spi - spi.close(eth_cfg[adapter].opts.spi) - netdrv.ctrl(adapter, netdrv.CTRL_UPDOWN, 0) - available[adapter] = connection_states.STOPED - elseif adapter == socket.LWIP_STA then - wlan.disconnect() - elseif adapter == socket.LWIP_GP then - mobile.flymode(nil, true) - end - log.info("exnetif", "鍏抽棴缃戝崱鍔熻兘", type_to_string(adapter)) - apply_priority() - return true - end -end - -return exnetif diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/explorer.html b/4G/tools/resource/soc_script/v2025.12.31.22/lib/explorer.html deleted file mode 100644 index e5db0dc..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/explorer.html +++ /dev/null @@ -1,591 +0,0 @@ - - - - - - LuatOS 鏂囦欢绠＄悊绯荤粺 - - - -
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LuatOS 鏂囦欢绠＄悊绯荤粺鐧诲綍

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- - - - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotecam.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotecam.lua deleted file mode 100644 index f087977..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotecam.lua +++ /dev/null @@ -1,473 +0,0 @@ ---[[ -@module exremotecam -@summary exremotecam 杩滅▼鎽勫儚澶碠SD鎺у埗鎵╁睍搴擄紝鎻愪緵鎽勫儚澶碠SD鏂囧瓧鏄剧ず璁剧疆鍜屾媿鐓у姛鑳姐 -@version 1.0 -@date 2025.12.29 -@author 鎷撴瘏鎭 -@usage -娉細鍦ㄤ娇鐢╡xremotecam 鎵╁睍搴撴椂锛岄渶瑕佺‘淇濈綉缁滆繛鎺ユ甯革紝鑳藉璁块棶鍒扮洰鏍囨憚鍍忓ご銆 - -鏈枃浠剁殑瀵瑰鎺ュ彛鏈2涓細 -1銆乪xremotecam.OSDsetup(Brand, Host, channel, text, X, Y)锛氳缃憚鍍忓ごOSD鏂囧瓧鏄剧ず --- 鍙傛暟璇存槑锛 --- Brand: 鎽勫儚澶村搧鐗岋紝褰撳墠浠呮敮鎸"Dhua"(澶у崕) --- Host: 鎽勫儚澶/NVR鐨処P鍦板潃 --- channel: 鎽勫儚澶撮氶亾鍙 --- text: OSD鏂囨湰鍐呭锛岄渶鐢ㄧ珫绾垮垎闅旓紝鏍煎紡濡"1111|2222|3333|4444" --- X: 鏄剧ず浣嶇疆鐨刋鍧愭爣 --- Y: 鏄剧ず浣嶇疆鐨刌鍧愭爣 - -2銆乪xremotecam.getphoto(Brand, Host, channel)锛氭帶鍒舵憚鍍忓ご鎷嶇収 --- 鍙傛暟璇存槑锛 --- Brand: 鎽勫儚澶村搧鐗岋紝褰撳墠浠呮敮鎸"Dhua"(澶у崕) --- Host: 鎽勫儚澶/NVR鐨処P鍦板潃 --- channel: 鎽勫儚澶撮氶亾鍙 --- 杩斿洖锛氳嫢SD鍗″彲鐢紝鍒欏浘鐗囦繚瀛樹负/sd/1.jpeg -]] - ---------------------------------鍚勫搧鐗屾憚鍍忓ごHTTP鍙傛暟閰嶇疆-------------------------------- --- 澶у崕鍙傛暟 -local DH_TextAlign = 0 -- 鏂囨湰瀵归綈鏂瑰紡锛0宸﹀榻愶紝3鍙冲榻 榛樿宸﹀榻 -local DH_channel = 0 -- 閫氶亾鍙 --- 澶у崕OSD榛樿閰嶇疆鍙傛暟 -local dh_osd_param = { - Host = "192.168.1.108", - url = "/cgi-bin/configManager.cgi?", - GetWidgest = "action=getConfig&name=VideoWidget", - SetWidgest = "action=setConfig&VideoWidget[0].FontColorType=Adapt&VideoWidget[0].CustomTitle[1].PreviewBlend=true&VideoWidget[0].CustomTitle[1].EncodeBlend=true&VideoWidget[0].CustomTitle[1].TextAlign="..DH_TextAlign.."&VideoWidget[0].CustomTitle[1].Text=", - Text = "NULL", - Postion = "&VideoWidget[0].CustomTitle[1].Rect[0]=83&VideoWidget[0].CustomTitle[1].Rect[1]=169&VideoWidget[0].CustomTitle[1].Rect[2]=2666&VideoWidget[0].CustomTitle[1].Rect[3]=607" -} --- 澶у崕鎶撳浘榛樿閰嶇疆鍙傛暟 -local DAHUA_MD5Param = { - username = "admin", - password = "Air123456", - realm = "Login to 7720fd71f7dd8d36eaabc67104aa4f38",--鍊艰鑾峰彇 - nonce = "dcd98b7102dd2f0e8b11d0f600bfb0c093", -- 绀轰緥nonce鍊 - method = "GET:", -- HTTP鏂规硶 - qop = "auth", - nc = "00000001", - cnonce = "KeA8e2Cy", - response = "NULL", - url = "/cgi-bin/snapshot.cgi?", - timerul = "/cgi-bin/global.cgi?" -} ---------------------------------鍚勫搧鐗屾憚鍍忓ごHTTP鍙傛暟閰嶇疆瀹屾瘯-------------------------------- - ---[[ -鎸夌珫绾(|)鍒嗗壊瀛楃涓诧紝鏀寔澶氱杩斿洖鏍煎紡 -@api split_string_by_pipe(input_str,return_type) -@string input_str 瑕佸垎鍓茬殑瀛楃涓诧紝鏍煎紡濡"1111|2222|3333" -@string/number return_type 杩斿洖绫诲瀷锛屽彲閫夊硷細 - "all" - 杩斿洖瀹屾暣鎷嗗垎鏁扮粍锛堥粯璁ゅ硷級 - "count" - 杩斿洖鍏冪礌鏁伴噺 - 鏁存暟 - 杩斿洖鎸囧畾绱㈠紩鐨勫厓绱狅紙绱㈠紩浠1寮濮嬶級 -@return 鏍规嵁return_type鍙傛暟涓嶅悓锛岃繑鍥炰笉鍚岀粨鏋滐細 - - "all": table - 鍖呭惈鎵鏈夊垎鍓插厓绱犵殑鏁扮粍 - - "count": number - 鍒嗗壊鍚庣殑鍏冪礌鏁伴噺 - - 鏁存暟绱㈠紩: string - 鎸囧畾绱㈠紩鐨勫厓绱狅紝绱㈠紩瓒婄晫鏃惰繑鍥為敊璇俊鎭 - - 鏃犳晥鍙傛暟: string - 閿欒鎻愮ず淇℃伅 -@usage: - -- 绀轰緥1: 瀹屾暣鏁扮粍杩斿洖 - -- 杈撳叆: "OSD琛1|OSD琛2|OSD琛3" - -- 浠ｇ爜: local result = split_string_by_pipe("OSD琛1|OSD琛2|OSD琛3") - -- 杈撳嚭: {"OSD琛1", "OSD琛2", "OSD琛3"} - - -- 绀轰緥2: 杩斿洖鍏冪礌鏁伴噺 - -- 杈撳叆: "OSD琛1|OSD琛2|OSD琛3" - -- 浠ｇ爜: local count = split_string_by_pipe("OSD琛1|OSD琛2|OSD琛3", "count") - -- 杈撳嚭: 3 - - -- 绀轰緥3: 杩斿洖鎸囧畾绱㈠紩鍏冪礌 - -- 杈撳叆: "OSD琛1|OSD琛2|OSD琛3" - -- 浠ｇ爜: local second_item = split_string_by_pipe("OSD琛1|OSD琛2|OSD琛3", 2) - -- 杈撳嚭: "OSD琛2" - - -- 绀轰緥4: 鍦∣SDsetup涓殑瀹為檯搴旂敤 - -- 浠ｇ爜: OSDsetup("Dhua", "192.168.1.108", 0, "娓╁害|婀垮害|澶╂皵|椋庡悜", 0, 2000) - -- 鍐呴儴澶勭悊: split_string_by_pipe("娓╁害|婀垮害|澶╂皵|椋庡悜") 寰楀埌 {"娓╁害", "婀垮害", "澶╂皵", "椋庡悜"} - -- 鏈缁堟晥鏋: 鍦ㄥぇ鍗庢憚鍍忓ごOSD涓婃樉绀鸿繖鍥涜鏂囧瓧 -]] -local function split_string_by_pipe(input_str, return_type) - -- 澶勭悊榛樿鍙傛暟锛堝鏋滄湭鎸囧畾 return_type锛岄粯璁よ繑鍥炲畬鏁存暟缁勶級 - return_type = return_type or "all" - -- 瀛樺偍鎷嗗垎鍚庣殑缁撴灉 - local split_result = {} - - -- 鏍稿績鎷嗗垎閫昏緫锛氶亶鍘嗗瓧绗︿覆锛屾寜 | 鍒嗗壊 - for item in string.gmatch(input_str, "[^|]+") do - table.insert(split_result, item) -- 灏嗗尮閰嶅埌鐨勫厓绱犲姞鍏ユ暟缁 - end - - -- 鏍规嵁 return_type 澶勭悊杩斿洖缁撴灉 - if return_type == "all" then - -- 杩斿洖瀹屾暣鎷嗗垎鏁扮粍 - return split_result - elseif return_type == "count" then - -- 杩斿洖鍏冪礌鏁伴噺锛#split_result 鏄 Lua 鑾峰彇鏁扮粍闀垮害鐨勬柟寮忥級 - return #split_result - elseif type(return_type) == "number" then - -- 杩斿洖鎸囧畾绱㈠紩鐨勫厓绱狅紙Lua 鏁扮粍绱㈠紩浠 1 寮濮嬶級 - if return_type >= 1 and return_type <= #split_result then - return split_result[return_type] - else - -- 澶勭悊绱㈠紩瓒婄晫 - return string.format("绱㈠紩 %d 瓒婄晫锛屽綋鍓嶅彧鏈 %d 涓厓绱狅紙绱㈠紩 1 鍒 %d锛", - return_type, #split_result, #split_result) - end - else - -- 澶勭悊鏃犳晥鐨 return_type 鍙傛暟 - return "return_type 鏃犳晥锛佸彲閫夊硷細'all'銆'count' 鎴栨暣鏁扮储寮" - end -end - ---[[ -瑙ｆ瀽骞堕獙璇丱SD鏄剧ず鍏冪礌锛岀‘淇濅笉瓒呭嚭鏈澶ф樉绀鸿鏁 -@api ElementJudg(Data, number) -@string Data 绔栫嚎鍒嗛殧鐨凮SD鏂囨湰鍐呭锛屾牸寮忓"1111|2222|3333" -@number number 鏈澶у厑璁告樉绀虹殑琛屾暟 -@return table 鍒嗗壊鍚庣殑鎵鏈塐SD鍏冪礌鏁扮粍 -@usage -local osd_elements = ElementJudg("琛1|琛2|琛3|琛4", 3) --- 杈撳嚭: "瓒呭嚭鏄剧ず鐨勮寖鍥,鍙兘鏄剧ず3琛" --- 杩斿洖: {"琛1", "琛2", "琛3", "琛4"} - -娉ㄦ剰浜嬮」: -1. 鍑芥暟浼氭墦鍗版墍鏈夎В鏋愬埌鐨勫厓绱犲強鍏剁储寮 -2. 褰撳厓绱犳暟閲忚秴杩囨渶澶ц鏁版椂锛屼細璁板綍璀﹀憡鏃ュ織 -3. 鏃犺鏄惁瓒呭嚭闄愬埗锛岄兘浼氳繑鍥炲畬鏁寸殑鍏冪礌鏁扮粍 -]] -local function ElementJudg(Data,number) - -- 浣跨敤split_string_by_pipe鍑芥暟鎸夌珫绾垮垎鍓睴SD鏁版嵁 - local all_items = split_string_by_pipe(Data) - - -- 閬嶅巻骞舵墦鍗版墍鏈夎В鏋愬埌鐨凮SD鍏冪礌鍙婂叾绱㈠紩 - for i, item in ipairs(all_items) do - log.info("鍏冪礌瑙ｆ瀽", "绱㈠紩", i, "鍊", item) - end - -- 鑾峰彇OSD鍏冪礌鐨勬绘暟 - local NUM = split_string_by_pipe(Data,"count") - - -- 妫鏌ュ厓绱犳暟閲忔槸鍚﹁秴杩囨渶澶у厑璁歌鏁 - if NUM > number then - -- 璁板綍璀﹀憡鏃ュ織锛屾彁绀鸿秴鍑烘樉绀鸿寖鍥 - log.info("瓒呭嚭鏄剧ず鐨勮寖鍥,鍙兘鏄剧ず"..number.."琛") - end - - -- 杩斿洖瀹屾暣鐨凮SD鍏冪礌鏁扮粍锛堟棤璁烘槸鍚﹁秴鍑洪檺鍒讹級 - return all_items -end - ---[[ -URL缂栫爜鍑芥暟锛岀敤浜庡皢瀛楃涓茶浆鎹负绗﹀悎URL鏍囧噯鐨勭紪鐮佹牸寮 -@api urlencode(str) -@string str 闇瑕佽繘琛孶RL缂栫爜鐨勫瓧绗︿覆 -@return string 缂栫爜鍚庣殑URL瀹夊叏瀛楃涓诧紝濡傛灉杈撳叆涓簄il鍒欒繑鍥炵┖瀛楃涓 -@usage: - local encoded = urlencode("Hello World!") - -- 杈撳嚭: "Hello+World%21" -]] -local function urlencode(str) - -- 妫鏌ヨ緭鍏ュ弬鏁版槸鍚﹀瓨鍦 - if (str) then - -- 灏嗘崲琛岀杞崲涓篊RLF鏍煎紡锛岀鍚圚TTP鏍囧噯 - str = string.gsub(str, "\n", "\r\n") - -- 瀵归潪瀛楁瘝鏁板瓧鍜岀┖鏍肩殑瀛楃杩涜%XX缂栫爜 - str = string.gsub(str, "([^%w ])", function(c) return string.format("%%%02X", string.byte(c)) end) - -- 灏嗙┖鏍艰浆鎹负+鍙凤紝绗﹀悎URL缂栫爜瑙勮寖 - str = string.gsub(str, " ", "+") - end - -- 杩斿洖缂栫爜鍚庣殑瀛楃涓叉垨绌哄瓧绗︿覆锛堝鏋滆緭鍏ヤ负nil锛 - return str or "" -end - ---[[ -璁＄畻Digest璁よ瘉涓殑HA1鍊硷紝鐢ㄤ簬缃戠粶鎽勫儚澶寸殑韬唤楠岃瘉 -@api CameraHA1(username,realm,password) -@string username 鐢ㄦ埛鍚 -@string realm 璁よ瘉鍩燂紝鐢辨湇鍔″櫒鍦401鍝嶅簲涓彁渚 -@string password 鐢ㄦ埛瀵嗙爜 -@return string 璁＄畻寰楀埌鐨凥A1鍊硷紙灏忓啓鐨凪D5鍝堝笇鍊硷級 -@usage: - local ha1 = CameraHA1("admin", "realm", "123456") - -- 杈撳嚭: md5("admin:realm:123456")鐨勫皬鍐欏搱甯屽 -]] -local function CameraHA1(username,realm,password) - -- 璁＄畻HA1鍊硷細MD5(鐢ㄦ埛鍚:璁よ瘉鍩:瀵嗙爜)锛屽苟杞崲涓哄皬鍐 - -- Digest璁よ瘉鏍囧噯瑕佹眰浣跨敤灏忓啓鐨勫搱甯屽 - local ha1 = string.lower(crypto.md5(username..":"..realm..":"..password)) - -- 杩斿洖璁＄畻寰楀埌鐨凥A1鍊 - return ha1 -end - ---[[ -澶勭悊Digest璁よ瘉锛屼粎鍦ㄦ敹鍒401鍝嶅簲鏃惰皟鐢 -@api handle_digest_auth(Host,url,params,headers,HA2) -@string Host 鎽勫儚澶寸殑IP鍦板潃 -@string url 璇锋眰鐨刄RL璺緞 -@string params 璇锋眰鍙傛暟 -@table headers 绗竴娆TTP璇锋眰杩斿洖鐨勫ご閮ㄤ俊鎭 -@string HA2 棰勫厛璁＄畻濂界殑HA2鍊 -@return boolean, table 璁よ瘉鏄惁鎴愬姛, 鏇存柊鍚庣殑璇锋眰澶撮儴 -@usage: - local code, headers, body = http.request("GET", "http://192.168.1.100/cgi-bin/test", initial_headers).wait() - if code == 401 then - local success, updated_headers = handle_digest_auth("192.168.1.100", "/cgi-bin/test", "param=value", headers, "ha2_value") - if success then - -- 浣跨敤鏇存柊鍚庣殑澶撮儴鍙戦佺浜屾璇锋眰 - end - end -]] -local function handle_digest_auth(Host, url, params, headers, HA2) - -- 灏唄eaders杞崲涓篔SON鏍煎紡浠ヤ究瑙ｆ瀽 - local str = json.encode(headers) - local Authenticate = json.decode(str) - -- 鑾峰彇WWW-Authenticate澶翠俊鎭 - local www = Authenticate["WWW-Authenticate"] - - if not www then - log.info("DigestAuth", "娌℃湁鎵惧埌WWW-Authenticate澶翠俊鎭") - return false, nil - end - - log.info("DigestAuth", "鑾峰彇鐨勯壌鏉冧俊鎭:", www) - - -- 浠庨壌鏉冧俊鎭腑鎻愬彇鎵闇鍙傛暟 - DAHUA_MD5Param.realm = string.match(www,"realm=\"(.-)\"") -- 鎻愬彇璁よ瘉鍩 - DAHUA_MD5Param.nonce = string.match(www,"nonce=\"(.-)\"") -- 鎻愬彇闅忔満鏁 - - if not DAHUA_MD5Param.realm or not DAHUA_MD5Param.nonce then - log.info("DigestAuth", "鏃犳硶鎻愬彇realm鎴杗once鍙傛暟") - return false, nil - end - - -- 璁＄畻HA1鍊硷紙鐢ㄦ埛鍚嶃佽璇佸煙銆佸瘑鐮佺殑MD5鍝堝笇锛 - local HA1 = CameraHA1(DAHUA_MD5Param.username, DAHUA_MD5Param.realm, DAHUA_MD5Param.password) - - -- 璁＄畻瀹屾暣鐨剅esponse鍊硷紙Digest璁よ瘉鐨勬牳蹇冿級 - -- response = MD5(HA1:nonce:nc:cnonce:qop:HA2) - DAHUA_MD5Param.response = string.lower(crypto.md5(HA1..":"..DAHUA_MD5Param.nonce..":"..DAHUA_MD5Param.nc..":"..DAHUA_MD5Param.cnonce..":"..DAHUA_MD5Param.qop..":"..HA2)) - - -- 鏋勫缓瀹屾暣鐨凙uthorization澶撮儴 - local authorization_header = "Digest username=\"" .. DAHUA_MD5Param.username .. "\", realm=\"" .. DAHUA_MD5Param.realm .. "\", nonce=\"" .. DAHUA_MD5Param.nonce .. "\", uri=\"" .. url..params.. "\", qop=" .. DAHUA_MD5Param.qop .. ", nc=" .. DAHUA_MD5Param.nc .. ", cnonce=\"" .. DAHUA_MD5Param.cnonce .. "\", response=\"" .. DAHUA_MD5Param.response.."\"" - - -- 鏇存柊璇锋眰澶撮儴锛屾坊鍔犺璇佷俊鎭 - local updated_headers = {['Host']=''..Host, ["Authorization"] = ''..authorization_header, ['Connection']='keep-alive'} - log.info("DigestAuth", "閴存潈淇℃伅閲嶇粍瀹屾垚") - - return true, updated_headers -end - ---[[ -璁剧疆澶у崕(Dahua)鎽勫儚澶寸殑OSD(灞忓箷鏄剧ず)妯″潡 -@api DH_set_osd_module(Host,Data,TextAlign,channel,x,y) -@string Host 鎽勫儚澶寸殑IP鍦板潃 -@string Data 瑕佹樉绀虹殑OSD鏂囨湰鍐呭 -@number TextAlign OSD鏂囨湰瀵归綈鏂瑰紡锛岄粯璁や负鍏ㄥ眬鐨凞H_TextAlign -@number channel 鎽勫儚澶撮氶亾鍙凤紝榛樿涓哄叏灞鐨凞H_channel -@number x OSD鏄剧ず鐨刋鍧愭爣锛岄粯璁や负0 -@number y OSD鏄剧ず鐨刌鍧愭爣锛岄粯璁や负0 -@return nil 鏃犺繑鍥炲硷紝鍑芥暟閫氳繃鏃ュ織杈撳嚭鎵ц缁撴灉 -@usage: - DH_set_osd_module("192.168.1.100", "娓╁害: 25鈩", 0, 1, 100, 200) - -- 鍔熻兘: 鍦↖P涓192.168.1.100鐨勬憚鍍忓ご閫氶亾1涓婏紝鍧愭爣(100,200)澶勬樉绀"娓╁害: 25鈩" -]] -local function DH_set_osd_module(Host,Data,TextAlign,channel,x,y) - -- 璁剧疆榛樿鍙傛暟鍊 - DH_TextAlign = TextAlign or DH_TextAlign -- 瀵归綈鏂瑰紡 濡傛灉娌″～鐢ㄩ粯璁ゅ煎乏瀵归綈 - channel = channel or DH_channel -- 閫氶亾鍙 濡傛灉娌″～鐢ㄩ粯璁ゅ0 - x = x or 0 -- x鍧愭爣 濡傛灉娌″～鐢ㄩ粯璁ゅ间负0 - y = y or 0 -- y鍧愭爣 濡傛灉娌″～鐢ㄩ粯璁ゅ间负0 - - -- 鏋勫缓OSD浣嶇疆鍙傛暟瀛楃涓 - dh_osd_param.Postion = "&VideoWidget["..channel.."].CustomTitle[1].Rect[0]="..x.."&VideoWidget["..channel.."].CustomTitle[1].Rect[1]="..y.."&VideoWidget["..channel.."].CustomTitle[1].Rect[2]=0".."&VideoWidget["..channel.."].CustomTitle[1].Rect[3]=0" - -- 鏋勫缓OSD璁剧疆鍙傛暟瀛楃涓 - dh_osd_param.SetWidgest = "action=setConfig&VideoWidget["..channel.."].FontColorType=Adapt&VideoWidget["..channel.."].CustomTitle[1].PreviewBlend=true&VideoWidget["..channel.."].CustomTitle[1].EncodeBlend=true&VideoWidget["..channel.."].CustomTitle[1].TextAlign="..DH_TextAlign.."&VideoWidget["..channel.."].CustomTitle[1].Text=" - - -- 瀵筄SD鏂囨湰鍐呭杩涜URL缂栫爜锛岀‘淇濈壒娈婂瓧绗︽纭紶杈 - local OsdData = urlencode(Data) - -- 鎷兼帴瀹屾暣鐨凮SD璁剧疆鍙傛暟 - local OSDTEXT = dh_osd_param.SetWidgest ..OsdData - ---log.info("鎵撳嵃鏀剧疆浣嶇疆",dh_osd_param.Postion) - - -- 璁＄畻HA2鍊硷紝鐢ㄤ簬Digest璁よ瘉 - -- HA2 = MD5(鏂规硶:URL璺緞:璇锋眰鍙傛暟) - local HA2 = string.lower(crypto.md5(DAHUA_MD5Param.method..dh_osd_param.url..OSDTEXT..dh_osd_param.Postion)) - -- 鏋勫缓HTTP璇锋眰澶撮儴 - local Camera_header = {["Accept-Encoding"]="identity",["Host"]=""..Host} - - -- 鍙戦佺涓娆TTP璇锋眰锛岃幏鍙栭壌鏉冧俊鎭 - local full_params = OSDTEXT..dh_osd_param.Postion - local full_url = "http://"..Host..dh_osd_param.url..full_params - local code, headers, body = http.request("GET", full_url, Camera_header).wait() - log.info("DHosd", "绗竴娆¤姹俬ttp锛宑ode锛", code, headers) -- 鎵撳嵃杩斿洖鐨勭姸鎬佺爜鍜屽ご閮ㄤ俊鎭 - - -- 澶勭悊HTTP璇锋眰杩斿洖缁撴灉 - if code == 401 then -- 401琛ㄧず闇瑕佽韩浠借璇 - -- 浣跨敤Digest璁よ瘉鍑芥暟澶勭悊璁よ瘉 - local success, updated_headers = handle_digest_auth(Host, dh_osd_param.url, full_params, headers, HA2) - if success then - -- 鍙戦佺浜屾HTTP璇锋眰锛岃繖娆″甫鏈夊畬鏁寸殑璁よ瘉淇℃伅 - local code, headers, body = http.request("GET", full_url, updated_headers).wait() - log.info("DHosd", "绗簩娆¤姹俬ttp锛宑ode锛", code) - else - log.info("DHosd", "Digest璁よ瘉澶辫触") - return - end - elseif code == -4 then - -- 澶勭悊閲嶇粍閿欒锛堝弬鏁伴敊璇級 - log.info("DHosd", "閲嶇粍閿欒锛岃妫鏌ュ弬鏁版槸鍚︽纭") - return -- 閫鍑哄嚱鏁帮紝鑺傜渷璧勬簮 - else - -- 澶勭悊鍏朵粬HTTP閿欒 - log.info("DHosd", "HTTP璇锋眰閿欒锛宑ode锛", code) - return -- 閫鍑哄嚱鏁帮紝鑺傜渷璧勬簮 - end -end - ---[[ -璁剧疆鎽勫儚澶碠SD(灞忓箷鏄剧ず)鏂囧瓧鍔熻兘 -@api OSDsetup(Brand,Host,channel,text,X,Y) -@string Brand 鎽勫儚澶村搧鐗岋紝褰撳墠浠呮敮鎸: "Dhua" - 澶у崕 -@string Host 鎽勫儚澶/NVR鐨処P鍦板潃 -@number channel 鎽勫儚澶撮氶亾鍙凤紙涓昏鐢ㄤ簬NVR锛 -@string text OSD鏂囨湰鍐呭锛岄渶鐢ㄧ珫绾垮垎闅旓紝鏍煎紡濡"1111|2222|3333|4444"锛屽ぇ鍗庢渶澶氭樉绀13琛 -@number X 鏄剧ず浣嶇疆鐨刋鍧愭爣 -@number Y 鏄剧ず浣嶇疆鐨刌鍧愭爣 -@return 鏃 鏃犺繑鍥炲 -@usage --- 澶у崕鎽勫儚澶碠SD娴嬭瘯 -OSDsetup("Dhua", "192.168.0.163", 0, "琛1|琛2|琛3", 0, 2000) - --- 澶氶氶亾NVR绀轰緥 -OSDsetup("Dhua", "192.168.0.200", 1, "娓╁害: 25鈩億婀垮害: 60%", 100, 50) -]] -local function OSDsetup(Brand,Host,channel,text,X,Y) - -- 鍒ゆ柇鎽勫儚澶村搧鐗 - if Brand == "Dhua" then - log.info("osdsetup","妫娴嬪埌澶у崕鎽勫儚澶达紝寮濮嬪垵濮嬪寲") - -- 瑙ｆ瀽骞堕獙璇丱SD鏂囨湰鍐呭锛屽ぇ鍗庢憚鍍忓ご鏈澶氭敮鎸13琛 - ElementJudg(text,13) - -- 璋冪敤澶у崕鎽勫儚澶碠SD璁剧疆鍑芥暟 - -- 鍙傛暟锛欼P鍦板潃銆丱SD鏂囨湰鏁扮粍銆佸榻愭柟寮忋侀氶亾鍙枫乆鍧愭爣銆乊鍧愭爣 - DH_set_osd_module(Host,text,0,channel,X,Y) - - -- 浠ヤ笅鍝佺墝鍨嬪彿鏆備笉鏀寔锛屼唬鐮佸凡娉ㄩ噴 - -- elseif Brand == "Hikvision" then - -- log.info("osdsetup","妫娴嬪埌娴峰悍鎽勫儚澶达紝寮濮嬪垵濮嬪寲") - -- local all_items = ElementJudg(Text,4) - -- HKOSDBdoyGetFun(Host,channel,all_items[1],all_items[2],all_items[3],all_items[4],X,Y) - -- elseif Brand == "Uniview" then - -- log.info("osdsetup","妫娴嬪埌瀹囪鎽勫儚澶达紝寮濮嬪垵濮嬪寲") - -- local all_items = ElementJudg(Text,6) - -- EZ_OSDSETFun(Host,channel,all_items[1],all_items[2],all_items[3],all_items[4],all_items[5],all_items[6],X,Y) - -- elseif Brand == "TianDiWeiye" then - -- log.info("osdsetup","妫娴嬪埌澶╁湴浼熶笟鎽勫儚澶达紝寮濮嬪垵濮嬪寲") - -- local all_items = ElementJudg(Text,6) - -- -- TDOSDModify(Host,t) - else - -- 澶勭悊涓嶆敮鎸佺殑鍝佺墝 - log.info("osdsetup","鍨嬪彿濉啓閿欒鎴栨殏涓嶆敮鎸侊紒锛侊紒") - end -end - ---[[ -澶у崕鎽勫儚澶存媿鐓у姛鑳斤紝鑾峰彇鎸囧畾閫氶亾鐨勫揩鐓у浘鐗 -@api DHPicture(Host,channel) -@string Host 鎽勫儚澶/NVR鐨処P鍦板潃 -@number channel 鎽勫儚澶撮氶亾鍙 -@return 鏃 鏃犺繑鍥炲硷紝鑻D鍗″彲鐢ㄥ垯鍥剧墖淇濆瓨涓/sd/1.jpeg -@usage --- 鑾峰彇澶у崕鎽勫儚澶撮氶亾0鐨勫揩鐓у浘鐗 -DHPicture("192.168.1.108", 0) - --- 鑾峰彇澶у崕NVR閫氶亾1鐨勫揩鐓у浘鐗 -DHPicture("192.168.0.200", 1) -]] -local function DHPicture(Host,channel) - log.info("DHPicture","寮濮嬫墽琛") - - -- 鏋勫缓鎷嶇収璇锋眰鍙傛暟锛氶氶亾鍙峰拰鍥剧墖绫诲瀷(0琛ㄧず蹇収) - local resultStr = "channel="..channel.."&type=0" - - -- 璁＄畻HA2鍊硷細瀵笻TTP鏂规硶銆乁RL璺緞鍜岃姹傚弬鏁拌繘琛孧D5鍔犲瘑 - local HA2 = string.lower(crypto.md5(DAHUA_MD5Param.method..DAHUA_MD5Param.url..resultStr)) - - -- 鍑嗗鍩虹HTTP璇锋眰澶撮儴 - local Camera_header = {["Accept-Encoding"]="identity",["Host"]=""..Host} - - -- 鍙戦佺涓娆TTP璇锋眰锛屼富瑕佺洰鐨勬槸鑾峰彇Digest璁よ瘉淇℃伅 - local full_url = "http://"..Host..DAHUA_MD5Param.url..resultStr - local code, headers, body = http.request("GET", full_url, Camera_header).wait() - log.info("DHPicture","绗竴娆¤姹俬ttp锛宑ode锛",code,headers) - - -- 鑾峰彇鍒伴壌鏉冧俊鎭 - if code ==401 then - -- 浣跨敤缁熶竴鐨凞igest璁よ瘉鍑芥暟澶勭悊璁よ瘉 - local success, updated_headers = handle_digest_auth(Host, DAHUA_MD5Param.url, resultStr, headers, HA2) - if success then - Camera_header = updated_headers - log.info("DHPicture","閴存潈淇℃伅閲嶇粍瀹屾垚") - else - log.info("DHPicture", "Digest璁よ瘉澶辫触") - return - end - end - - -- 妫鏌D鍗＄姸鎬 - local can_save_to_sd = false - local data, err = fatfs.getfree("/sd") - if data then - can_save_to_sd = true - log.info("DHPicture", "SD鍗″彲鐢ㄧ┖闂翠俊鎭:", json.encode(data)) - else - log.info("DHPicture", "鏃犳硶鑾峰彇SD鍗＄┖闂翠俊鎭:", err) - end - - -- 鏍规嵁SD鍗＄姸鎬佸彂閫佽姹 - local code, headers, body - if can_save_to_sd then - -- 鍙戦佺浜屾璇锋眰锛堝甫鏈夊畬鏁寸殑璁よ瘉淇℃伅锛夛紝鑾峰彇鍥剧墖骞朵繚瀛樺埌/sd/1.jpeg - code, headers, body = http.request("GET", full_url, Camera_header, nil, {dst = "/sd/1.jpeg"}).wait() - else - -- 鍙戦佺浜屾璇锋眰锛堝甫鏈夊畬鏁寸殑璁よ瘉淇℃伅锛夛紝涓嶄繚瀛樺浘鐗 - code, headers, body = http.request("GET", full_url, Camera_header).wait() - log.info("DHPicture", "娌℃湁妫娴嬪埌SD鍗★紝鏃犳硶淇濆瓨鍥剧墖鍒癝D鍗′腑锛岃纭SD鍗＄姸鎬佸悗閲嶈瘯") - end - - log.info("DHPicture","绗簩娆¤姹俬ttp锛宑ode锛", code, body) - if code == 200 then - log.info("DHPicture","鎷嶇収瀹屾垚") - end -end - ---[[ -澶氬搧鐗屾憚鍍忓ご鎷嶇収閫氱敤鎺ュ彛锛屾牴鎹搧鐗岃皟鐢ㄥ搴斿巶鍟嗙殑鎷嶇収鍔熻兘 -@api getphoto(Brand,Host,channel) -@string Brand 鎽勫儚澶村搧鐗岋紝褰撳墠浠呮敮鎸: "Dhua" - 澶у崕 -@string Host 鎽勫儚澶/NVR鐨処P鍦板潃 -@number channel 鎽勫儚澶撮氶亾鍙 -@return 鏃 鏃犺繑鍥炲硷紝鑻D鍗″彲鐢ㄥ垯鍥剧墖淇濆瓨涓/sd/1.jpeg -@usage --- 鑾峰彇澶у崕鎽勫儚澶撮氶亾0鐨勫揩鐓у浘鐗 -getphoto("Dhua", "192.168.1.108", 1) - --- 鑾峰彇澶у崕NVR閫氶亾1鐨勫揩鐓у浘鐗 -getphoto("Dhua", "192.168.0.200", 1) -]] -local function getphoto(Brand,Host,channel) - -- 鍒ゆ柇鎽勫儚澶村搧鐗 - if Brand == "Dhua" then - log.info("getphoto","妫娴嬪埌澶у崕鎽勫儚澶达紝寮濮嬪垵濮嬪寲") - DHPicture(Host,channel) - else - -- 澶勭悊涓嶆敮鎸佺殑鍝佺墝 - log.info("getphoto","鍨嬪彿濉啓閿欒鎴栨殏涓嶆敮鎸侊紒锛侊紒") - return - end -end - -return { - OSDsetup = OSDsetup, - getphoto = getphoto -} \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotefile.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotefile.lua deleted file mode 100644 index a8503f9..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exremotefile.lua +++ /dev/null @@ -1,1604 +0,0 @@ ---[[ -@module exremotefile -@summary exremotefile 杩滅▼鏂囦欢绠＄悊绯荤粺鎵╁睍搴擄紝鎻愪緵AP鐑偣鍒涘缓銆丼D鍗℃寕杞姐丼ERVER鏂囦欢绠＄悊鏈嶅姟鍣ㄧ瓑鍔熻兘锛屾敮鎸佹枃浠舵祻瑙堛佷笂浼犮佷笅杞藉拰鍒犻櫎鎿嶄綔銆 -@version 1.0 -@date 2025.09.10 -@author 鎷撴瘏鎭 -@usage -娉細鍦ㄤ娇鐢╡xremotefile 鎵╁睍搴撴椂锛岄渶瑕佸皢鍚屼竴鐩綍涓嬬殑explorer.html鏂囦欢鐑у綍杩涙ā缁勪腑锛屽惁鍒欐棤娉曞惎鍔╯erver鏈嶅姟鍣ㄦ潵鍒涘缓鏂囦欢绠＄悊绯荤粺!!! - -娉細濡傛灉浣跨敤Air8000寮鍙戞澘娴嬭瘯锛屽繀椤昏嚜瀹氫箟閰嶇疆is_8000_development_board = true -鍥犱负Air8000寮鍙戞澘涓奣F鍜屼互澶綉鏄悓涓涓猄PI锛屼娇鐢ㄥ紑鍙戞澘鏃跺繀椤昏灏嗕互澶綉鎷夐珮 -濡傛灉浣跨敤鍏朵粬纭欢锛岄渶瑕佹牴鎹‖浠跺師鐞嗗浘鏉ュ喅瀹氭槸鍚﹂渶瑕佹鎿嶄綔 - -鏈枃浠剁殑瀵瑰鎺ュ彛鏈2涓細 -1銆乪xremotefile.open(ap_opts, sdcard_opts, server_opts)锛氬惎鍔ㄨ繙绋嬫枃浠剁鐞嗙郴缁燂紝鍙厤缃瓵P鍙傛暟銆丼D鍗″弬鏁板拰鏈嶅姟鍣ㄥ弬鏁 --- 鍚姩鍚庤繛鎺P鐑偣锛岀洿鎺ヤ娇鐢╨uatools鏃ュ織涓粯璁ょ殑鍦板潃"http://192.168.4.1:80/explorer.html"鏉ヨ闂枃浠剁鐞嗘湇鍔″櫒銆 --- 濡傛灉浣跨敤鑷畾涔夐厤缃紝鍒欓渶瑕佹牴鎹厤缃腑鐨剆erver_addr鍜宻erver_port鍙傛暟鏉ヨ闂枃浠剁鐞嗘湇鍔″櫒銆 - -2銆乪xremotefile.close()锛氬叧闂繙绋嬫枃浠剁鐞嗙郴缁燂紝鍋滄AP鐑偣銆佸嵏杞絊D鍗″拰鍏抽棴HTTP鏈嶅姟鍣 -]] - --- 瀵煎叆蹇呰鐨勬ā鍧 -dnsproxy = require("dnsproxy") -dhcpsrv = require("dhcpsrv") - -local exremotefile = {} -local is_initialized = false -local user_server_opts = {} -local user_sdcard_opts = {} -local ETH3V3_EN = 140 -- Air8000寮鍙戞澘浠ュお缃戜緵鐢 -local SPI_ETH_CS = 12 -- Air8000寮鍙戞澘浠ュお缃戠墖閫 - --- AP榛樿閰嶇疆 -local default_ap_opts = { - ap_ssid = "LuatOS_FileHub", - ap_pwd = "12345678" -} - --- SPI榛樿閰嶇疆 -local default_sdcard_opts = { - spi_id = 1, - spi_cs = 20, - is_8000_development_board = false, - is_sdio = false -} - --- server榛樿閰嶇疆 -local default_server_opts = { - user_name = "admin", - user_pwd = "123456", - server_addr = "192.168.4.1", - server_port = 80 -} - --- 淇濆瓨妯″潡寮曠敤锛岀敤浜庡悗缁叧闂搷浣 -local modules = { - ap = nil, - http_server = nil -} - --- 鍒涘缓AP鐑偣 -local function create_ap(ap_opts, server_opts) - log.info("WIFI", "鍒涘缓AP鐑偣: " .. ap_opts.ap_ssid) - log.info("WIFI", "AP瀵嗙爜: " .. ap_opts.ap_pwd) - - -- 鍒濆鍖朩iFi - wlan.init() - sys.wait(100) - - -- 鍒涘缓AP - wlan.createAP(ap_opts.ap_ssid, ap_opts.ap_pwd) - - -- 閰嶇疆IP - netdrv.ipv4(socket.LWIP_AP, server_opts.server_addr, "255.255.255.0", "0.0.0.0") - - -- 绛夊緟缃戠粶鍑嗗灏辩华 - while netdrv.ready(socket.LWIP_AP) ~= true do - sys.wait(100) - end - - -- 璁剧疆DNS浠ｇ悊 - dnsproxy.setup(socket.LWIP_AP, socket.LWIP_GP) - - -- 鍒涘缓DHCP鏈嶅姟鍣 - dhcpsrv.create({adapter=socket.LWIP_AP}) - - -- 鍙戝竷AP鍒涘缓瀹屾垚浜嬩欢 - sys.publish("AP_CREATE_OK") - - log.info("WIFI", "AP鐑偣鍒涘缓鎴愬姛") -end - --- 鍒濆鍖朣D鍗 -local function init_sdcard(sdcard_opts) - log.info("SDCARD", "寮濮嬪垵濮嬪寲SD鍗") - - -- 鍙岄噸楠岃瘉锛岀‘璁や娇鐢ㄧ殑鏄疉ir8000寮鍙戞澘 - if sdcard_opts.is_8000_development_board == true then - if sdcard_opts.spi_cs == 20 then - if sdcard_opts.spi_id == 1 then - -- 娉細Air8000寮鍙戞澘涓奣F鍜屼互澶綉鏄悓涓涓猄PI锛屼娇鐢ㄥ紑鍙戞澘鏃跺繀椤昏灏嗕互澶綉鎷夐珮 - -- 濡傛灉浣跨敤鍏朵粬纭欢锛岄渶瑕佹牴鎹‖浠跺師鐞嗗浘鏉ュ喅瀹氭槸鍚﹂渶瑕佹鎿嶄綔 - -- 閰嶇疆浠ュお缃戜緵鐢靛紩鑴氾紝璁剧疆涓鸿緭鍑烘ā寮忥紝骞跺惎鐢ㄤ笂鎷夌數闃 - gpio.setup(ETH3V3_EN, 1, gpio.PULLUP) - -- 閰嶇疆浠ュお缃戠墖閫夊紩鑴氾紝璁剧疆涓鸿緭鍑烘ā寮忥紝骞跺惎鐢ㄤ笂鎷夌數闃 - gpio.setup(SPI_ETH_CS, 1, gpio.PULLUP) - log.info("sdcard_init", "浣跨敤鐨勬槸寮鍙戞澘锛屽紑濮嬪皢浠ュお缃戞媺楂") - end - end - end - - local mount_result = nil - - if not sdcard_opts.is_sdio then - -- 閰嶇疆SPI锛岃缃畇pi_id锛屾尝鐗圭巼涓400000锛岀敤浜嶴D鍗″垵濮嬪寲 - local result = spi.setup(sdcard_opts.spi_id, nil, 0, 0, 8, 400 * 1000) - log.info("sdcard_init", "open spi", result) - -- 閰嶇疆SD鍗＄墖閫夊紩鑴氾紝璁剧疆涓鸿緭鍑烘ā寮忥紝骞跺惎鐢ㄤ笂鎷夌數闃 - gpio.setup(sdcard_opts.spi_cs, 1, gpio.PULLUP) - -- 鎸傝浇SD鍗″埌鏂囦欢绯荤粺锛屾寚瀹氭寕杞界偣涓"/sd" - mount_result = fatfs.mount(fatfs.SPI, "/sd", sdcard_opts.spi_id, sdcard_opts.spi_cs, 24 * 1000 * 1000) - else - -- gpio13涓8101TF鍗＄殑渚涚數鎺у埗寮曡剼锛屽湪鎸傝浇鍓嶉渶瑕佽缃负楂樼數骞筹紝涓嶈兘鐪佺暐 - gpio.setup(13, 1) - mount_result = fatfs.mount(fatfs.SDIO, "/sd", 24 * 1000 * 1000) - end - log.info("SDCARD", "鎸傝浇SD鍗＄粨鏋:", mount_result) - - -- 鑾峰彇SD鍗＄殑鍙敤绌洪棿淇℃伅 - local data, err = fatfs.getfree("/sd") - if data then - log.info("SDCARD", "SD鍗″彲鐢ㄧ┖闂翠俊鎭:", json.encode(data)) - else - log.info("SDCARD", "鑾峰彇SD鍗＄┖闂村け璐:", err) - end - - return mount_result -end - --- 浼氳瘽绠＄悊 -local authenticated_sessions = {} - --- 鑾峰彇鏂囦欢淇℃伅 -local function get_file_info(path) - log.info("FILE_INFO", "鑾峰彇鏂囦欢淇℃伅: " .. path) - - -- 鑾峰彇鏂囦欢鍚 - local filename = path:match("([^/]+)$") or "" - - -- 鑾峰彇澶у皬 - local direct_size = io.fileSize(path) - if direct_size and direct_size > 0 then - log.info("FILE_INFO", "鑾峰彇鏂囦欢澶у皬鎴愬姛: " .. direct_size .. " 瀛楄妭") - return { - name = filename, - size = direct_size, - isDirectory = false, - path = path - } - end - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦紝閬垮厤瀵规枃浠惰繘琛岄敊璇殑鐩綍鍒ゆ柇 - if not io.exists(path) then - log.info("FILE_INFO", "鏂囦欢涓嶅瓨鍦: " .. path) - return { - name = filename, - size = 0, - isDirectory = false, - path = path - } - end - - -- 灏濊瘯鍒ゆ柇鏄惁涓虹洰褰 - local ret, data = io.lsdir(path, 1, 0) - if ret and data and type(data) == "table" and #data > 0 then - log.info("FILE_INFO", "璺緞鏄竴涓洰褰: " .. path) - return { - name = filename, - size = 0, - isDirectory = true, - path = path - } - end - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if not io.exists(path) then - log.info("FILE_INFO", "鏂囦欢涓嶅瓨鍦: " .. path) - return { - name = filename, - size = 0, - isDirectory = false, - path = path - } - end - - -- 灏濊瘯鎵撳紑鏂囦欢鑾峰彇澶у皬 - local file = io.open(path, "rb") - if file then - -- 灏濊瘯鑾峰彇鏂囦欢澶у皬 - local file_size = io.fileSize(path) - - -- 濡傛灉杩斿洖0鎴杗il锛屽皾璇曢氳繃璇诲彇鏂囦欢鍐呭鑾峰彇澶у皬 - if not file_size or file_size == 0 then - log.info("FILE_INFO", "鑾峰彇鏂囦欢澶у皬锛屽皾璇曡鍙栨枃浠跺唴瀹") - local content = file:read("*a") - file_size = #content - log.info("FILE_INFO", "浣跨敤鏂囦欢鍐呭闀垮害鑾峰彇澶у皬: " .. file_size .. " 瀛楄妭") - else - log.info("FILE_INFO", "鑾峰彇鏂囦欢澶у皬鎴愬姛: " .. file_size .. " 瀛楄妭") - end - - file:close() - log.info("FILE_INFO", "鎴愬姛鑾峰彇鏂囦欢淇℃伅: " .. filename .. ", 澶у皬: " .. file_size .. " 瀛楄妭") - return { - name = filename, - size = file_size, - isDirectory = false, - path = path - } - end -end - --- 瀹氫箟绯荤粺鏂囦欢鐨勮鍒欙紙绯荤粺鏂囦欢涓嶆樉绀猴級 -local function is_system_file(filename) - -- 绯荤粺鏂囦欢鎵╁睍鍚嶅垪琛 - local system_extensions = {".luac", ".html", ".md"} - -- 鐗规畩绯荤粺鏂囦欢鍚 - local special_system_files = {".airm2m_all_crc#.bin"} - - -- 妫鏌ユ枃浠跺悕鏄惁鍖归厤鐗规畩绯荤粺鏂囦欢鍚 - for _, sys_file in ipairs(special_system_files) do - if filename == sys_file then - return true - end - end - - -- 妫鏌ユ枃浠舵墿灞曞悕鏄惁涓虹郴缁熸枃浠舵墿灞曞悕 - for _, ext in ipairs(system_extensions) do - if filename:sub(-#ext) == ext then - return true - end - end - - return false -end - --- 鎵弿鐩綍 -local function scan_with_lsdir(path, files) - log.info("LIST_DIR", "寮濮嬫壂鎻忕洰褰") - -- 纭繚璺緞鏍煎紡姝ｇ‘锛屽鐞嗗灞傜洰褰曞拰缂栫爜闂 - local scan_path = path - log.info("LIST_DIR", "鍘熷璺緞: " .. scan_path) - - -- 瑙勮寖鍖栬矾寰勶紝澶勭悊URL缂栫爜娈嬬暀闂 - scan_path = scan_path:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - log.info("LIST_DIR", "瑙ｇ爜鍚庤矾寰: " .. scan_path) - - -- 绉婚櫎澶氫綑鐨勬枩鏉 - scan_path = scan_path:gsub("//+", "/") - log.info("LIST_DIR", "鍘婚噸鏂滄潬鍚庤矾寰: " .. scan_path) - - -- 瑙勮寖鍖栬矾寰勶紝绉婚櫎鍙兘鐨勫熬閮ㄦ枩鏉 - scan_path = scan_path:gsub("/*$", "") - log.info("LIST_DIR", "绉婚櫎灏鹃儴鏂滄潬鍚庤矾寰: " .. scan_path) - - -- 纭繚璺緞浠/寮澶 - if not scan_path:match("^/") then - scan_path = "/" .. scan_path - end - log.info("LIST_DIR", "纭繚浠/寮澶村悗璺緞: " .. scan_path) - - -- 纭繚璺緞浠/缁撳熬 - scan_path = scan_path .. (scan_path == "" and "" or "/") - - log.info("LIST_DIR", "寮濮嬫壂鎻忚矾寰: " .. scan_path) - - -- 鎵弿鐩綍锛屾渶澶氬垪鍑50涓枃浠讹紝浠庣0涓紑濮 - local ret, data = io.lsdir(scan_path, 50, 0) - - if ret then - log.info("LIST_DIR", "鎴愬姛鑾峰彇鐩綍鍐呭锛屾枃浠舵暟閲: " .. #data) - log.info("LIST_DIR", "鐩綍鍐呭: " .. json.encode(data)) - - -- 閬嶅巻鐩綍鍐呭 - for i = 1, #data do - local entry = data[i] - local is_dir = (entry.type ~= 0) - local entry_type = is_dir and "鐩綍" or "鏂囦欢" - log.info("LIST_DIR", "鎵惧埌鏉＄洰: " .. entry.name .. ", 绫诲瀷: " .. entry_type) - - local full_path = scan_path .. entry.name - - -- 澶勭悊鐩綍鍜屾枃浠剁殑涓嶅悓閫昏緫 - if is_dir then - -- 瀵逛簬鐩綍锛岀洿鎺ユ瀯閫犱俊鎭 - local dir_info = { - name = entry.name, - size = 0, - isDirectory = true, - path = full_path - } - -- 杩囨护sd鍗＄郴缁熸枃浠跺す鐩綍 - if entry.name ~= "System Volume Information" then - table.insert(files, dir_info) - log.info("LIST_DIR", "娣诲姞鐩綍: " .. entry.name .. ", 璺緞: " .. full_path) - end - else - -- 妫鏌ユ槸鍚︿负鐢ㄦ埛鏂囦欢 - local is_user_file = not is_system_file(entry.name) - - -- 鍙湁鐢ㄦ埛鏂囦欢鎵嶄細琚坊鍔犲埌鍒楄〃涓 - if is_user_file then - -- 瀵逛簬鏂囦欢锛岃皟鐢╣et_file_info鑾峰彇璇︾粏淇℃伅 - local file_info = get_file_info(full_path) - if file_info and file_info.size ~= nil then - file_info.isDirectory = false - table.insert(files, file_info) - log.info("LIST_DIR", "娣诲姞鏂囦欢: " .. entry.name .. ", 澶у皬: " .. file_info.size .. - " 瀛楄妭, 璺緞: " .. file_info.path) - else - -- 濡傛灉get_file_info澶辫触锛屼娇鐢ㄩ粯璁ゅ - local default_info = { - name = entry.name, - size = entry.size or 0, - isDirectory = false, - path = full_path - } - table.insert(files, default_info) - log.info("LIST_DIR", "娣诲姞鏂囦欢(榛樿淇℃伅): " .. entry.name .. ", 澶у皬: " .. - (entry.size or 0) .. " 瀛楄妭") - end - end - end - end - return true - else - log.info("LIST_DIR", "鎵弿澶辫触: " .. (data or "鏈煡閿欒")) - end - return false -end - --- 鍒楀嚭鐩綍 -local function list_directory(path) - -- 鍒濆鍖栨枃浠跺垪琛 - local files = {} - - log.info("LIST_DIR", "寮濮嬪鐞嗙洰褰曡姹: " .. path) - - -- 鎵弿鏂规硶琛 - local scan_success = scan_with_lsdir(path, files) - - -- 璁板綍鎵弿缁撴灉 - if scan_success then - log.info("LIST_DIR", "鎵弿鏂规硶鎴愬姛") - else - log.info("LIST_DIR", "鎵弿鏂规硶澶辫触") - end - - log.info("LIST_DIR", "鐩綍鎵弿瀹屾垚锛屾诲叡鎵惧埌鏂囦欢鏁伴噺: " .. #files) - return files -end - --- 浼氳瘽楠岃瘉 -local function validate_session(headers) - -- 鑾峰彇Cookie涓殑session_id - local cookies = headers['Cookie'] or '' - local session_id = nil - if cookies then - session_id = cookies:match('session_id=([^;]+)') - end - - -- 妫鏌ヤ細璇滻D鏄惁宸茶璇 - if session_id and authenticated_sessions[session_id] then - return true - else - return false - end -end - --- 鐢熸垚浼氳瘽ID -local function generate_session_id() - local chars = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" - local id = "" - for i = 1, 32 do - local rand = math.random(1, #chars) - id = id .. chars:sub(rand, rand) - end - return id -end - --- 妫鏌ュ瓧绗︿覆鏄惁浠ユ寚瀹氬墠缂寮澶 -local function string_starts_with(str, prefix) - return string.sub(str, 1, string.len(prefix)) == prefix -end - --- 瑙ｆ瀽鏂囦欢涓婁紶鏁版嵁 -local function parse_multipart_data(body, boundary) - log.info("UPLOAD", "寮濮嬭В鏋愭暟鎹紝body澶у皬: " .. #body .. " 瀛楄妭") - - local result = {} - local parts = {} - local boundary_pattern = "--" .. boundary - - -- 寮濮嬭В鏋 - if #body > 0 then - log.info("UPLOAD", "浣跨敤绠鍖栬В鏋愭柟娉曞鐞嗕笂浼犳暟鎹") - - -- 棣栧厛灏濊瘯浠巄ody涓彁鍙栨枃浠跺悕 - local filename_match = string.match(body, 'filename="([^"]+)"') - if filename_match then - result.filename = filename_match - log.info("UPLOAD", "鎴愬姛鎻愬彇鏂囦欢鍚: " .. filename_match) - end - - -- 鏌ユ壘鍐呭寮濮嬩綅缃 - local content_start = string.find(body, "\r\n\r\n") - if content_start then - -- 鎻愬彇鍐呭閮ㄥ垎 - local content = string.sub(body, content_start + 4) - - -- 绉婚櫎鏈熬鍙兘鐨刡oundary - local end_pos = string.find(content, "\r\n--" .. boundary, 1, true) - if end_pos then - content = string.sub(content, 1, end_pos - 1) - end - - -- 娓呯悊鍐呭 - content = string.gsub(content, "\r\n$", "") - content = string.gsub(content, "\n$", "") - - if #content > 0 then - result.content = content - result.size = #content - log.info("UPLOAD", "瑙ｆ瀽鎴愬姛锛岃幏鍙栧唴瀹瑰ぇ灏: " .. #content .. " 瀛楄妭") - end - end - end - - log.info("UPLOAD", "multipart鏁版嵁瑙ｆ瀽瀹屾垚锛" .. (result.content and (result.filename and "鎴愬姛鑾峰彇鏂囦欢: " .. result.filename or "鎴愬姛鑾峰彇鏂囦欢鍐呭") or "鏈壘鍒版湁鏁堟枃浠跺唴瀹")) - return result -end - --- 鍐欏叆鏂囦欢锛屾敮鎸佸垎鍖呭啓鍏 -local function write_file_with_chunks(file_path, content) - -- 妫鏌ヨ矾寰勫墠缂 - local storage_type = "鍐呭瓨" -- 榛樿鍐呭瓨瀛樺偍 - if string.sub(file_path, 1, 4) == "/sd/" then - storage_type = "sdcard" - -- 鑾峰彇SD鍗″彲鐢ㄧ┖闂 - local data, err = fatfs.getfree("/sd") - if not data then - log.error("UPLOAD", "SD鍗℃湭鎸傝浇鎴栦笉鍙敤") - return false, "SD鍗℃湭鎸傝浇鎴栦笉鍙敤" - end - - -- 璁剧疆涓簊d鍗″彲鐢ㄧ┖闂插唴瀛樼┖闂 - local free_space = tonumber(data.free_kb) - - -- 濡傛灉鏃犳硶鑾峰彇鏈夋晥绌洪棿鍊硷紝璁剧疆榛樿鍊间互璺宠繃绌洪棿妫鏌 - if not free_space or free_space <= 0 then - log.warn("UPLOAD", "鏃犳硶鑾峰彇鍑嗙‘鐨凷D鍗″彲鐢ㄧ┖闂达紝璺宠繃绌洪棿妫鏌") - free_space = #content + 1 - end - - -- 纭繚free_space鏄暟瀛楃被鍨 - if type(free_space) ~= "number" then - log.error("UPLOAD", "鏃犳硶鑾峰彇鏈夋晥鐨凷D鍗＄┖闂村ぇ灏") - -- 杩欓噷鍙互閫夋嫨璺宠繃绌洪棿妫鏌ョ户缁墽琛岋紝鎴栬呰繑鍥為敊璇 - -- 涓轰簡閬垮厤宕╂簝锛屾垜浠烦杩囩┖闂存鏌 - else - -- 妫鏌D鍗＄┖闂存槸鍚﹁冻澶 - if free_space < #content then - log.error("UPLOAD", "SD鍗＄┖闂翠笉瓒筹紝闇瑕 " .. #content .. " 瀛楄妭锛屽彲鐢 " .. free_space .. " 瀛楄妭") - return false, "SD鍗＄┖闂翠笉瓒" - end - end - end - - log.info("UPLOAD", "寮濮嬪啓鍏ユ枃浠跺埌" .. storage_type .. ": " .. file_path) - - -- 淇濈暀瀹屾暣璺緞锛屼笉瑕佸彧鎻愬彇鏂囦欢鍚 - -- 鍙湁褰撹矾寰勪笉鏄粷瀵硅矾寰勶紙涓嶄互/寮澶达級鏃舵墠闇瑕佺壒娈婂鐞 - if not file_path:match("^/") then - -- 濡傛灉涓嶆槸缁濆璺緞锛屽彲鑳介渶瑕佽幏鍙栨枃浠跺悕锛屼絾淇濈暀鐩稿璺緞 - local filename = file_path:match("[^/]+$") - -- 淇濇寔鍘熷璺緞涓嶅彉锛岀‘淇濆啓鍏ュ埌姝ｇ‘浣嶇疆 - log.info("UPLOAD", "浣跨敤鐩稿璺緞: " .. file_path) - end - - -- 鏍规嵁鐩爣瀛樺偍绫诲瀷璋冩暣鍒嗗潡澶у皬 - local chunk_size - if storage_type == "sdcard" then - -- SD鍗″啓鍏ヤ娇鐢ㄨ緝澶у垎鍧椾互鎻愰珮鎬ц兘 - chunk_size = 32 * 1024 -- 32KB - else - -- 鍐呭瓨鍐欏叆浣跨敤杈冨皬鍒嗗潡浠ラ伩鍏嶅唴瀛樺嘲鍊 - chunk_size = 16 * 1024 -- 16KB - end - - -- 瀹夊叏鍦版墦寮鏂囦欢杩涜鍐欏叆锛屼娇鐢ㄦ洿鍋ュ．鐨勯敊璇鐞 - local file, err - - -- 灏濊瘯涓嶅悓鐨勬枃浠舵墦寮妯″紡 - local modes = {"wb", "w"} - - for _, mode in ipairs(modes) do - -- 鍏堝皾璇曞垹闄ゅ彲鑳藉瓨鍦ㄧ殑鍚屽悕鏂囦欢锛堝拷鐣ラ敊璇級 - pcall(os.remove, file_path) - - file, err = io.open(file_path, mode) - if file then - log.info("UPLOAD", "鎴愬姛浠ユā寮" .. mode .. "鎵撳紑鏂囦欢: " .. file_path) - break - else - log.warn("UPLOAD", "鏃犳硶浠ユā寮" .. mode .. "鎵撳紑鏂囦欢: " .. file_path .. ", 閿欒: " .. (err or "鏈煡閿欒")) - end - end - - if not file then - -- 灏濊瘯鎻愬彇鍘熷鏂囦欢鍚嶏紝纭繚浣跨敤鍘熷鍚嶇О - local original_filename = file_path:match("([^/]+)$") or "upload_file" - - -- 瀵逛簬鍐呭瓨瀛樺偍 - if storage_type == "鍐呭瓨" then - log.info("UPLOAD", "灏濊瘯浣跨敤鏍圭洰褰曡矾寰: /" .. original_filename) - file, err = io.open("/" .. original_filename, "w") - if file then - file_path = "/" .. original_filename - else - -- 濡傛灉web杩樻槸涓嶈兘鏄剧ず锛屼娇鐢ㄩ殢鏈轰复鏃舵枃浠跺悕 - -- 鍏堜娇鐢ㄥ師濮嬫枃浠跺悕锛屼笉娣诲姞鏃堕棿鎴冲拰闅忔満鏁 - local simple_filename = original_filename - log.info("UPLOAD", "灏濊瘯浣跨敤鍘熷鏂囦欢鍚: " .. simple_filename) - file, err = io.open(simple_filename, "w") - if not file then - -- 娣诲姞鏃堕棿鎴虫柟寮忔樉绀烘枃浠跺悕锛屾帓闄ゅ洜涓烘枃浠跺悕瀵艰嚧鐨勬棤娉曟樉绀 - simple_filename = original_filename .. "_" .. os.time() - log.info("UPLOAD", "灏濊瘯浣跨敤甯︽椂闂存埑鐨勬枃浠跺悕: " .. simple_filename) - file, err = io.open(simple_filename, "w") - file_path = simple_filename - else - file_path = simple_filename - end - end - else - -- SD鍗″瓨鍌ㄦ椂鐨勫鐞 - log.info("UPLOAD", "灏濊瘯浣跨敤鏂囦欢鍚: " .. original_filename) - file, err = io.open(original_filename, "w") - file_path = original_filename - end - end - - if not file then - log.error("UPLOAD", "鏈缁堟棤娉曞垱寤烘枃浠: " .. file_path .. ", 閿欒: " .. (err or "鏈煡閿欒")) - return false, "鏃犳硶鍒涘缓鏂囦欢: " .. (err or "鏈煡閿欒") - end - - -- 浣跨敤鍒嗗潡鍐欏叆 - local total_size = #content - local pos = 1 - local chunks_written = 0 - - -- 浼樺寲鏂囦欢鍐欏叆杩囩▼ - while pos <= total_size do - local chunk_end = math.min(pos + chunk_size - 1, total_size) - local chunk = string.sub(content, pos, chunk_end) - local chunk_len = #chunk - - local success, write_err = file:write(chunk) - if not success then - file:close() - log.error("UPLOAD", "鍐欏叆鏂囦欢澶辫触(鍧" .. chunks_written .. "): " .. file_path .. ", 閿欒: " .. (write_err or "鏈煡閿欒")) - return false, "鍐欏叆鏂囦欢澶辫触: " .. (write_err or "鏈煡閿欒") - end - - -- 鍦⊿D鍗″啓鍏ユ椂锛屾瘡鍐欏叆涓涓潡灏卞埛鏂扮紦鍐插尯锛岄伩鍏嶆暟鎹涪澶 - if storage_type == "sdcard" then - file:flush() - end - - chunks_written = chunks_written + 1 - pos = pos + chunk_size - end - - -- 纭繚鎵鏈夋暟鎹兘鍐欏叆瀛樺偍浠嬭川 - file:flush() - file:close() - - -- 楠岃瘉鍐欏叆鏄惁鎴愬姛锛堝皾璇曡鍙栨枃浠跺ぇ灏忥級 - local file_info = get_file_info(file_path) - if file_info and file_info.size == total_size then - log.info("UPLOAD", "鏂囦欢鍐欏叆鎴愬姛(" .. chunks_written .. "鍧): " .. file_path .. ", 澶у皬: " .. total_size .. " 瀛楄妭, 瀛樺偍绫诲瀷: " .. storage_type) - return true, nil, file_path -- 杩斿洖瀹為檯浣跨敤鐨勬枃浠惰矾寰 - else - log.warn("UPLOAD", "鏂囦欢鍐欏叆鍙兘涓嶅畬鏁: " .. file_path .. ", 鏈熸湜澶у皬: " .. total_size .. ", 瀹為檯澶у皬: " .. (file_info and file_info.size or "鏈煡")) - return true, "鏂囦欢鍐欏叆鍙兘涓嶅畬鏁", file_path -- 杩斿洖瀹為檯浣跨敤鐨勬枃浠惰矾寰 - end -end - --- server璇锋眰澶勭悊 -local function handle_http_request(fd, method, uri, headers, body) - log.info("HTTP", method, uri) - - -- 鐧诲綍 - if uri == "/login" and method == "POST" then - local data = json.decode(body or "{}") - log.info("LOGIN", "鏀跺埌鐧诲綍璇锋眰锛岀敤鎴峰悕: " .. (data and data.username or "绌")) - if data and data.username == user_server_opts.user_name and data.password == user_server_opts.user_pwd then - local session_id = generate_session_id() - authenticated_sessions[session_id] = os.time() - - -- 璁＄畻宸茶璇佷細璇濇暟閲 - local session_count = 0 - for _ in pairs(authenticated_sessions) do - session_count = session_count + 1 - end - - log.info("LOGIN", "鐧诲綍鎴愬姛锛佺敤鎴峰悕: " .. data.username) - log.info("LOGIN", "鐢熸垚SessionID: " .. session_id) - log.info("LOGIN", "褰撳墠宸茶璇佷細璇濇暟閲: " .. session_count) - - -- 璁剧疆Cookie - return 200, { - ["Content-Type"] = "application/json", - ["Set-Cookie"] = "session_id=" .. session_id .. "; Path=/; Max-Age=3600" - }, json.encode({ - success = true, - session_id = session_id - }) - else - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒" - }) - end - end - - -- 鐧诲嚭 - if uri == "/logout" and method == "POST" then - local cookie = headers["Cookie"] or "" - for session_id in cookie:gmatch("session_id=([^;]+)") do - authenticated_sessions[session_id] = nil - end - return 200, { - ["Set-Cookie"] = "session_id=; Path=/; Expires=Thu, 01 Jan 1970 00:00:00 GMT" - }, "" - end - - -- 妫鏌ヨ璇 - if uri == "/check-auth" then - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - authenticated = validate_session(headers) - }) - end - - -- 鎵弿鏂囦欢鎺ュ彛 - if string_starts_with(uri, "/scan-files") then - log.info("SCAN", "鏀跺埌鏂囦欢鎵弿璇锋眰") - - -- 妫鏌ヤ紶缁熻璇佹柟寮 - local is_authenticated = validate_session(headers) - - -- 濡傛灉浼犵粺璁よ瘉澶辫触锛屽皾璇曚粠URL鍙傛暟涓幏鍙栫敤鎴峰悕鍜屽瘑鐮 - if not is_authenticated then - local url_username = uri:match("username=([^&]+)") - local url_password = uri:match("password=([^&]+)") - if url_username and url_password then - url_username = url_username:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - url_password = url_password:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if url_username == user_server_opts.user_name and url_password == user_server_opts.user_pwd then - log.info("AUTH", "鎵弿璇锋眰閫氳繃URL鍙傛暟璁よ瘉鎴愬姛") - is_authenticated = true - else - log.info("AUTH", "鎵弿璇锋眰URL鍙傛暟璁よ瘉澶辫触: 鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒") - end - else - log.info("AUTH", "鎵弿璇锋眰URL涓病鏈夋壘鍒扮敤鎴峰悕鍜屽瘑鐮佸弬鏁") - end - end - - -- 濡傛灉璁よ瘉浠嶇劧澶辫触锛岃繑鍥炴湭鎺堟潈璁块棶 - if not is_authenticated then - log.info("HTTP", "鏈巿鏉冭闂枃浠舵壂鎻忓姛鑳") - return 401, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏈巿鏉冭闂" - }) - end - - -- 鎵ц鏂囦欢鎵弿 - log.info("SCAN", "寮濮嬫壂鎻忓唴閮ㄦ枃浠剁郴缁熷拰TF鍗...") - - -- 瀹氫箟瑕佹壂鎻忕殑鎸傝浇鐐癸紝鍖呮嫭SD鍗℃寕杞界偣 - local mount_points = {"/", "/luadb/", "/sd/"} - local found_files = {} - - -- 瀵规瘡涓寕杞界偣鎵ц鎵弿 - for _, mount_point in ipairs(mount_points) do - log.info("SCAN", "寮濮嬫壂鎻忔寕杞界偣: " .. mount_point) - - -- 濡傛灉璺緞涓嶄互/缁撳熬锛屾坊鍔/纭繚璺緞鏍煎紡姝ｇ‘ - local scan_path = mount_point - if not scan_path:match("/$") then - scan_path = scan_path .. (scan_path == "" and "" or "/") - end - - -- 鎵弿鐩綍 - log.info("SCAN", "寮濮嬫壂鎻忚矾寰: " .. scan_path) - -- 灏濊瘯鍒楀嚭鐩綍鍐呭锛屾渶澶氬垪鍑50涓枃浠 - local ret, data = io.lsdir(scan_path, 50, 0) - - if ret then - log.info("SCAN", "鎴愬姛鑾峰彇鐩綍鍐呭锛屾枃浠舵暟閲: " .. #data) - log.info("SCAN", "鐩綍鍐呭: " .. json.encode(data)) - - -- 閬嶅巻鐩綍鍐呭 - for i = 1, #data do - local entry = data[i] - local full_path = scan_path .. entry.name - - -- 濡傛灉鏄枃浠讹紙type == 0锛夛紝娣诲姞鍒版枃浠跺垪琛 - if entry.type == 0 then - local info = get_file_info(full_path) - if info then - table.insert(found_files, { - name = entry.name, - size = info.size, - path = full_path - }) - log.info("SCAN", "鎵惧埌鏂囦欢: " .. entry.name .. ", 澶у皬: " .. info.size .. - " 瀛楄妭, 璺緞: " .. full_path) - else - -- 濡傛灉get_file_info澶辫触锛屼娇鐢╥o.lsdir杩斿洖鐨勫ぇ灏 - table.insert(found_files, { - name = entry.name, - size = entry.size or 0, - path = full_path - }) - log.info("SCAN", "鎵惧埌鏂囦欢: " .. entry.name .. ", 澶у皬: " .. (entry.size or 0) .. - " 瀛楄妭, 璺緞: " .. full_path) - end - else - -- 濡傛灉鏄洰褰曪紝璁板綍浣嗕笉娣诲姞鍒版枃浠跺垪琛 - log.info("SCAN", "鎵惧埌鐩綍: " .. entry.name .. ", 璺緞: " .. full_path) - end - end - else - log.info("SCAN", "鎵弿澶辫触: " .. (data or "鏈煡閿欒")) - end - - local list_files = list_directory(mount_point) - if list_files then - for _, file in ipairs(list_files) do - -- 鍙褰曢潪鐩綍鏂囦欢 - if not file.isDirectory then - -- 纭繚鏂囦欢璺緞姝ｇ‘ - local file_path = file.path or (mount_point .. (mount_point == "/" and "" or "/") .. file.name) - - -- 妫鏌ユ枃浠舵槸鍚﹀凡娣诲姞 - local is_exists = false - for _, f in ipairs(found_files) do - if f.name == file.name and f.path == file_path then - is_exists = true - break - end - end - if not is_exists then - table.insert(found_files, { - name = file.name, - size = file.size, - path = file_path - }) - log.info("SCAN", - "浠巐ist_directory娣诲姞鏂囦欢: " .. file.name .. ", 澶у皬: " .. file.size .. - " 瀛楄妭, 璺緞: " .. file_path) - end - end - end - end - - log.info("SCAN", "鎸傝浇鐐规壂鎻忓畬鎴: " .. mount_point .. ", 鎵惧埌鏂囦欢: " .. #found_files .. " 涓") - end - - -- 鎵弿瀹屾垚鍚庯紝鎵撳嵃璇︾粏鐨勬枃浠跺垪琛 - log.info("SCAN", "鏂囦欢鎵弿瀹屾垚锛屾诲叡鎵惧埌鏂囦欢鏁伴噺: " .. #found_files) - for i, file in ipairs(found_files) do - log.info("SCAN", "鏂囦欢[" .. i .. "]: " .. file.name .. ", 澶у皬: " .. file.size .. " 瀛楄妭, 璺緞: " .. - file.path) - end - - -- 杩斿洖鎵弿缁撴灉 - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = true, - foundFiles = #found_files, - files = found_files, - message = "鏂囦欢鎵弿瀹屾垚" - }) - end - - -- 鏂囦欢鍒楄〃 - if string_starts_with(uri, "/list") then - - -- 妫鏌ヤ紶缁熻璇佹柟寮 - local is_authenticated = validate_session(headers) - - -- 濡傛灉浼犵粺璁よ瘉澶辫触锛屽皾璇曚粠URL鍙傛暟涓幏鍙栫敤鎴峰悕鍜屽瘑鐮 - if not is_authenticated then - local url_username = uri:match("username=([^&]+)") - local url_password = uri:match("password=([^&]+)") - if url_username and url_password then - url_username = url_username:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - url_password = url_password:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if url_username == user_server_opts.user_name and url_password == user_server_opts.user_pwd then - log.info("AUTH", "閫氳繃URL鍙傛暟璁よ瘉鎴愬姛") - is_authenticated = true - else - log.info("AUTH", "URL鍙傛暟璁よ瘉澶辫触: 鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒") - end - else - log.info("AUTH", "URL涓病鏈夋壘鍒扮敤鎴峰悕鍜屽瘑鐮佸弬鏁") - end - end - - -- 濡傛灉璁よ瘉浠嶇劧澶辫触锛岃繑鍥炴湭鎺堟潈璁块棶 - if not is_authenticated then - log.info("HTTP", "鏈巿鏉冭闂枃浠跺垪琛") - return 401, { - ["Content-Type"] = "text/plain" - }, "鏈巿鏉冭闂" - end - -- 鑻ユ病鏈夎幏鍙栧埌URI涓璸ath鍙傛暟锛屽垯榛樿浣跨敤/luadb鐩綍锛岄槻姝㈡枃浠舵棤娉曚笂浼 - local path = uri:match("path=([^&]+)") or "/luadb" - -- 纭繚璺緞涓嶄細琚敊璇瘑鍒负绌烘垨鏍硅矾寰 - if path == "" or path == "/" then - path = "/luadb" - log.info("HTTP", "淇榛樿璺緞涓: " .. path) - end - log.info("HTTP", "璇锋眰鐨勬枃浠跺垪琛ㄨ矾寰: " .. path) - -- 灏%xx鏍煎紡鐨勫崄鍏繘鍒惰浆涔夊簭鍒楄繕鍘熶负瀵瑰簲瀛楃 - path = path:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - log.info("HTTP", "瑙ｇ爜鍚庣殑鏂囦欢鍒楄〃璺緞: " .. path) - - -- 璋冪敤list_directory鍑芥暟鎵弿鐩綍 - log.info("HTTP", "寮濮嬫壂鎻忕洰褰") - local files = list_directory(path) - - -- 璇锋眰鏍硅矾寰勬椂锛岃繃婊ょ郴缁熸枃浠 - if path == "/" then - log.info("HTTP", "杩囨护鏍硅矾寰勪腑鐨勭郴缁熸枃浠") - local filtered_files = {} - for _, file in ipairs(files) do - -- 杩囨护.nvm绯荤粺鏂囦欢鍜岀郴缁熼厤缃枃浠 - if not file.isDirectory and not file.name:match("%.nvm$") and file.name ~= "plat_config" then - table.insert(filtered_files, file) - end - end - files = filtered_files - -- 濡傛灉鏄/luadb璺緞璇锋眰锛屾坊鍔犳牴鐩綍涓嬬殑涓婁紶鏂囦欢锛屽苟纭繚杩囨护绯荤粺鏂囦欢 - elseif path == "/luadb" then - log.info("HTTP", "鎵弿鏍圭洰褰曚笅鐨勪笂浼犳枃浠") - local root_files = list_directory("/") - for _, file in ipairs(root_files) do - -- 鍙坊鍔犳枃浠讹紝涓嶆坊鍔犵洰褰曪紝杩囨护绯荤粺鏂囦欢 - if not file.isDirectory and not file.name:match("%.nvm$") and file.name ~= "plat_config" then - table.insert(files, file) - log.info("HTTP", "娣诲姞涓婁紶鏂囦欢: " .. file.name .. ", 澶у皬: " .. file.size) - end - end - end - - -- 璁板綍浼犵粰椤甸潰鐨勬枃浠舵暟鎹 - log.info("HTTP", "鍑嗗杩斿洖鏂囦欢鍒楄〃锛屾暟閲: " .. #files) - for i, file in ipairs(files) do - log.info("HTTP", "鏂囦欢[" .. i .. "]: " .. file.name .. ", 澶у皬: " .. file.size) - end - - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = true, - files = files - }) - end - - -- 鏂囦欢涓嬭浇 - if string_starts_with(uri, "/download") then - log.info("DOWNLOAD", "鏀跺埌涓嬭浇璇锋眰: " .. uri) - - -- 妫鏌ヤ紶缁熻璇佹柟寮 - local is_authenticated = validate_session(headers) - - -- 濡傛灉浼犵粺璁よ瘉澶辫触锛屽皾璇曚粠URL鍙傛暟涓幏鍙栫敤鎴峰悕鍜屽瘑鐮 - if not is_authenticated then - local url_username = uri:match("username=([^&]+)") - local url_password = uri:match("password=([^&]+)") - if url_username and url_password then - url_username = url_username:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - url_password = url_password:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if url_username == user_server_opts.user_name and url_password == user_server_opts.user_pwd then - log.info("AUTH", "涓嬭浇璇锋眰閫氳繃URL鍙傛暟璁よ瘉鎴愬姛") - is_authenticated = true - else - log.info("AUTH", "涓嬭浇璇锋眰URL鍙傛暟璁よ瘉澶辫触: 鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒") - end - else - log.info("AUTH", "涓嬭浇璇锋眰URL涓病鏈夋壘鍒扮敤鎴峰悕鍜屽瘑鐮佸弬鏁") - end - end - - -- 濡傛灉璁よ瘉浠嶇劧澶辫触锛岃繑鍥炴湭鎺堟潈璁块棶 - if not is_authenticated then - log.info("HTTP", "鏈巿鏉冭闂枃浠朵笅杞") - return 401, { - ["Content-Type"] = "text/plain" - }, "鏈巿鏉冭闂" - end - - -- 鑾峰彇璇锋眰鐨勬枃浠惰矾寰 - local path = uri:match("path=([^&]+)") or "" - path = path:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if not io.exists(path) then - log.info("DOWNLOAD", "鏂囦欢涓嶅瓨鍦: " .. path) - return 404, { - ["Content-Type"] = "text/plain" - }, "鏂囦欢涓嶅瓨鍦" - end - - -- 灏濊瘯鎵撳紑鏂囦欢浠ョ‘璁ゅ彲璁块棶鎬у苟鑾峰彇鏂囦欢淇℃伅 - local file = io.open(path, "rb") - if not file then - log.info("DOWNLOAD", "鏂囦欢鏃犳硶鎵撳紑: " .. path) - return 404, { - ["Content-Type"] = "text/plain" - }, "鏂囦欢鏃犳硶鎵撳紑" - end - - -- 鑾峰彇鏂囦欢鍚 - local filename = path:match("([^/]+)$") - - -- 鑾峰彇鏂囦欢澶у皬 - local file_size = io.fileSize(path) - - -- 鍏抽棴鏂囦欢 - file:close() - - log.info("DOWNLOAD", "纭鏂囦欢淇℃伅: " .. filename .. ", 澶у皬: " .. file_size .. " 瀛楄妭") - - -- 浣跨敤httpsrv涓嬭浇锛岀洿鎺ラ噸瀹氬悜URL - -- 濡傞渶瑕佷笅杞芥枃浠剁郴缁熶腑123.mp3锛岀洿鎺ラ噸瀹氬悜鍒癠RL:http://192.168.4.1/123.mp3 - -- 濡傛灉璺緞浠/sd/寮澶达紝鍒欎繚鐣欏畬鏁寸殑sd璺緞 - local redirect_url = "/" .. filename - if string_starts_with(path, "/sd/") then - -- 淇濈暀瀹屾暣鐨剆d璺緞锛屼互渚跨洿鎺ヨ闂畇d鍗℃枃浠跺強鍏跺瓙鐩綍 - redirect_url = path - end - - log.info("DOWNLOAD", "寮濮嬩笅杞芥枃浠讹細" .. redirect_url) - - -- 杩斿洖HTTP 302閲嶅畾鍚戝搷搴 - return 302, { - ["Location"] = redirect_url, - ["Content-Type"] = "text/html" - }, [[ - - 閲嶅畾鍚戜笅杞 - -

姝ｅ湪閲嶅畾鍚戝埌鏂囦欢涓嬭浇...

- - - ]] - end - - -- 鏂囦欢涓婁紶 - if string_starts_with(uri, "/upload") and method == "POST" then - log.info("UPLOAD", "鏀跺埌鏂囦欢涓婁紶璇锋眰") - - -- 妫鏌ヤ紶缁熻璇佹柟寮 - local is_authenticated = validate_session(headers) - - -- 濡傛灉浼犵粺璁よ瘉澶辫触锛屽皾璇曚粠URL鍙傛暟涓幏鍙栫敤鎴峰悕鍜屽瘑鐮 - if not is_authenticated then - local url_username = uri:match("username=([^&]+)") - local url_password = uri:match("password=([^&]+)") - if url_username and url_password then - url_username = url_username:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - url_password = url_password:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if url_username == user_server_opts.user_name and url_password == user_server_opts.user_pwd then - log.info("AUTH", "涓婁紶璇锋眰閫氳繃URL鍙傛暟璁よ瘉鎴愬姛") - is_authenticated = true - else - log.info("AUTH", "涓婁紶璇锋眰URL鍙傛暟璁よ瘉澶辫触: 鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒") - end - else - log.info("AUTH", "涓婁紶璇锋眰URL涓病鏈夋壘鍒扮敤鎴峰悕鍜屽瘑鐮佸弬鏁") - end - end - - -- 濡傛灉璁よ瘉浠嶇劧澶辫触锛岃繑鍥炴湭鎺堟潈璁块棶 - if not is_authenticated then - log.info("HTTP", "鏈巿鏉冭闂枃浠朵笂浼") - return 401, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏈巿鏉冭闂" - }) - end - - -- 鑾峰彇涓婁紶鍙傛暟 - local target_path = uri:match("path=([^&]+)") or "/luadb" - local filename = uri:match("filename=([^&]+)") - - -- URL瑙ｇ爜 - target_path = target_path:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - - if filename then - filename = filename:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - else - log.error("UPLOAD", "鏈彁渚涙枃浠跺悕") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏈彁渚涙枃浠跺悕" - }) - end - - -- 楠岃瘉鐩爣璺緞 - if target_path ~= "/luadb" and target_path ~= "/sd" then - log.error("UPLOAD", "鏃犳晥鐨勪笂浼犵洰鏍囪矾寰: " .. target_path) - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏃犳晥鐨勪笂浼犵洰鏍囪矾寰" - }) - end - - -- 妫鏌D鍗℃槸鍚︽寕杞斤紙濡傛灉鐩爣鏄疭D鍗★級 - if target_path == "/sd" then - local free_space = fatfs.getfree("/sd") - if not free_space then - log.error("UPLOAD", "SD鍗℃湭鎸傝浇") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "SD鍗℃湭鎸傝浇" - }) - end - end - - -- 鏋勫缓瀹屾暣鐨勬枃浠惰矾寰 - local file_path = target_path .. "/" .. filename - - -- 杈撳嚭headers鐨勫畬鏁村唴瀹癸紝甯姪璇婃柇闂 - if headers then - log.info("UPLOAD", "headers琛ㄧ被鍨: " .. type(headers)) - local headers_str = "{ " - for k, v in pairs(headers) do - headers_str = headers_str .. k .. "=" .. tostring(v) .. ", " - end - headers_str = headers_str .. "}" - log.info("UPLOAD", "鎵鏈夎姹傚ご: " .. headers_str) - else - log.warn("UPLOAD", "headers鍙傛暟涓簄il") - end - - -- 鑾峰彇Content-Type澶撮儴锛屽皾璇曞绉嶅彲鑳界殑閿悕 - local content_type = "" - if headers then - -- 灏濊瘯鏍囧噯鐨凜ontent-Type閿 - content_type = headers["Content-Type"] or headers["content-type"] or headers["Content-type"] or "" - log.info("UPLOAD", "鎺ユ敹鍒扮殑Content-Type: '" .. content_type .. "'") - end - - -- 閲囩敤姝ｅ垯琛ㄨ揪寮忓鐞嗗悇绉嶆牸寮忕殑boundary鍙傛暟 - -- 灏濊瘯澶氱鏍煎紡鐨勫尮閰 - local boundary = nil - if content_type and content_type ~= "" then - boundary = - -- 鍖归厤涓嶅甫寮曞彿鐨刡oundary: boundary=abc123 - content_type:match("boundary=([^; ]+)") or - -- 鍖归厤甯﹀紩鍙风殑boundary: boundary="abc123" - content_type:match('boundary="([^"]+)"') or - -- 鍖归厤甯﹀崟寮曞彿鐨刡oundary: boundary='abc123' - content_type:match("boundary='([^']+)'") - end - - if not boundary then - log.warn("UPLOAD", "Content-Type涓湭鎵惧埌boundary锛屽皾璇曚粠璇锋眰浣撲腑鎻愬彇") - - -- 鐩存帴浠庤姹備綋涓彁鍙朾oundary - if body and body ~= "" then - -- 灏濊瘯鍖归厤璇锋眰浣撲腑鐨勭涓涓猙oundary琛岋紝閫氬父鏍煎紡涓 "--xxxxxxx" - local body_boundary = body:match("^%-%-(.+)") - if body_boundary then - boundary = body_boundary - log.info("UPLOAD", "鎴愬姛浠庤姹備綋涓彁鍙朾oundary: ") - else - -- 灏濊瘯鍖归厤鍙兘鐨凜ontent-Type琛 - local body_content_type = body:match("Content%-Type: multipart/form%-data; boundary=(.+)") - if body_content_type then - boundary = body_content_type - log.info("UPLOAD", "鎴愬姛浠庤姹備綋涓殑Content-Type鎻愬彇boundary: ") - else - log.error("UPLOAD", "鏃犳硶瑙ｆ瀽multipart杈圭晫锛孋ontent-Type涓虹┖锛岃姹備綋涓篃鏈壘鍒") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏃犳硶瑙ｆ瀽涓婁紶鏁版嵁鏍煎紡" - }) - end - end - else - log.error("UPLOAD", "璇锋眰浣撲负绌猴紝鏃犳硶鎻愬彇boundary") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "璇锋眰浣撲负绌猴紝鏃犳硶瑙ｆ瀽涓婁紶鏁版嵁" - }) - end - end - - log.info("UPLOAD", "鎴愬姛瑙ｆ瀽boundary: " .. boundary) - - log.info("UPLOAD", "涓婁紶鍙傛暟: 鐩爣璺緞=" .. target_path .. ", 鏂囦欢鍚=" .. filename .. ", 瀹屾暣璺緞=" .. file_path) - - -- 瑙ｆ瀽multipart鏁版嵁 - local upload_data = parse_multipart_data(body or "", boundary) - - if not upload_data.content then - log.error("UPLOAD", "鏃犳硶瑙ｆ瀽涓婁紶鏂囦欢鏁版嵁") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏃犳硶瑙ｆ瀽涓婁紶鏂囦欢鏁版嵁" - }) - end - - -- 妫鏌ユ枃浠跺ぇ灏忥紙200KB闄愬埗锛 - if #upload_data.content > 200 * 1024 then - log.error("UPLOAD", "鏂囦欢澶у皬瓒呰繃闄愬埗: " .. #upload_data.content .. " 瀛楄妭") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏂囦欢澶у皬瓒呰繃200KB闄愬埗" - }) - end - - -- 妫鏌d瀹归噺鍜屽唴瀛樺閲 - local available_space - if target_path == "/luadb" then - -- 妫鏌ョ郴缁熷唴瀛樺閲 - local total_mem, used_mem, max_used_mem = rtos.meminfo("sys") - if total_mem and used_mem then - local free_mem = total_mem - used_mem - log.info("UPLOAD", "绯荤粺鍐呭瓨淇℃伅 - 鎬诲唴瀛:", total_mem, "宸茬敤:", used_mem, "鍙敤:", free_mem) - -- 璁剧疆鍙敤绌洪棽鍐呭瓨绌洪棿 - available_space = free_mem - else - log.info("UPLOAD", "鑾峰彇绯荤粺鍐呭瓨淇℃伅澶辫触锛屾棤娉曡繘琛屼笂浼") - return 200, {["Content-Type"] = "application/json"}, - json.encode({ - success = false, - message = "鑾峰彇绯荤粺鍐呭瓨澶辫触锛屾棤娉曡繘琛屼笂浼" - }) - end - elseif target_path == "/sd" then - -- 鑾峰彇SD鍗″彲鐢ㄧ┖闂 - local data, err = fatfs.getfree("/sd") - if data then - log.info("UPLOAD", "SD鍗″彲鐢ㄧ┖闂翠俊鎭:", json.encode(data)) - -- 璁剧疆涓簊d鍗″彲鐢ㄧ┖闂插唴瀛樼┖闂 - available_space = tonumber(data.free_kb) - else - log.info("UPLOAD", "鑾峰彇SD鍗＄┖闂村け璐:", err) - available_space = 1024 * 1024 -- 榛樿1MB - end - end - - if available_space and available_space < #upload_data.content * 2 then -- 棰勭暀瓒冲鐨勭┖闂 - log.error("UPLOAD", "瀛樺偍绌洪棿涓嶈冻: 闇瑕 " .. #upload_data.content * 2 .. " 瀛楄妭, 鍙敤 " .. available_space .. " 瀛楄妭") - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "瀛樺偍绌洪棿涓嶈冻锛岄渶瑕佽嚦灏 " .. (#upload_data.content * 2) .. " 瀛楄妭" - }) - end - - -- 鍐欏叆鏂囦欢锛屼繚瀛樺師濮嬭姹傝矾寰 - local original_requested_path = file_path - local success, err, actual_path = write_file_with_chunks(file_path, upload_data.content) - - if success then - -- 鏃ュ織璁板綍 - log.info("UPLOAD", "鏂囦欢涓婁紶鎴愬姛: " .. filename .. ", 澶у皬: " .. #upload_data.content .. " 瀛楄妭, 瀹為檯淇濆瓨璺緞: " .. actual_path) - -- 涓婁紶鎴愬姛鍚庡啀娆℃敹闆嗗瀮鍦 - collectgarbage() - - -- 鐢熸垚鍝嶅簲淇℃伅 - local message = "鏂囦欢涓婁紶鎴愬姛" - if actual_path ~= original_requested_path then - message = message .. ", 鐢变簬鐩綍闄愬埗锛屽凡淇濆瓨鍒: " .. actual_path - end - - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = true, - message = message, - filename = filename, - size = #upload_data.content, - path = actual_path, - original_path = original_requested_path - }) - else - log.error("UPLOAD", "鏂囦欢涓婁紶澶辫触: " .. (err or "鏈煡閿欒")) - -- 鍗充娇澶辫触涔熷皾璇曟敹闆嗗瀮鍦 - collectgarbage() - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏂囦欢涓婁紶澶辫触: " .. (err or "鏈煡閿欒") - }) - end - end - - -- 鏂囦欢鍒犻櫎 - if string_starts_with(uri, "/delete") and method == "POST" then - -- 妫鏌ヤ紶缁熻璇佹柟寮 - local is_authenticated = validate_session(headers) - - -- 濡傛灉浼犵粺璁よ瘉澶辫触锛屽皾璇曚粠URL鍙傛暟涓幏鍙栫敤鎴峰悕鍜屽瘑鐮 - if not is_authenticated then - local url_username = uri:match("username=([^&]+)") - local url_password = uri:match("password=([^&]+)") - if url_username and url_password then - url_username = url_username:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - url_password = url_password:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if url_username == user_server_opts.user_name and url_password == user_server_opts.user_pwd then - log.info("AUTH", "閫氳繃URL鍙傛暟璁よ瘉鎴愬姛") - is_authenticated = true - else - log.info("AUTH", "URL鍙傛暟璁よ瘉澶辫触: 鐢ㄦ埛鍚嶆垨瀵嗙爜閿欒") - end - else - log.info("AUTH", "URL涓病鏈夋壘鍒扮敤鎴峰悕鍜屽瘑鐮佸弬鏁") - end - end - - -- 濡傛灉璁よ瘉浠嶇劧澶辫触锛岃繑鍥炴湭鎺堟潈璁块棶 - if not is_authenticated then - log.info("HTTP", "鏈巿鏉冭闂枃浠跺垹闄") - return 401, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏈巿鏉冭闂" - }) - end - local path = uri:match("path=([^&]+)") or "" - path = path:gsub("%%(%x%x)", function(hex) - return string.char(tonumber(hex, 16)) - end) - if not io.exists(path) then - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鏂囦欢涓嶅瓨鍦" - }) - end - -- 灏濊瘯鍒犻櫎鏂囦欢 - local ok, err = os.remove(path) - if ok then - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = true, - message = "鏂囦欢鍒犻櫎鎴愬姛" - }) - else - return 200, { - ["Content-Type"] = "application/json" - }, json.encode({ - success = false, - message = "鍒犻櫎澶辫触: " .. (err or "鏈煡閿欒") - }) - end - end - - -- 棣栭〉 - if uri == "/" then - local html_file = io.open("/index.html", "r") - if html_file then - local content = html_file:read("*a") - html_file:close() - return 200, { - ["Content-Type"] = "text/html" - }, content - end - end - - -- 鐩存帴鏂囦欢璺緞璁块棶 - -- 妫鏌ユ槸鍚︽槸API璺緞锛屽鏋滀笉鏄紝鍒欏皾璇曚綔涓烘枃浠惰矾寰勮闂 - local is_api_path = string_starts_with(uri, "/login") or string_starts_with(uri, "/logout") or - string_starts_with(uri, "/check-auth") or string_starts_with(uri, "/scan-files") or - string_starts_with(uri, "/list") or string_starts_with(uri, "/download") or - string_starts_with(uri, "/delete") or uri == "/" - - if not is_api_path then - log.info("DIRECT_ACCESS", "灏濊瘯鐩存帴璁块棶鏂囦欢: " .. uri) - - -- 纭畾瀹為檯鏂囦欢璺緞 - local file_path = uri - - -- 濡傛灉璺緞涓嶆槸浠/sd/寮澶达紝鍒欓粯璁ゅ湪/luadb/鐩綍涓嬫煡鎵 - if not string_starts_with(file_path, "/sd/") then - -- 绉婚櫎寮澶寸殑鏂滄潬 - if file_path:sub(1, 1) == "/" then - file_path = file_path:sub(2) - end - -- 娣诲姞/luadb/鍓嶇紑 - file_path = "/luadb/" .. file_path - end - - log.info("DIRECT_ACCESS", "瑙ｆ瀽鍚庣殑瀹為檯鏂囦欢璺緞: " .. file_path) - - -- 妫鏌ユ枃浠舵槸鍚﹀瓨鍦 - if not io.exists(file_path) then - log.info("DIRECT_ACCESS", "鏂囦欢涓嶅瓨鍦: " .. file_path) - return 404, { - ["Content-Type"] = "text/plain" - }, "鏂囦欢涓嶅瓨鍦" - end - - -- 灏濊瘯鎵撳紑鏂囦欢 - local file = io.open(file_path, "rb") - if not file then - log.info("DIRECT_ACCESS", "鏂囦欢鏃犳硶鎵撳紑: " .. file_path) - return 404, { - ["Content-Type"] = "text/plain" - }, "鏂囦欢鏃犳硶鎵撳紑" - end - - -- 鑾峰彇鏂囦欢鍚 - local filename = file_path:match("([^/]+)$") - - -- 璇诲彇鏂囦欢鍐呭 - local content = file:read("*a") - - -- 鍏抽棴鏂囦欢 - file:close() - - log.info("DIRECT_ACCESS", "鏂囦欢璇诲彇瀹屾垚: " .. filename .. ", 澶у皬: " .. #content .. " 瀛楄妭") - - -- 璁剧疆HTTP澶撮儴 - local response_headers = { - ["Content-Type"] = "application/octet-stream", - ["Content-Disposition"] = "attachment; filename=\"" .. filename .. "\"" - } - - return 200, response_headers, content - end - - return 404, { - ["Content-Type"] = "text/plain" - }, "椤甸潰鏈壘鍒" -end - --- server鏈嶅姟鍣ㄥ惎鍔ㄤ换鍔 -local function http_server_start_task(server_opts, ap_opts) - -- 绛夊緟AP鍒濆鍖栧畬鎴 - sys.waitUntil("AP_CREATE_OK") - - -- 纭SD鍗℃槸鍚︽寕杞芥垚鍔 - local retry_count = 0 - local max_retries = 3 - - while retry_count < max_retries do - local free_space, err = fatfs.getfree("/sd") - if free_space then - log.info("HTTP", "SD鍗℃寕杞芥垚鍔燂紝鍙敤绌洪棿: " .. json.encode(free_space)) - break - else - retry_count = retry_count + 1 - log.warn("HTTP", "SD鍗℃寕杞芥鏌ュけ璐 (" .. retry_count .. "): " .. (err or "鏈煡閿欒")) - if retry_count < max_retries then - sys.wait(1000) - else - log.error("HTTP", "SD鍗℃寕杞藉け璐ワ紝灏嗙户缁惎鍔ㄤ絾鍙兘鏃犳硶璁块棶SD鍗″唴瀹") - end - end - end - - -- 鍚姩HTTP鏈嶅姟鍣 - httpsrv.start(server_opts.server_port, handle_http_request, socket.LWIP_AP) - - log.info("HTTP", "鏂囦欢鏈嶅姟鍣ㄥ凡鍚姩") - log.info("HTTP", "璇疯繛鎺iFi: " .. ap_opts.ap_ssid .. "锛屽瘑鐮: " .. ap_opts.ap_pwd) - log.info("HTTP", "鐒跺悗璁块棶: http://" .. server_opts.server_addr.. ":" .. server_opts.server_port .. "/explorer.html") -end - - ---[[ -鍚姩鏂囦欢绠＄悊绯荤粺锛屽寘鎷垱寤篈P鐑偣銆佹寕杞絋F/SD鍗″拰鍚姩SERVER鏂囦欢绠＄悊鏈嶅姟鍣ㄥ姛鑳 -@api exremotefile.open(ap_opts, sdcard_opts, server_opts) -@table ap_opts 鍙夛紝AP閰嶇疆閫夐」琛 -@table sdcard_opts 鍙夛紝TF/SD鍗℃寕杞介厤缃夐」琛 -@table server_opts 鍙夛紝鏈嶅姟鍣ㄩ厤缃夐」琛 -@return 鏃 鏃犺繑鍥炲 -@usage --- 涓銆佷娇鐢ㄩ粯璁ゅ弬鏁板垱寤簊erver鏈嶅姟鍣 --- 鍚姩鍚庤繛鎺ラ粯璁P鐑偣锛岀洿鎺ヤ娇鐢ㄦ棩蹇椾腑榛樿鐨勫湴鍧"http://192.168.4.1:80/explorer.html"鏉ヨ闂枃浠剁鐞嗘湇鍔″櫒銆 -exremotefile.open() - - --- 浜屻佽嚜瀹氫箟鍙傛暟鍚姩 --- 鍚姩鍚庤繛鎺ヨ嚜瀹氫箟AP鐑偣锛岃闂棩蹇椾腑鑷畾涔夌殑鍦板潃"http://"server_addr":"server_port"/explorer.html"鏉ヨ闂枃浠剁鐞嗘湇鍔″櫒銆 -exremotefile.open({ - ap_ssid = "LuatOS_FileHub", -- WiFi鍚嶇О - ap_pwd = "12345678" -- WiFi瀵嗙爜 -}, -{ - spi_id = 1, -- SPI缂栧彿 - spi_cs = 12, -- CS鐗囬夊紩鑴 - is_8000_development_board = false, -- 鏄惁浣跨敤8000寮鍙戞澘 - is_sdio = false -- 鏄惁浣跨敤sdio鎸傝浇 -}, -{ - server_addr = "192.168.4.1", -- 鏈嶅姟鍣ㄥ湴鍧 - server_port = 80, -- 鏈嶅姟鍣ㄧ鍙 - user_name = "admin", -- 鐢ㄦ埛鍚 - user_pwd = "123456" -- 瀵嗙爜 -}) -]] -function exremotefile.open(ap_opts, sdcard_opts, server_opts) - if is_initialized then - log.warn("exremotefile", "鏂囦欢绠＄悊绯荤粺宸茬粡鍦ㄨ繍琛屼腑") - return - end - - log.info("exremotefile", "鍚姩鏂囦欢绠＄悊绯荤粺") - - -- 鍚堝苟閰嶇疆 - if ap_opts then - log.info("check_config", "寮濮嬫鏌P鍙傛暟") - if not ap_opts.ap_ssid then - ap_opts.ap_ssid = default_ap_opts.ap_ssid - log.info("check_config", "AP娌℃湁璁剧疆ssid锛岀敤榛樿閰嶇疆",ap_opts.ap_ssid) - end - if not ap_opts.ap_pwd then - ap_opts.ap_pwd = default_ap_opts.ap_pwd - log.info("check_config", "AP娌℃湁璁剧疆pwd锛岀敤榛樿閰嶇疆",ap_opts.ap_pwd) - end - log.info("check_config", "AP鍙傛暟閰嶇疆瀹屾瘯") - else - ap_opts = default_ap_opts - log.info("check_config", "娌℃湁AP鍙傛暟锛岀敤榛樿閰嶇疆") - end - - if sdcard_opts then - log.info("check_config", "寮濮嬫鏌F/SD鎸傝浇鍙傛暟") - if not sdcard_opts.spi_id then - sdcard_opts.spi_id = default_sdcard_opts.spi_id - log.info("check_config", "TF/SD鎸傝浇娌℃湁璁剧疆spi鍙凤紝鐢ㄩ粯璁ら厤缃",sdcard_opts.spi_id) - end - if not sdcard_opts.spi_cs then - sdcard_opts.spi_cs = default_sdcard_opts.spi_cs - log.info("check_config", "TF/SD鎸傝浇娌℃湁璁剧疆cs鐗囬夎剼锛岀敤榛樿閰嶇疆",sdcard_opts.spi_cs) - end - log.info("check_config", "TF/SD鎸傝浇鍙傛暟閰嶇疆瀹屾瘯") - else - sdcard_opts = default_sdcard_opts - log.info("check_config", "娌℃湁TF/SD鎸傝浇鍙傛暟锛岀敤榛樿閰嶇疆") - end - - if server_opts then - log.info("check_config", "寮濮嬫鏌ERVER鍙傛暟") - if not server_opts.server_addr then - server_opts.server_addr = default_server_opts.server_addr - log.info("check_config", "SERVER娌℃湁璁剧疆addr锛岀敤榛樿閰嶇疆",server_opts.server_addr) - end - if not server_opts.server_port then - server_opts.server_port = default_server_opts.server_port - log.info("check_config", "SERVER娌℃湁璁剧疆port锛岀敤榛樿閰嶇疆",server_opts.server_port) - end - if not server_opts.user_name then - server_opts.user_name = default_server_opts.user_name - log.info("check_config", "SERVER娌℃湁璁剧疆user_name锛岀敤榛樿閰嶇疆",server_opts.user_name) - end - if not server_opts.user_pwd then - server_opts.user_pwd = default_server_opts.user_pwd - log.info("check_config", "SERVER娌℃湁璁剧疆user_pwd锛岀敤榛樿閰嶇疆",server_opts.user_pwd) - end - log.info("check_config", "SERVER鍙傛暟閰嶇疆瀹屾瘯") - else - server_opts = default_server_opts - log.info("check_config", "娌℃湁SERVER鍙傛暟锛岀敤榛樿閰嶇疆") - end - - user_sdcard_opts = sdcard_opts - user_server_opts = server_opts - -- 鍒涘缓AP鐑偣 - create_ap(ap_opts, server_opts) - - -- 鍒濆鍖朣D鍗 - local mount_result = init_sdcard(sdcard_opts) - if not mount_result then - log.error("exremotefile", "SD鍗″垵濮嬪寲澶辫触") - end - - -- 鍚姩HTTP鏈嶅姟鍣 - sys.taskInit(http_server_start_task, server_opts, ap_opts) - - is_initialized = true - log.info("exremotefile", "鏂囦欢绠＄悊绯荤粺鍚姩瀹屾垚") -end - ---[[ -鍏抽棴鏂囦欢绠＄悊绯荤粺锛屽寘鎷仠姝TTP鏂囦欢鏈嶅姟鍣ㄣ佸彇娑圱F/SD鍗℃寕杞藉拰鍋滄AP鐑偣 -@api exremotefile.close() -@return 鏃 鏃犺繑鍥炲 -@usage --- 鍏抽棴鏂囦欢绠＄悊绯荤粺 --- exremotefile.close() -]] -function exremotefile.close() - if not is_initialized then - log.warn("exremotefile", "鏂囦欢绠＄悊绯荤粺灏氭湭鍚姩") - return - end - - log.info("exremotefile", "鍏抽棴鏂囦欢绠＄悊绯荤粺") - - -- 鍋滄HTTP鏈嶅姟鍣 - httpsrv.stop(user_server_opts.server_port, nil, socket.LWIP_AP) - -- 鍙栨秷鎸傝浇SD鍗 - fatfs.unmount("/sd") - -- 鍋滄AP鐑偣 - wlan.stopAP() - - -- 鍏抽棴鎵鐢⊿PI - spi.close(user_sdcard_opts.spi_id) - - -- 鍏抽棴鎵鐢↖O - if user_sdcard_opts.is_8000_development_board == true then - gpio.close(ETH3V3_EN) - gpio.close(SPI_ETH_CS) - end - gpio.close(user_sdcard_opts.spi_cs) - - is_initialized = false - log.info("exremotefile", "鏂囦欢绠＄悊绯荤粺宸插叧闂") -end - -return exremotefile \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/extalk.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/extalk.lua deleted file mode 100644 index 60555ff..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/extalk.lua +++ /dev/null @@ -1,588 +0,0 @@ ---[[ -@module extalk -@summary extalk鎵╁睍搴 -@version 1.1.1 -@date 2025.09.18 -@author 姊佸仴 -@usage - local extalk = require "extalk" - -- 閰嶇疆骞跺垵濮嬪寲 - extalk.setup({ - key = "your_product_key", - heart_break_time = 30, - contact_list_cbfnc = function(dev_list) end, - state_cbfnc = function(state) end - }) - -- 鍙戣捣瀵硅 - extalk.start("remote_device_id") - -- 缁撴潫瀵硅 - extalk.stop() -]] - -local extalk = {} - --- 妯″潡甯搁噺锛堜繚鐣欏師濮嬫暟鎹粨鏋勶級 -extalk.START = 1 -- 閫氳瘽寮濮 -extalk.STOP = 2 -- 閫氳瘽缁撴潫 -extalk.UNRESPONSIVE = 3 -- 鏈搷搴 -extalk.ONE_ON_ONE = 5 -- 涓瀵逛竴鏉ョ數 -extalk.BROADCAST = 6 -- 骞挎挱 - -local AIRTALK_TASK_NAME = "airtalk_task" - --- 娑堟伅绫诲瀷甯搁噺锛堜繚鐣欏師濮嬫暟鎹粨鏋勶級 -local MSG_CONNECT_ON_IND = 0 -local MSG_CONNECT_OFF_IND = 1 -local MSG_AUTH_IND = 2 -local MSG_SPEECH_ON_IND = 3 -local MSG_SPEECH_OFF_IND = 4 -local MSG_SPEECH_CONNECT_TO = 5 -local MSG_SPEECH_STOP_TEST_END = 22 - --- 璁惧鐘舵佸父閲忥紙淇濈暀鍘熷鏁版嵁缁撴瀯锛 -local SP_T_NO_READY = 0 -- 绂荤嚎鐘舵佹棤娉曞璁 -local SP_T_IDLE = 1 -- 瀵硅绌洪棽鐘舵 -local SP_T_CONNECTING = 2 -- 涓诲姩鍙戣捣瀵硅 -local SP_T_CONNECTED = 3 -- 瀵硅涓 - -local SUCC = "success" - --- 鍏ㄥ眬鐘舵佸彉閲忥紙淇濈暀鍘熷鏁版嵁缁撴瀯锛 -local g_state = SP_T_NO_READY -- 璁惧鐘舵 -local g_mqttc = nil -- mqtt瀹㈡埛绔 -local g_local_id -- 鏈満ID -local g_stask_start = false -- 鏈満ID -local g_remote_id -- 瀵圭ID -local g_s_type -- 瀵硅鐨勬ā寮忥紝瀛楃涓插舰寮 -local g_s_topic -- 瀵硅鐢ㄧ殑topic -local g_s_mode -- 瀵硅鐨勬ā寮 -local g_dev_list -- 瀵硅鍒楄〃 -local g_dl_topic -- 涓嬭娑堟伅topic妯℃澘 - --- 閰嶇疆鍙傛暟 -local extalk_configs_local = { - key = 0, -- 椤圭洰key锛屼竴鑸渶瑕佸拰main鐨凱RODUCT_KEY淇濇寔涓鑷 - heart_break_time = 0, -- 蹇冭烦闂撮殧(鍗曚綅绉) - contact_list_cbfnc = nil, -- 鑱旂郴浜哄洖璋冨嚱鏁帮紝鍚澶囧彿鍜屾樀绉 - state_cbfnc = nil, -- 鐘舵佸洖璋冿紝鍒嗕负瀵硅寮濮嬶紝瀵硅缁撴潫锛屾湭鍝嶅簲 -} - --- 宸ュ叿鍑芥暟锛氬弬鏁版鏌 -local function check_param(param, expected_type, name) - if type(param) ~= expected_type then - log.error(string.format("鍙傛暟閿欒: %s 搴斾负 %s 绫诲瀷锛屽疄闄呬负 %s", - name, expected_type, type(param))) - return false - end - return true -end - --- MQTT娑堟伅鍙戝竷鍑芥暟锛岄泦涓鐞嗘墍鏈夊彂甯冩搷浣滃苟鎵撳嵃鏃ュ織 -local function publish_message(topic, payload) - if g_mqttc then - log.info("MQTT鍙戝竷 - 涓婚:", topic, "鍐呭:", payload) - g_mqttc:publish(topic, payload) - else - log.error("MQTT瀹㈡埛绔湭鍒濆鍖栵紝鏃犳硶鍙戝竷娑堟伅") - end -end - - --- 瀵硅瓒呮椂澶勭悊 -function extalk.wait_speech_to() - log.info("涓诲姩璇锋眰瀵硅瓒呮椂鏃犲簲绛") - extalk.speech_off(true, false) -end - - --- 鍙戦侀壌鏉冩秷鎭 -local function auth() - if g_state == SP_T_NO_READY and g_mqttc then - local topic = string.format("ctrl/uplink/%s/0001", g_local_id) - local payload = json.encode({ - ["key"] = extalk_configs_local.key, - ["device_type"] = 1 - }) - publish_message(topic, payload) - end -end - --- 鍙戦佸績璺虫秷鎭 -local function heart() - if g_mqttc then - adc.open(adc.CH_VBAT) - local vbat = adc.get(adc.CH_VBAT) - adc.close(adc.CH_VBAT) - local topic = string.format("ctrl/uplink/%s/0005", g_local_id) - local payload = json.encode({ - ["csq"] = mobile.csq(), - ["battery"] = vbat - }) - publish_message(topic, payload) - end -end - --- 寮濮嬪璁 -local function speech_on(ssrc, sample) - g_state = SP_T_CONNECTED - g_mqttc:subscribe(g_s_topic) - airtalk.set_topic(g_s_topic) - airtalk.set_ssrc(ssrc) - log.info("瀵硅妯″紡", g_s_mode) - airtalk.speech(true, g_s_mode, sample) - sys.sendMsg(AIRTALK_TASK_NAME, MSG_SPEECH_ON_IND, true) - -- sys.timerLoopStart(heart, extalk_configs_local.heart_break_time * 1000) - sys.timerStopAll(extalk.wait_speech_to) -end - --- 缁撴潫瀵硅 -function extalk.speech_off(need_upload, need_ind) - if g_state == SP_T_CONNECTED then - g_mqttc:unsubscribe(g_s_topic) - airtalk.speech(false) - g_s_topic = nil - end - - g_state = SP_T_IDLE - sys.timerStopAll(auth) - - sys.timerStopAll(extalk.wait_speech_to) - - if need_upload and g_mqttc then - local topic = string.format("ctrl/uplink/%s/0004", g_local_id) - publish_message(topic, json.encode({["to"] = g_remote_id})) - end - - if need_ind then - sys.sendMsg(AIRTALK_TASK_NAME, MSG_SPEECH_OFF_IND, true) - end -end - - --- 鍛戒护澶勭悊锛氳姹傚璁插簲绛 -local function handle_speech_response(obj) - if g_state ~= SP_T_CONNECTING then - log.error("state", g_state, "need", SP_T_CONNECTING) - return - end - - if obj and obj["result"] == SUCC and g_s_topic == obj["topic"] then - -- 寮濮嬪璁 - local sample_rate = obj["audio_code"] == "amr-nb" and 8000 or 16000 - speech_on(obj["ssrc"], sample_rate) - return - else - log.info(obj["result"], obj["topic"], g_s_topic) - sys.sendMsg(AIRTALK_TASK_NAME, MSG_SPEECH_ON_IND, false) - end - - g_s_topic = nil - g_state = SP_T_IDLE -end - --- 鍛戒护澶勭悊锛氬绔潵鐢 -local function handle_incoming_call(obj) - if not obj or not obj["topic"] or not obj["ssrc"] or not obj["audio_code"] or not obj["type"] then - local response = { - ["result"] = "failed", - ["topic"] = obj and obj["topic"] or "", - ["info"] = "鏃犳晥鐨勮姹傚弬鏁" - } - publish_message(string.format("ctrl/uplink/%s/8102", g_local_id), json.encode(response)) - return - end - - -- 闈炵┖闂茬姸鎬佹棤娉曟帴鏀舵潵鐢 - if g_state ~= SP_T_IDLE then - log.error("state", g_state, "need", SP_T_IDLE) - local response = { - ["result"] = "failed", - ["topic"] = obj["topic"], - ["info"] = "device is busy" - } - publish_message(string.format("ctrl/uplink/%s/8102", g_local_id), json.encode(response)) - return - end - - local response, from = {}, nil - - -- 鎻愬彇瀵圭ID - from = string.match(obj["topic"], "audio/(.*)/.*/.*") - if not from then - response = { - ["result"] = "failed", - ["topic"] = obj["topic"], - ["info"] = "topic error" - } - publish_message(string.format("ctrl/uplink/%s/8102", g_local_id), json.encode(response)) - return - end - - -- 澶勭悊涓瀵逛竴閫氳瘽 - if obj["type"] == "one-on-one" then - g_s_topic = obj["topic"] - g_remote_id = from - g_s_type = "one-on-one" - g_s_mode = airtalk.MODE_PERSON - - -- 瑙﹀彂鍥炶皟 - if extalk_configs_local.state_cbfnc then - extalk_configs_local.state_cbfnc({ - state = extalk.ONE_ON_ONE, - id = from - }) - end - - response = {["result"] = SUCC, ["topic"] = obj["topic"], ["info"] = ""} - local sample_rate = obj["audio_code"] == "amr-nb" and 8000 or 16000 - speech_on(obj["ssrc"], sample_rate) - end - - -- 澶勭悊骞挎挱 - if obj["type"] == "broadcast" then - g_s_topic = obj["topic"] - g_remote_id = from - g_s_mode = airtalk.MODE_GROUP_LISTENER - g_s_type = "broadcast" - - -- 瑙﹀彂鍥炶皟 - if extalk_configs_local.state_cbfnc then - extalk_configs_local.state_cbfnc({ - state = extalk.BROADCAST, - id = from - }) - end - - response = {["result"] = SUCC, ["topic"] = obj["topic"], ["info"] = ""} - local sample_rate = obj["audio_code"] == "amr-nb" and 8000 or 16000 - speech_on(obj["ssrc"], sample_rate) - end - - -- 鍙戦佸搷搴 - publish_message(string.format("ctrl/uplink/%s/8102", g_local_id), json.encode(response)) -end - --- 鍛戒护澶勭悊锛氬绔寕鏂 -local function handle_remote_hangup(obj) - local response = {} - - if g_state == SP_T_IDLE then - response = {["result"] = "failed", ["info"] = "no speech"} - else - log.info("0103", obj, obj["type"], g_s_type) - if obj and obj["type"] == g_s_type then - response = {["result"] = SUCC, ["info"] = ""} - extalk.speech_off(false, true) - else - response = {["result"] = "failed", ["info"] = "type mismatch"} - end - end - - publish_message(string.format("ctrl/uplink/%s/8103", g_local_id), json.encode(response)) -end - --- 鍛戒护澶勭悊锛氭洿鏂拌澶囧垪琛 -local function handle_device_list_update(obj) - local response = {} - if obj then - g_dev_list = obj["dev_list"] - response = {["result"] = SUCC, ["info"] = ""} - else - response = {["result"] = "failed", ["info"] = "json info error"} - end - - publish_message(string.format("ctrl/uplink/%s/8101", g_local_id), json.encode(response)) -end - --- 鍛戒护澶勭悊锛氶壌鏉冪粨鏋 -local function handle_auth_result(obj) - if obj and obj["result"] == SUCC then - publish_message(string.format("ctrl/uplink/%s/0002", g_local_id), "") -- 鏇存柊鍒楄〃 - sys.timerLoopStart(heart, extalk_configs_local.heart_break_time * 1000) -- 鍙戣捣蹇冭烦 - else - sys.sendMsg(AIRTALK_TASK_NAME, MSG_AUTH_IND, false, - "閴存潈澶辫触" .. (obj and obj["info"] or "")) - log.error("閴存潈澶辫触,鍙兘鏄病鏈変慨鏀筆RODUCT_KEY") - end -end - --- 鍛戒护澶勭悊锛氳澶囧垪琛ㄦ洿鏂板簲绛 -local function handle_device_list_response(obj) - if obj and obj["result"] == SUCC then - g_dev_list = obj["dev_list"] - if extalk_configs_local.contact_list_cbfnc then - extalk_configs_local.contact_list_cbfnc(g_dev_list) - end - g_state = SP_T_IDLE - sys.sendMsg(AIRTALK_TASK_NAME, MSG_AUTH_IND, true) -- 瀹屾暣鐧诲綍娴佺▼缁撴潫 - else - sys.sendMsg(AIRTALK_TASK_NAME, MSG_AUTH_IND, false, "鏇存柊璁惧鍒楄〃澶辫触") - end -end - --- 鍛戒护瑙ｆ瀽璺敱琛 -local cmd_handlers = { - ["8003"] = handle_speech_response, -- 璇锋眰瀵硅搴旂瓟 - ["0102"] = handle_incoming_call, -- 骞冲彴閫氱煡瀵圭瀵硅寮濮 - ["0103"] = handle_remote_hangup, -- 骞冲彴閫氱煡缁堢瀵硅缁撴潫 - ["0101"] = handle_device_list_update,-- 骞冲彴閫氱煡缁堢鏇存柊瀵硅璁惧鍒楄〃 - ["8001"] = handle_auth_result, -- 骞冲彴瀵归壌鏉冨簲绛 - ["8002"] = handle_device_list_response -- 骞冲彴瀵圭粓绔幏鍙栫粓绔垪琛ㄥ簲绛 -} - --- 瑙ｆ瀽鎺ユ敹鍒扮殑娑堟伅 -local function analyze_v1(cmd, topic, obj) - -- 蹇界暐蹇冭烦鍜岀粨鏉熷璁茬殑搴旂瓟 - if cmd == "8005" or cmd == "8004" then - return - end - - -- 鏌ユ壘骞舵墽琛屽搴旂殑鍛戒护澶勭悊鍣 - local handler = cmd_handlers[cmd] - if handler then - handler(obj) - else - log.warn("鏈鐞嗙殑鍛戒护", cmd) - end -end - --- MQTT鍥炶皟澶勭悊 -local function mqtt_cb(mqttc, event, topic, payload) - log.info(event, topic or "") - - if event == "conack" then - -- MQTT杩炴帴鎴愬姛锛屽紑濮嬭嚜瀹氫箟閴存潈娴佺▼ - sys.sendMsg(AIRTALK_TASK_NAME, MSG_CONNECT_ON_IND) - g_mqttc:subscribe("ctrl/downlink/" .. g_local_id .. "/#") - elseif event == "suback" then - if g_state == SP_T_NO_READY then - if topic then - auth() - else - sys.sendMsg(AIRTALK_TASK_NAME, MSG_AUTH_IND, false, - "璁㈤槄澶辫触" .. "ctrl/downlink/" .. g_local_id .. "/#") - end - elseif g_state == SP_T_CONNECTED and not topic then - extalk.speech_off(false, true) - end - elseif event == "recv" then - local result = string.match(topic, g_dl_topic) - if result then - local obj = json.decode(payload) - analyze_v1(result, topic, obj) - end - elseif event == "disconnect" then - extalk.speech_off(false, true) - g_state = SP_T_NO_READY - elseif event == "error" then - log.error("MQTT閿欒鍙戠敓",topic,payload) - end -end - --- 浠诲姟娑堟伅澶勭悊 -local function task_cb(msg) - if msg[1] == MSG_SPEECH_CONNECT_TO then - extalk.speech_off(true, false) - else - log.info("鏈鐞嗘秷鎭", msg[1], msg[2], msg[3], msg[4]) - end -end - --- 瀵硅浜嬩欢鍥炶皟 -local function airtalk_event_cb(event, param) - log.info("airtalk event", event, param) - if event == airtalk.EVENT_ERROR then - if param == airtalk.ERROR_NO_DATA and g_s_mode == airtalk.MODE_PERSON then - log.error("闀挎椂闂存病鏈夋敹鍒伴煶棰戞暟鎹") - extalk.speech_off(true, true) - end - end -end - --- MQTT浠诲姟涓诲惊鐜 -local function airtalk_mqtt_task() - if g_stask_start then - log.info("airtalk task 宸茬粡鍒濆鍖栦簡") - return true - end - - g_stask_start = true - local msg, online = nil, false - - -- 鍒濆鍖栨湰鍦癐D - g_local_id = mobile.imei() - g_dl_topic = "ctrl/downlink/" .. g_local_id .. "/(%w%w%w%w)" - - -- 鍒涘缓MQTT瀹㈡埛绔 - g_mqttc = mqtt.create(nil, "mqtt.airtalk.luatos.com", 1883, false, {rxSize = 32768}) - - -- 閰嶇疆瀵硅鍙傛暟 - airtalk.config(airtalk.PROTOCOL_MQTT, g_mqttc, 200) -- 缂撳啿鑷冲皯200ms鎾斁 - airtalk.on(airtalk_event_cb) - airtalk.start() - - -- 閰嶇疆MQTT瀹㈡埛绔 - g_mqttc:auth(g_local_id, g_local_id, mobile.muid()) - g_mqttc:keepalive(240) -- 榛樿鍊240s - g_mqttc:autoreconn(true, 15000) -- 鑷姩閲嶈繛鏈哄埗 - g_mqttc:debug(false) - g_mqttc:on(mqtt_cb) - - log.info("璁惧淇℃伅", g_local_id, mobile.muid()) - - -- 寮濮嬭繛鎺 - g_mqttc:connect() - online = false - - while true do - -- 绛夊緟MQTT杩炴帴鎴愬姛 - msg = sys.waitMsg(AIRTALK_TASK_NAME, MSG_CONNECT_ON_IND) - log.info("connected") - - -- 澶勭悊鐧诲綍娴佺▼ - while not online do - msg = sys.waitMsg(AIRTALK_TASK_NAME, MSG_AUTH_IND, 30000) -- 30绉掕秴鏃 - - if type(msg) == 'table' then - online = msg[2] - if online then - -- 閴存潈閫氳繃锛60鍒嗛挓鍚庨噸鏂伴壌鏉 - sys.timerLoopStart(auth, 3600000) - else - log.info(msg[3]) - -- 閴存潈澶辫触锛5鍒嗛挓鍚庨噸璇 - sys.timerLoopStart(auth, 300000) - end - else - -- 瓒呮椂鏈敹鍒伴壌鏉冪粨鏋滐紝閲嶆柊鍙戦 - auth() - end - end - - log.info("瀵硅绠＄悊骞冲彴宸茶繛鎺") - - -- 澶勭悊鍦ㄧ嚎鐘舵佷笅鐨勬秷鎭 - while online do - msg = sys.waitMsg(AIRTALK_TASK_NAME) - - if type(msg) == 'table' and type(msg[1]) == "number" then - if msg[1] == MSG_SPEECH_STOP_TEST_END then - if g_state ~= SP_T_CONNECTING and g_state ~= SP_T_CONNECTED then - log.info("娌℃湁瀵硅", g_state) - else - extalk.speech_off(true, false) - end - elseif msg[1] == MSG_SPEECH_ON_IND then - if extalk_configs_local.state_cbfnc then - local state = msg[2] and extalk.START or extalk.UNRESPONSIVE - extalk_configs_local.state_cbfnc({state = state}) - end - elseif msg[1] == MSG_SPEECH_OFF_IND then - if extalk_configs_local.state_cbfnc then - extalk_configs_local.state_cbfnc({state = extalk.STOP}) - end - elseif msg[1] == MSG_CONNECT_OFF_IND then - log.info("connect", msg[2]) - online = msg[2] - end - else - log.info(type(msg), type(msg and msg[1])) - end - - msg = nil -- 娓呯悊寮曠敤 - end - - online = false -- 閲嶇疆鍦ㄧ嚎鐘舵 - end -end - --- 妯″潡鍒濆鍖 -function extalk.setup(extalk_configs) - - if not extalk_configs or type(extalk_configs) ~= "table" then - log.error("AirTalk閰嶇疆蹇呴』涓簍able绫诲瀷") - return false - end - - -- 妫鏌ラ厤缃弬鏁 - if not check_param(extalk_configs.key, "string", "key") then - return false - end - extalk_configs_local.key = extalk_configs.key - - if not check_param(extalk_configs.heart_break_time, "number", "heart_break_time") then - return false - end - extalk_configs_local.heart_break_time = extalk_configs.heart_break_time - - if not check_param(extalk_configs.contact_list_cbfnc, "function", "contact_list_cbfnc") then - return false - end - extalk_configs_local.contact_list_cbfnc = extalk_configs.contact_list_cbfnc - - if not check_param(extalk_configs.state_cbfnc, "function", "state_cbfnc") then - return false - end - extalk_configs_local.state_cbfnc = extalk_configs.state_cbfnc - - -- 鍚姩浠诲姟 - sys.taskInitEx(airtalk_mqtt_task, AIRTALK_TASK_NAME, task_cb) - return true -end - --- 寮濮嬪璁 -function extalk.start(id) - - if g_state ~= SP_T_IDLE then - log.warn("姝ｅ湪瀵硅鏃犳硶寮濮嬶紝褰撳墠鐘舵:", g_state) - return false - end - - if id == nil then - -- 骞挎挱妯″紡 - g_remote_id = "all" - g_state = SP_T_CONNECTING - g_s_mode = airtalk.MODE_GROUP_SPEAKER - g_s_type = "broadcast" - g_s_topic = string.format("audio/%s/all/%s", - g_local_id, string.sub(tostring(mcu.ticks()), -4, -1)) - - publish_message(string.format("ctrl/uplink/%s/0003", g_local_id), - json.encode({["topic"] = g_s_topic, ["type"] = g_s_type})) - sys.timerStart(extalk.wait_speech_to, 15000) - else - -- 涓瀵逛竴妯″紡 - log.info("鍚", id, "涓诲姩鍙戣捣瀵硅") - if id == g_local_id then - log.error("涓嶅厑璁告湰鏈虹粰鏈満鎷ㄦ墦鐢佃瘽") - return false - end - - g_state = SP_T_CONNECTING - g_remote_id = id - g_s_mode = airtalk.MODE_PERSON - g_s_type = "one-on-one" - g_s_topic = string.format("audio/%s/%s/%s", - g_local_id, id, string.sub(tostring(mcu.ticks()), -4, -1)) - - publish_message(string.format("ctrl/uplink/%s/0003", g_local_id), - json.encode({["topic"] = g_s_topic, ["type"] = g_s_type})) - sys.timerStart(extalk.wait_speech_to, 15000) - end - - return true -end - --- 缁撴潫瀵硅 -function extalk.stop() - if g_state ~= SP_T_CONNECTING and g_state ~= SP_T_CONNECTED then - log.info("娌℃湁瀵硅锛屽綋鍓嶇姸鎬:", g_state) - return false - end - - log.info("涓诲姩鏂紑瀵硅") - extalk.speech_off(true, false) - return true -end - -return extalk diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/extp.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/extp.lua deleted file mode 100644 index 30366b4..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/extp.lua +++ /dev/null @@ -1,431 +0,0 @@ --- extp.lua - 瑙︽懜绯荤粺妯″潡 ---[[ -@module extp -@summary 瑙︽懜绯荤粺鎷撳睍搴 -@version 1.1.1 -@date 2025.11.20 -@author 姹熻 -@usage -鏈枃浠朵负瑙︽懜绯荤粺鎷撳睍搴擄紝鏍稿績涓氬姟閫昏緫涓猴細 -1銆佸垵濮嬪寲瑙︽懜璁惧锛屾敮鎸佸绉嶈Е鎽歌姱鐗 -2銆佸鐞嗗師濮嬭Е鎽告暟鎹苟瑙ｆ瀽涓哄悇绉嶆墜鍔夸簨浠 -3銆侀氳繃缁熶竴娑堟伅鎺ュ彛鍙戝竷瑙︽懜浜嬩欢 -4銆佹彁渚涙秷鎭彂甯冩帶鍒跺姛鑳 -5銆佹彁渚涙粦鍔ㄥ拰闀挎寜闃堝奸厤缃姛鑳 - -鏀寔鐨勮Е鎽镐簨浠剁被鍨嬪寘鎷細 -RAW_DATA銆乀OUCH_DOWN銆丮OVE_X銆丮OVE_Y銆丼WIPE_LEFT銆丼WIPE_RIGHT銆 -SWIPE_UP銆丼WIPE_DOWN銆丼INGLE_TAP銆丩ONG_PRESS - -鏈枃浠剁殑瀵瑰鎺ュ彛鏈5涓細 -1銆乪xtp.init(param)锛氳Е鎽歌澶囧垵濮嬪寲鍑芥暟 -2銆乪xtp.set_publish_enabled(msg_type, enabled)锛氳缃秷鎭彂甯冪姸鎬 -3銆乪xtp.get_publish_enable(msg_type)锛氳幏鍙栨秷鎭彂甯冪姸鎬 -4銆乪xtp.set_swipe_threshold(threshold)锛氳缃粦鍔ㄥ垽瀹氶槇鍊 -5銆乪xtp.set_long_press_threshold(threshold)锛氳缃暱鎸夊垽瀹氶槇鍊 - -鎵鏈夎Е鎽镐簨浠跺潎閫氳繃sys.publish("BASE_TOUCH_EVENT", event_type, ...)鍙戝竷 -]] - -local extp = {} - --- 瑙︽懜鐘舵佸彉閲 -local state = "IDLE" -- 褰撳墠鐘舵侊細IDLE(绌洪棽), DOWN(鎸変笅), MOVE(绉诲姩) -local touch_down_x = 0 -- 鎸変笅鏃剁殑X鍧愭爣 -local touch_down_y = 0 -- 鎸変笅鏃剁殑Y鍧愭爣 -local touch_down_time = 0 -- 鎸変笅鏃剁殑鏃堕棿鎴 -local swipe_threshold = 45 -- 婊戝姩鍒ゅ畾闃堝硷紙鍍忕礌锛 -local long_press_threshold = 500 -- 闀挎寜鍒ゅ畾闃堝硷紙姣锛 -local swipe_direction = nil -- 婊戝姩鏂瑰悜锛堢敤浜嶮OVE鐘舵侊級 - --- 娑堟伅鍙戝竷鎺у埗琛紝榛樿鍏ㄩ儴鎵撳紑 -local publish_control = { - RAW_DATA = false, -- 鍘熷瑙︽懜鏁版嵁 - TOUCH_DOWN = false, -- 鎸変笅浜嬩欢 - MOVE_X = false, -- 姘村钩绉诲姩 - MOVE_Y = false, -- 鍨傜洿绉诲姩 - SWIPE_LEFT = false, -- 鍚戝乏婊戝姩 - SWIPE_RIGHT = false, -- 鍚戝彸婊戝姩 - SWIPE_UP = false, -- 鍚戜笂婊戝姩 - SWIPE_DOWN = false, -- 鍚戜笅婊戝姩 - SINGLE_TAP = true, -- 鍗曞嚮 - LONG_PRESS = true -- 闀挎寜 -} - --- 瀹氫箟鏀寔鐨勮Е鎽歌姱鐗囬厤缃 -local tp_configs = { - cst820 = { i2c_speed = i2c.FAST, tp_model = "cst820" }, - gt9157 = { i2c_speed = i2c.FAST, tp_model = "gt9157" }, - cst9220 = { i2c_speed = i2c.SLOW, tp_model = "cst9220" }, - jd9261t = { i2c_speed = i2c.FAST, tp_model = "jd9261t" }, - gt911 = { i2c_speed = i2c.SLOW, tp_model = "gt911" }, - AirLCD_1010 = { i2c_speed = i2c.SLOW, tp_model = "gt911" }, - Air780EHM_LCD_4 = { i2c_speed = i2c.SLOW, tp_model = "gt911" }, - AirLCD_1020 = { i2c_speed = i2c.SLOW, tp_model = "gt911" } -} - --- 鐗规畩鍨嬪彿鐨勯粯璁ら厤缃 -local special_tp_configs = { - Air780EHM_LCD_4 = { - i2c_id = 1, - pin_rst = 1, - pin_int = 22 - }, - AirLCD_1010 = { - i2c_id = 0, - pin_rst = 20, - pin_int = gpio.WAKEUP0 - }, - AirLCD_1020 = { - i2c_id = i2c.createSoft(0, 1), - pin_rst = 28, - pin_int = 7 - } -} - ---[[ -璁剧疆娑堟伅鍙戝竷鐘舵 -@api extp.set_publish_enabled(msg_type, enabled) -@string msg_type 娑堟伅绫诲瀷锛屾敮鎸"ALL"鎴栧叿浣撲簨浠剁被鍨 -@bool enabled 鏄惁鍚敤鍙戝竷 -@return bool 鎿嶄綔鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage --- 鍚敤鍗曞嚮浜嬩欢 -extp.set_publish_enabled("SINGLE_TAP", true) - --- 绂佺敤鎵鏈夋秷鎭彂甯 -extp.set_publish_enabled("ALL", false) -]] -function extp.set_publish_enabled(msg_type, enabled) - if msg_type == "ALL" then - for k, _ in pairs(publish_control) do - publish_control[k] = enabled - end - log.info("extp", "鎵鏈夋秷鎭彂甯", enabled and "鍚敤" or "绂佺敤") - return true - elseif publish_control[msg_type] ~= nil then - publish_control[msg_type] = enabled - log.info("extp", msg_type, "娑堟伅鍙戝竷", enabled and "鍚敤" or "绂佺敤") - return true - else - log.error("extp", "鏈煡鐨勬秷鎭被鍨:", msg_type) - return false - end -end - ---[[ -鑾峰彇娑堟伅鍙戝竷鐘舵 -@api extp.get_publish_enable(msg_type) -@string msg_type 娑堟伅绫诲瀷锛"ALL"鎴栧叿浣撲簨浠剁被鍨 -@return bool|table 鍙戝竷鐘舵佹垨鎵鏈夌姸鎬佽〃 -@usage --- 鑾峰彇鍗曞嚮浜嬩欢鐘舵 -local enabled = extp.get_publish_enable("SINGLE_TAP") - --- 鑾峰彇鎵鏈夌姸鎬 -local all_status = extp.get_publish_enable("ALL") -]] -function extp.get_publish_enable(msg_type) - if msg_type == "ALL" then - -- 杩斿洖瀹屾暣鐨勫彂甯冩帶鍒惰〃 - return publish_control - elseif publish_control[msg_type] ~= nil then - return publish_control[msg_type] - else - log.error("extp", "鏈煡鐨勬秷鎭被鍨:", msg_type) - return nil - end -end - ---[[ -璁剧疆婊戝姩鍒ゅ畾闃堝 -@api extp.set_swipe_threshold(threshold) -@number threshold 婊戝姩鍒ゅ畾闃堝硷紙鍍忕礌锛 -@return bool 璁剧疆鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage --- 璁剧疆婊戝姩闃堝间负50鍍忕礌 -extp.set_swipe_threshold(50) -]] -function extp.set_swipe_threshold(threshold) - if type(threshold) == "number" and threshold > 0 then - swipe_threshold = threshold - log.info("extp", "婊戝姩鍒ゅ畾闃堝艰缃负:", threshold) - return true - else - log.error("extp", "鏃犳晥鐨勬粦鍔ㄩ槇鍊:", threshold) - return false - end -end - ---[[ -璁剧疆闀挎寜鍒ゅ畾闃堝 -@api extp.set_long_press_threshold(threshold) -@number threshold 闀挎寜鍒ゅ畾闃堝硷紙姣锛 -@return bool 璁剧疆鎴愬姛杩斿洖true锛屽け璐ヨ繑鍥瀎alse -@usage --- 璁剧疆闀挎寜闃堝间负800姣 -extp.set_long_press_threshold(800) -]] -function extp.set_long_press_threshold(threshold) - if type(threshold) == "number" and threshold > 0 then - long_press_threshold = threshold - log.info("extp", "闀挎寜鍒ゅ畾闃堝艰缃负:", threshold) - return true - else - log.error("extp", "鏃犳晥鐨勯暱鎸夐槇鍊:", threshold) - return false - end -end - --- 瑙︽懜鍥炶皟鍑芥暟 --- 鍙傛暟: tp_device-瑙︽懜璁惧瀵硅薄, tp_data-瑙︽懜鏁版嵁 -local function tp_callback(tp_device, tp_data) - -- 鍙戝竷鍘熷鏁版嵁 - if publish_control.RAW_DATA then - sys.publish("BASE_TOUCH_EVENT", "RAW_DATA", tp_device, tp_data) - end - - if type(tp_data[1]) ~= "table" then return end - - local event_type = tp_data[1].event - local x = tp_data[1].x - local y = tp_data[1].y - -- 鑾峰彇楂樼簿搴︽椂闂存埑 - local _, ms_l = mcu.ticks2(1) - -- 浣跨敤绯荤粺鏃堕棿鎴虫垨瑙︽懜鏁版嵁涓殑鏃堕棿鎴 - local timestamp = ms_l or tp_data[1].timestamp - if not event_type then return end - - if event_type == 2 then -- 鎶墜浜嬩欢 - if state == "DOWN" or state == "MOVE" then - local moveX = x - touch_down_x - local moveY = y - touch_down_y - - if moveX < -swipe_threshold then - if publish_control.SWIPE_LEFT then - sys.publish("BASE_TOUCH_EVENT", "SWIPE_LEFT", moveX, 0) - end - elseif moveX > swipe_threshold then - if publish_control.SWIPE_RIGHT then - sys.publish("BASE_TOUCH_EVENT", "SWIPE_RIGHT", moveX, 0) - end - elseif moveY < -swipe_threshold then - if publish_control.SWIPE_UP then - sys.publish("BASE_TOUCH_EVENT", "SWIPE_UP", 0, moveY) - end - elseif moveY > swipe_threshold then - if publish_control.SWIPE_DOWN then - sys.publish("BASE_TOUCH_EVENT", "SWIPE_DOWN", 0, moveY) - end - else - -- 璁＄畻鎸変笅鏃堕棿 - local press_time = timestamp - touch_down_time - - -- 鍒ゆ柇鏄崟鍑昏繕鏄暱鎸 - if press_time < long_press_threshold then - if publish_control.SINGLE_TAP then - sys.publish("BASE_TOUCH_EVENT", "SINGLE_TAP", touch_down_x, touch_down_y) - end - else - if publish_control.LONG_PRESS then - sys.publish("BASE_TOUCH_EVENT", "LONG_PRESS", touch_down_x, touch_down_y) - end - end - end - state = "IDLE" - end - elseif event_type == 1 or event_type == 3 then -- 鎸変笅鎴栫Щ鍔ㄤ簨浠 - if state == "IDLE" and event_type == 1 then - -- 浠庣┖闂茬姸鎬佹帴鏀跺埌鎸変笅浜嬩欢 - state = "DOWN" - touch_down_x = x - touch_down_y = y - touch_down_time = timestamp - swipe_direction = nil - - -- 鍙戝竷鎸変笅浜嬩欢 - if publish_control.TOUCH_DOWN then - sys.publish("BASE_TOUCH_EVENT", "TOUCH_DOWN", x, y) - end - elseif state == "DOWN" and event_type == 3 then - -- 鍦ㄦ寜涓嬬姸鎬佷笅鎺ユ敹鍒扮Щ鍔ㄤ簨浠 - if math.abs(x - touch_down_x) >= swipe_threshold or math.abs(y - touch_down_y) >= swipe_threshold then - state = "MOVE" - -- 纭畾婊戝姩鏂瑰悜 - if math.abs(x - touch_down_x) > math.abs(y - touch_down_y) then - -- 姘村钩婊戝姩 - if x - touch_down_x < 0 then - swipe_direction = "LEFT" - else - swipe_direction = "RIGHT" - end - else - -- 鍨傜洿婊戝姩 - if y - touch_down_y < 0 then - swipe_direction = "UP" - else - swipe_direction = "DOWN" - end - end - end - elseif state == "MOVE" and event_type == 3 then - -- 鍦ㄧЩ鍔ㄧ姸鎬佷笅鎺ユ敹鍒扮Щ鍔ㄤ簨浠 - -- 鏍规嵁婊戝姩鏂瑰悜鍙戝竷鐩稿簲鐨勭Щ鍔ㄤ簨浠 - if swipe_direction == "LEFT" or swipe_direction == "RIGHT" then - -- 姘村钩婊戝姩锛屽彂甯僊OVE_X浜嬩欢 - if publish_control.MOVE_X then - sys.publish("BASE_TOUCH_EVENT", "MOVE_X", x - touch_down_x, 0) - end - else - -- 鍨傜洿婊戝姩锛屽彂甯僊OVE_Y浜嬩欢 - if publish_control.MOVE_Y then - sys.publish("BASE_TOUCH_EVENT", "MOVE_Y", 0, y - touch_down_y) - end - end - end - end -end - ---[[ -鍒濆鍖栬Е鎽歌澶 -@api extp.init(param) -@table param 瑙︽懜鑺墖閰嶇疆鍙傛暟锛屽弬鑰冨簱鐨勮鏄庡強demo鐢ㄦ硶 -@return bool 鍒濆鍖栨垚鍔熻繑鍥瀟rue锛屽け璐ヨ繑鍥瀎alse -@usage --- 鍩虹瑙︽懜鍒濆鍖 -extp.init({ - tp_model = "gt911", - i2c_id = 0, - pin_rst = 20, - pin_int = 21 -}) - --- 浣跨敤棰勫畾涔夐厤缃 -extp.init({tp_model = "AirLCD_1010"}) - --- 甯﹀睆骞曞昂瀵哥殑鍒濆鍖 -extp.init({ - tp_model = "gt911", - i2c_id = 0, - pin_rst = 20, - pin_int = 21, - w = 480, - h = 320 -}) -]] -function extp.init(param) - if type(param) ~= "table" then - log.error("extp", "鍙傛暟蹇呴』涓鸿〃") - return false - end - - -- 妫鏌ュ繀瑕佸弬鏁 - if not param.tp_model then - log.error("extp", "缂哄皯蹇呰鍙傛暟: tp_model") - return false - end - - local tp_model = param.tp_model - - -- 妫鏌ユ槸鍚︽敮鎸佽鍨嬪彿 - local config = tp_configs[tp_model] - if not config then - log.error("extp", "涓嶆敮鎸佺殑瑙︽懜鍨嬪彿:", tp_model) - return false - end - - -- 鐗规畩鍨嬪彿鍙傛暟澶勭悊 - local final_param = {} - final_param.tp_model = tp_model - - -- 澶勭悊鐗规畩鍨嬪彿鐨勯粯璁ら厤缃 - if special_tp_configs[tp_model] then - local default_config = special_tp_configs[tp_model] - - if tp_model == "Air780EHM_LCD_4" then - -- Air780EHM_LCD_4: 寮哄埗浣跨敤榛樿閰嶇疆锛屽拷鐣ヤ紶鍏ョ殑鍏朵粬鍙傛暟 - final_param.i2c_id = default_config.i2c_id - final_param.pin_rst = default_config.pin_rst - final_param.pin_int = default_config.pin_int - log.info("extp", "Air780EHM_LCD_4浣跨敤鍥哄畾閰嶇疆") - else - -- AirLCD_1010 鍜 AirLCD_1020: 浣跨敤浼犲叆鍙傛暟锛屽鏋滄湭浼犲叆鍒欎娇鐢ㄩ粯璁ら厤缃 - final_param.i2c_id = param.i2c_id or default_config.i2c_id - final_param.pin_rst = param.pin_rst or default_config.pin_rst - final_param.pin_int = param.pin_int or default_config.pin_int - - -- 璁板綍浣跨敤鐨勯厤缃潵婧 - if param.i2c_id then - log.info("extp", tp_model, "浣跨敤浼犲叆鐨刬2c_id") - else - log.info("extp", tp_model, "浣跨敤榛樿i2c_id") - end - - if param.pin_rst then - log.info("extp", tp_model, "浣跨敤浼犲叆鐨刾in_rst") - else - log.info("extp", tp_model, "浣跨敤榛樿pin_rst") - end - - if param.pin_int then - log.info("extp", tp_model, "浣跨敤浼犲叆鐨刾in_int") - else - log.info("extp", tp_model, "浣跨敤榛樿pin_int") - end - end - else - -- 鍏朵粬鍨嬪彿锛氱洿鎺ヤ娇鐢ㄤ紶鍏ュ弬鏁 - final_param.i2c_id = param.i2c_id - final_param.pin_rst = param.pin_rst - final_param.pin_int = param.pin_int - end - - local tp_i2c_id, tp_pin_rst, tp_pin_int = final_param.i2c_id, final_param.pin_rst or 255, final_param.pin_int - - -- 鏋勫缓tp.init鐨勫弬鏁拌〃锛屽鍔爓鍜宧鍙夊弬鏁 - local tp_init_params = { - port = tp_i2c_id, - pin_rst = tp_pin_rst, - pin_int = tp_pin_int - } - - -- 濡傛灉浼犲叆浜唚鍜宧鍙傛暟锛屽垯娣诲姞鍒板弬鏁拌〃涓 - if param.w then - tp_init_params.w = param.w - log.info("extp", "璁剧疆灞忓箷瀹藉害:", param.w) - end - - if param.h then - tp_init_params.h = param.h - log.info("extp", "璁剧疆灞忓箷楂樺害:", param.h) - end - - -- 缁熶竴鍒濆鍖栨祦绋 - if type(tp_i2c_id) ~= "userdata" and config.i2c_speed ~= nil then - i2c.setup(tp_i2c_id, config.i2c_speed) - end - - -- 浣跨敤鍖呭惈w鍜宧鍙傛暟鐨則able璋冪敤tp.init - local tp_device = tp.init(config.tp_model, tp_init_params, tp_callback) - if tp_device ~= nil then return true end - - if tp_device == nil then - -- 濡傛灉绗竴娆″垵濮嬪寲澶辫触锛屽皾璇曚笉甯in_rst鐨勫垵濮嬪寲 - tp_init_params.pin_rst = 255 - local tp_device = tp.init(config.tp_model, tp_init_params, tp_callback) - - if tp_device ~= nil then return true end - end - - -- 鑻ョ‖浠惰Е鎽稿垵濮嬪寲澶辫触锛屽皾璇昉C瑙︽懜鍥為 - log.warn("extp", "瑙︽懜鍒濆鍖栧け璐ワ紝灏濊瘯PC瑙︽懜鍥為") - local ok_pc, dev_pc = pcall(tp.init, "pc", { port = 0 }, tp_callback) - if ok_pc and dev_pc then - log.info("extp", "PC瑙︽懜鍥為鎴愬姛") - return true - end - log.error("extp", "PC瑙︽懜鍥為澶辫触") - return false -end - -return extp \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib.lua deleted file mode 100644 index 76e772b..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib.lua +++ /dev/null @@ -1,313 +0,0 @@ ---[[ -@module exvib -@summary exvib 涓夎酱鍔犻熷害浼犳劅鍣ㄦ墿灞曞簱 -@version 1.0 -@date 2025.08.10 -@author 鏉庢簮榫 -@usage --- 鐢ㄦ硶瀹炰緥 -娉ㄦ剰: - -1. exvib.lua鍙傜敤浜庡悎瀹欏唴閮ㄩ泦鎴愪簡G-Sensor鍔犻熷害浼犳劅鍣―A221鐨勬ā缁勫瀷鍙凤紝 -鐩墠浠呮湁Air8000绯诲垪妯＄粍鍐呯疆浜咲A221锛孉ir7000鎺ㄥ嚭鏃朵篃浼氬唴缃鍨嬪彿G-Sensor锛 - -2. DA221鍦ˋir8000鍐呴儴閫氳繃I2C1涓庝箣閫氫俊锛屽苟閫氳繃WAKEUP2鎺ユ敹杩愬姩鐩戞祴涓柇锛 -濡傛偍浣跨敤鍚堝畽鍏跺畠鍨嬪彿妯＄粍澶栨帴DA221鏃讹紝姣斿Air780EGH锛屽缓璁笌Air8000淇濇寔涓鑷翠篃閫夌敤I2C1鍜學AKEUP2 -(璇ョ鑴氬嵆涓篈ir780EGH鐨凱IN79:USIM_DET)锛岃繖鏍蜂究鍙互鏃犵紳浣跨敤鏈墿灞曞簱锛孌A221鐨勪緵搴斿晢涓鸿嫃宸炴槑鐨 -濡傞渶閲囪喘DA221鎴栬呭叾浠栨洿楂樼鐨勫姞閫熷害浼犳劅鍣ㄥ彲浠ヨ仈绯讳粬浠紱 - -3. DA221浣滀负鍔犻熷害浼犳劅鍣紝LuatOS浠呮敮鎸佽繍鍔ㄦ娴嬭繖涓鍔熻兘锛屼富瑕佺敤浜庨渿鍔ㄦ娴嬶紝杩愬姩妫娴嬶紝璺屽掓娴嬶紝 -鎼厤GNSS瀹炵幇闇囧姩鐒跺悗瀹氫綅鐨勫姛鑳斤紝鍏朵綑鍔熻兘璇疯嚜琛岀爺绌讹紝鍚堝畽鎻愪緵浜嗕笁绉嶅簲鐢ㄥ満鏅紝濡傛灉闇瑕侀傞厤鑷繁鐨勫満鏅渶姹傦紝 -璇峰弬鑰冩墜鍐屽弬鏁拌嚜琛屼慨鏀逛唬鐮侊紝璋冭瘯閫傚悎鑷繁鍦烘櫙鐨勪紶鎰熷櫒鍊硷紝鍚堝畽涓嶆彁渚汥A221浠讳綍鍏跺畠鍔熻兘鐨勪换浣曞舰寮忕殑鎶鏈敮鎸侊紱 - -鍏充簬exvib搴撶殑涓夌妯″紡涓昏鐢ㄤ簬浠ヤ笅鍦烘櫙锛 -1锛屽井灏忛渿鍔ㄦ娴嬶紝鐢ㄤ簬妫娴嬭交寰渿鍔ㄧ殑鍦烘櫙锛屼緥濡傜敤鎵嬫暡鍑绘闈紱鍔犻熷害閲忕▼2g锛 -2锛岃繍鍔ㄦ娴嬶紝鐢ㄤ簬鐢靛姩杞︽垨姹借溅琛岄┒鏃剁殑妫娴嬪拰浜鸿璧板拰璺戞鏃剁殑妫娴嬶紱鍔犻熷害閲忕▼4g锛 -3锛岃穼鍊掓娴嬶紝鐢ㄤ簬浜烘垨鐗╀綋鐬棿璺屽掓椂鐨勬娴嬶紱鍔犻熷害閲忕▼8g锛 - -exvib=require("exvib") - -local intPin=gpio.WAKEUP2 --涓柇妫娴嬭剼锛屽唴閮ㄥ浐瀹歸akeup2 -local tid --鑾峰彇瀹氭椂鎵撳紑鐨勫畾鏃跺櫒id -local num=0 --璁℃暟鍣 -local ticktable={0,0,0,0,0} --瀛樻斁5娆′腑鏂殑tick鍊硷紝鐢ㄤ簬鍋氭湁鏁堥渿鍔ㄥ姣 -local eff=false --鏈夋晥闇囧姩鏍囧織浣嶏紝鐢ㄤ簬鍒ゆ柇鏄惁瑙﹀彂瀹氫綅 - - ---鏈夋晥闇囧姩妯″紡 ---tick璁℃暟鍣紝姣忕+1鐢ㄤ簬瀛樻斁5娆′腑鏂殑tick鍊硷紝鐢ㄤ簬鍋氭湁鏁堥渿鍔ㄥ姣 --- local function tick() --- num=num+1 --- end --- --姣忕杩愯涓娆¤鏃 --- sys.timerLoopStart(tick,1000) - --- --鏈夋晥闇囧姩鍒ゆ柇 --- local function ind() --- log.info("int", gpio.get(intPin)) --- if gpio.get(intPin) == 1 then --- --鎺ユ敹鏁版嵁濡傛灉澶т簬5灏卞垹鎺夌涓涓 --- if #ticktable>=5 then --- log.info("table.remove",table.remove(ticktable,1)) --- end --- --瀛樺叆鏂扮殑tick鍊 --- table.insert(ticktable,num) --- log.info("tick",num,(ticktable[5]-ticktable[1]<10),ticktable[5]>0) --- log.info("tick2",ticktable[1],ticktable[2],ticktable[3],ticktable[4],ticktable[5]) --- --琛ㄩ暱搴︿负5涓旓紝绗5娆′腑鏂椂闂撮棿闅斿噺鍘荤涓娆￠棿闅斿皬浜10s锛屼笖绗5娆″间负鏈夋晥鍊 --- if #ticktable>=5 and (ticktable[5]-ticktable[1]<10 and ticktable[1]>0) then --- log.info("vib", "xxx") --- --鏄惁瑕佸幓瑙﹀彂鏈夋晥闇囧姩閫昏緫 --- if eff==false then --- sys.publish("EFFECTIVE_VIBRATION") --- end --- end --- end --- end - --- --璁剧疆30s鍒嗛挓涔嬪悗鍐嶅垽鏂槸鍚︽湁鏁堥渿鍔ㄥ嚱鏁 --- local function num_cb() --- eff=false --- end - --- local function eff_vib() --- --瑙﹀彂涔嬪悗eff璁剧疆涓簍rue锛30鍒嗛挓涔嬪悗鍐嶈Е鍙戞湁鏁堥渿鍔 --- eff=true --- --30鍒嗛挓涔嬪悗鍐嶈Е鍙戞湁鏁堥渿鍔 --- sys.timerStart(num_cb,180000) --- end - --- sys.subscribe("EFFECTIVE_VIBRATION",eff_vib) - - - ---鎸佺画闇囧姩妯″紡 - ---鎸佺画闇囧姩妯″紡涓柇鍑芥暟 -local function ind() - log.info("int", gpio.get(intPin)) - --涓婂崌娌夸负瑙﹀彂闇囧姩涓柇 - if gpio.get(intPin) == 1 then - local x,y,z = exvib.read_xyz() --璇诲彇x锛寉锛寊杞寸殑鏁版嵁 - log.info("x", x..'g', "y", y..'g', "z", z..'g') - end -end - - -local function vib_fnc() - -- 1锛屽井灏忛渿鍔ㄦ娴嬶紝鐢ㄤ簬妫娴嬭交寰渿鍔ㄧ殑鍦烘櫙锛屼緥濡傜敤鎵嬫暡鍑绘闈紱鍔犻熷害閲忕▼2g锛 - -- 2锛岃繍鍔ㄦ娴嬶紝鐢ㄤ簬鐢靛姩杞︽垨姹借溅琛岄┒鏃剁殑妫娴嬪拰浜鸿璧板拰璺戞鏃剁殑妫娴嬶紱鍔犻熷害閲忕▼4g锛 - -- 3锛岃穼鍊掓娴嬶紝鐢ㄤ簬浜烘垨鐗╀綋鐬棿璺屽掓椂鐨勬娴嬶紱鍔犻熷害閲忕▼8g锛 - --鎵撳紑闇囧姩妫娴嬪姛鑳 - exvib.open(1) - --璁剧疆gpio闃叉姈100ms - gpio.debounce(intPin, 100) - --璁剧疆gpio涓柇瑙﹀彂鏂瑰紡wakeup2鍞ら啋鑴氶粯璁や负鍙岃竟娌胯Е鍙 - gpio.setup(intPin, ind) - -end - -sys.taskInit(vib_fnc) - -]] -local exvib={} -local i2cId=0 -local bsp=rtos.bsp() -if bsp:find("780") then - i2cId = 1 -end -local da221Addr = 0x27 -local soft_reset = {0x00, 0x24} -- 杞欢澶嶄綅鍦板潃 -local chipid_addr = 0x01 -- 鑺墖ID鍦板潃 -local rangeaddr = {0x0f, 0x00} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁2g --- local rangeaddr = {0x0f, 0x01} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁4g --- local rangeaddr = {0x0f, 0x10} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁8g -local int_set1_reg = {0x16, 0x87} --璁剧疆x,y,z鍙戠敓鍙樺寲鏃讹紝浜х敓涓柇 -local int_set2_reg = {0x17, 0x10} --浣胯兘鏂版暟鎹腑鏂紝鏁版嵁鍙樺寲鏃讹紝浜х敓涓柇锛屾湰绋嬪簭涓嶈缃 -local int_map1_reg = {0x19, 0x04} --杩愬姩鐨勬椂鍊欙紝浜х敓涓柇 -local int_map2_reg = {0x1a, 0x01} - -local active_dur_addr = {0x27, 0x01} -- 璁剧疆婵娲绘椂闂达紝榛樿0x01 -local active_ths_addr = {0x28, 0x33} -- 璁剧疆婵娲婚槇鍊硷紝鐏垫晱搴︽渶楂 --- local active_ths_addr = {0x28, 0x80} -- 璁剧疆婵娲婚槇鍊硷紝鐏垫晱搴﹂備腑 --- local active_ths_addr = {0x28, 0xFE} -- 璁剧疆婵娲婚槇鍊硷紝鐏垫晱搴︽渶浣 -local odr_addr = {0x10, 0x08} -- 璁剧疆閲囨牱鐜 100Hz -local mode_addr = {0x11, 0x00} -- 璁剧疆姝ｅ父妯″紡 -local int_latch_addr = {0x21, 0x02} -- 璁剧疆涓柇閿佸瓨 - -local x_lsb_reg = 0x02 -- X杞碙SB瀵勫瓨鍣ㄥ湴鍧 -local x_msb_reg = 0x03 -- X杞碝SB瀵勫瓨鍣ㄥ湴鍧 -local y_lsb_reg = 0x04 -- Y杞碙SB瀵勫瓨鍣ㄥ湴鍧 -local y_msb_reg = 0x05 -- Y杞碝SB瀵勫瓨鍣ㄥ湴鍧 -local z_lsb_reg = 0x06 -- Z杞碙SB瀵勫瓨鍣ㄥ湴鍧 -local z_msb_reg = 0x07 -- Z杞碝SB瀵勫瓨鍣ㄥ湴鍧 - -local active_state = 0x0b -- 婵娲荤姸鎬佸瘎瀛樺櫒鍦板潃 -local active_state_data - -local rangemode=1 -local x_accel -local y_accel -local z_accel ---[[ - 鑾峰彇da221鐨剎yz杞存暟鎹 -@api exvib.read_xyz() -@return number x杞存暟鎹紝number y杞存暟鎹紝number z杞存暟鎹 -@usage - local x,y,z = exvib.read_xyz() --璇诲彇x锛寉锛寊杞寸殑鏁版嵁 - log.info("x", x..'g', "y", y..'g', "z", z..'g') -]] -function exvib.read_xyz() - -- da221鏄疞SB鍦ㄥ墠锛孧SB鍦ㄥ悗锛屾瘡涓瘎瀛樺櫒閮芥槸1瀛楄妭鏁版嵁锛屾瘡娆¤鍙栭兘鏄6涓瘎瀛樺櫒鏁版嵁涓璧疯幏鍙 - -- 鍥犳鐩存帴浠嶺杞碙SB瀵勫瓨鍣(0x02)寮濮嬭繛缁鍙6瀛楄妭鏁版嵁(X/Y/Z鍚2瀛楄妭)锛岄伩鍏嶅嚭鐜版暟鎹挄瑁傞棶棰 - i2c.send(i2cId, da221Addr, x_lsb_reg, 1) - local recv_data = i2c.recv(i2cId, da221Addr, 6) - - -- LSB鏁版嵁鏍煎紡涓: D[3] D[2] D[1] D[0] unused unused unused unused - -- MSB鏁版嵁鏍煎紡涓: D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] - -- 鏁版嵁浣嶄负12浣嶏紝闇瑕佸皢MSB鏁版嵁宸︾Щ4浣嶏紝LSB鏁版嵁鍙崇Щ4浣嶏紝鏈鍚庤繘琛屾垨杩愮畻 - -- 瑙ｆ瀽X杞存暟鎹 (LSB鍦ㄥ墠锛孧SB鍦ㄥ悗) - - local x_data = (string.byte(recv_data, 2) << 4) | (string.byte(recv_data, 1) >> 4) - - -- 瑙ｆ瀽Y杞存暟鎹 (LSB鍦ㄥ墠锛孧SB鍦ㄥ悗) - local y_data = (string.byte(recv_data, 4) << 4) | (string.byte(recv_data, 3) >> 4) - - -- 瑙ｆ瀽Z杞存暟鎹 (LSB鍦ㄥ墠锛孧SB鍦ㄥ悗) - local z_data = (string.byte(recv_data, 6) << 4) | (string.byte(recv_data, 5) >> 4) - - - -- 杞崲涓12浣嶆湁绗﹀彿鏁存暟 - -- 鍒ゆ柇X杞存暟鎹槸鍚﹀ぇ浜2047锛岃嫢澶т簬鍒欒〃绀烘暟鎹负璐熸暟 - -- 鍥犱负12浣嶆湁绗﹀彿鏁存暟鐨勮寖鍥存槸 -2048 鍒 2047锛屽師濮嬫暟鎹负鏃犵鍙峰舰寮忥紝澶т簬2047鐨勯儴鍒嗛渶瑕佽浆鎹负璐熸暟 - -- 閫氳繃鍑忓幓4096 (2^12) 灏嗘棤绗﹀彿鏁拌浆鎹负瀵瑰簲鐨勬湁绗﹀彿璐熸暟 - if x_data > 2047 then x_data = x_data - 4096 end - -- 鍒ゆ柇Y杞存暟鎹槸鍚﹀ぇ浜2047锛岃嫢澶т簬鍒欒繘琛屽悓鏍风殑鏈夌鍙疯浆鎹 - if y_data > 2047 then y_data = y_data - 4096 end - -- 鍒ゆ柇Z杞存暟鎹槸鍚﹀ぇ浜2047锛岃嫢澶т簬鍒欒繘琛屽悓鏍风殑鏈夌鍙疯浆鎹 - if z_data > 2047 then z_data = z_data - 4096 end - - -- 杞崲涓哄姞閫熷害鍊硷紙鍗曚綅锛歡锛 - - if rangemode == 1 then - x_accel = x_data / 1024 - y_accel = y_data / 1024 - z_accel = z_data / 1024 - - elseif rangemode == 2 then - x_accel = x_data / 512 - y_accel = y_data / 512 - z_accel = z_data / 512 - - elseif rangemode == 3 then - x_accel = x_data / 256 - y_accel = y_data / 256 - z_accel = z_data / 256 - else - x_accel = x_data / 1024 - y_accel = y_data / 1024 - z_accel = z_data / 1024 - end - - -- 杈撳嚭鍔犻熷害鍊硷紙鍗曚綅锛歡锛 - return x_accel, y_accel, z_accel -end - ---鍒濆鍖杁a221 -local function da221_init() - if bsp:find("780") then - gpio.setup(23, 1, gpio.PULLUP) -- gsensor 寮鍏 - else - gpio.setup(24, 1, gpio.PULLUP) -- gsensor 寮鍏 - end - --鍏抽棴i2c - i2c.close(i2cId) - --閲嶆柊鎵撳紑i2c,i2c閫熷害璁剧疆涓轰綆閫 - i2c.setup(i2cId, i2c.SLOW) - - sys.wait(50) - i2c.send(i2cId, da221Addr, soft_reset, 1) --澶嶄綅da221 - sys.wait(50) - i2c.send(i2cId, da221Addr, chipid_addr, 1) --璇诲彇鑺墖id - local chipid = i2c.recv(i2cId, da221Addr, 1) --鎺ユ敹杩斿洖鐨勮姱鐗噄d - log.info("i2c", "chipid",chipid:toHex()) - if string.byte(chipid) == 0x13 then - log.info("exvib init success") - else - log.info("exvib init fail") - end - -- 璁剧疆瀵勫瓨鍣 - i2c.send(i2cId, da221Addr, rangeaddr, 1) --璁剧疆鍔犻熷害閲忕▼锛岄粯璁2g - sys.wait(5) - i2c.send(i2cId, da221Addr, int_set1_reg, 1) --璁剧疆x,y,z鍙戠敓鍙樺寲鏃讹紝浜х敓涓柇 - sys.wait(5) - i2c.send(i2cId, da221Addr, int_map1_reg, 1)--杩愬姩鐨勬椂鍊欙紝浜х敓涓柇 - sys.wait(5) - i2c.send(i2cId, da221Addr, active_dur_addr, 1)-- 璁剧疆婵娲绘椂闂达紝榛樿0x00 - sys.wait(5) - i2c.send(i2cId, da221Addr, active_ths_addr, 1)-- 璁剧疆婵娲婚槇鍊 - sys.wait(5) - i2c.send(i2cId, da221Addr, mode_addr, 1)-- 璁剧疆妯″紡 - sys.wait(5) - i2c.send(i2cId, da221Addr, odr_addr, 1)-- 璁剧疆閲囨牱鐜 - sys.wait(5) - i2c.send(i2cId, da221Addr, int_latch_addr, 1)-- 璁剧疆涓柇閿佸瓨 涓柇涓鏃﹁Е鍙戝皢淇濇寔锛岀洿鍒版墜鍔ㄦ竻闄 - sys.wait(5) -end - ---[[ - 鎵撳紑da221 -@api exvib.open(mode) -@number da221妯″紡璁剧疆锛1锛屽井灏忛渿鍔ㄦ娴嬶紝鐢ㄤ簬妫娴嬭交寰渿鍔ㄧ殑鍦烘櫙锛屼緥濡傜敤鎵嬫暡鍑绘闈紱鍔犻熷害閲忕▼2g锛 - 2锛岃繍鍔ㄦ娴嬶紝鐢ㄤ簬鐢靛姩杞︽垨姹借溅琛岄┒鏃剁殑妫娴嬪拰浜鸿璧板拰璺戞鏃剁殑妫娴嬶紱鍔犻熷害閲忕▼4g锛 - 3锛岃穼鍊掓娴嬶紝鐢ㄤ簬浜烘垨鐗╀綋鐬棿璺屽掓椂鐨勬娴嬶紱鍔犻熷害閲忕▼8g锛 -@return nil 鏃犺繑鍥炲 -@usage - exvib.open(1) -]] -function exvib.open(mode) - rangemode=mode - if mode==1 or tonumber(mode)==1 then - --杞诲井妫娴 - log.info("杞诲井妫娴") - rangeaddr = {0x0f, 0x00} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁2g - active_ths_addr = {0x28, 0x33} -- 璁剧疆婵娲婚槇鍊 - odr_addr = {0x10, 0x04} -- 璁剧疆閲囨牱鐜 15.63Hz - active_dur_addr = {0x27, 0x01} -- 璁剧疆婵娲绘椂闂 - elseif mode==2 or tonumber(mode)==2 then - --甯歌妫娴 - log.info("杩愬姩妫娴") - rangeaddr = {0x0f, 0x01} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁4g - active_ths_addr = {0x28, 0x26} -- 璁剧疆婵娲婚槇鍊 - odr_addr = {0x10, 0x08} -- 璁剧疆閲囨牱鐜 250Hz - active_dur_addr = {0x27, 0x14} -- 璁剧疆婵娲绘椂闂 - elseif mode==3 or tonumber(mode)==3 then - log.info("楂樺姩鎬佹娴") - --楂樺姩鎬佹娴 - rangeaddr = {0x0f, 0x02} -- 璁剧疆鍔犻熷害閲忕▼锛岄粯璁8g - active_ths_addr = {0x28, 0x80} -- 璁剧疆婵娲婚槇鍊 - odr_addr = {0x10, 0x0F} -- 璁剧疆閲囨牱鐜 1000Hz - active_dur_addr = {0x27, 0x04} -- 璁剧疆婵娲绘椂闂 - end - sys.taskInit(da221_init) -end - ---[[ - 鍏抽棴da221 -@api exvib.close() -@return nil 鏃犺繑鍥炲 -@usage - exvib.close() -]] -function exvib.close() - if bsp:find("780") then - gpio.close(23) -- gsensor渚涚數鍏抽棴 - else - gpio.close(24) -- gsensor渚涚數鍏抽棴 - end - gpio.close(24) -- gsensor渚涚數鍏抽棴 - log.info("exvib close..") -end - - -return exvib \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib1.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib1.lua deleted file mode 100644 index 9b9e974..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/exvib1.lua +++ /dev/null @@ -1,211 +0,0 @@ ---[[ -@summary exvib1鎵╁睍搴 -@version 1.0 -@date 2025.09.07 -@author 瀛熶紵 -@usage --- 搴旂敤鍦烘櫙 -姝ゅ簱閫傜敤浜庢粴鐝犻渿鍔ㄤ紶鎰熷櫒BL_2529,涓昏鐩殑鏄鎸姩涓柇杩涜杩囨护锛岃瘑鍒湁鏁堥渿鍔 -瀵逛簬涓浜涢渿鍔ㄤ紶鎰熷櫒鐨勪腑鏂鑴氱畻娉曞鐞嗭紝涔熷彲浠ョ敤鍋氬弬鑰冦 - -瀹炵幇鐨勫姛鑳斤細 -1. GPIO 涓柇妫娴嬶細閫氳繃 GPIO 寮曡剼妫娴嬮渿鍔ㄤ紶鎰熷櫒浜х敓鐨勮剦鍐蹭俊鍙 -2. 鍙岄噸娑堟姈鏈哄埗锛 - - io涓柇娑堟姈 gpio.debounce() -3. 鏃堕棿绐楀彛妫娴嬶細鍦ㄦ寚瀹氭椂闂寸獥鍙(time_window)鍐呯粺璁¤剦鍐叉暟閲 -4. 闃堝艰Е鍙戯細褰撹剦鍐叉暟瓒呰繃璁惧畾闃堝(pulse_threshold)鏃惰Е鍙戝洖璋 -5. 鑴夊啿瓒呮椂鏈哄埗锛氬湪妫娴嬬姸鎬佷笅锛屽鏋滆秴杩噋ulse_timeout鏃堕棿娌℃湁鏂扮殑鑴夊啿锛屽垯鎻愬墠缁撴潫褰撳墠妫娴嬪懆鏈熷苟鍒ゆ柇鏄惁瑙﹀彂鍥炶皟 - -鐘舵佹満宸ヤ綔娴佺▼锛 -- IDLE鐘舵侊細绛夊緟绗竴涓湁鏁堣剦鍐 -- DETECTING鐘舵侊細杩涘叆妫娴嬬獥鍙ｏ紝缁熻鑴夊啿鏁伴噺 -- 瑙﹀彂鏉′欢锛 -鏃堕棿绐楀彛缁撴潫 -鑴夊啿绌洪棽鏃堕棿瓒呰繃璁惧畾瓒呮椂 -- 缁撴灉鍒ゆ柇锛氳剦鍐叉暟鈮ラ槇鍊煎垯璋冪敤鐢ㄦ埛鍥炶皟 - --- 鐢ㄦ硶瀹炰緥 -鏈墿灞曞簱瀵瑰鎻愪緵浜嗕互涓2涓帴鍙ｏ細 -1锛夊惎鍔ㄩ渿鍔ㄦ娴嬪姛鑳 exvib1.open(opts) -2锛夊仠姝㈤渿鍔ㄦ娴嬪姛鑳 exvib1.close() - ---鍔犺浇exvib1鎵╁睍搴 -local exvib1= require "exvib1" - --- 闇囧姩浜嬩欢鍥炶皟 -local function vibration_cb(pulse_cnt) - log.info("VIB", "detected! pulses =", pulse_cnt) -end ---婕旂ず鏈绠鍗曠殑浣跨敤鏂规硶锛岄兘浣跨敤榛樿閰嶇疆 -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, -}) - - -浠ヤ笅涓篹xvib1鎵╁睍搴撲袱涓嚱鏁扮殑璇︾粏璇存槑鍙婁唬鐮佸疄鐜帮細 -]] - -local exvib1 = {} - --- 榛樿閰嶇疆 -local cfg = { - gpio_pin = nil, -- 浼犳劅鍣ㄤ腑鏂墍鎺 GPIO - pull = gpio.PULLUP, - trigger = gpio.RISING, - debounce_irq = 100, -- gpio娑堟姈鏃堕棿锛実pio.debounce 鏃堕棿(ms) - time_window = 1000, -- 妫娴嬬獥鍙(ms) - pulse_threshold = 3, -- 瑙﹀彂闃堝 - pulse_timeout = 200, -- 鑴夊啿瓒呮椂(ms) - poll_interval = 10, -- 鐘舵佹満杞(ms) - on_event = nil, -- 鐢ㄦ埛鍥炶皟 -} - --- 鍐呴儴鐘舵 -local st = { - pulse_cnt = 0, - last_valid = 0, - detect_t0 = 0, - state = "IDLE", -} - --- 閲嶇疆鍐呴儴鐘舵侊紝灏嗙姸鎬佹満缃负绌洪棽鐘舵佸苟娓呴浂鑴夊啿璁℃暟 -local function reset() - st.state = "IDLE" - st.pulse_cnt = 0 -end - --- GPIO 涓柇澶勭悊鍑芥暟锛岀敤浜庡鐞嗕紶鎰熷櫒鐨勮剦鍐蹭俊鍙 -local function isr() - local now = mcu.ticks() - st.pulse_cnt = st.pulse_cnt + 1 - st.last_valid = now - -- 濡傛灉褰撳墠鐘舵佷负绌洪棽鐘舵 - if st.state == "IDLE" then - -- 鍒囨崲鍒版娴嬬姸鎬 - st.state = "DETECTING" - -- 璁板綍妫娴嬪紑濮嬫椂闂 - st.detect_t0 = now - end -end - --- 鐘舵佹満澶勭悊鍑芥暟锛岀敤浜庢娴嬫槸鍚︽弧瓒抽渿鍔ㄨЕ鍙戞潯浠 -local function fsm() - -- 濡傛灉褰撳墠鐘舵佷笉鏄娴嬬姸鎬侊紝鍒欑洿鎺ヨ繑鍥 - if st.state ~= "DETECTING" then return end - local now = mcu.ticks() - -- 澶勭悊鏃堕棿鎴虫孩鍑烘儏鍐 - if now < st.detect_t0 or now < st.last_valid then - st.detect_t0 = 0 - st.last_valid = 0 - return -- 绛夊緟涓嬫璋冪敤閲嶆柊鍒ゆ柇 - end - - -- 璁＄畻浠庢娴嬪紑濮嬪埌鐜板湪缁忚繃鐨勬椂闂 - local elapsed = now - st.detect_t0 - -- 鍒ゆ柇鏄惁鑴夊啿绌洪棽鏃堕棿杩囬暱 - local idle_too_long = (now - st.last_valid) >= cfg.pulse_timeout - -- 褰撴娴嬬獥鍙ｇ粨鏉熸垨鑰呰剦鍐茬┖闂叉椂闂磋繃闀挎椂 - if elapsed >= cfg.time_window or idle_too_long then - -- 妫鏌ヨ剦鍐茶鏁版槸鍚﹁揪鍒拌Е鍙戦槇鍊硷紝骞朵笖鐢ㄦ埛鍥炶皟鍑芥暟瀛樺湪 - if st.pulse_cnt >= cfg.pulse_threshold and st.on_event then - -- 璋冪敤鐢ㄦ埛鍥炶皟鍑芥暟骞朵紶鍏ヨ剦鍐茶鏁板 - st.on_event(st.pulse_cnt) - end - -- 閲嶇疆鍐呴儴鐘舵 - reset() - end -end ---[[ -鍚姩闇囧姩妫娴嬪姛鑳 -@api exvib1.open(opts) -@table opts 閰嶇疆鍙傛暟琛紝鐢ㄤ簬鑷畾涔夐渿鍔ㄦ娴嬪姛鑳界殑鍚勯」灞炴с -@return nil 鏃犺繑鍥炲 -@usage --- 閰嶇疆鍙傛暟浠嬬粛 ---local otps = { --- gpio_pin --"浼犳劅鍣ㄤ腑鏂墍鎺 GPIO 寮曡剼鍙凤紝榛樿鍊间负 nil", --- pull --"涓婃媺/涓嬫媺妯″紡锛屽彲閫 gpio.PULLUP 鎴 gpio.PULLDOWN锛岄粯璁ゅ间负 gpio.PULLUP", --- trigger --"瑙﹀彂鏂瑰紡锛屽彲閫 gpio.RISING 鎴 gpio.FALLING锛岄粯璁ゅ间负 gpio.RISING", --- debounce_irq --"GPIO 娑堟姈鏃堕棿锛屽崟浣嶄负姣锛岄粯璁ゅ间负 100", --- time_window --"妫娴嬬獥鍙ｆ椂闂达紝鍗曚綅涓烘绉掞紝榛樿鍊间负 1000", --- pulse_threshold --"瑙﹀彂闃堝硷紝鍗宠繛缁剦鍐叉鏁帮紝榛樿鍊间负 3", --- pulse_timeout --"鑴夊啿瓒呮椂鏃堕棿锛屽崟浣嶄负姣锛岄粯璁ゅ间负 200", --- poll_interval --"鐘舵佹満杞鏃堕棿锛屽崟浣嶄负姣锛岄粯璁ゅ间负 10", --- on_event --"鐢ㄦ埛鍥炶皟鍑芥暟锛岀敤浜庡鐞嗘娴嬪埌鐨勯渿鍔ㄤ簨浠讹紝榛樿鍊间负 nil", ---} --- 闇囧姩浜嬩欢鍥炶皟 -local function vibration_cb(pulse_cnt) - log.info("VIB", "detected! pulses =", pulse_cnt) -end -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, -}) ---涓嶅悓鍦烘櫙涓嬬殑鍙傛暟閰嶇疆鍙弬鑰冧笅闈㈢殑绀轰緥 ---楂樼伒鏁忓害锛屽搷搴斿揩锛岃瑙﹀彲鑳介珮 -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, - time_window = 300, -- 妫娴嬬獥鍙(ms) - pulse_threshold = 1, -- 瑙﹀彂闃堝 - pulse_timeout = 100, -- 鑴夊啿瓒呮椂(ms) -}) ---榛樿閰嶇疆锛岃緝楂樼伒鏁忓害 -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, - time_window = 1000, -- 妫娴嬬獥鍙(ms) - pulse_threshold = 3, -- 瑙﹀彂闃堝 - pulse_timeout = 200, -- 鑴夊啿瓒呮椂(ms) -}) - ---涓瓑鐏垫晱搴︼紝 -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, - time_window = 2000, -- 妫娴嬬獥鍙(ms) - pulse_threshold = 3, -- 瑙﹀彂闃堝 - pulse_timeout = 300, -- 鑴夊啿瓒呮椂(ms) -}) ---浣庣伒鏁忓害锛屽噺灏戣鎶 -exvib1.open({ - gpio_pin = 24, - on_event = vibration_cb, - time_window = 3000, -- 妫娴嬬獥鍙(ms) - pulse_threshold = 10, -- 瑙﹀彂闃堝 - pulse_timeout = 500, -- 鑴夊啿瓒呮椂(ms) -}) -]] --- 鍚姩闇囧姩妫娴嬪姛鑳 -function exvib1.open(opts) - -- 濡傛灉娌℃湁浼犲叆閰嶇疆鍙傛暟锛屽垯浣跨敤绌鸿〃 - opts = opts or {} - -- 鐢ㄤ紶鍏ョ殑閰嶇疆鍙傛暟鏇存柊榛樿閰嶇疆 - for k, v in pairs(opts) do cfg[k] = v end - -- 鏇存柊鐢ㄦ埛鍥炶皟鍑芥暟锛屽鏋滀紶鍏ヤ簡鏂扮殑鍥炶皟鍒欎娇鐢ㄦ柊鐨勶紝鍚﹀垯淇濇寔鍘熸湁鍥炶皟 - st.on_event = opts.on_event or st.on_event - -- 閰嶇疆 GPIO 娑堟姈鏃堕棿锛岃缃腑鏂鐞嗗嚱鏁般佷笂鎷夋ā寮忓拰瑙﹀彂鏂瑰紡 - gpio.debounce(cfg.gpio_pin, cfg.debounce_irq) - gpio.setup(cfg.gpio_pin, isr, cfg.pull, cfg.trigger) - -- 鍚姩瀹氭椂鍣ㄥ惊鐜皟鐢ㄧ姸鎬佹満澶勭悊鍑芥暟 - sys.timerLoopStart(fsm, cfg.poll_interval) - log.info("Vibration", "start on gpio", cfg.gpio_pin) -end - ---[[ -鍏抽棴闇囧姩妫娴嬪姛鑳 -@api exvib1.close() -@return nil 鏃犺繑鍥炲 -@usage -exvib1.close() --鍏抽棴闇囧姩妫娴嬪姛鑳 ---]] -function exvib1.close() - -- 鍏抽棴 GPIO 寮曡剼 - gpio.close(cfg.gpio_pin) - -- 鍋滄瀹氭椂鍣 - sys.timerStop(fsm) - reset() -end - -return exvib1 diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc0310.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc0310.lua deleted file mode 100644 index 45d95b8..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc0310.lua +++ /dev/null @@ -1,55 +0,0 @@ -local config = { - mode = 1, - is_msb = 1, - rx_bit = 2, - seq_type = 1, - is_ddr = 0x00010101, - i2c_slave_addr = 0x21, - width = 640, - height = 480, - init_cmds = {{0xfe, 0xf0}, {0xfe, 0xf0}, {0xfe, 0x00}, {0xfc, 0x16}, {0xfc, 0x16}, {0xf2, 0x07}, {0xf3, 0x83}, - {0xf5, 0x07}, {0xf7, 0x88}, {0xf8, 0x00}, {0xf9, 0x4f}, {0xfa, 0x11}, {0xfc, 0xce}, {0xfd, 0x00}, - - {0x00, 0x2f}, {0x01, 0x0f}, {0x02, 0x04}, {0x03, 0x02}, {0x04, 0x12}, {0x09, 0x00}, {0x0a, 0x00}, - {0x0b, 0x00}, {0x0c, 0x04}, {0x0d, 0x01}, {0x0e, 0xe8}, {0x0f, 0x02}, {0x10, 0x88}, {0x16, 0x00}, - {0x17, 0x14}, {0x18, 0x1a}, {0x19, 0x14}, {0x1b, 0x48}, {0x1c, 0x6c}, {0x1e, 0x6b}, {0x1f, 0x28}, - {0x20, 0x8b}, {0x21, 0x49}, {0x22, 0xd0}, {0x23, 0x04}, {0x24, 0xff}, {0x34, 0x20}, {0x26, 0x23}, - {0x28, 0xff}, {0x29, 0x00}, {0x32, 0x04}, {0x33, 0x10}, {0x37, 0x20}, {0x38, 0x10}, {0x47, 0x80}, - {0x4e, 0x66}, {0xa8, 0x02}, {0xa9, 0x80}, {0x40, 0xff}, {0x41, 0x21}, {0x42, 0xcf}, {0x44, 0x00}, - {0x45, 0xa0}, {0x46, 0x02}, {0x4a, 0x11}, {0x4b, 0x01}, {0x4c, 0x20}, {0x4d, 0x05}, {0x4f, 0x01}, - {0x50, 0x01}, {0x55, 0x01}, {0x56, 0xe0}, {0x57, 0x02}, {0x58, 0x80}, {0x70, 0x70}, {0x5a, 0x84}, - {0x5b, 0xc9}, {0x5c, 0xed}, {0x77, 0x74}, {0x78, 0x40}, {0x79, 0x5f}, {0x82, 0x14}, {0x83, 0x0b}, - {0x89, 0xf0}, {0x8f, 0xaa}, {0x90, 0x8c}, {0x91, 0x90}, {0x92, 0x03}, {0x93, 0x03}, {0x94, 0x05}, - {0x95, 0x65}, {0x96, 0xf0}, {0xfe, 0x00}, {0x9a, 0x20}, {0x9b, 0x80}, {0x9c, 0x40}, {0x9d, 0x80}, - {0xa1, 0x30}, {0xa2, 0x32}, {0xa4, 0x30}, {0xa5, 0x30}, {0xaa, 0x10}, {0xac, 0x22}, {0xfe, 0x00}, - {0xbf, 0x08}, {0xc0, 0x16}, {0xc1, 0x28}, {0xc2, 0x41}, {0xc3, 0x5a}, {0xc4, 0x6c}, {0xc5, 0x7a}, - {0xc6, 0x96}, {0xc7, 0xac}, {0xc8, 0xbc}, {0xc9, 0xc9}, {0xca, 0xd3}, {0xcb, 0xdd}, {0xcc, 0xe5}, - {0xcd, 0xf1}, {0xce, 0xfa}, {0xcf, 0xff}, {0xd0, 0x40}, {0xd1, 0x34}, {0xd2, 0x34}, {0xd3, 0x40}, - {0xd6, 0xf2}, {0xd7, 0x1b}, {0xd8, 0x18}, {0xdd, 0x03}, {0xfe, 0x01}, {0x05, 0x30}, {0x06, 0x75}, - {0x07, 0x40}, {0x08, 0xb0}, {0x0a, 0xc5}, {0x0b, 0x11}, {0x0c, 0x00}, {0x12, 0x52}, {0x13, 0x38}, - {0x18, 0x95}, {0x19, 0x96}, {0x1f, 0x20}, {0x20, 0xc0}, {0x3e, 0x40}, {0x3f, 0x57}, {0x40, 0x7d}, - {0x03, 0x60}, {0x44, 0x00}, {0xfe, 0x01}, {0x1c, 0x91}, {0x21, 0x15}, {0x50, 0x80}, {0x56, 0x04}, - {0x59, 0x08}, {0x5b, 0x02}, {0x61, 0x8d}, {0x62, 0xa7}, {0x63, 0xd0}, {0x65, 0x06}, {0x66, 0x06}, - {0x67, 0x84}, {0x69, 0x08}, {0x6a, 0x25}, {0x6b, 0x01}, {0x6c, 0x00}, {0x6d, 0x02}, {0x6e, 0xf0}, - {0x6f, 0x80}, {0x76, 0x80}, {0x78, 0xaf}, {0x79, 0x75}, {0x7a, 0x40}, {0x7b, 0x50}, {0x7c, 0x0c}, - {0x90, 0xc9}, {0x91, 0xbe}, {0x92, 0xe2}, {0x93, 0xc9}, {0x95, 0x1b}, {0x96, 0xe2}, {0x97, 0x49}, - {0x98, 0x1b}, {0x9a, 0x49}, {0x9b, 0x1b}, {0x9c, 0xc3}, {0x9d, 0x49}, {0x9f, 0xc7}, {0xa0, 0xc8}, - {0xa1, 0x00}, {0xa2, 0x00}, {0x86, 0x00}, {0x87, 0x00}, {0x88, 0x00}, {0x89, 0x00}, {0xa4, 0xb9}, - {0xa5, 0xa0}, {0xa6, 0xba}, {0xa7, 0x92}, {0xa9, 0xba}, {0xaa, 0x80}, {0xab, 0x9d}, {0xac, 0x7f}, - {0xae, 0xbb}, {0xaf, 0x9d}, {0xb0, 0xc8}, {0xb1, 0x97}, {0xb3, 0xb7}, {0xb4, 0x7f}, {0xb5, 0x00}, - {0xb6, 0x00}, {0x8b, 0x00}, {0x8c, 0x00}, {0x8d, 0x00}, {0x8e, 0x00}, {0x94, 0x55}, {0x99, 0xa6}, - {0x9e, 0xaa}, {0xa3, 0x0a}, {0x8a, 0x00}, {0xa8, 0x55}, {0xad, 0x55}, {0xb2, 0x55}, {0xb7, 0x05}, - {0x8f, 0x00}, {0xb8, 0xcb}, {0xb9, 0x9b}, {0xfe, 0x01}, {0xd0, 0x38}, {0xd1, 0x00}, {0xd2, 0x02}, - {0xd3, 0x04}, {0xd4, 0x38}, {0xd5, 0x12}, {0xd6, 0x30}, {0xd7, 0x00}, {0xd8, 0x0a}, {0xd9, 0x16}, - {0xda, 0x39}, {0xdb, 0xf8}, {0xfe, 0x01}, {0xc1, 0x3c}, {0xc2, 0x50}, {0xc3, 0x00}, {0xc4, 0x40}, - {0xc5, 0x30}, {0xc6, 0x30}, {0xc7, 0x10}, {0xc8, 0x00}, {0xc9, 0x00}, {0xdc, 0x20}, {0xdd, 0x10}, - {0xdf, 0x00}, {0xde, 0x00}, {0x01, 0x10}, {0x0b, 0x31}, {0x0e, 0x50}, {0x0f, 0x0f}, {0x10, 0x6e}, - {0x12, 0xa0}, {0x15, 0x60}, {0x16, 0x60}, {0x17, 0xe0}, {0xcc, 0x0c}, {0xcd, 0x10}, {0xce, 0xa0}, - {0xcf, 0xe6}, {0x45, 0xf7}, {0x46, 0xff}, {0x47, 0x15}, {0x48, 0x03}, {0x4f, 0x60}, {0xfe, 0x00}, - {0x05, 0x01}, {0x06, 0x32}, {0x07, 0x00}, {0x08, 0x0c}, {0xfe, 0x01}, {0x25, 0x00}, {0x26, 0x3c}, - {0x27, 0x01}, {0x28, 0xdc}, {0x29, 0x01}, {0x2a, 0xe0}, {0x2b, 0x01}, {0x2c, 0xe0}, {0x2d, 0x01}, - {0x2e, 0xe0}, {0x3c, 0x20}, -- SPI閰嶇疆 - {0xfe, 0x03}, {0x52, 0xa2}, {0x53, 0x24}, {0x54, 0x20}, {0x55, 0x00}, {0x59, 0x1f}, {0x5a, 0x00}, {0x5b, 0x80}, - {0x5c, 0x02}, {0x5d, 0xe0}, {0x5e, 0x01}, {0x51, 0x03}, {0x64, 0x04}, {0xfe, 0x00}, {0x44, 0x02}} -} -return config diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc032a.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc032a.lua deleted file mode 100644 index dacc324..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/gc032a.lua +++ /dev/null @@ -1,60 +0,0 @@ -local config = { - mode = 1, - is_msb = 1, - rx_bit = 2, - seq_type = 1, - is_ddr = 0x00010101, - i2c_slave_addr = 0x21, - width = 640, - height = 480, - init_cmds = {{0xf3, 0x83}, {0xf5, 0x08}, {0xf7, 0x01}, {0xf8, 0x01}, {0xf9, 0x4e}, {0xfa, 0x00}, {0xfc, 0x02}, - {0xfe, 0x02}, {0x81, 0x03}, {0xfe, 0x00}, {0x77, 0x64}, {0x78, 0x40}, {0x79, 0x60}, {0xfe, 0x00}, - {0x03, 0x01}, {0x04, 0xcb}, {0x05, 0x01}, {0x06, 0xb2}, {0x07, 0x00}, {0x08, 0x10}, {0x0a, 0x00}, - {0x0c, 0x00}, {0x0d, 0x01}, {0x0e, 0xe8}, {0x0f, 0x02}, {0x10, 0x88}, {0x17, 0x54}, {0x19, 0x08}, - {0x1a, 0x0a}, {0x1f, 0x40}, {0x20, 0x30}, {0x2e, 0x80}, {0x2f, 0x2b}, {0x30, 0x1a}, {0xfe, 0x02}, - {0x03, 0x02}, {0x05, 0xd7}, {0x06, 0x60}, {0x08, 0x80}, {0x12, 0x89}, {0xfe, 0x03}, {0x52, 0xba}, - {0x53, 0x24}, {0x54, 0x20}, {0x55, 0x00}, {0x59, 0x1f}, {0x5a, 0x00}, {0x5b, 0x80}, {0x5c, 0x02}, - {0x5d, 0xe0}, {0x5e, 0x01}, {0x51, 0x03}, {0x64, 0x04}, {0xfe, 0x00}, {0xfe, 0x00}, {0x18, 0x02}, - {0xfe, 0x02}, {0x40, 0x22}, {0x45, 0x00}, {0x46, 0x00}, {0x49, 0x20}, {0x4b, 0x3c}, {0x50, 0x20}, - {0x42, 0x10}, {0xfe, 0x01}, {0x0a, 0xc5}, {0x45, 0x00}, {0xfe, 0x00}, {0x40, 0xff}, {0x41, 0x25}, - {0x42, 0xef}, {0x43, 0x10}, {0x44, 0x83}, {0x46, 0x22}, {0x49, 0x03}, {0x52, 0x02}, {0x54, 0x00}, - {0xfe, 0x02}, {0x22, 0xf6}, {0xfe, 0x01}, {0xc1, 0x38}, {0xc2, 0x4c}, {0xc3, 0x00}, {0xc4, 0x2c}, - {0xc5, 0x24}, {0xc6, 0x18}, {0xc7, 0x28}, {0xc8, 0x11}, {0xc9, 0x15}, {0xca, 0x20}, {0xdc, 0x7a}, - {0xdd, 0xa0}, {0xde, 0x80}, {0xdf, 0x88}, {0xfe, 0x01}, {0x50, 0xc1}, {0x56, 0x34}, {0x58, 0x04}, - {0x65, 0x06}, {0x66, 0x0f}, {0x67, 0x04}, {0x69, 0x20}, {0x6a, 0x40}, {0x6b, 0x81}, {0x6d, 0x12}, - {0x6e, 0xc0}, {0x7b, 0x2a}, {0x7c, 0x0c}, {0xfe, 0x01}, {0x90, 0xe3}, {0x91, 0xc2}, {0x92, 0xff}, - {0x93, 0xe3}, {0x95, 0x1c}, {0x96, 0xff}, {0x97, 0x44}, {0x98, 0x1c}, {0x9a, 0x44}, {0x9b, 0x1c}, - {0x9c, 0x64}, {0x9d, 0x44}, {0x9f, 0x71}, {0xa0, 0x64}, {0xa1, 0x00}, {0xa2, 0x00}, {0x86, 0x00}, - {0x87, 0x00}, {0x88, 0x00}, {0x89, 0x00}, {0xa4, 0xc2}, {0xa5, 0x9b}, {0xa6, 0xc8}, {0xa7, 0x92}, - {0xa9, 0xc9}, {0xaa, 0x96}, {0xab, 0xa9}, {0xac, 0x99}, {0xae, 0xce}, {0xaf, 0xa9}, {0xb0, 0xcf}, - {0xb1, 0x9d}, {0xb3, 0xcf}, {0xb4, 0xac}, {0xb5, 0x00}, {0xb6, 0x00}, {0x8b, 0x00}, {0x8c, 0x00}, - {0x8d, 0x00}, {0x8e, 0x00}, {0x94, 0x55}, {0x99, 0xa6}, {0x9e, 0xaa}, {0xa3, 0x0a}, {0x8a, 0x00}, - {0xa8, 0x55}, {0xad, 0x55}, {0xb2, 0x55}, {0xb7, 0x05}, {0x8f, 0x00}, {0xb8, 0xc7}, {0xb9, 0xa0}, - - {0xfe, 0x01}, {0xd0, 0x40}, {0xd1, 0x00}, {0xd2, 0x00}, {0xd3, 0xfa}, {0xd4, 0x4a}, {0xd5, 0x02}, - - {0xd6, 0x44}, {0xd7, 0xfa}, {0xd8, 0x04}, {0xd9, 0x08}, {0xda, 0x5c}, {0xdb, 0x02}, {0xfe, 0x00}, - - {0xfe, 0x00}, {0xba, 0x00}, {0xbb, 0x04}, {0xbc, 0x0a}, {0xbd, 0x0e}, {0xbe, 0x22}, {0xbf, 0x30}, - {0xc0, 0x3d}, {0xc1, 0x4a}, {0xc2, 0x5d}, {0xc3, 0x6b}, {0xc4, 0x7a}, {0xc5, 0x85}, {0xc6, 0x90}, - {0xc7, 0xa5}, {0xc8, 0xb5}, {0xc9, 0xc2}, {0xca, 0xcc}, {0xcb, 0xd5}, {0xcc, 0xde}, {0xcd, 0xea}, - {0xce, 0xf5}, {0xcf, 0xff}, {0xfe, 0x00}, {0x5a, 0x08}, {0x5b, 0x0f}, {0x5c, 0x15}, {0x5d, 0x1c}, - {0x5e, 0x28}, {0x5f, 0x36}, {0x60, 0x45}, {0x61, 0x51}, {0x62, 0x6a}, {0x63, 0x7d}, {0x64, 0x8d}, - {0x65, 0x98}, {0x66, 0xa2}, {0x67, 0xb5}, {0x68, 0xc3}, {0x69, 0xcd}, {0x6a, 0xd4}, {0x6b, 0xdc}, - {0x6c, 0xe3}, {0x6d, 0xf0}, {0x6e, 0xf9}, {0x6f, 0xff}, {0xfe, 0x00}, {0x70, 0x50}, {0xfe, 0x00}, - {0x4f, 0x01}, {0xfe, 0x01}, {0x0c, 0x01}, {0x0d, 0x00}, {0x12, 0xa0}, {0x13, 0x38}, {0x1f, 0x40}, - {0x20, 0x40}, {0x23, 0x0a}, {0x26, 0x9a}, {0x3e, 0x20}, {0x3f, 0x2d}, {0x40, 0x40}, {0x41, 0x5b}, - {0x42, 0x82}, {0x43, 0xb7}, {0x04, 0x0a}, {0x02, 0x79}, {0x03, 0xc0}, {0xfe, 0x01}, {0xcc, 0x08}, - {0xcd, 0x08}, {0xce, 0xa4}, {0xcf, 0xec}, {0xfe, 0x00}, {0x81, 0xb8}, {0x82, 0x04}, {0x83, 0x10}, - {0x84, 0x01}, {0x86, 0x50}, {0x87, 0x18}, {0x88, 0x10}, {0x89, 0x70}, {0x8a, 0x20}, {0x8b, 0x10}, - {0x8c, 0x08}, {0x8d, 0x0a}, {0xfe, 0x00}, {0x8f, 0xaa}, {0x90, 0x1c}, {0x91, 0x52}, {0x92, 0x03}, - {0x93, 0x03}, {0x94, 0x08}, {0x95, 0x6a}, {0x97, 0x00}, {0x98, 0x00}, {0xfe, 0x00}, {0x9a, 0x30}, - {0x9b, 0x50}, {0xa1, 0x30}, {0xa2, 0x66}, {0xa4, 0x28}, {0xa5, 0x30}, {0xaa, 0x28}, {0xac, 0x32}, - - {0xfe, 0x00}, {0xd1, 0x3f}, {0xd2, 0x3f}, {0xd3, 0x38}, {0xd6, 0xf4}, {0xd7, 0x1d}, {0xdd, 0x72}, - {0xde, 0x84}, {0xfe, 0x00}, {0x05, 0x01}, {0x06, 0xad}, {0x07, 0x00}, {0x08, 0x10}, {0xfe, 0x01}, - {0x25, 0x00}, {0x26, 0x4d}, {0x27, 0x01}, {0x28, 0xce}, {0x29, 0x01}, {0x2a, 0xce}, {0x2b, 0x01}, - {0x2c, 0xce}, {0x2d, 0x01}, {0x2e, 0xce}, {0x2f, 0x01}, {0x30, 0xce}, {0x31, 0x01}, {0x32, 0xce}, - {0x33, 0x01}, {0x34, 0xce}, {0x3c, 0x10}, {0xfe, 0x00}, {0x44, 0x03}} -} -return config diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpdns.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpdns.lua deleted file mode 100644 index eaa7ae4..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpdns.lua +++ /dev/null @@ -1,79 +0,0 @@ ---[[ -@module httpdns -@summary 浣跨敤Http杩涜鍩熷悕瑙ｆ瀽 -@version 1.0 -@date 2023.07.13 -@author wendal -@usage --- 閫氳繃闃块噷DNS鑾峰彇缁撴灉 -local ip = httpdns.ali("air32.cn") -log.info("httpdns", "air32.cn", ip) - --- 閫氳繃鑵捐DNS鑾峰彇缁撴灉 -local ip = httpdns.tx("air32.cn") -log.info("httpdns", "air32.cn", ip) -]] - -local httpdns = {} - ---[[ -閫氳繃闃块噷DNS鑾峰彇缁撴灉 -@api httpdns.ali(domain_name, opts) -@string 鍩熷悕 -@table opts 鍙夊弬鏁, 涓巋ttp.request鐨刼pts鍙傛暟涓鑷 -@return string ip鍦板潃 -@usage -local ip = httpdns.ali("air32.cn") -log.info("httpdns", "air32.cn", ip) --- 鎸囧畾缃戠粶閫傞厤鍣 -local ip = httpdns.ali("air32.cn", {adapter=socket.LWIP_STA, timeout=3000}) -log.info("httpdns", "air32.cn", ip) -]] -function httpdns.ali(n, opts) - if n == nil then return end - if opts == nil then - opts = {timeout=3000} - elseif opts.timeout == nil then - opts.timeout = 3000 - end - local code, _, body = http.request("GET", "http://223.5.5.5/resolve?short=1&name=" .. tostring(n), nil, nil, opts).wait() - if code == 200 and body and #body > 2 then - local jdata = json.decode(body) - if jdata and #jdata > 0 then - return jdata[1] - end - end -end - - ---[[ -閫氳繃鑵捐DNS鑾峰彇缁撴灉 -@api httpdns.tx(domain_name, opts) -@string 鍩熷悕 -@table opts 鍙夊弬鏁, 涓巋ttp.request鐨刼pts鍙傛暟涓鑷 -@return string ip鍦板潃 -@usage -local ip = httpdns.tx("air32.cn") -log.info("httpdns", "air32.cn", ip) - --- 鎸囧畾缃戠粶閫傞厤鍣 -local ip = httpdns.tx("air32.cn", {adapter=socket.LWIP_STA, timeout=3000}) -log.info("httpdns", "air32.cn", ip) -]] -function httpdns.tx(n, opts) - if n == nil then return end - if opts == nil then - opts = {timeout=3000} - elseif opts.timeout == nil then - opts.timeout = 3000 - end - local code, _, body = http.request("GET", "http://119.29.29.29/d?dn=" .. tostring(n), nil, nil, opts).wait() - if code == 200 and body and #body > 2 then - local tmp = body:split(",") - if tmp then return tmp[1] end - end -end - -return httpdns - - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpplus.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpplus.lua deleted file mode 100644 index a07c533..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/httpplus.lua +++ /dev/null @@ -1,714 +0,0 @@ ---[[ -@module httpplus -@summary http搴撶殑琛ュ厖 -@version 1.0 -@date 2023.11.23 -@author wendal -@demo httpplus -@tag LUAT_USE_NETWORK -@usage --- 鏈簱鏀寔鐨勫姛鑳芥湁: --- 1. 澶ф枃浠朵笂浼犵殑闂,涓嶉檺澶у皬 --- 2. 浠绘剰闀垮害鐨刪eader璁剧疆 --- 3. 浠绘剰闀垮害鐨刡ody璁剧疆 --- 4. 閴存潈URL鑷姩璇嗗埆 --- 5. body浣跨敤zbuff杩斿洖,鍙洿鎺ヤ紶杈撶粰uart绛夊簱 - --- 涓巋ttp搴撶殑宸紓 --- 1. 涓嶆敮鎸佹枃浠朵笅杞 --- 2. 涓嶆敮鎸乫ota - --- 鏀寔 http 1.0 鍜 http 1.1, 涓嶆敮鎸乭ttp2.0 --- 鏀寔 GET/POST/PUT/DELETE/HEAD 绛夊父鐢ㄦ柟娉,涔熸敮鎸佽嚜瀹氫箟method --- 鏀寔 HTTP 鍜 HTTPS 鍗忚 --- 鏀寔 IPv4 鍜 IPv6 --- 鏀寔 HTTP 閴存潈 --- 鏀寔 multipart/form-data 涓婁紶鏂囦欢鍜岃〃鍗 --- 鏀寔 application/x-www-form-urlencoded 涓婁紶琛ㄥ崟 --- 鏀寔 application/json 涓婁紶json鏁版嵁 --- 鏀寔 鑷畾涔 body 涓婁紶浠绘剰鏁版嵁 --- 鏀寔 鑷畾涔 headers --- 鏀寔 澶ф枃浠朵笂浼,涓嶉檺澶у皬 --- 鏀寔 zbuff 浣滀负 body 涓婁紶鍜屽搷搴旇繑鍥 --- 鏀寔 bodyfile 鐩存帴鎶婃枃浠跺唴瀹逛綔涓篵ody涓婁紶 --- 鏀寔 涓婁紶鏃朵娇鐢ㄨ嚜瀹氫箟缂撳啿鍖, 2025.9.25 鏂板 -]] - - -local httpplus = {} -local TAG = "httpplus" - -local function http_opts_parse(opts) - if not opts then - log.error(TAG, "opts涓嶈兘涓簄il") - return -100, "opts涓嶈兘涓簄il" - end - if not opts.url or #opts.url < 5 then - log.error(TAG, "URL涓嶅瓨鍦ㄦ垨鑰呭お鐭簡", opts.url) - return -100, "URL涓嶅瓨鍦ㄦ垨鑰呭お鐭簡" - end - if not opts.headers then - opts.headers = {} - end - - if opts.debug or httpplus.debug then - if not opts.log then - opts.log = log.debug - end - else - opts.log = function() - -- log.info(TAG, "鏃犳棩蹇") - end - end - - -- 瑙ｆ瀽url - -- 鍏堝垽鏂崗璁槸鍚﹀姞瀵 - local is_ssl = false - local tmp = "" - if opts.url:startsWith("https://") then - is_ssl = true - tmp = opts.url:sub(9) - elseif opts.url:startsWith("http://") then - tmp = opts.url:sub(8) - else - tmp = opts.url - end - -- log.info("http鍒嗚В闃舵1", is_ssl, tmp) - -- 鐒跺悗鍒ゆ柇host娈 - local uri = "" - local host = "" - local port = 0 - if tmp:find("/") then - uri = tmp:sub((tmp:find("/"))) -- 娉ㄦ剰find浼氳繑鍥炲涓 - tmp = tmp:sub(1, tmp:find("/") - 1) - else - uri = "/" - end - -- log.info("http鍒嗚В闃舵2", is_ssl, tmp, uri) - if tmp == nil or #tmp == 0 then - log.error(TAG, "闈炴硶鐨刄RL", opts.url) - return -101, "闈炴硶鐨刄RL" - end - -- 鏈夋棤閴存潈淇℃伅 - if tmp:find("@") then - local auth = tmp:sub(1, tmp:find("@") - 1) - if not opts.headers["Authorization"] then - opts.headers["Authorization"] = "Basic " .. auth:toBase64() - end - -- log.info("http閴存潈淇℃伅", auth, opts.headers["Authorization"]) - tmp = tmp:sub(tmp:find("@") + 1) - end - -- 瑙ｆ瀽绔彛 - if tmp:find(":") then - host = tmp:sub(1, tmp:find(":") - 1) - port = tmp:sub(tmp:find(":") + 1) - port = tonumber(port) - else - host = tmp - end - if not port or port < 1 then - if is_ssl then - port = 443 - else - port = 80 - end - end - -- 鏀跺熬宸ヤ綔 - if not opts.headers["Host"] then - if (is_ssl and port == 443) or ((not is_ssl) and port == 80) then - opts.headers["Host"] = host - else - opts.headers["Host"] = string.format("%s:%d", host, port) - end - end - -- Connection 蹇呴』鍏抽棴 - opts.headers["Connection"] = "Close" - - -- 澶嶄綅涓浜涘彉閲,鍏嶅緱鍒ゆ柇鍑洪敊 - opts.is_closed = nil - opts.body_len = 0 - - -- multipart闇瑕乥oundary - local boundary = "------------------------16ef6e68ef" .. tostring(os.time()) - opts.boundary = boundary - opts.mp = {} - - if opts.files then - -- 寮哄埗璁剧疆涓簍rue - opts.multipart = true - end - - -- 琛ㄥ崟鏁版嵁 - if opts.forms then - if opts.multipart then - for kk, vv in pairs(opts.forms) do - local tmp = string.format("--%s\r\nContent-Disposition: form-data; name=\"%s\"\r\n\r\n", boundary, kk) - table.insert(opts.mp, {vv, tmp, "form"}) - opts.body_len = opts.body_len + #tmp + #vv + 2 - -- log.info("褰撳墠body闀垮害", opts.body_len, "鏁版嵁闀垮害", #vv) - end - else - if not opts.headers["Content-Type"] then - opts.headers["Content-Type"] = "application/x-www-form-urlencoded;charset=UTF-8" - end - local buff = zbuff.create(256) - for kk, vv in pairs(opts.forms) do - buff:copy(nil, string.urlEncode(tostring(kk))) - buff:copy(nil, "=") - buff:copy(nil, string.urlEncode(tostring(vv))) - buff:copy(nil, "&") - end - if buff:used() > 0 then - buff:del(-1, 1) - opts.body = buff - opts.body_len = buff:used() - opts.log(TAG, "鏅氳〃鍗", opts.body) - end - end - end - - if opts.files then - -- 寮哄埗璁剧疆涓簍rue - opts.multipart = true - local contentType = - { - txt = "text/plain", -- 鏂囨湰 - jpg = "image/jpeg", -- JPG 鏍煎紡鍥剧墖 - jpeg = "image/jpeg", -- JPEG 鏍煎紡鍥剧墖 - png = "image/png", -- PNG 鏍煎紡鍥剧墖 - gif = "image/gif", -- GIF 鏍煎紡鍥剧墖 - html = "text/html", -- HTML - json = "application/json", -- JSON - mp4 = "video/mp4", -- MP4 鏍煎紡瑙嗛 - mp3 = "audio/mp3", -- MP3 鏍煎紡闊抽 - webm = "video/webm", -- WebM 鏍煎紡瑙嗛 - } - for kk, vv in pairs(opts.files) do - local ct = contentType[vv:match("%.(%w+)$")] or "application/octet-stream" - local fname = vv:match("([^/\\]+)$") or vv - local tmp = string.format("--%s\r\nContent-Disposition: form-data; name=\"%s\"; filename=\"%s\"\r\nContent-Type: %s\r\n\r\n", boundary, kk, fname, ct) - -- log.info("鏂囦欢浼犺緭澶", tmp) - table.insert(opts.mp, {vv, tmp, "file"}) - opts.body_len = opts.body_len + #tmp + io.fileSize(vv) + 2 - -- log.info("褰撳墠body闀垮害", opts.body_len, "鏂囦欢闀垮害", io.fileSize(vv), fname, ct) - end - end - - - -- 濡傛灉multipart妯″紡 - if opts.multipart then - -- 濡傛灉娌′富鍔ㄨ缃産ody, 閭ｄ箞琛ヤ釜缁撳熬 - if not opts.body then - opts.body_len = opts.body_len + #boundary + 2 + 2 + 2 - end - -- Content-Type娌¤缃? 閭ｅ氨璁剧疆涓涓 - if not opts.headers["Content-Type"] then - opts.headers["Content-Type"] = "multipart/form-data; boundary="..boundary - end - end - - -- 鐩存帴璁剧疆bodyfile - if opts.bodyfile then - local fd = io.open(opts.bodyfile, "rb") - if not fd then - log.error("httpplus", "bodyfile澶辫触,鏂囦欢涓嶅瓨鍦", opts.bodyfile) - return -104, "bodyfile澶辫触,鏂囦欢涓嶅瓨鍦" - end - fd:close() - opts.body_len = io.fileSize(opts.bodyfile) - end - - -- 鏈夎缃産ody, 鑰屼笖娌¤缃暱搴 - if opts.body and (not opts.body_len or opts.body_len == 0) then - -- body鏄痾buff鐨勬儏鍐 - if type(opts.body) == "userdata" then - opts.body_len = opts.body:used() - -- body鏄痡son鐨勬儏鍐 - elseif type(opts.body) == "table" then - opts.body = json.encode(opts.body, "7f") - if opts.body then - opts.body_len = #opts.body - if not opts.headers["Content-Type"] then - opts.headers["Content-Type"] = "application/json;charset=UTF-8" - opts.log(TAG, "JSON", opts.body) - end - end - -- 鍏朵粬鎯呭喌灏卞彧鑳藉綋鏂囨湰浜 - else - opts.body = tostring(opts.body) - opts.body_len = #opts.body - end - end - -- 涓瀹氳璁剧疆Content-Length,鑰屼笖寮哄埗瑕嗙洊瀹㈡埛鑷畾涔夌殑鍊 - -- opts.body_len = opts.body_len or 0 - opts.headers["Content-Length"] = tostring(opts.body_len or 0) - - -- 濡傛灉娌¤缃甿ethod, 鑷姩琛ラ綈 - if not opts.method or #opts.method == 0 then - if opts.body_len > 0 then - opts.method = "POST" - else - opts.method = "GET" - end - else - -- 纭繚涓瀹氭槸澶у啓瀛楁瘝 - opts.method = opts.method:upper() - end - - if opts.debug then - opts.log(TAG, is_ssl, host, port, uri, json.encode(opts.headers)) - end - - - -- 鎶婂墿浣欑殑灞炴ц缃ソ - opts.host = host - opts.port = port - opts.uri = uri - opts.is_ssl = is_ssl - - if not opts.timeout or opts.timeout == 0 then - opts.timeout = 30 - end - - return -- 鎴愬姛瀹屾垚,涓嶉渶瑕佽繑鍥炲 -end - - - -local function zbuff_find(buff, str) - -- log.info("zbuff鏌ユ壘", buff:used(), #str) - if buff:used() < #str then - return - end - local maxoff = buff:used() - maxoff = maxoff - #str - local tmp = zbuff.create(#str) - tmp:write(str) - -- log.info("tmp鏁版嵁", tmp:query():toHex()) - for i = 0, maxoff, 1 do - local flag = true - for j = 0, #str - 1, 1 do - -- log.info("瀵规瘮", i, j, string.char(buff[i+j]):toHex(), string.char(tmp[j]):toHex(), buff[i+j] ~= tmp[j]) - if buff[i+j] ~= tmp[j] then - flag = false - break - end - end - if flag then - return i - end - end -end - -local function resp_parse(opts) - -- log.info("杩欓噷--------") - local header_offset = zbuff_find(opts.rx_buff, "\r\n\r\n") - -- log.info("澶撮儴鍋忕Щ閲", header_offset) - if not header_offset then - log.warn(TAG, "娌℃湁妫娴嬪埌http鍝嶅簲澶撮儴,闈炴硶鍝嶅簲") - opts.resp_code = -198 - return - end - local state_line_offset = zbuff_find(opts.rx_buff, "\r\n") - local state_line = opts.rx_buff:query(0, state_line_offset) - local tmp = state_line:split(" ") - if not tmp or #tmp < 2 then - log.warn(TAG, "闈炴硶鐨勫搷搴旇", state_line) - opts.resp_code = -197 - return - end - local code = tonumber(tmp[2]) - if not code then - log.warn(TAG, "闈炴硶鐨勫搷搴旂爜", tmp[2]) - opts.resp_code = -196 - return - end - opts.resp_code = code - opts.resp = { - headers = {} - } - opts.log(TAG, "state code", code) - -- TODO 瑙ｆ瀽header鍜宐ody - - opts.rx_buff:del(0, state_line_offset + 2) - -- opts.log(TAG, "鍓╀綑鐨勫搷搴斾綋", opts.rx_buff:query()) - - -- 瑙ｆ瀽headers锛堜粎鎸夐涓啋鍙锋媶鍒嗭紝淇濈暀鍊间腑鐨勫啋鍙凤級 - while 1 do - local offset = zbuff_find(opts.rx_buff, "\r\n") - if not offset then - log.warn(TAG, "涓嶅悎娉曠殑鍓╀綑headers", opts.rx_buff:query()) - break - end - if offset == 0 then - -- header鐨勬渶鍚庝竴涓┖琛 - opts.rx_buff:del(0, 2) - break - end - local line = opts.rx_buff:query(0, offset) - opts.rx_buff:del(0, offset + 2) - local name, value = line:match("^([^:]+):%s*(.*)$") - if name and value then - name = name:trim() - value = value:trim() - opts.log(TAG, name, value) - opts.resp.headers[name] = value - else - opts.log(TAG, "蹇界暐闈炴硶header琛", line) - end - end - - -- if opts.resp_code < 299 then - -- 瑙ｆ瀽body - -- 鏈塁ontent-Length灏卞ソ鍔 - if opts.resp.headers["Content-Length"] then - opts.log(TAG, "鏈塁ontent-Length", opts.resp.headers["Content-Length"]) - local declared = tonumber(opts.resp.headers["Content-Length"]) or 0 - if declared > 0 and opts.rx_buff:used() >= declared then - opts.rx_buff:resize(declared) - end - opts.resp.body = opts.rx_buff - elseif opts.resp.headers["Transfer-Encoding"] == "chunked" then - -- 瑙ｆ瀽 chunked 缂栫爜锛氶暱搴﹁锛堝彲鍚垎鍙锋墿灞曪級+ 鏁版嵁 + CRLF锛屾湯鍧楅暱搴︿负0 - local function zbuff_find_from(buff, str, start_off) - local used = buff:used() - if used - start_off < #str then return end - local maxoff = used - #str - local tmp2 = zbuff.create(#str) - tmp2:write(str) - for i = start_off, maxoff, 1 do - local ok = true - for j = 0, #str - 1, 1 do - if buff[i+j] ~= tmp2[j] then ok = false; break end - end - if ok then return i end - end - end - local body = zbuff.create(opts.rx_buff:used()) - local pos = 0 - while true do - local line_end = zbuff_find_from(opts.rx_buff, "\r\n", pos) - if not line_end then - log.error(TAG, "闈炴硶鐨刢hunk闀垮害琛") - break - end - local len_line = opts.rx_buff:query(pos, line_end - pos) - local semi = len_line:find(";") - local hex = semi and len_line:sub(1, semi - 1) or len_line - local clen = tonumber(hex, 16) - if not clen then - log.error(TAG, "闈炴硶鐨刢hunk闀垮害鍊", len_line) - break - end - pos = line_end + 2 - if clen == 0 then - -- 鏈潡锛氬拷鐣ュ悗缁 trailers - break - end - if pos + clen > opts.rx_buff:used() then - log.error(TAG, "chunk鏁版嵁闀垮害涓嶈冻") - break - end - local chunk = opts.rx_buff:query(pos, clen) - body:copy(nil, chunk) - pos = pos + clen + 2 -- 璺宠繃鏁版嵁鍙婂叾鍚庣殑CRLF - end - opts.resp.body = body - end - -- end - - -- 娓呯┖rx_buff - opts.rx_buff = nil - - -- 瀹岀粨鏁ｈ姳 -end - --- socket 鍥炶皟鍑芥暟 -local function http_socket_cb(opts, event) - opts.log(TAG, "tcp.event", string.format("%08X", event)) - if event == socket.ON_LINE then - -- TCP閾炬帴宸插缓绔, 閭ｅ氨鍙互涓婅浜 - -- opts.state = "ON_LINE" - sys.publish(opts.topic) - elseif event == socket.TX_OK then - -- 鏁版嵁浼犺緭瀹屾垚, 濡傛灉鏄枃浠朵笂浼犲氨闇瑕佽繖涓秷鎭 - -- opts.state = "TX_OK" - sys.publish(opts.topic) - elseif event == socket.EVENT then - -- 鏀跺埌鏁版嵁鎴栬呴摼鎺ユ柇寮浜, 杩欓噷鎬婚渶瑕佽鍙栦竴娆℃墠鐭ラ亾 - local succ, data_len = socket.rx(opts.netc, opts.rx_buff) - if succ and data_len > 0 then - opts.log(TAG, "鏀跺埌鏁版嵁", data_len, "鎬婚暱", opts.rx_buff:used()) - -- opts.log(TAG, "鏁版嵁", opts.rx_buff:query()) - else - if not opts.is_closed then - opts.log(TAG, "鏈嶅姟鍣ㄥ凡缁忔柇寮浜嗚繛鎺ユ垨鎺ユ敹鍑洪敊") - opts.is_closed = true - sys.publish(opts.topic) - end - end - elseif event == socket.CLOSED then - log.info(TAG, "杩炴帴宸插叧闂") - opts.is_closed = true - sys.publish(opts.topic) - end -end - -local function http_exec(opts) - local fail_check = true - local netc = socket.create(opts.adapter, function(sc, event) - if opts.netc then - return http_socket_cb(opts, event) - end - end) - if not netc then - log.error(TAG, "鍒涘缓socket澶辫触浜!!") - return -102 - end - opts.netc = netc - opts.rx_buff = zbuff.create(1024) - opts.topic = tostring(netc) - socket.config(netc, nil,nil, opts.is_ssl) - if opts.debug_socket then - socket.debug(netc, true) - end - if not socket.connect(netc, opts.host, opts.port, opts.try_ipv6) then - log.warn(TAG, "璋冪敤socket.connect杩斿洖閿欒浜") - return -103, "璋冪敤socket.connect杩斿洖閿欒浜" - end - local ret = sys.waitUntil(opts.topic, 5000) - if ret == false then - log.warn(TAG, "寤虹珛杩炴帴瓒呮椂浜!!!") - return -104, "寤虹珛杩炴帴瓒呮椂浜!!!" - end - - -- 棣栧厛鏄ご閮 - local line = string.format("%s %s HTTP/1.1\r\n", opts.method:upper(), opts.uri) - -- opts.log(TAG, line) - socket.tx(netc, line) - for k, v in pairs(opts.headers) do - line = string.format("%s: %s\r\n", k, v) - socket.tx(netc, line) - end - line = "\r\n" - socket.tx(netc, line) - - -- 鐒跺悗鏄痓ody - local rbody = "" - local write_counter = 0 - local fbuf = nil - if (opts.mp and #opts.mp > 0) or opts.bodyfile or (opts.body and type(opts.body) == "userdata" and opts.body:used() > 4*1024) then - if opts.upload_file_buff then - fbuf = opts.upload_file_buff - else - if hmeta and hmeta.chip and hmeta.chip() == "EC718HM" then - fbuf = zbuff.create(1024 * 128, 0, zbuff.HEAP_PSRAM) -- 718hm鍙互128k鐨,鏀炬墜鍘荤敤 - elseif hmeta and hmeta.chip and hmeta.chip() == "EC718PM" then - fbuf = zbuff.create(1024 * 64, 0, zbuff.HEAP_PSRAM) -- Air8101/7258鍙互128k鐨,鏀炬墜鍘荤敤 - elseif hmeta and hmeta.chip and hmeta.chip() == "BK7258" then - fbuf = zbuff.create(1024 * 128, 0, zbuff.HEAP_PSRAM) -- Air8101/7258鍙互128k鐨,鏀炬墜鍘荤敤 - else - fbuf = zbuff.create(1024 * 24, 0, zbuff.HEAP_PSRAM) -- 鍏朵粬妯＄粍灏辨槸灏忕殑鐢ㄥ惂 - end - end - if fbuf == nil then - fbuf = zbuff.create(1024 * 8, 0, zbuff.HEAP_PSRAM) -- 鍒涘缓涓涓皬鐨,浣滀负闃插尽 - if fbuf == nil then - fbuf = zbuff.create(1500, 0, zbuff.HEAP_PSRAM) -- 鍒涘缓涓涓渶灏忕殑,鏈鍚庨槻寰 - end - end - opts.log(TAG, "涓婁紶浣跨敤缂撳啿鍖", fbuf:len()) - end - - if opts.mp and #opts.mp > 0 then - opts.log(TAG, "鎵цmulitpart涓婁紶妯″紡") - for k, v in pairs(opts.mp) do - fail_check = socket.tx(netc, v[2]) - write_counter = write_counter + #v[2] - if v[3] == "file" then - -- log.info("鍐欏叆鏂囦欢鏁版嵁澶", v[2]) - local fd = io.open(v[1], "rb") - -- log.info("鍐欏叆鏂囦欢鏁版嵁", v[1]) - if fd then - local total = 0 - while not opts.is_closed do - fbuf:seek(0) - local ok, flen = fd:fill(fbuf) - if not ok or flen <= 0 then - break - end - fbuf:seek(flen) - opts.log(TAG, "鍐欏叆鏂囦欢鏁版嵁", "闀垮害", flen, "鎬昏", total) - if socket.tx(netc, fbuf) == false then - log.warn(TAG, "socket.tx杩斿洖閿欒浜, 浼犻佸け璐!!!!") - fail_check = false - break - end - write_counter = write_counter + flen - -- 娉ㄦ剰, 杩欓噷瑕佺瓑寰匱X_OK浜嬩欢 - sys.waitUntil(opts.topic, 1000) - end - fd:close() - end - else - socket.tx(netc, v[1]) - write_counter = write_counter + #v[1] - end - socket.tx(netc, "\r\n") - write_counter = write_counter + 2 - end - -- rbody = rbody .. "--" .. opts.boundary .. "--\r\n" - socket.tx(netc, "--") - socket.tx(netc, opts.boundary) - socket.tx(netc, "--\r\n") - write_counter = write_counter + #opts.boundary + 2 + 2 + 2 - elseif opts.bodyfile then - local fd = io.open(opts.bodyfile, "rb") - -- log.info("鍐欏叆鏂囦欢鏁版嵁", v[1]) - if fd then - local total = 0 - while not opts.is_closed do - fbuf:seek(0) - local ok, flen = fd:fill(fbuf) - if not ok or flen <= 0 then - break - end - fbuf:seek(flen) - total = total + flen - opts.log(TAG, "鍐欏叆鏂囦欢鏁版嵁", "闀垮害", flen, "鎬昏", total) - if socket.tx(netc, fbuf) == false then - log.warn(TAG, "socket.tx杩斿洖閿欒浜, 浼犻佸け璐!!!!") - fail_check = false - break - end - write_counter = write_counter + flen - -- 娉ㄦ剰, 杩欓噷瑕佺瓑寰匱X_OK浜嬩欢 - sys.waitUntil(opts.topic, 1000) - end - fd:close() - end - elseif opts.body then - if type(opts.body) == "string" and #opts.body > 0 then - socket.tx(netc, opts.body) - write_counter = write_counter + #opts.body - elseif type(opts.body) == "userdata" then - opts.log(TAG, "浣跨敤zbuff涓婁紶鏁版嵁", opts.body:used()) - write_counter = write_counter + opts.body:used() - if opts.body:used() <= 4*1024 then - fail_check = socket.tx(netc, opts.body) - else - local offset = 0 - local tmpbuff = opts.body - local tsize = tmpbuff:used() - while offset < tsize do - -- TODO 搴旇浣跨敤fbuf鏉ュ仛缂撳啿鍖猴紝鑰屼笉鏄痶oStr - opts.log(TAG, "body(zbuff)鍒嗘鍐欏叆", offset, tsize) - fbuf:seek(0) - if tsize - offset > fbuf:len() then - fbuf:copy(0, tmpbuff, offset, fbuf:len()) - fbuf:seek(fbuf:len()) - if socket.tx(netc, fbuf) == false then - log.warn(TAG, "socket.tx杩斿洖閿欒浜, 浼犻佸け璐!!!!") - fail_check = false - break - end - offset = offset + fbuf:len() - sys.waitUntil(opts.topic, 1000) - else - fbuf:copy(0, tmpbuff, offset, tsize - offset) - fbuf:seek(tsize - offset) - fail_check = socket.tx(netc, fbuf) - break - end - end - end - end - end - -- log.info("鍐欏叆闀垮害", "鏈熸湜", opts.body_len, "瀹為檯", write_counter) - -- log.info("hex", rbody) - if not fail_check then - log.warn(TAG, "鍙戦佹暟鎹け璐, 缁堟璇锋眰") - opts.resp_code = -199 - return - end - - -- 澶勭悊鍝嶅簲淇℃伅 - while not opts.is_closed and opts.timeout > 0 do - log.info(TAG, "绛夊緟鏈嶅姟鍣ㄥ畬鎴愬搷搴") - sys.waitUntil(opts.topic, 1000) - opts.timeout = opts.timeout - 1 - end - log.info(TAG, "鏈嶅姟鍣ㄥ凡瀹屾垚鍝嶅簲,寮濮嬭В鏋愬搷搴") - resp_parse(opts) - -- log.info("鎵ц瀹屾垚", "杩斿洖缁撴灉") -end - ---[[ -鎵цHTTP璇锋眰 -@api httpplus.request(opts) -@table 璇锋眰鍙傛暟,鏄竴涓猼able,鏈璧风爜寰楁湁url灞炴 -@return int 鍝嶅簲鐮,鏈嶅姟鍣ㄨ繑鍥炵殑鐘舵佺爜>=100, 鑻ユ湰鍦版娴嬪埌閿欒,浼氳繑鍥<0鐨勫 -@return 鏈嶅姟鍣ㄦ甯稿搷搴旀椂杩斿洖缁撴灉, 鍚﹀垯鏄敊璇俊鎭垨鑰卬il -@usage --- 璇锋眰鍙傛暟浠嬬粛 -local opts = { - url = "https://httpbin.air32.cn/abc", -- 蹇呴, 鐩爣URL - method = "POST", -- 鍙,榛樿GET, 濡傛灉鏈塨ody,files,forms鍙傛暟,浼氳缃垚POST - headers = {}, -- 鍙,鑷畾涔夌殑棰濆header - files = {}, -- 鍙,閿煎鐨勫舰寮,鏂囦欢涓婁紶,鑻ュ瓨鍦ㄦ湰鍙傛暟,浼氬己鍒朵互multipart/form-data褰㈠紡涓婁紶 - forms = {}, -- 鍙,閿煎鐨勫舰寮,琛ㄥ崟鍙傛暟,鑻ュ瓨鍦ㄦ湰鍙傛暟,濡傛灉涓嶅瓨鍦╢iles,鎸塧pplication/x-www-form-urlencoded涓婁紶 - body = "abc=123",-- 鍙,鑷畾涔塨ody鍙傛暟, 瀛楃涓/zbuff/table鍧囧彲, 浣嗕笉鑳戒笌files鍜宖orms鍚屾椂瀛樺湪 - debug = false, -- 鍙,鎵撳紑璋冭瘯鏃ュ織,榛樿false - try_ipv6 = false, -- 鍙,鏄惁浼樺厛灏濊瘯ipv6鍦板潃,榛樿鏄痜alse - adapter = nil, -- 鍙,缃戠粶閫傞厤鍣ㄧ紪鍙, 榛樿鏄嚜鍔ㄩ - timeout = 30, -- 鍙,璇诲彇鏈嶅姟鍣ㄥ搷搴旂殑瓒呮椂鏃堕棿,鍗曚綅绉,榛樿30 - bodyfile = "xxx", -- 鍙,鐩存帴鎶婃枃浠跺唴瀹逛綔涓篵ody涓婁紶, 浼樺厛绾ч珮浜巄ody鍙傛暟 - upload_file_buff = zbuff.create(1024*64) -- 鍙,涓婁紶鏃朵娇鐢ㄧ殑缂撳啿鍖,榛樿浼氭牴鎹瀷鍙峰垱寤轰竴涓猙uff -} - -local code, resp = httpplus.request({url="https://httpbin.air32.cn/get"}) -log.info("http", code) --- 杩斿洖鍊紃esp鐨勮鏄 --- 鎯呭喌1, code >= 100 鏃, resp浼氭槸涓猼able, 鍖呭惈2涓厓绱 -if code >= 100 then - -- headers, 鏄釜table - log.info("http", "headers", json.encode(resp.headers)) - -- body, 鏄釜zbuff - -- 閫氳繃query鍑芥暟鍙互杞负lua鐨剆tring - log.info("http", "headers", resp.body:query()) - -- 涔熷彲浠ラ氳繃uart.tx绛夋敮鎸亃buff鐨勫嚱鏁拌浆鍙戝嚭鍘 - -- uart.tx(1, resp.body) -end --- 鎯呭喌2, code < 0 鏃, resp浼氭槸涓敊璇俊鎭瓧绗︿覆 - --- 瀵箄pload_file_buff鍙傛暟鐨勮鏄 --- 1. 濡傛灉涓婁紶鐨勬枃浠舵瘮杈冨ぇ,寤鸿浼犲叆杩欎釜鍙傛暟,閬垮厤姣忔閮藉垱寤哄拰閿姣佺紦鍐插尯 --- 2. 濡傛灉涓嶄紶鍏ヨ繖涓弬鏁,鏈簱浼氭牴鎹笉鍚岀殑妯＄粍鍨嬪彿鍒涘缓涓涓悎閫傜殑缂撳啿鍖 --- 3. 澶氫釜鍚屾椂鎵ц鐨刪ttpplus璇锋眰,涓嶅彲浠ュ叡鐢ㄥ悓涓涓紦鍐插尯 -]] -function httpplus.request(opts) - -- 鍙傛暟瑙ｆ瀽 - local ret = http_opts_parse(opts) - if ret then - return ret - end - - -- 鎵ц璇锋眰 - local ret, msg = pcall(http_exec, opts) - if opts.netc then - -- 娓呯悊杩炴帴 - if not opts.is_closed then - socket.close(opts.netc) - end - socket.release(opts.netc) - opts.netc = nil - end - -- 澶勭悊鍝嶅簲鎴栭敊璇 - if not ret then - log.error(TAG, msg) - return -199, msg - end - return opts.resp_code, opts.resp -end - -return httpplus diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc.lua deleted file mode 100644 index 59daea3..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc.lua +++ /dev/null @@ -1,283 +0,0 @@ ---[[ -@module lbsLoc -@summary lbsLoc 鍙戦佸熀绔欏畾浣嶈姹 -@version 1.0 -@date 2022.12.16 -@author luatos -@usage --- lbsloc 鏄紓姝ュ洖璋冩帴鍙ｏ紝 --- lbsloc2 鏄槸鍚屾鎺ュ彛銆 --- lbsloc姣攍bsloc2澶氫簡涓涓姹傚湴鍧鏂囨湰鐨勫姛鑳姐 --- lbsloc 鍜 lbsloc2 閮芥槸鍏嶈垂LBS瀹氫綅鐨勫疄鐜版柟寮忥紱 --- airlbs 鎵╁睍搴撴槸鏀惰垂 LBS 鐨勫疄鐜版柟寮忋 - ---娉ㄦ剰:鍥犱娇鐢ㄤ簡sys.wait()鎵鏈塧pi闇瑕佸湪鍗忕▼涓娇鐢 ---鐢ㄦ硶瀹炰緥 ---娉ㄦ剰锛氭澶勭殑PRODUCT_KEY浠呬緵婕旂ず浣跨敤锛屼笉鑳界敤浜庣敓浜х幆澧 ---閲忎骇椤圭洰涓竴瀹氳浣跨敤鑷繁鍦╥ot.openluat.com涓垱寤虹殑椤圭洰productKey,椤圭洰璇︽儏閲屽彲浠ユ煡鐪 ---鍩虹珯瀹氫綅鐨勫潗鏍囩郴鏄 WSG84 -PRODUCT_KEY = "123" -local lbsLoc = require("lbsLoc") --- 鍔熻兘:鑾峰彇鍩虹珯瀵瑰簲鐨勭粡绾害鍚庣殑鍥炶皟鍑芥暟 --- 鍙傛暟:-- result锛歯umber绫诲瀷锛0琛ㄧず鎴愬姛锛1琛ㄧず缃戠粶鐜灏氭湭灏辩华锛2琛ㄧず杩炴帴鏈嶅姟鍣ㄥけ璐ワ紝3琛ㄧず鍙戦佹暟鎹け璐ワ紝4琛ㄧず鎺ユ敹鏈嶅姟鍣ㄥ簲绛旇秴鏃讹紝5琛ㄧず鏈嶅姟鍣ㄨ繑鍥炴煡璇㈠け璐ワ紱涓0鏃讹紝鍚庨潰鐨5涓弬鏁版墠鏈夋剰涔 - -- lat锛歴tring绫诲瀷锛岀含搴︼紝鏁存暟閮ㄥ垎3浣嶏紝灏忔暟閮ㄥ垎7浣嶏紝渚嬪031.2425864 - -- lng锛歴tring绫诲瀷锛岀粡搴︼紝鏁存暟閮ㄥ垎3浣嶏紝灏忔暟閮ㄥ垎7浣嶏紝渚嬪121.4736522 - -- addr锛氱洰鍓嶆棤鎰忎箟 - -- time锛歴tring绫诲瀷鎴栬卬il锛屾湇鍔″櫒杩斿洖鐨勬椂闂达紝6涓瓧鑺傦紝骞存湀鏃ユ椂鍒嗙锛岄渶瑕佽浆涓哄崄鍏繘鍒惰鍙 - -- 绗竴涓瓧鑺傦細骞村噺鍘2000锛屼緥濡2017骞达紝鍒欎负0x11 - -- 绗簩涓瓧鑺傦細鏈堬紝渚嬪7鏈堝垯涓0x07锛12鏈堝垯涓0x0C - -- 绗笁涓瓧鑺傦細鏃ワ紝渚嬪11鏃ュ垯涓0x0B - -- 绗洓涓瓧鑺傦細鏃讹紝渚嬪18鏃跺垯涓0x12 - -- 绗簲涓瓧鑺傦細鍒嗭紝渚嬪59鍒嗗垯涓0x3B - -- 绗叚涓瓧鑺傦細绉掞紝渚嬪48绉掑垯涓0x30 - -- locType锛歯umble绫诲瀷鎴栬卬il锛屽畾浣嶇被鍨嬶紝0琛ㄧず鍩虹珯瀹氫綅鎴愬姛锛255琛ㄧずWIFI瀹氫綅鎴愬姛 -function getLocCb(result, lat, lng, addr, time, locType) - log.info("testLbsLoc.getLocCb", result, lat, lng) - -- 鑾峰彇缁忕含搴︽垚鍔, 鍧愭爣绯籛GS84 - if result == 0 then - log.info("鏈嶅姟鍣ㄨ繑鍥炵殑鏃堕棿", time:toHex()) - log.info("瀹氫綅绫诲瀷,鍩虹珯瀹氫綅鎴愬姛杩斿洖0", locType) - end -end - -sys.taskInit(function() - sys.waitUntil("IP_READY", 30000) - while 1 do - mobile.reqCellInfo(15) - sys.waitUntil("CELL_INFO_UPDATE", 3000) - lbsLoc.request(getLocCb) - sys.wait(60000) - end -end) -]] - -local sys = require "sys" -local sysplus = require("sysplus") -local libnet = require("libnet") - -local lbsLoc = {} -local d1Name = "lbsLoc" - ---- ASCII瀛楃涓 杞寲涓 BCD缂栫爜鏍煎紡瀛楃涓(浠呮敮鎸佹暟瀛) --- @string inStr 寰呰浆鎹㈠瓧绗︿覆 --- @number destLen 杞崲鍚庣殑瀛楃涓叉湡鏈涢暱搴︼紝濡傛灉瀹為檯涓嶈冻锛屽垯濉厖F --- @return string data,杞崲鍚庣殑瀛楃涓 --- @usage -local function numToBcdNum(inStr,destLen) - local l,t,num = string.len(inStr or ""),{} - destLen = destLen or (inStr:len()+1)/2 - for i=1,l,2 do - num = tonumber(inStr:sub(i,i+1),16) - if i==l then - num = 0xf0+num - else - num = (num%0x10)*0x10 + (num-(num%0x10))/0x10 - end - table.insert(t,num) - end - - local s = string.char(unpack(t)) - - l = string.len(s) - if l < destLen then - s = s .. string.rep("\255",destLen-l) - elseif l > destLen then - s = string.sub(s,1,destLen) - end - - return s -end - ---- BCD缂栫爜鏍煎紡瀛楃涓 杞寲涓 鍙风爜ASCII瀛楃涓(浠呮敮鎸佹暟瀛) --- @string num 寰呰浆鎹㈠瓧绗︿覆 --- @return string data,杞崲鍚庣殑瀛楃涓 --- @usage -local function bcdNumToNum(num) - local byte,v1,v2 - local t = {} - - for i=1,num:len() do - byte = num:byte(i) - v1,v2 = bit.band(byte,0x0f),bit.band(bit.rshift(byte,4),0x0f) - - if v1 == 0x0f then break end - table.insert(t,v1) - - if v2 == 0x0f then break end - table.insert(t,v2) - end - - return table.concat(t) -end - - -local function netCB(msg) - --log.info("鏈鐞嗘秷鎭", msg[1], msg[2], msg[3], msg[4]) -end - - -local function enCellInfo(s) - local ret,t,mcc,mnc,lac,ci,rssi,k,v,m,n,cntrssi = "",{} - for k,v in pairs(s) do - mcc,mnc,lac,ci,rssi = v.mcc,v.mnc,v.tac,v.cid,((v.rsrq + 144) >31) and 31 or (v.rsrq + 144) - local handle = nil - for k,v in pairs(t) do - if v.lac == lac and v.mcc == mcc and v.mnc == mnc then - if #v.rssici < 8 then - table.insert(v.rssici,{rssi=rssi,ci=ci}) - end - handle = true - break - end - end - if not handle then - table.insert(t,{mcc=mcc,mnc=mnc,lac=lac,rssici={{rssi=rssi,ci=ci}}}) - end - log.debug("rssi,mcc,mnc,lac,ci", rssi,mcc,mnc,lac,ci) - end - for k,v in pairs(t) do - ret = ret .. pack.pack(">HHb",v.lac,v.mcc,v.mnc) - for m,n in pairs(v.rssici) do - cntrssi = bit.bor(bit.lshift(((m == 1) and (#v.rssici-1) or 0),5),n.rssi or n.rsrp) - ret = ret .. pack.pack(">bi",cntrssi,n.ci) - end - end - return string.char(#t)..ret -end - -local function enWifiInfo(tWifi) - local ret,cnt = "", 0 - if tWifi then - for k,v in pairs(tWifi) do - -- log.info("lbsLoc.enWifiInfo",k,v) - ret = ret..pack.pack("Ab",(k:gsub(":","")):fromHex(),(v<0) and (v+255) or v) - cnt = cnt+1 - end - end - return string.char(cnt)..ret -end - -local function enMuid() --鑾峰彇妯″潡MUID - local muid = mobile.muid() - return string.char(muid:len())..muid -end - -local function trans(str) - local s = str - if str:len()<10 then - s = str..string.rep("0",10-str:len()) - end - - return s:sub(1,3).."."..s:sub(4,10) -end - - -local function taskClient(cbFnc, reqAddr, timeout, productKey, host, port,reqTime, reqWifi) - if mobile.status() == 0 then - if not sys.waitUntil("IP_READY", timeout) then return cbFnc(1) end - sys.wait(500) - end - if productKey == nil then - productKey = "" - end - local retryCnt = 0 - local reqStr = pack.pack("bAbAAAAA", productKey:len(), productKey, - (reqAddr and 2 or 0) + (reqTime and 4 or 0) + 8 +(reqWifi and 16 or 0) + 32, "", - numToBcdNum(mobile.imei()), enMuid(), - enCellInfo(mobile.getCellInfo()), - enWifiInfo(reqWifi)) - log.debug("reqStr", reqStr:toHex()) - local rx_buff = zbuff.create(17) - -- sys.wait(5000) - while true do - local result,succ,param - local netc = socket.create(nil, d1Name) -- 鍒涘缓socket瀵硅薄 - if not netc then cbFnc(6) return end -- 鍒涘缓socket澶辫触 - socket.debug(netc, false) - socket.config(netc, nil, true, nil) - --result = libnet.waitLink(d1Name, 0, netc) - result = libnet.connect(d1Name, 5000, netc, host, port) - if result then - while true do - -- log.info(" lbsloc socket_service connect true") - result = libnet.tx(d1Name, 0, netc, reqStr) ---鍙戦佹暟鎹 - if result then - result, param = libnet.wait(d1Name, 15000 + retryCnt * 5, netc) - if not result then - socket.close(netc) - socket.release(netc) - retryCnt = retryCnt+1 - if retryCnt>=3 then return cbFnc(4) end - break - end - succ, param = socket.rx(netc, rx_buff) -- 鎺ユ敹鏁版嵁 - -- log.info("鏄惁鎺ユ敹鍜屾暟鎹暱搴", succ, param) - if param ~= 0 then -- 濡傛灉鎺ユ敹鎴愬姛 - socket.close(netc) -- 鍏抽棴杩炴帴 - socket.release(netc) - local read_buff = rx_buff:toStr(0, param) - rx_buff:clear() - log.debug("lbsLoc receive", read_buff:toHex()) - if read_buff:len() >= 11 and(read_buff:byte(1) == 0 or read_buff:byte(1) == 0xFF) then - local locType = read_buff:byte(1) - cbFnc(0, trans(bcdNumToNum(read_buff:sub(2, 6))), - trans(bcdNumToNum(read_buff:sub(7, 11))), reqAddr and - read_buff:sub(13, 12 + read_buff:byte(12)) or nil, - reqTime and read_buff:sub(reqAddr and (13 + read_buff:byte(12)) or 12, -1) or "", - locType) - else - log.warn("lbsLoc.query", "鏍规嵁鍩虹珯鏌ヨ缁忕含搴﹀け璐") - if read_buff:byte(1) == 2 then - log.warn("lbsLoc.query","main.lua涓殑PRODUCT_KEY鍜屾璁惧鍦╥ot.openluat.com涓墍灞為」鐩殑ProductKey蹇呴』涓鑷达紝璇峰幓妫鏌") - else - log.warn("lbsLoc.query","鍩虹珯鏁版嵁搴撴煡璇笉鍒版墍鏈夊皬鍖虹殑浣嶇疆淇℃伅") - -- log.warn("lbsLoc.query","鍦╰race涓悜涓婃悳绱ncellinfo锛岀劧鍚庡湪鐢佃剳娴忚鍣ㄤ腑鎵撳紑http://bs.openluat.com/锛屾墜鍔ㄦ煡鎵緀ncellinfo鍚庣殑鎵鏈夊皬鍖轰綅缃") - -- log.warn("lbsLoc.query","濡傛灉鎵嬪姩鍙互鏌ュ埌浣嶇疆锛屽垯鏈嶅姟鍣ㄥ瓨鍦˙UG锛岀洿鎺ュ悜鎶鏈汉鍛樺弽鏄犻棶棰") - -- log.warn("lbsLoc.query","濡傛灉鎵嬪姩鏃犳硶鏌ュ埌浣嶇疆锛屽垯鍩虹珯鏁版嵁搴撹繕娌℃湁鏀跺綍褰撳墠璁惧鐨勫皬鍖轰綅缃俊鎭紝鍚戞妧鏈汉鍛樺弽棣堬紝鎴戜滑浼氬敖蹇敹褰") - end - cbFnc(5) - end - return - else - socket.close(netc) - socket.release(netc) - retryCnt = retryCnt+1 - if retryCnt>=3 then return cbFnc(4) end - break - end - else - socket.close(netc) - socket.release(netc) - retryCnt = retryCnt+1 - if retryCnt>=3 then return cbFnc(3) end - break - end - end - else - socket.close(netc) - socket.release(netc) - retryCnt = retryCnt + 1 - if retryCnt >= 3 then return cbFnc(2) end - end - end -end - - ---[[ -鍙戦佸熀绔欏畾浣嶈姹 -@api lbsLoc.request(cbFnc,reqAddr,timeout,productKey,host,port,reqTime,reqWifi) -@function cbFnc 鐢ㄦ埛鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓猴細cbFnc(result,lat,lng,addr,time,locType) -@bool reqAddr 鏄惁璇锋眰鏈嶅姟鍣ㄨ繑鍥炲叿浣撶殑浣嶇疆瀛楃涓蹭俊鎭紝宸茬粡涓嶆敮鎸,濉玣alse鎴栬卬il -@number timeout 璇锋眰瓒呮椂鏃堕棿锛屽崟浣嶆绉掞紝榛樿20000姣 -@string productKey IOT缃戠珯涓婄殑浜у搧KEY锛屽鏋滃湪main.lua涓畾涔変簡PRODUCT_KEY鍙橀噺锛屽垯姝ゅ弬鏁板彲浠ヤ紶nil -@string host 鏈嶅姟鍣ㄥ煙鍚, 榛樿 "bs.openluat.com" ,鍙夊鐢ㄦ湇鍔″櫒(涓嶄繚璇佸彲鐢) "bs.air32.cn" -@string port 鏈嶅姟鍣ㄧ鍙ｏ紝榛樿"12411",涓鑸笉闇瑕佽缃 -@return nil 鏃犺繑鍥炲 -@usage --- 鎻愰啋: 杩斿洖鐨勫潗鏍囧, 鏄疻GS84鍧愭爣绯 -]] -function lbsLoc.request(cbFnc,reqAddr,timeout,productKey,host,port,reqTime,reqWifi) - sysplus.taskInitEx(taskClient, d1Name, netCB, cbFnc, reqAddr,timeout or 20000,productKey or _G.PRODUCT_KEY,host or "bs.openluat.com",port or "12411", reqTime == nil and true or reqTime,reqWifi) -end - -return lbsLoc diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc2.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc2.lua deleted file mode 100644 index 23a96bc..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/lbsLoc2.lua +++ /dev/null @@ -1,229 +0,0 @@ ---[[ -@module lbsLoc2 -@summary 鍩虹珯瀹氫綅v2 -@version 1.0 -@date 2023.5.23 -@author wendal -@demo lbsLoc2 -@usage --- lbsloc 鏄紓姝ュ洖璋冩帴鍙ｏ紝 --- lbsloc2 鏄槸鍚屾鎺ュ彛銆 --- lbsloc姣攍bsloc2澶氫簡涓涓姹傚湴鍧鏂囨湰鐨勫姛鑳姐 --- lbsloc 鍜 lbsloc2 閮芥槸鍏嶈垂LBS瀹氫綅鐨勫疄鐜版柟寮忥紱 --- airlbs 鎵╁睍搴撴槸鏀惰垂 LBS 鐨勫疄鐜版柟寮忋 - --- 娉ㄦ剰: --- 1. 鍥犱娇鐢ㄤ簡sys.wait()鎵鏈塧pi闇瑕佸湪鍗忕▼涓娇鐢 --- 2. 浠呮敮鎸佸崟鍩虹珯瀹氫綅, 鍗冲綋鍓嶈仈缃戠殑鍩虹珯 --- 3. 鏈湇鍔″綋鍓嶅浜庢祴璇曠姸鎬 -sys.taskInit(function() - sys.waitUntil("IP_READY", 30000) - -- mobile.reqCellInfo(60) - -- sys.wait(1000) - while mobile do -- 娌℃湁mobile搴撳氨娌℃湁鍩虹珯瀹氫綅 - mobile.reqCellInfo(15) - sys.waitUntil("CELL_INFO_UPDATE", 3000) - local lat, lng, t = lbsLoc2.request(5000) - -- local lat, lng, t = lbsLoc2.request(5000, "bs.openluat.com") - log.info("lbsLoc2", lat, lng, (json.encode(t or {}))) - sys.wait(60000) - end -end) -]] - -local sys = require "sys" - -local lbsLoc2 = {} - -local function numToBcdNum(inStr,destLen) - local l,t,num = string.len(inStr or ""),{} - destLen = destLen or (inStr:len()+1)/2 - for i=1,l,2 do - num = tonumber(inStr:sub(i,i+1),16) - if i==l then - num = 0xf0+num - else - num = (num%0x10)*0x10 + (num-(num%0x10))/0x10 - end - table.insert(t,num) - end - - local s = string.char(unpack(t)) - - l = string.len(s) - if l < destLen then - s = s .. string.rep("\255",destLen-l) - elseif l > destLen then - s = string.sub(s,1,destLen) - end - - return s -end - ---- BCD缂栫爜鏍煎紡瀛楃涓 杞寲涓 鍙风爜ASCII瀛楃涓(浠呮敮鎸佹暟瀛) --- @string num 寰呰浆鎹㈠瓧绗︿覆 --- @return string data,杞崲鍚庣殑瀛楃涓 --- @usage -local function bcdNumToNum(num) - local byte,v1,v2 - local t = {} - - for i=1,num:len() do - byte = num:byte(i) - v1,v2 = bit.band(byte,0x0f),bit.band(bit.rshift(byte,4),0x0f) - - if v1 == 0x0f then break end - table.insert(t,v1) - - if v2 == 0x0f then break end - table.insert(t,v2) - end - - return table.concat(t) -end - -lbsLoc2.imei = numToBcdNum(mobile.imei()) - -local function enCellInfo(s) - -- 鏀归犳垚鍗曞熀绔, 鍙嶆鏈嶅姟鍣ㄤ篃鍙鍗曞熀绔 - local v = s[1] - log.info("cell", json.encode(v)) - local ret = pack.pack(">HHbbi",v.tac,v.mcc,v.mnc,31,v.cid) - return string.char(1)..ret -end - -local function trans(str) - local s = str - if str:len()<10 then - s = str..string.rep("0",10-str:len()) - end - - return s:sub(1,3).."."..s:sub(4,10) -end - ---[[ -鎵ц瀹氫綅璇锋眰 -@api lbsLoc2.request(timeout, host, port, reqTime) -@number 璇锋眰瓒呮椂鏃堕棿,鍗曚綅姣,榛樿15000 -@number 鏈嶅姟鍣ㄥ湴鍧,鏈夐粯璁ゅ,鍙互鏄煙鍚,涓鑸笉闇瑕佸～ -@number 鏈嶅姟鍣ㄧ鍙,榛樿12411,涓鑸笉闇瑕佸～ -@bool 鏄惁瑕佹眰杩斿洖鏈嶅姟鍣ㄦ椂闂 -@return string 鑻ユ垚鍔,杩斿洖瀹氫綅鍧愭爣鐨勭含搴,鍚﹀垯浼氳繑杩榥il -@return string 鑻ユ垚鍔,杩斿洖瀹氫綅鍧愭爣鐨勭粡搴,鍚﹀垯浼氳繑杩榥il -@return table 鏈嶅姟鍣ㄦ椂闂,涓滃叓鍖烘椂闂. 褰搑eqTime涓簍rue涓斿畾浣嶆垚鍔熸墠浼氳繑鍥 -@usage --- 鍏充簬鍧愭爣绯 --- 閮ㄥ垎鎯呭喌涓嬩細杩斿洖GCJ02鍧愭爣绯, 閮ㄥ垎鎯呭喌杩斿洖鐨勬槸WGS84鍧愭爣 --- 鍘嗗彶鏁版嵁宸茬粡鏃犳硶鍒嗚鲸鍏蜂綋鍧愭爣绯 --- 閴翠簬涓ょ鍧愭爣绯讳箣闂寸殑璇樊骞朵笉澶,灏忎簬鍩虹珯瀹氫綅鏈韩鐨勮宸, 绾犲亸鐨勬剰涔変笉澶 -sys.taskInit(function() - sys.waitUntil("IP_READY", 30000) - -- mobile.reqCellInfo(60) - -- sys.wait(1000) - while mobile do -- 娌℃湁mobile搴撳氨娌℃湁鍩虹珯瀹氫綅 - mobile.reqCellInfo(15) - sys.waitUntil("CELL_INFO_UPDATE", 3000) - local lat, lng, t = lbsLoc2.request(5000) - -- local lat, lng, t = lbsLoc2.request(5000, "bs.openluat.com") - log.info("lbsLoc2", lat, lng, (json.encode(t or {}))) - sys.wait(60000) - end -end) -]] -function lbsLoc2.request(timeout, host, port, reqTime) - if mobile.status() == 0 then - return - end - local hosts = host and {host} or {"free.bs.air32.cn", "bs.openluat.com"} - port = port and tonumber(port) or 12411 - local sc = socket.create(nil, function(sc, event) - -- log.info("lbsLoc", "event", event, socket.ON_LINE, socket.TX_OK, socket.EVENT) - if event == socket.ON_LINE then - --log.info("lbsLoc", "宸茶繛鎺") - sys.publish("LBS_CONACK") - elseif event == socket.TX_OK then - --log.info("lbsLoc", "鍙戦佸畬鎴") - sys.publish("LBS_TX") - elseif event == socket.EVENT then - --log.info("lbsLoc", "鏈夋暟鎹潵") - sys.publish("LBS_RX") - end - end) - if sc == nil then - return - end - -- socket.debug(sc, true) - socket.config(sc, nil, true) - local rxbuff = zbuff.create(64) - for k, rhost in pairs(hosts) do - local reqStr = string.char(0, (reqTime and 4 or 0) +8) .. lbsLoc2.imei - local tmp = nil - if mobile.scell then - local scell = mobile.scell() - if scell and scell.mcc then - -- log.debug("lbsLoc2", "浣跨敤褰撳墠椹荤綉鍩虹珯鐨勪俊鎭") - tmp = pack.pack(">bHHbbi", 1, scell.tac, scell.mcc, scell.mnc, 31, scell.eci) - end - end - if tmp == nil then - local cells = mobile.getCellInfo() - if cells == nil or #cells == 0 then - socket.release(sc) - return - end - reqStr = reqStr .. enCellInfo(cells) - else - reqStr = reqStr .. tmp - end - -- log.debug("lbsLoc2", "寰呭彂閫佹暟鎹", (reqStr:toHex())) - log.debug("lbsLoc2", rhost, port) - if socket.connect(sc, rhost, port) and sys.waitUntil("LBS_CONACK", 1000) then - if socket.tx(sc, reqStr) and sys.waitUntil("LBS_TX", 1000) then - socket.wait(sc) - if sys.waitUntil("LBS_RX", timeout or 15000) then - local succ, data_len = socket.rx(sc, rxbuff) - -- log.debug("lbsLoc", "rx", succ, data_len) - if succ and data_len > 0 then - socket.close(sc) - break - else - log.debug("lbsLoc", "rx鏁版嵁澶辫触", rhost) - end - else - log.debug("lbsLoc", "绛夊緟鏁版嵁瓒呮椂", rhost) - end - else - log.debug("lbsLoc", "tx璋冪敤澶辫触鎴朤X_ACK瓒呮椂", rhost) - end - else - log.debug("lbsLoc", "connect璋冪敤澶辫触鎴朇ONACK瓒呮椂", rhost) - end - socket.close(sc) - --sys.wait(100) - end - sys.wait(100) - socket.release(sc) - if rxbuff:used() > 0 then - local resp = rxbuff:toStr(0, rxbuff:used()) - log.debug("lbsLoc2", "rx", (resp:toHex())) - if resp:len() >= 11 and(resp:byte(1) == 0 or resp:byte(1) == 0xFF) then - local lat = trans(bcdNumToNum(resp:sub(2, 6))) - local lng = trans(bcdNumToNum(resp:sub(7, 11))) - local t = nil - if resp:len() >= 17 then - t = { - year=resp:byte(12) + 2000, - month=resp:byte(13), - day=resp:byte(14), - hour=resp:byte(15), - min=resp:byte(16), - sec=resp:byte(17), - } - end - return lat, lng, t - end - end - rxbuff:del() -end - -return lbsLoc2 diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota.lua deleted file mode 100644 index bcbea04..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota.lua +++ /dev/null @@ -1,145 +0,0 @@ ---[[ -@module libfota -@summary libfota fota鍗囩骇 -@version 1.0 -@date 2023.02.01 -@author Dozingfiretruck -@demo fota -@usage ---娉ㄦ剰:鍥犱娇鐢ㄤ簡sys.wait()鎵鏈塧pi闇瑕佸湪鍗忕▼涓娇鐢 ---鐢ㄦ硶瀹炰緥 -local libfota = require("libfota") - --- 鍔熻兘:鑾峰彇fota鐨勫洖璋冨嚱鏁 --- 鍙傛暟: --- result:number绫诲瀷 --- 0琛ㄧず鎴愬姛 --- 1琛ㄧず杩炴帴澶辫触 --- 2琛ㄧずurl閿欒 --- 3琛ㄧず鏈嶅姟鍣ㄦ柇寮 --- 4琛ㄧず鎺ユ敹鎶ユ枃閿欒 --- 5琛ㄧず浣跨敤iot骞冲彴VERSION闇瑕佷娇鐢 xxx.yyy.zzz褰㈠紡 -function libfota_cb(result) - log.info("fota", "result", result) - -- fota鎴愬姛 - if result == 0 then - rtos.reboot() --濡傛灉杩樻湁鍏朵粬浜嬫儏瑕佸仛,灏变笉瑕佺珛鍒籸eboot - end -end - ---娉ㄦ剰!!!:浣跨敤鍚堝畽iot骞冲彴,蹇呴』鐢╨uatools閲忎骇鐢熸垚鐨.bin鏂囦欢!!! 鑷缓鏈嶅姟鍣ㄥ彲浣跨敤.ota鏂囦欢!!! ---娉ㄦ剰!!!:浣跨敤鍚堝畽iot骞冲彴,蹇呴』鐢╨uatools閲忎骇鐢熸垚鐨.bin鏂囦欢!!! 鑷缓鏈嶅姟鍣ㄥ彲浣跨敤.ota鏂囦欢!!! ---娉ㄦ剰!!!:浣跨敤鍚堝畽iot骞冲彴,蹇呴』鐢╨uatools閲忎骇鐢熸垚鐨.bin鏂囦欢!!! 鑷缓鏈嶅姟鍣ㄥ彲浣跨敤.ota鏂囦欢!!! - ---涓嬫柟绀轰緥涓哄悎瀹檌ot骞冲彴,鍦板潃:http://iot.openluat.com -libfota.request(libfota_cb) - ---濡備娇鐢ㄨ嚜寤烘湇鍔″櫒,鑷鏇存崲url --- 瀵硅嚜瀹氫箟鏈嶅姟鍣ㄧ殑瑕佹眰鏄: --- 鑻ラ渶瑕佸崌绾, 鍝嶅簲http 200, body涓哄崌绾ф枃浠剁殑鍐呭 --- 鑻ヤ笉闇瑕佸崌绾, 鍝嶅簲300鎴栦互涓婄殑浠ｇ爜,鍔″繀娉ㄦ剰 -libfota.request(libfota_cb,"http://xxxxxx.com/xxx/upgrade?version=" .. _G.VERSION) - --- 鑻ラ渶瑕佸畾鏃跺崌绾 --- 鍚堝畽iot骞冲彴 -sys.timerLoopStart(libfota.request, 4*3600*1000, libfota_cb) --- 鑷缓骞冲彴 -sys.timerLoopStart(libfota.request, 4*3600*1000, libfota_cb, "http://xxxxxx.com/xxx/upgrade?version=" .. _G.VERSION) -]] - -local sys = require "sys" -local sysplus = require "sysplus" - -local libfota = {} - - -local function fota_task(cbFnc,storge_location, len, param1,ota_url,ota_port,libfota_timeout,server_cert, client_cert, client_key, client_password, show_otaurl) - if cbFnc == nil then - cbFnc = function() end - end - -- 鑻ta_url娌℃湁浼,閭ｅ氨鏄敤鍚堝畽iot骞冲彴 - if ota_url == nil then - if _G.PRODUCT_KEY == nil then - -- 蹇呴』鍦╩ain.lua瀹氫箟 PRODUCT_KEY = "xxx" - -- iot骞冲彴鏂板缓椤圭洰鍚, 椤圭洰璇︽儏涓彲浠ユ煡鍒 - log.error("fota", "iot.openluat.com need PRODUCT_KEY!!!") - cbFnc(5) - return - else - local x,y,z = string.match(_G.VERSION,"(%d+).(%d+).(%d+)") - if x and y and z then - local query = "" - local firmware_name = _G.PROJECT.. "_" .. rtos.firmware() - local version = _G.VERSION - if mobile then - query = "imei=" .. mobile.imei() - version = rtos.version():sub(2) .. "." .. x .. "." .. z - firmware_name = _G.PROJECT.. "_LuatOS-SoC_" .. rtos.bsp() - elseif wlan and wlan.getMac then - query = "mac=" .. wlan.getMac() - version = rtos.version():sub(2) .. "." .. x .. "." .. z - firmware_name = _G.PROJECT.. "_LuatOS-SoC_" .. rtos.bsp() - else - query = "uid=" .. mcu.unique_id():toHex() - end - local tmp = "http://iot.openluat.com/api/site/firmware_upgrade?project_key=%s&firmware_name=%s&version=%s&%s" - ota_url = string.format(tmp, _G.PRODUCT_KEY, firmware_name, version, query) - else - log.error("fota", "_G.VERSION must be xxx.yyy.zzz!!!") - cbFnc(5) - return - end - end - end - local ret - local opts = {timeout = libfota_timeout} - if fota then - opts.fota = true - else - os.remove("/update.bin") - opts.dst = "/update.bin" - end - if show_otaurl == nil or show_otaurl == true then - log.info("fota.url", ota_url) - end - local code, headers, body = http.request("GET", ota_url, nil, nil, opts, server_cert, client_cert, client_key, client_password).wait() - log.info("http fota", code, headers, body) - if code == 200 or code == 206 then - if body == 0 then - ret = 4 - else - ret = 0 - end - elseif code == -4 then - ret = 1 - elseif code == -5 then - ret = 3 - else - ret = 4 - end - cbFnc(ret) -end - ---[[ -fota鍗囩骇 -@api libfota.request(cbFnc,ota_url,storge_location, len, param1,ota_port,libfota_timeout,server_cert, client_cert, client_key, client_password) -@function cbFnc 鐢ㄦ埛鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓猴細cbFnc(result) , 蹇呴』浼 -@string ota_url 鍗囩骇URL, 鑻ヤ笉濉垯鑷姩浣跨敤鍚堝畽iot骞冲彴 -@number/string storge_location 鍙,fota鏁版嵁瀛樺偍鐨勮捣濮嬩綅缃
濡傛灉鏄痠nt锛屽垯鏄敱鑺墖骞冲彴鍏蜂綋鍒ゆ柇
濡傛灉鏄痵tring锛屽垯瀛樺偍鍦ㄦ枃浠剁郴缁熶腑
濡傛灉涓簄il锛屽垯鐢卞簳灞傚喅瀹氬瓨鍌ㄤ綅缃 -@number len 鍙,鏁版嵁瀛樺偍鐨勬渶澶х┖闂 -@userdata param1,鍙,濡傛灉鏁版嵁瀛樺偍鍦╯piflash鏃,涓簊pi_device -@number ota_port 鍙,璇锋眰绔彛,榛樿80 -@number libfota_timeout 鍙,璇锋眰瓒呮椂鏃堕棿,鍗曚綅姣,榛樿30000姣 -@string server_cert 鍙,鏈嶅姟鍣╟a璇佷功鏁版嵁 -@string client_cert 鍙,瀹㈡埛绔瘉涔︽暟鎹 -@string client_key 鍙,瀹㈡埛绔閽ュ姞瀵嗘暟鎹 -@string client_password 鍙,瀹㈡埛绔閽ュ彛浠ゆ暟鎹 -@boolean show_otaurl 鍙,鏄惁浠庢棩蹇椾腑杈撳嚭鎵撳嵃OTA鍗囩骇鍖呯殑URL璺緞锛岄粯璁や細鎵撳嵃 -@return nil 鏃犺繑鍥炲 -]] -function libfota.request(cbFnc,ota_url,storge_location, len, param1,ota_port,libfota_timeout,server_cert, client_cert, client_key, client_password, show_otaurl) - sys.taskInit(fota_task, cbFnc,storge_location, len, param1,ota_url, ota_port,libfota_timeout or 180000,server_cert, client_cert, client_key, client_password, show_otaurl) -end - -return libfota - diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota2.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota2.lua deleted file mode 100644 index 82542c0..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libfota2.lua +++ /dev/null @@ -1,219 +0,0 @@ ---[[ -@module libfota2 -@summary fota鍗囩骇v2 -@version 1.1 -@date 2024.11.22 -@author wendal/HH -@demo fota2 -@usage ---鐢ㄦ硶瀹炰緥 -local libfota2 = require("libfota2") - --- 鍔熻兘:鑾峰彇fota鐨勫洖璋冨嚱鏁 --- 鍙傛暟: --- result:number绫诲瀷 --- 0琛ㄧず鎴愬姛 --- 1琛ㄧず杩炴帴澶辫触 --- 2琛ㄧずurl閿欒 --- 3琛ㄧず鏈嶅姟鍣ㄦ柇寮 --- 4琛ㄧず鎺ユ敹鎶ユ枃閿欒 --- 5琛ㄧず浣跨敤iot骞冲彴VERSION闇瑕佷娇鐢 xxx.yyy.zzz褰㈠紡 -function libfota_cb(result) - log.info("fota", "result", result) - -- fota鎴愬姛 - if result == 0 then - rtos.reboot() --濡傛灉杩樻湁鍏朵粬浜嬫儏瑕佸仛,鑷鍐冲畾reboot鐨勬椂鏈 - end -end - ---涓嬫柟绀轰緥涓哄悎瀹檌ot骞冲彴,鍦板潃:http://iot.openluat.com -libfota2.request(libfota_cb) - ---濡備娇鐢ㄨ嚜寤烘湇鍔″櫒,鑷鏇存崲url --- 瀵硅嚜瀹氫箟鏈嶅姟鍣ㄧ殑瑕佹眰鏄: --- 鑻ラ渶瑕佸崌绾, 鍝嶅簲http 200, body涓哄崌绾ф枃浠剁殑鍐呭 --- 鑻ヤ笉闇瑕佸崌绾, 鍝嶅簲300鎴栦互涓婄殑浠ｇ爜,鍔″繀娉ㄦ剰 -local opts = {url="http://xxxxxx.com/xxx/upgrade"} --- opts鐨勮缁嗚鏄, 鐪嬪悗闈㈢殑鍑芥暟API鏂囨。 -libfota2.request(libfota_cb, opts) - --- 鑻ラ渶瑕佸畾鏃跺崌绾 --- 鍚堝畽iot骞冲彴 -sys.timerLoopStart(libfota2.request, 4*3600*1000, libfota_cb) --- 鑷缓骞冲彴 -sys.timerLoopStart(libfota2.request, 4*3600*1000, libfota_cb, opts) -]] - -local sys = require "sys" -require "sysplus" - -local libfota2 = {} - --- 鍗曠嫭鍒ゆ柇涓嬫湇鍔″櫒涓嬪彂鐨勬暟鎹槸涓嶆槸"{"寮澶"}"缁撳熬鐨勫瓧绗︿覆 -local function isjson(str) - local start, _ = string.find(str, "^%{") - local _, end_ = string.find(str, "%}$") - return start == 1 and end_ == #str and string.sub(str, 2, #str - 1):find("%B{") == nil -end - -local function fota_task(cbFnc, opts) - local ret = 0 - local url = opts.url - local code, headers, body = http.request(opts.method, opts.url, opts.headers, opts.body, opts, opts.server_cert, - opts.client_cert, opts.client_key, opts.client_password).wait() - -- log.info("http fota", code, headers, body) - if code == 200 or code == 206 then - if body == 0 then - ret = 4 - else - ret = 0 - end - elseif code == -4 then - ret = 1 - elseif code == -5 then - ret = 3 - else - log.info("libfota2", code, body) - ret = 4 - local hziot = "iot.openluat.com" - local msg, json_body, result - if string.find(url, hziot) then - log.info("浣跨敤鍚堝畽鏈嶅姟鍣,鎺ヤ笅鏉ヨВ鏋恇ody閲岀殑code") - json_body, result = json.decode(body) - -- 濡傛灉json瑙ｆ瀽澶辫触锛岃瘉鏄庢湇鍔″櫒涓嬪彂鐨勪笉鏄痡son - if result == 1 and isjson(body) then - code = json_body["code"] - else - -- 杩欎釜鍊奸殢渚垮彇鐨勶紝鍙涓嶅拰鍏朵粬瀹氫箟閲嶅灏辫 - code = 1111111111111 - end - if code == 43 then - log.info("璇风瓑寰", - ",浜戝钩鍙扮敓鎴愬樊鍒嗗崌绾у寘闇瑕佺瓑寰,涓鍒颁笁鍒嗛挓鍚庝簯骞冲彴鐢熸垚瀹屾垚宸垎鍖呬究鍙互璇锋眰鎴愬姛") - elseif code == 3 then - log.info("鏃犳晥鐨勮澶", "妫鏌ヨ姹傞敭鍚(imei灏忓啓)姝ｇ‘鎬") - elseif code == 17 then - log.info("鏃犳潈闄", - "璁惧浼氫笂鎶mei銆佸浐浠跺悕銆侀」鐩甼ey,鏈嶅姟鍣ㄤ細浠ユ鏌ュ嚭璁惧銆佸浐浠躲侀」鐩笁 鏉¤褰曪紝濡傛灉 杩欎笁鑰呬笉鍦ㄥ悓涓涓敤鎴峰悕涓嬶紝灏变細璁や负鏃犳潈闄愩傝澶囦笉鍦ㄩ」鐩甼ey瀵瑰簲鐨勮处鎴蜂笅锛屽彲瀵绘壘鍚堝畽鎶鏈敮鎸佹煡璇㈣璁惧鍦ㄥ摢涓处鎴蜂笅锛屾牳瀹炴儏鍐靛悗鍙慨鏀硅澶囧綊灞") - elseif code == 21 then - log.info("涓嶅厑璁稿崌绾", "璇锋鏌OT骞冲彴,鏄惁瀵瑰簲imei琚姝簡鍗囩骇") - elseif code == 25 then - log.info("鏃犳晥鐨勯」鐩", - "productkey涓嶄竴鑷,妫鏌ユ槸鍚﹀瓨鍦ㄦ嫾鍐欓敊璇,妫鏌ユā鍧楁槸鍚﹀湪鏈汉璐︽埛涓,鑻ヤ笉鍦ㄦ湰浜鸿处鎴蜂笅,璇疯仈绯诲悎瀹欏伐浣滀汉鍛樺鐞") - elseif code == 26 then - log.info("鏃犳晥鐨勫浐浠", - "鍥轰欢鍚嶇О閿欒,椤圭洰涓病鏈夊搴旂殑鍥轰欢,涔熸湁鍙兘鏄敤鎴疯嚜宸变慨鏀逛簡鍥轰欢鍚嶇О,鍙鐓у崌绾ф棩蹇椾腑璁惧褰撳墠鍥轰欢鍚嶄笌鍗囩骇閰嶇疆涓浐浠跺悕鏄惁鐩稿悓(鍥轰欢鍚嶇О,鍥轰欢鍔熻兘瑕佸畬鍏ㄤ竴鑷,鍙槸鐗堟湰鍙蜂笉鍚)") - elseif code == 27 then - log.info("宸叉槸鏈鏂扮増鏈", - "1.璁惧鐨勫浐浠/鑴氭湰鐗堟湰楂樹簬鎴栫瓑浜庝簯骞冲彴涓婄殑鐗堟湰鍙 2.鐢ㄦ埛椤圭洰鍗囩骇閰嶇疆涓湭娣诲姞璇ヨ澶 3.浜戝钩鍙板崌绾ч厤缃腑锛屾槸鍚﹀崌绾ч厤缃负鍚") - elseif code == 40 then - log.info("寰幆鍗囩骇", - "浜戝钩鍙拌繘鍏ヨ澶囧垪琛ㄦ悳绱㈣绂佹鐨刬mei,瑙ｉ櫎绂佹鍗囩骇鍗冲彲. 浜戝钩鍙伴槻姝㈡ā鍧楀湪鍗囩骇澶辫触鍚,鍙嶅璇锋眰鍗囩骇瀵艰嚧娴侀噺鍗℃祦閲忚楀敖,鍦ㄦā鍧椾竴澶╄姹傚崌绾у叚娆″悗浼氱姝㈡ā鍧楀崌绾. 鍙湪骞冲彴瑙ｉ櫎") - elseif code == 1111111111111 then - log.info("浜戝钩鍙颁笅鍙戠殑涓嶆槸json", "鎴戠湅鐪媌ody鏄釜浠涔堜笢瑗", type(body), body) - else - log.info("涓嶆槸涓婇潰鐨勯偅浜涢敊璇痗ode", code) - end - end - end - - cbFnc(ret) -end - ---[[ -fota鍗囩骇 -@api libfota2.request(cbFnc, opts) -@function cbFnc 鐢ㄦ埛鍥炶皟鍑芥暟锛屽洖璋冨嚱鏁扮殑璋冪敤褰㈠紡涓猴細cbFnc(result) , 蹇呴』浼 -@table fota鍙傛暟, 鍚庨潰鏈夎缁嗘弿杩 -@return nil 鏃犺繑鍥炲 -@usaga - --- opts鍙傛暟璇存槑, 鎵鏈夊弬鏁伴兘鏄彲閫夌殑 --- 1. opts.url string 鍗囩骇鎵闇瑕佺殑URL, 鑻ヤ娇鐢ㄥ悎瀹檌ot骞冲彴,鍒欎笉闇瑕佸～ --- 2. opts.version string 鐗堟湰鍙, 榛樿鏄 BSP鐗堟湰鍙.x.z鏍煎紡 --- 3. opts.timeout int 璇锋眰瓒呮椂鏃堕棿, 榛樿300000姣,鍗曚綅姣 --- 4. opts.project_key string 鍚堝畽IOT骞冲彴鐨勯」鐩甼ey, 榛樿鍙栧叏灞鍙橀噺PRODUCT_KEY. 鑷缓鏈嶅姟鍣ㄤ笉鐢ㄥ～ --- 5. opts.imei string 璁惧璇嗗埆鐮, 榛樿鍙朓MEI(Cat.1妯″潡)鎴朩LAN MAC鍦板潃(wifi妯″潡)鎴朚CU鍞竴ID --- 6. opts.firmware_name string 鍥轰欢鍚嶇О,榛樿鏄 _G.PROJECT.. "_LuatOS-SoC_" .. rtos.bsp() --- 7. opts.server_cert string 鏈嶅姟鍣ㄨ瘉涔, 榛樿涓嶄娇鐢 --- 8. opts.client_cert string 瀹㈡埛绔瘉涔, 榛樿涓嶄娇鐢 --- 9. opts.client_key string 瀹㈡埛绔閽, 榛樿涓嶄娇鐢 --- 10. opts.client_password string 瀹㈡埛绔閽ュ彛浠, 榛樿涓嶄娇鐢 --- 11. opts.method string 璇锋眰鏂规硶, 榛樿鏄疓ET --- 12. opts.headers table 棰濆娣诲姞鐨勮姹傚ご,榛樿涓嶉渶瑕 --- 13. opts.body string 棰濆娣诲姞鐨勮姹俠ody,榛樿涓嶉渶瑕 -]] -function libfota2.request(cbFnc, opts) - if not opts then - opts = {} - end - if fota then - opts.fota = true - else - os.remove("/update.bin") - opts.dst = "/update.bin" - end - if not cbFnc then - cbFnc = function(ret) - end - end - -- 澶勭悊URL - if not opts.url then - opts.url = "http://iot.openluat.com/api/site/firmware_upgrade?" - end - local query = "" - if opts.url:sub(1, 3) ~= "###" and not opts.url_done then - -- 琛ラ綈project_key鍑芥暟 - if not opts.project_key then - opts.project_key = _G.PRODUCT_KEY - if not opts.project_key then - log.error("libfota2", "iot.openluat.com need PRODUCT_KEY!!!") - cbFnc(5) - return - end - end - -- 琛ラ綈version鍙傛暟 - if not opts.version then - local x, y, z = string.match(_G.VERSION, "(%d+).(%d+).(%d+)") - opts.version = rtos.version():sub(2) .. "." .. x .. "." .. z - end - -- 琛ラ綈firmware_name鍙傛暟 - if not opts.firmware_name then - opts.firmware_name = _G.PROJECT .. "_LuatOS-SoC_" .. rtos.bsp() - end - -- 琛ラ綈imei鍙傛暟 - if not opts.imei then - if mobile then - query = "imei=" .. mobile.imei() - elseif wlan and wlan.getMac then - query = "mac=" .. wlan.getMac() - else - query = "uid=" .. mcu.unique_id():toHex() - end - end - - -- 鐒跺悗鎷兼帴鍒版渶缁堢殑url閲 - if not opts.imei then - opts.url = string.format("%s%s&project_key=%s&firmware_name=%s&version=%s", opts.url, query, opts.project_key, opts.firmware_name, opts.version) - else - opts.url = string.format("%simei=%s&project_key=%s&firmware_name=%s&version=%s", opts.url, opts.imei, opts.project_key, opts.firmware_name, opts.version) - end - else - if opts.url:sub(1,3)=="###" then - opts.url = opts.url:sub(4) - end - end - opts.url_done = true - -- 澶勭悊method - if not opts.method then - opts.method = "GET" - end - log.info("libfota2.url", opts.method, opts.url) - log.info("libfota2.imei/mac/uid", query) - log.info("libfota2.project_key", opts.project_key) - log.info("libfota2.firmware_name", opts.firmware_name) - log.info("libfota2.version", opts.version) - sys.taskInit(fota_task, cbFnc, opts) -end - -return libfota2 diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libnet.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/libnet.lua deleted file mode 100644 index 867260b..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/libnet.lua +++ /dev/null @@ -1,168 +0,0 @@ ---[[ -@module libnet -@summary libnet 鍦╯ocket搴撳熀纭涓婄殑鍚屾闃诲api锛宻ocket搴撴湰韬槸寮傛闈為樆濉瀉pi -@version 1.0 -@date 2023.03.16 -@author lisiqi -]] - -local libnet = {} - ---[[ -闃诲绛夊緟缃戝崱鐨勭綉缁滆繛鎺ヤ笂锛屽彧鑳界敤浜巗ysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑 -@api libnet.waitLink(taskName,timeout,...) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鑷寸瓑寰 -@... 鍏朵粬鍙傛暟鍜宻ocket.linkup涓鑷 -@return boolean 澶辫触鎴栬呰秴鏃惰繑鍥瀎alse 鎴愬姛杩斿洖true -]] -function libnet.waitLink(taskName, timeout, ...) - local succ, result = socket.linkup(...) - if not succ then - return false - end - if not result then - result = sysplus.waitMsg(taskName, socket.LINK, timeout) - else - return true - end - if type(result) == 'table' and result[2] == 0 then - return true - else - return false - end -end - - ---[[ -闃诲绛夊緟IP鎴栬呭煙鍚嶈繛鎺ヤ笂锛屽鏋滃姞瀵嗚繛鎺ヨ繕瑕佺瓑鎻℃墜瀹屾垚锛屽彧鑳界敤浜巗ysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑 -@api libnet.connect(taskName,timeout,...) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鑷寸瓑寰 -@... 鍏朵粬鍙傛暟鍜宻ocket.connect涓鑷 -@return boolean 澶辫触鎴栬呰秴鏃惰繑鍥瀎alse 鎴愬姛杩斿洖true -]] -function libnet.connect(taskName,timeout, ... ) - local succ, result = socket.connect(...) - if not succ then - return false - end - if not result then - result = sysplus.waitMsg(taskName, socket.ON_LINE, timeout) - else - return true - end - if type(result) == 'table' and result[2] == 0 then - return true - else - return false - end -end - ---[[ -闃诲绛夊緟瀹㈡埛绔繛鎺ヤ笂锛屽彧鑳界敤浜巗ysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑 -@api libnet.listen(taskName,timeout,...) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鑷寸瓑寰 -@... 鍏朵粬鍙傛暟鍜宻ocket.listen涓鑷 -@return boolean 澶辫触鎴栬呰秴鏃惰繑鍥瀎alse 鎴愬姛杩斿洖true -]] -function libnet.listen(taskName,timeout, ... ) - local succ, result = socket.listen(...) - if not succ then - return false - end - if not result then - result = sysplus.waitMsg(taskName, socket.ON_LINE, timeout) - else - return true - end - if type(result) == 'table' and result[2] == 0 then - return true - else - return false - end -end - ---[[ -闃诲绛夊緟鏁版嵁鍙戦佸畬鎴愶紝鍙兘鐢ㄤ簬sysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑 -@api libnet.tx(taskName,timeout,...) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鐩寸瓑寰 -@... 鍏朵粬鍙傛暟鍜宻ocket.tx涓鑷 -@return boolean 澶辫触鎴栬呰秴鏃惰繑鍥瀎alse锛岀紦鍐插尯婊′簡鎴栬呮垚鍔熻繑鍥瀟rue -@return boolean 缂撳瓨鍖烘槸鍚︽弧浜 -]] -function libnet.tx(taskName,timeout, ...) - local succ, is_full, result = socket.tx(...) - if not succ then - return false, is_full - end - if is_full then - return true, true - end - if not result then - result = sysplus.waitMsg(taskName, socket.TX_OK, timeout) - else - return true, is_full - end - if type(result) == 'table' and result[2] == 0 then - return true, false - else - return false, is_full - end -end - ---[[ -闃诲绛夊緟鏂扮殑缃戠粶浜嬩欢锛屽彧鑳界敤浜巗ysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑锛屽彲浠ラ氳繃sysplus.sendMsg(taskName,socket.EVENT,0)鎴栬卻ys_send(taskName,socket.EVENT,0)寮哄埗閫鍑 -@api libnet.wait(taskName,timeout, netc) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鑷寸瓑寰 -@userdata socket.create杩斿洖鐨刵etc -@return boolean 缃戠粶寮傚父杩斿洖false锛屽叾浠栬繑鍥瀟rue -@return boolean 瓒呮椂杩斿洖false锛屾湁鏂扮殑缃戠粶浜嬩欢鍒拌繑鍥瀟rue -]] -function libnet.wait(taskName,timeout, netc) - local succ, result = socket.wait(netc) - if not succ then - return false,false - end - if not result then - result = sysplus.waitMsg(taskName, socket.EVENT, timeout) - else - return true,true - end - if type(result) == 'table' then - if result[2] == 0 then - return true, true - else - return false, false - end - else - return true, false - end -end - ---[[ -闃诲绛夊緟缃戠粶鏂紑杩炴帴锛屽彧鑳界敤浜巗ysplus.taskInitEx鍒涘缓鐨勪换鍔″嚱鏁颁腑 -@api libnet.close(taskName,timeout, netc) -@string 浠诲姟鏍囧織 -@int 瓒呮椂鏃堕棿锛屽鏋==0鎴栬呯┖锛屽垯娌℃湁瓒呮椂涓鑷寸瓑寰 -@userdata socket.create杩斿洖鐨刵etc -]] -function libnet.close(taskName,timeout, netc) - local succ, result = socket.discon(netc) - if not succ then - socket.close(netc) - return - end - if not result then - result = sysplus.waitMsg(taskName, socket.CLOSED, timeout) - else - socket.close(netc) - return - end - socket.close(netc) -end - -return libnet \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/netLed.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/netLed.lua deleted file mode 100644 index 725c255..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/netLed.lua +++ /dev/null @@ -1,251 +0,0 @@ ---[[ -@module netLed -@summary netLed 缃戠粶鐘舵佹寚绀虹伅 -@version 1.0 -@date 2023.02.21 -@author DingHeng -@usage ---娉ㄦ剰:鍥犱娇鐢ㄤ簡sys.wait()鎵鏈塧pi闇瑕佸湪鍗忕▼涓娇鐢 --- 鐢ㄦ硶瀹炰緥 -local netLed = require ("netLed") - -local LEDA = gpio.setup(27,1,gpio.PULLUP) --LED寮曡剼鍒ゆ柇璧嬪肩粨鏉 -sys.taskInit(function() ---鍛煎惛鐏 -sys.wait(5080)--寤舵椂5绉掔瓑寰呯綉缁滄敞鍐 -log.info("mobile.status()", mobile.status()) - while true do - if mobile.status() == 1 then--宸叉敞鍐 - sys.wait(688) - netLed.setupBreateLed(LEDA) - end - end -end) -]] - -netLed = {} --- 寮曠敤sys搴 -local sys = require("sys") - - -local simError --SIM鍗＄姸鎬侊細true涓哄紓甯,false鎴栬卬il涓烘甯 -local flyMode --鏄惁澶勪簬椋炶妯″紡锛歵rue涓烘槸,false鎴栬卬il涓哄惁 -local gprsAttached --鏄惁闄勭潃涓奊PRS缃戠粶,true涓烘槸,false鎴栬卬il涓哄惁 -local socketConnected --鏄惁鏈塻ocket杩炴帴涓婂悗鍙,true涓烘槸,false鎴栬卬il涓哄惁 - ---[[ -缃戠粶鎸囩ず鐏〃绀虹殑宸ヤ綔鐘舵 -NULL锛氬姛鑳藉叧闂姸鎬 -FLYMODE锛氶琛屾ā寮 -SIMERR锛氭湭妫娴嬪埌SIM鍗℃垨鑰匰IM鍗￠攣pin鐮佺瓑SIM鍗″紓甯 -IDLE锛氭湭娉ㄥ唽GPRS缃戠粶 -GPRS锛氬凡闄勭潃GPRS鏁版嵁缃戠粶 -SCK锛歴ocket宸茶繛鎺ヤ笂鍚庡彴 -]] -local ledState = "NULL" -local ON,OFF = 1,2 ---鍚勭宸ヤ綔鐘舵佷笅閰嶇疆鐨勭偣浜佺唲鐏椂闀匡紙鍗曚綅姣锛 -local ledBlinkTime = -{ - NULL = {0,0xFFFF}, --甯哥伃 - FLYMODE = {0,0xFFFF}, --甯哥伃 - SIMERR = {300,5700}, --浜300姣,鐏5700姣 - IDLE = {300,3700}, --浜300姣,鐏3700姣 - GPRS = {300,700}, --浜300姣,鐏700姣 - SCK = {100,100}, --浜100姣,鐏100姣 -} - - -local ledSwitch = false --缃戠粶鎸囩ず鐏紑鍏,true涓烘墦寮,false鎴栬卬il涓哄叧闂 -local LEDPIN = 27 --缃戠粶鎸囩ず鐏粯璁IN鑴氾紙GPIO27锛 -local lteSwitch = false --LTE鎸囩ず鐏紑鍏,true涓烘墦寮,false鎴栬卬il涓哄叧闂 -local LTEPIN = 26 --LTE鎸囩ず鐏粯璁IN鑴氾紙GPIO26锛 - - ---[[ -鏇存柊缃戠粶鎸囩ず鐏〃绀虹殑宸ヤ綔鐘舵 -@api netLed.setState -@return nil 鏃犺繑鍥炲 -@usage -netLed.setState() -]] - function netLed.setState() - log.info("netLed.setState",ledSwitch,ledState,flyMode,simError,gprsAttached,socketConnected) - if ledSwitch then - local newState = "IDLE" - if flyMode then - newState = "FLYMODE" - elseif simError then - newState = "SIMERR" - elseif socketConnected then - newState = "SCK" - elseif gprsAttached then - newState = "GPRS" - end - --鎸囩ず鐏姸鎬佸彂鐢熷彉鍖 - if newState~=ledState then - ledState = newState - sys.publish("NET_LED_UPDATE") - end - end -end - ---[[ -缃戠粶鎸囩ず鐏ā鍧楃殑杩愯浠诲姟 -@api netLed.taskLed(ledPinSetFunc) -@return nil 鏃犺繑鍥炲 -@usage -local LEDA = gpio.setup(27,1,gpio.PULLUP) --LED寮曡剼鍒ゆ柇璧嬪肩粨鏉 -netLed.taskLed(LEDA) -]] -function netLed.taskLed(ledPinSetFunc) - while true do - --log.info("netLed.taskLed",ledPinSetFunc,ledSwitch,ledState) - if ledSwitch then - local onTime,offTime = ledBlinkTime[ledState][ON],ledBlinkTime[ledState][OFF] - if onTime>0 then - ledPinSetFunc(1) - if not sys.waitUntil("NET_LED_UPDATE", onTime) then - if offTime>0 then - ledPinSetFunc(0) - sys.waitUntil("NET_LED_UPDATE", offTime) - end - end - else if offTime>0 then - ledPinSetFunc(0) - sys.waitUntil("NET_LED_UPDATE", offTime) - end - end - else - ledPinSetFunc(0) - break - end - end -end - ---[[ -LTE鎸囩ず鐏ā鍧楃殑杩愯浠诲姟 -@api netLed.taskLte(ledPinSetFunc) -@return nil 鏃犺繑鍥炲 -@usage -local LEDA = gpio.setup(27,1,gpio.PULLUP) --LED寮曡剼鍒ゆ柇璧嬪肩粨鏉 -netLed.taskLte(LEDA) -]] - function netLed.taskLte(ledPinSetFunc) - while true do - local _,arg = sys.waitUntil("LTE_LED_UPDATE") - if lteSwitch then - ledPinSetFunc(arg and 1 or 0) - end - end -end - ---[[ -閰嶇疆缃戠粶鎸囩ず鐏拰LTE鎸囩ず鐏苟涓旂珛鍗虫墽琛岄厤缃悗鐨勫姩浣 -@api netLed.setup(flag,ledpin,ltepin) -@bool flag 鏄惁鎵撳紑缃戠粶鎸囩ず鐏拰LTE鎸囩ず鐏姛鑳,true涓烘墦寮,false涓哄叧闂 -@number ledPin 鎺у埗缃戠粶鎸囩ず鐏棯鐑佺殑GPIO寮曡剼,渚嬪pio.P0_1琛ㄧずGPIO1 -@number ltePin 鎺у埗LTE鎸囩ず鐏棯鐑佺殑GPIO寮曡剼,渚嬪pio.P0_4琛ㄧずGPIO4 -@return nil 鏃犺繑鍥炲 -@usage -netLed.setup(true,27,0) -]] -function netLed.setup(flag,ledPin,ltePin) - --log.info("netLed.setup",flag,pin,ledSwitch) - local oldSwitch = ledSwitch - if flag~=ledSwitch then - ledSwitch = flag - sys.publish("NET_LED_UPDATE") - end - if flag and not oldSwitch then - sys.taskInit(netLed.taskLed, gpio.setup(ledPin or LEDPIN, 0)) - end - if flag~=lteSwitch then - lteSwitch = flag - end - if flag and ltePin and not oldSwitch then - sys.taskInit(netLed.taskLte, gpio.setup(ltePin, 0)) - end -end - ---[[ -閰嶇疆鏌愮宸ヤ綔鐘舵佷笅鎸囩ず鐏偣浜拰鐔勭伃鐨勬椂闀匡紙濡傛灉鐢ㄦ埛涓嶉厤缃,浣跨敤netLed.lua涓璴edBlinkTime閰嶇疆鐨勯粯璁ゅ硷級 -@api netLed.setBlinkTime(state,on,off) -@string state 鏌愮宸ヤ綔鐘舵,浠呮敮鎸"FLYMODE"銆"SIMERR"銆"IDLE"銆"GSM"銆"GPRS"銆"SCK" -@number on 鎸囩ず鐏偣浜椂闀,鍗曚綅姣,0xFFFF琛ㄧず甯镐寒,0琛ㄧず甯哥伃 -@number off 鎸囩ず鐏唲鐏椂闀,鍗曚綅姣,0xFFFF琛ㄧず甯哥伃,0琛ㄧず甯镐寒 -@return nil 鏃犺繑鍥炲 -@usage -netLed.setBlinkTime(("FLYMODE",1000,500) --琛ㄧず椋炶妯″紡宸ヤ綔鐘舵佷笅,鎸囩ず鐏棯鐑佽寰嬩负: 浜1绉,鐏8.5绉 -]] -function netLed.setBlinkTime(state,on,off) - if not ledBlinkTime[state] then log.error("netLed.setBlinkTime") return end - local updated - if on and ledBlinkTime[state][ON]~=on then - ledBlinkTime[state][ON] = on - updated = true - end - if off and ledBlinkTime[state][OFF]~=off then - ledBlinkTime[state][OFF] = off - updated = true - end - --log.info("netLed.setBlinkTime",state,on,off,updated) - if updated then sys.publish("NET_LED_UPDATE") end -end - ---[[ -鍛煎惛鐏 -@api netLed.setupBreateLed(ledPin) -@function ledPin 鍛煎惛鐏殑ledPin(1)鐢╬ins.setup娉ㄥ唽杩斿洖鐨勬柟娉 -@return nil 鏃犺繑鍥炲 -@usage -local netLed = require ("netLed") -local LEDA = gpio.setup(27,1,gpio.PULLUP) --LED寮曡剼鍒ゆ柇璧嬪肩粨鏉 -sys.taskInit(function() ---鍛煎惛鐏 -sys.wait(5080)--寤舵椂5绉掔瓑寰呯綉缁滄敞鍐 -log.info("mobile.status()", mobile.status()) - while true do - if mobile.status() == 1 then--宸叉敞鍐 - sys.wait(688) - netLed.setupBreateLed(LEDA) - end - end -end) -]] -function netLed.setupBreateLed(ledPin) --- 鍛煎惛鐏殑鐘舵併丳WM鍛ㄦ湡 - local bLighting, bDarking, LED_PWM = false, true, 18 - if bLighting then - for i = 1, LED_PWM - 1 do - ledPin(0) - sys.wait(i) - ledPin(1) - sys.wait(LED_PWM - i) - end - bLighting = false - bDarking = true - ledPin(0) - sys.wait(700) - end - if bDarking then - for i = 1, LED_PWM - 1 do - ledPin(0) - sys.wait(LED_PWM - i) - ledPin(1) - sys.wait(i) - end - bLighting = true - bDarking = false - ledPin(1) - sys.wait(700) - end -end - -sys.subscribe("FLYMODE", function(mode) if flyMode~=mode then flyMode=mode netLed.setState() end end) -sys.subscribe("SIM_IND", function(para) if simError~=(para~="RDY") and simError~=(para~="GET_NUMBER") then simError=(para~="RDY") netLed.setState() end log.info("sim status", para) end) -sys.subscribe("IP_LOSE", function() if gprsAttached then gprsAttached=false netLed.setState() end log.info("mobile", "IP_LOSE", (adapter or -1) == socket.LWIP_GP) end) -sys.subscribe("IP_READY", function(ip, adapter) if gprsAttached~=adapter then gprsAttached=adapter netLed.setState() end log.info("mobile", "IP_READY", ip, (adapter or -1) == socket.LWIP_GP) end) -sys.subscribe("SOCKET_ACTIVE", function(active) if socketConnected~=active then socketConnected=active netLed.setState() end end) - -return netLed \ No newline at end of file diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/screen_data_table.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/screen_data_table.lua deleted file mode 100644 index 2509e5c..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/screen_data_table.lua +++ /dev/null @@ -1,26 +0,0 @@ --- screen_data_table.lua ) --- 姝ゆ枃浠跺彧鍖呭惈灞忓箷鐩稿叧閰嶇疆鏁版嵁 - -local screen_data_table = { - lcdargs = { - LCD_MODEL = "AirLCD_1001", - pin_vcc = 24, - pin_rst = 36, - pin_pwr = 25, - pin_pwm = 2, - port = lcd.HWID_0, - direction = 0, - w = 320, - h = 480, - xoffset = 0, - yoffset = 0, - }, - touch = { - TP_MODEL = "Air780EHM_LCD_4", -- 瑙︽懜鑺墖鍨嬪彿 - i2c_id = 1, -- I2C鎬荤嚎ID - pin_rst = 255, -- 瑙︽懜鑺墖澶嶄綅寮曡剼(闈炲繀椤) - pin_int = 22 -- 瑙︽懜鑺墖涓柇寮曡剼 - }, -} - -return screen_data_table diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/udpsrv.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/udpsrv.lua deleted file mode 100644 index 8d0c46a..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/udpsrv.lua +++ /dev/null @@ -1,101 +0,0 @@ ---[[ -@module udpsrv -@summary UDP鏈嶅姟鍣 -@version 1.0 -@date 2023.7.28 -@author wendal -@demo socket -@tag LUAT_USE_NETWORK -@usage --- 鍏蜂綋鐢ㄦ硶璇锋煡 -闃卍emo -]] - -local sys = require "sys" - -local udpsrv = {} -local srvs = {} - ---[[ -鍒涘缓UDP鏈嶅姟鍣 -@api udpsrv.create(port, topic, adapter) -@int 绔彛鍙, 蹇呭～, 蹇呴』澶т簬0灏忎簬65525 -@string 鏀跺彇UDP鏁版嵁鐨則opic,蹇呭～ -@int 缃戠粶閫傞厤缂栧彿, 榛樿涓簄il,鍙 -@return table UDP鏈嶅姟鐨勫疄浣, 鑻ュ垱寤哄け璐ヤ細杩斿洖nil -]] -function udpsrv.create(port, topic, adapter) - local srv = {} - -- udpsrv.port = port - -- srv.topic = topic - srv.rxbuff = zbuff.create(1500) - local sc = socket.create(adapter, function(sc, event) - -- log.info("udpsrv", sc, event, "EVENT", socket.EVENT, "CLOSED", socket.CLOSED) - if event == socket.EVENT then - local rxbuff = srv.rxbuff - while 1 do - local succ, data_len, remote_ip, remote_port = socket.rx(sc, rxbuff) - -- log.info("udpsrv", "???", succ, data_len, remote_ip, remote_port) - if succ and data_len and data_len > 0 then - local resp = rxbuff:toStr(0, rxbuff:used()) - rxbuff:del() - if remote_ip and #remote_ip == 5 then - local ip1,ip2,ip3,ip4 = remote_ip:byte(2),remote_ip:byte(3),remote_ip:byte(4),remote_ip:byte(5) - remote_ip = string.format("%d.%d.%d.%d", ip1, ip2, ip3, ip4) - else - remote_ip = nil - end - sys.publish(topic, resp, remote_ip, remote_port) - else - if not succ then - socket.close(sc) - socket.connect(sc, "255.255.255.255", 0) - end - break - end - end - elseif event == socket.CLOSED then - log.info("dhcpsrv", "缃戠粶涓柇,鎵ц鍏抽棴娴佺▼") - socket.close(self.sc) - end - end) - if sc == nil then - return - end - srv.sc = sc - -- socket.debug(sc, true) - socket.config(sc, port, true) - if socket.connect(sc, "255.255.255.255", 0) then - srv.send = function(self, data, ip, port) - if self.sc and data then - -- log.info("why?", self.sc, data, ip, port) - return socket.tx(self.sc, data, ip, port) - end - end - srv.close = function(self) - socket.close(self.sc) - -- sys.wait(200) - socket.release(self.sc) - srvs[self.sc] = nil - self.sc = nil - end - srvs[srv.sc] = true - -- log.info("udpsrv", "鐩戝惉寮濮") - return srv - end - socket.close(sc) - -- sys.wait(200) - socket.release(sc) - -- log.info("udpsrv", "鐩戝惉澶辫触") -end - -sys.subscribe("IP_READY", function() - for sc, value in pairs(srvs) do - log.info("udpsrv", "鑷姩閲嶈繛udpsrv", sc) - if sc then - socket.connect(sc, "255.255.255.255", 0) - end - end -end) - -return udpsrv diff --git a/4G/tools/resource/soc_script/v2025.12.31.22/lib/xmodem.lua b/4G/tools/resource/soc_script/v2025.12.31.22/lib/xmodem.lua deleted file mode 100644 index f20cee0..0000000 --- a/4G/tools/resource/soc_script/v2025.12.31.22/lib/xmodem.lua +++ /dev/null @@ -1,222 +0,0 @@ ---[[ -@module xmodem -@summary xmodem 鍗忚 -@version 1.0 -@date 2025.10.17 -@author Dozingfiretruck -@usage ---鍔犺浇xmodem妯″潡 -xmodem=require ("xmodem") - ---璁剧疆榛樿filepath涓鸿剼鏈尯鐨剆end.bin鏂囦欢 -local filepath="/luadb/send.bin" - -local taskName = "xmodem_run" - - -local uart_id = 1 --涓插彛鍙 - -local baudrate = 115200 --娉㈢壒鐜 - -local file_path=filepath --鏂囦欢璺緞 - -local send_type=true --true琛ㄧず鍗曟鍙戦128瀛楄妭锛宖alse琛ㄧず鍗曟鍙戦1024瀛楄妭 - -local inform_data="wait C" --鍙戦佸墠鎻愮ず淇℃伅锛屽憡鐭ュ鏂硅鍙戦丆瀛楃鏉ユ帴鏀舵枃浠 - --- 澶勭悊鏈瘑鍒殑娑堟伅 -local function xmodem_run_cb(msg) - log.info("xmodem_run_cb", msg[1], msg[2], msg[3], msg[4]) -end - ---http鑾峰彇鏂囦欢鍑芥暟 -local function http_recived_cb() - while not socket.adapter(socket.dft()) do - log.warn("httpplus_app_task_func", "wait IP_READY", socket.dft()) - -- 鍦ㄦ澶勯樆濉炵瓑寰呴粯璁ょ綉鍗¤繛鎺ユ垚鍔熺殑娑堟伅"IP_READY" - -- 鎴栬呯瓑寰1绉掕秴鏃堕鍑洪樆濉炵瓑寰呯姸鎬; - -- 娉ㄦ剰锛氭澶勭殑1000姣瓒呮椂涓嶈淇敼鐨勬洿闀匡紱 - -- 鍥犱负褰撲娇鐢╡xnetif.set_priority_order閰嶇疆澶氫釜缃戝崱杩炴帴澶栫綉鐨勪紭鍏堢骇鏃讹紝浼氶殣寮忕殑淇敼榛樿浣跨敤鐨勭綉鍗 - -- 褰揺xnetif.set_priority_order鐨勮皟鐢ㄦ椂搴忓拰姝ゅ鐨剆ocket.adapter(socket.dft())鍒ゆ柇鏃跺簭鏈夊彲鑳戒笉鍖归厤 - -- 姝ゅ鐨1绉掞紝鑳藉淇濊瘉锛屽嵆浣挎椂搴忎笉鍖归厤锛屼篃鑳1绉掗挓閫鍑洪樆濉炵姸鎬侊紝鍐嶅幓鍒ゆ柇socket.adapter(socket.dft()) - sys.waitUntil("IP_READY", 1000) - end - local path = "/send.bin" - -- 浠ヤ笅閾炬帴浠呯敤浜庢祴璇曪紝绂佹鐢ㄤ簬鐢熶骇鐜 - local code, headers, body_size = http.request("GET", "http://airtest.openluat.com:2900/download/send.bin", nil, nil, {dst=path}).wait() - log.info("http", code==200 and "success" or "error", code) - if code==200 then - log.info("HTTP receive ok",body_size) - file = io.open(path, "rb") - if file then - content = file:read("*a") - log.info("鏂囦欢璇诲彇", "璺緞:" .. path, "鍐呭:" .. content) - file:close() - else - log.error("鏂囦欢鎿嶄綔", "鏃犳硶鎵撳紑鏂囦欢璇诲彇鍐呭", "璺緞:" .. path) - end - file_path=path - end - -end - --- 瀹氫箟涓涓獂modem_run鍑芥暟锛岀敤浜庣敤xmodem鍙戦佹枃浠 -local function xmodem_run() - --濡傛灉闇瑕乭ttp涓嬭浇鏂囦欢锛岀劧鍚庡彂閫佷笅杞界殑鏂囦欢锛屽彲浠ユ墦寮涓嬮潰鐨刪ttp_recived_cb()鍑芥暟 - -- http_recived_cb() - - --鍚姩xmodem鍙戦 - local result=xmodem.send(uart_id,baudrate,file_path,send_type,inform_data) - --绛夊緟鏃堕棿12绉掞紝绛夊緟鎺ユ敹鏂瑰彂閫丆瀛楃鍚姩鍙戦侊紝鍙戦佺粨鏉熷悗鎺ユ敹绔彂閫丄CK:0x06琛ㄧず鎺ユ敹瀹屾垚锛屾枃浠跺叏閮ㄤ紶杈撳畬鎴愪箣鍚庢ā鍧楀彂閫丒OT鈥嬶細0x04琛ㄧず浼犺緭缁撴潫锛屾帴鏀剁杩斿洖0x06琛ㄧず纭缁撴潫 - log.info("Xmodem", "start") - - log.info("Xmodem", "send result", result) - --鍒ゆ柇鏄惁浼犺緭鎴愬姛锛屼紶杈撴槸鍚︽垚鍔燂紝閮介渶瑕佸叧闂瓁modem - if result then - log.info("Xmodem", "send success") - xmodem.close(uart_id) - else - log.info("Xmodem", "send failed") - xmodem.close(uart_id) - end - -end - ---鍒涘缓骞朵笖鍚姩涓涓猼ask ---杩愯杩欎釜task鐨勪富鍑芥暟xmodem_run -sys.taskInit(xmodem_run, taskName,xmodem_run_cb) - - -]] -local xmodem = {} - -local sys = require "sys" - -local HEAD -local DATA_SIZE - -local SOH = 0x01 -- Modem鏁版嵁澶 128 -local STX = 0x02 -- Modem鏁版嵁澶 1K -local EOT = 0x04 -- 鍙戦佺粨鏉 -local ACK = 0x06 -- 搴旂瓟 -local NAK = 0x15 -- 闈炲簲绛 -local CAN = 0x18 -- 鍙栨秷鍙戦 -local CTRLZ = 0x1A -- 濉厖 -local CRC_CHR = 0x43 -- C: ASCII瀛楃C -local CRC_SIZE = 2 -local FRAME_ID_SIZE = 2 -local DATA_SIZE_SOH = 128 -local DATA_SIZE_STX = 1024 - - -local function uart_cb(id, len) - local data = uart.read(id, 1024) - if #data == 0 then - return - end - log.info("xmodem", "uart璇诲彇鍒版暟鎹:", data:toHex()) - data = data:byte(1) - sys.publish("xmodem", data) -end - - ---[[ -xmodem 鍙戦佹枃浠 -@api xmodem.send(uart_id,baudrate,type,inform_data) -@number uart_id uart绔彛鍙 -@number uart_br uart娉㈢壒鐜 -@string file_path 鏂囦欢璺緞 -@bool type 1k/128 榛樿1k -@return bool 鍙戦佺粨鏋 -@usage -xmodem.send(1, 115200, "/luadb/send.bin",true) -]] - -function xmodem.send(uart_id,baudrate,file_path,type,inform_data) - local ret, flen, cnt, crc - if type then - HEAD = SOH - DATA_SIZE = DATA_SIZE_SOH - else - HEAD = STX - DATA_SIZE = DATA_SIZE_STX - end - local XMODEM_SIZE = 1+FRAME_ID_SIZE+DATA_SIZE+CRC_SIZE - local packsn = 0 - local xmodem_buff = zbuff.create(XMODEM_SIZE) - local data_buff = zbuff.create(DATA_SIZE) - local fd = io.open(file_path, "rb") - if fd then - uart.setup(uart_id,baudrate) - uart.on(uart_id, "receive", uart_cb) - if inform_data and inform_data~="" then - uart.write(uart_id,inform_data) - end - local result, data = sys.waitUntil("xmodem", 12000) - if result and (data == CRC_CHR or data == NAK) then - cnt = 1 - while true do - data_buff:set(0, CTRLZ) - ret, flen = fd:fill(data_buff,0,DATA_SIZE) - log.info("xmodem", "鍙戦佺", cnt, "鍖") - if flen > 0 then - data_buff:seek(0) - crc = crypto.crc16("XMODEM",data_buff) - packsn = (packsn+1) & 0xff - xmodem_buff[0] = 0x02 - xmodem_buff[1] = packsn - xmodem_buff[2] = 0xff-xmodem_buff[1] - data_buff:seek(DATA_SIZE) - xmodem_buff:copy(3, data_buff) - xmodem_buff[1027] = crc>>8 - xmodem_buff[1028] = crc&0xff - xmodem_buff:seek(XMODEM_SIZE) - -- log.info(xmodem_buff:used()) - :: RESEND :: - uart.tx(uart_id, xmodem_buff) - result, data = sys.waitUntil("xmodem", 10000) - if result and data == ACK then - cnt = cnt + 1 - elseif result and data == NAK then - goto RESEND - else - uart.write(uart_id, string.char(EOT)) - log.info("xmodem", "鍙戦佸け璐") - return false - end - if flen ~= DATA_SIZE then - log.info("xmodem", "鏂囦欢鍒板ご浜") - break - end - else - log.info("xmodem", "鏂囦欢鍒板ご浜") - break - end - end - uart.write(uart_id, string.char(EOT)) - fd:close() - return true - else - log.info("xmodem", "涓嶆敮鎸佺殑璧峰鏁版嵁鍖",data) - return false - end - else - log.info("xmodem", "寰呬紶杈撶殑鏂囦欢涓嶅瓨鍦") - return false - end -end - ---[[ -鍏抽棴xmodem -@api xmodem.close(uart_id) -@number uart_id uart绔彛鍙 -@usage --- 鎵цxmodem浼犺緭鍚, 鏃犺鏄惁浼犺緭鎴愬姛, 閮藉缓璁叧闂瓁modem涓婁笅鏂, 涔熶細鍏抽棴uart -xmodem.close(2) -]] -function xmodem.close(uart_id) - uart.on(uart_id, "receive") - uart.close(uart_id) -end - -return xmodem